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radv: Add logic for subsampled format descriptions.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (pCreateInfo->format != format_list->pViewFormats[i])
113 return false;
114 }
115 } else {
116 return false;
117 }
118 }
119
120 return true;
121 }
122
123 static bool
124 radv_use_dcc_for_image(struct radv_device *device,
125 const struct radv_image *image,
126 const struct radv_image_create_info *create_info,
127 const VkImageCreateInfo *pCreateInfo)
128 {
129 bool dcc_compatible_formats;
130 bool blendable;
131
132 /* DCC (Delta Color Compression) is only available for GFX8+. */
133 if (device->physical_device->rad_info.chip_class < VI)
134 return false;
135
136 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
137 return false;
138
139 /* FIXME: DCC is broken for shareable images starting with GFX9 */
140 if (device->physical_device->rad_info.chip_class >= GFX9 &&
141 image->shareable)
142 return false;
143
144 /* TODO: Enable DCC for storage images. */
145 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
146 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
147 return false;
148
149 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
150 return false;
151
152 if (vk_format_is_subsampled(pCreateInfo->format))
153 return false;
154
155 /* TODO: Enable DCC for mipmaps and array layers. */
156 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
157 return false;
158
159 if (create_info->scanout)
160 return false;
161
162 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
163 * 2x can be enabled with an option.
164 */
165 if (pCreateInfo->samples > 2 ||
166 (pCreateInfo->samples == 2 &&
167 !device->physical_device->dcc_msaa_allowed))
168 return false;
169
170 /* Determine if the formats are DCC compatible. */
171 dcc_compatible_formats =
172 radv_is_colorbuffer_format_supported(pCreateInfo->format,
173 &blendable);
174
175 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
176 const struct VkImageFormatListCreateInfoKHR *format_list =
177 (const struct VkImageFormatListCreateInfoKHR *)
178 vk_find_struct_const(pCreateInfo->pNext,
179 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
180
181 /* We have to ignore the existence of the list if viewFormatCount = 0 */
182 if (format_list && format_list->viewFormatCount) {
183 /* compatibility is transitive, so we only need to check
184 * one format with everything else. */
185 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
186 if (!radv_dcc_formats_compatible(pCreateInfo->format,
187 format_list->pViewFormats[i]))
188 dcc_compatible_formats = false;
189 }
190 } else {
191 dcc_compatible_formats = false;
192 }
193 }
194
195 if (!dcc_compatible_formats)
196 return false;
197
198 return true;
199 }
200
201 static int
202 radv_init_surface(struct radv_device *device,
203 const struct radv_image *image,
204 struct radeon_surf *surface,
205 const struct radv_image_create_info *create_info)
206 {
207 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
208 unsigned array_mode = radv_choose_tiling(device, create_info);
209 const struct vk_format_description *desc =
210 vk_format_description(pCreateInfo->format);
211 bool is_depth, is_stencil;
212
213 is_depth = vk_format_has_depth(desc);
214 is_stencil = vk_format_has_stencil(desc);
215
216 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
217 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
218
219 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
220 /* align byte per element on dword */
221 if (surface->bpe == 3) {
222 surface->bpe = 4;
223 }
224 surface->flags = RADEON_SURF_SET(array_mode, MODE);
225
226 switch (pCreateInfo->imageType){
227 case VK_IMAGE_TYPE_1D:
228 if (pCreateInfo->arrayLayers > 1)
229 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
230 else
231 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
232 break;
233 case VK_IMAGE_TYPE_2D:
234 if (pCreateInfo->arrayLayers > 1)
235 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
236 else
237 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
238 break;
239 case VK_IMAGE_TYPE_3D:
240 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
241 break;
242 default:
243 unreachable("unhandled image type");
244 }
245
246 if (is_depth) {
247 surface->flags |= RADEON_SURF_ZBUFFER;
248 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
249 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
250 }
251
252 if (is_stencil)
253 surface->flags |= RADEON_SURF_SBUFFER;
254
255 if (device->physical_device->rad_info.chip_class >= GFX9 &&
256 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
257 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
258 vk_format_is_compressed(pCreateInfo->format))
259 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
260
261 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
262
263 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
264 surface->flags |= RADEON_SURF_DISABLE_DCC;
265
266 if (create_info->scanout)
267 surface->flags |= RADEON_SURF_SCANOUT;
268 return 0;
269 }
270
271 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
272 {
273 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
274 }
275
276 static inline unsigned
277 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
278 {
279 if (stencil)
280 return image->surface.u.legacy.stencil_tiling_index[level];
281 else
282 return image->surface.u.legacy.tiling_index[level];
283 }
284
285 static unsigned radv_map_swizzle(unsigned swizzle)
286 {
287 switch (swizzle) {
288 case VK_SWIZZLE_Y:
289 return V_008F0C_SQ_SEL_Y;
290 case VK_SWIZZLE_Z:
291 return V_008F0C_SQ_SEL_Z;
292 case VK_SWIZZLE_W:
293 return V_008F0C_SQ_SEL_W;
294 case VK_SWIZZLE_0:
295 return V_008F0C_SQ_SEL_0;
296 case VK_SWIZZLE_1:
297 return V_008F0C_SQ_SEL_1;
298 default: /* VK_SWIZZLE_X */
299 return V_008F0C_SQ_SEL_X;
300 }
301 }
302
303 static void
304 radv_make_buffer_descriptor(struct radv_device *device,
305 struct radv_buffer *buffer,
306 VkFormat vk_format,
307 unsigned offset,
308 unsigned range,
309 uint32_t *state)
310 {
311 const struct vk_format_description *desc;
312 unsigned stride;
313 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
314 uint64_t va = gpu_address + buffer->offset;
315 unsigned num_format, data_format;
316 int first_non_void;
317 desc = vk_format_description(vk_format);
318 first_non_void = vk_format_get_first_non_void_channel(vk_format);
319 stride = desc->block.bits / 8;
320
321 num_format = radv_translate_buffer_numformat(desc, first_non_void);
322 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
323
324 va += offset;
325 state[0] = va;
326 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
327 S_008F04_STRIDE(stride);
328
329 if (device->physical_device->rad_info.chip_class != VI && stride) {
330 range /= stride;
331 }
332
333 state[2] = range;
334 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
335 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
336 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
337 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
338 S_008F0C_NUM_FORMAT(num_format) |
339 S_008F0C_DATA_FORMAT(data_format);
340 }
341
342 static void
343 si_set_mutable_tex_desc_fields(struct radv_device *device,
344 struct radv_image *image,
345 const struct legacy_surf_level *base_level_info,
346 unsigned base_level, unsigned first_level,
347 unsigned block_width, bool is_stencil,
348 bool is_storage_image, uint32_t *state)
349 {
350 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
351 uint64_t va = gpu_address;
352 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
353 uint64_t meta_va = 0;
354 if (chip_class >= GFX9) {
355 if (is_stencil)
356 va += image->surface.u.gfx9.stencil_offset;
357 else
358 va += image->surface.u.gfx9.surf_offset;
359 } else
360 va += base_level_info->offset;
361
362 state[0] = va >> 8;
363 if (chip_class >= GFX9 ||
364 base_level_info->mode == RADEON_SURF_MODE_2D)
365 state[0] |= image->surface.tile_swizzle;
366 state[1] &= C_008F14_BASE_ADDRESS_HI;
367 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
368
369 if (chip_class >= VI) {
370 state[6] &= C_008F28_COMPRESSION_EN;
371 state[7] = 0;
372 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
373 meta_va = gpu_address + image->dcc_offset;
374 if (chip_class <= VI)
375 meta_va += base_level_info->dcc_offset;
376 } else if (!is_storage_image &&
377 radv_image_is_tc_compat_htile(image)) {
378 meta_va = gpu_address + image->htile_offset;
379 }
380
381 if (meta_va) {
382 state[6] |= S_008F28_COMPRESSION_EN(1);
383 state[7] = meta_va >> 8;
384 state[7] |= image->surface.tile_swizzle;
385 }
386 }
387
388 if (chip_class >= GFX9) {
389 state[3] &= C_008F1C_SW_MODE;
390 state[4] &= C_008F20_PITCH_GFX9;
391
392 if (is_stencil) {
393 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
394 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
395 } else {
396 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
397 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
398 }
399
400 state[5] &= C_008F24_META_DATA_ADDRESS &
401 C_008F24_META_PIPE_ALIGNED &
402 C_008F24_META_RB_ALIGNED;
403 if (meta_va) {
404 struct gfx9_surf_meta_flags meta;
405
406 if (image->dcc_offset)
407 meta = image->surface.u.gfx9.dcc;
408 else
409 meta = image->surface.u.gfx9.htile;
410
411 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
412 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
413 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
414 }
415 } else {
416 /* SI-CI-VI */
417 unsigned pitch = base_level_info->nblk_x * block_width;
418 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
419
420 state[3] &= C_008F1C_TILING_INDEX;
421 state[3] |= S_008F1C_TILING_INDEX(index);
422 state[4] &= C_008F20_PITCH_GFX6;
423 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
424 }
425 }
426
427 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
428 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
429 {
430 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
431 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
432
433 /* GFX9 allocates 1D textures as 2D. */
434 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
435 image_type = VK_IMAGE_TYPE_2D;
436 switch (image_type) {
437 case VK_IMAGE_TYPE_1D:
438 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
439 case VK_IMAGE_TYPE_2D:
440 if (nr_samples > 1)
441 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
442 else
443 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
444 case VK_IMAGE_TYPE_3D:
445 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
446 return V_008F1C_SQ_RSRC_IMG_3D;
447 else
448 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
449 default:
450 unreachable("illegal image type");
451 }
452 }
453
454 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
455 {
456 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
457
458 if (swizzle[3] == VK_SWIZZLE_X) {
459 /* For the pre-defined border color values (white, opaque
460 * black, transparent black), the only thing that matters is
461 * that the alpha channel winds up in the correct place
462 * (because the RGB channels are all the same) so either of
463 * these enumerations will work.
464 */
465 if (swizzle[2] == VK_SWIZZLE_Y)
466 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
467 else
468 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
469 } else if (swizzle[0] == VK_SWIZZLE_X) {
470 if (swizzle[1] == VK_SWIZZLE_Y)
471 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
472 else
473 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
474 } else if (swizzle[1] == VK_SWIZZLE_X) {
475 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
476 } else if (swizzle[2] == VK_SWIZZLE_X) {
477 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
478 }
479
480 return bc_swizzle;
481 }
482
483 /**
484 * Build the sampler view descriptor for a texture.
485 */
486 static void
487 si_make_texture_descriptor(struct radv_device *device,
488 struct radv_image *image,
489 bool is_storage_image,
490 VkImageViewType view_type,
491 VkFormat vk_format,
492 const VkComponentMapping *mapping,
493 unsigned first_level, unsigned last_level,
494 unsigned first_layer, unsigned last_layer,
495 unsigned width, unsigned height, unsigned depth,
496 uint32_t *state,
497 uint32_t *fmask_state)
498 {
499 const struct vk_format_description *desc;
500 enum vk_swizzle swizzle[4];
501 int first_non_void;
502 unsigned num_format, data_format, type;
503
504 desc = vk_format_description(vk_format);
505
506 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
507 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
508 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
509 } else {
510 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
511 }
512
513 first_non_void = vk_format_get_first_non_void_channel(vk_format);
514
515 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
516 if (num_format == ~0) {
517 num_format = 0;
518 }
519
520 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
521 if (data_format == ~0) {
522 data_format = 0;
523 }
524
525 /* S8 with either Z16 or Z32 HTILE need a special format. */
526 if (device->physical_device->rad_info.chip_class >= GFX9 &&
527 vk_format == VK_FORMAT_S8_UINT &&
528 radv_image_is_tc_compat_htile(image)) {
529 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
530 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
531 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
532 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
533 }
534 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
535 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
536 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
537 height = 1;
538 depth = image->info.array_size;
539 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
540 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
541 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
542 depth = image->info.array_size;
543 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
544 depth = image->info.array_size / 6;
545
546 state[0] = 0;
547 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
548 S_008F14_NUM_FORMAT_GFX6(num_format));
549 state[2] = (S_008F18_WIDTH(width - 1) |
550 S_008F18_HEIGHT(height - 1) |
551 S_008F18_PERF_MOD(4));
552 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
553 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
554 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
555 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
556 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
557 0 : first_level) |
558 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
559 util_logbase2(image->info.samples) :
560 last_level) |
561 S_008F1C_TYPE(type));
562 state[4] = 0;
563 state[5] = S_008F24_BASE_ARRAY(first_layer);
564 state[6] = 0;
565 state[7] = 0;
566
567 if (device->physical_device->rad_info.chip_class >= GFX9) {
568 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
569
570 /* Depth is the last accessible layer on Gfx9.
571 * The hw doesn't need to know the total number of layers.
572 */
573 if (type == V_008F1C_SQ_RSRC_IMG_3D)
574 state[4] |= S_008F20_DEPTH(depth - 1);
575 else
576 state[4] |= S_008F20_DEPTH(last_layer);
577
578 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
579 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
580 util_logbase2(image->info.samples) :
581 image->info.levels - 1);
582 } else {
583 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
584 state[4] |= S_008F20_DEPTH(depth - 1);
585 state[5] |= S_008F24_LAST_ARRAY(last_layer);
586 }
587 if (image->dcc_offset) {
588 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
589
590 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
591 } else {
592 /* The last dword is unused by hw. The shader uses it to clear
593 * bits in the first dword of sampler state.
594 */
595 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
596 if (first_level == last_level)
597 state[7] = C_008F30_MAX_ANISO_RATIO;
598 else
599 state[7] = 0xffffffff;
600 }
601 }
602
603 /* Initialize the sampler view for FMASK. */
604 if (radv_image_has_fmask(image)) {
605 uint32_t fmask_format, num_format;
606 uint64_t gpu_address = radv_buffer_get_va(image->bo);
607 uint64_t va;
608
609 va = gpu_address + image->offset + image->fmask.offset;
610
611 if (device->physical_device->rad_info.chip_class >= GFX9) {
612 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
613 switch (image->info.samples) {
614 case 2:
615 num_format = V_008F14_IMG_FMASK_8_2_2;
616 break;
617 case 4:
618 num_format = V_008F14_IMG_FMASK_8_4_4;
619 break;
620 case 8:
621 num_format = V_008F14_IMG_FMASK_32_8_8;
622 break;
623 default:
624 unreachable("invalid nr_samples");
625 }
626 } else {
627 switch (image->info.samples) {
628 case 2:
629 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
630 break;
631 case 4:
632 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
633 break;
634 case 8:
635 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
636 break;
637 default:
638 assert(0);
639 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
640 }
641 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
642 }
643
644 fmask_state[0] = va >> 8;
645 fmask_state[0] |= image->fmask.tile_swizzle;
646 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
647 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
648 S_008F14_NUM_FORMAT_GFX6(num_format);
649 fmask_state[2] = S_008F18_WIDTH(width - 1) |
650 S_008F18_HEIGHT(height - 1);
651 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
652 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
653 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
654 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
655 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
656 fmask_state[4] = 0;
657 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
658 fmask_state[6] = 0;
659 fmask_state[7] = 0;
660
661 if (device->physical_device->rad_info.chip_class >= GFX9) {
662 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
663 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
664 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
665 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
666 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
667 } else {
668 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
669 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
670 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
671 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
672 }
673 } else if (fmask_state)
674 memset(fmask_state, 0, 8 * 4);
675 }
676
677 static void
678 radv_query_opaque_metadata(struct radv_device *device,
679 struct radv_image *image,
680 struct radeon_bo_metadata *md)
681 {
682 static const VkComponentMapping fixedmapping;
683 uint32_t desc[8], i;
684
685 /* Metadata image format format version 1:
686 * [0] = 1 (metadata format identifier)
687 * [1] = (VENDOR_ID << 16) | PCI_ID
688 * [2:9] = image descriptor for the whole resource
689 * [2] is always 0, because the base address is cleared
690 * [9] is the DCC offset bits [39:8] from the beginning of
691 * the buffer
692 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
693 */
694 md->metadata[0] = 1; /* metadata image format version 1 */
695
696 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
697 md->metadata[1] = si_get_bo_metadata_word1(device);
698
699
700 si_make_texture_descriptor(device, image, false,
701 (VkImageViewType)image->type, image->vk_format,
702 &fixedmapping, 0, image->info.levels - 1, 0,
703 image->info.array_size - 1,
704 image->info.width, image->info.height,
705 image->info.depth,
706 desc, NULL);
707
708 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
709 image->surface.blk_w, false, false, desc);
710
711 /* Clear the base address and set the relative DCC offset. */
712 desc[0] = 0;
713 desc[1] &= C_008F14_BASE_ADDRESS_HI;
714 desc[7] = image->dcc_offset >> 8;
715
716 /* Dwords [2:9] contain the image descriptor. */
717 memcpy(&md->metadata[2], desc, sizeof(desc));
718
719 /* Dwords [10:..] contain the mipmap level offsets. */
720 if (device->physical_device->rad_info.chip_class <= VI) {
721 for (i = 0; i <= image->info.levels - 1; i++)
722 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
723 md->size_metadata = (11 + image->info.levels - 1) * 4;
724 }
725 }
726
727 void
728 radv_init_metadata(struct radv_device *device,
729 struct radv_image *image,
730 struct radeon_bo_metadata *metadata)
731 {
732 struct radeon_surf *surface = &image->surface;
733
734 memset(metadata, 0, sizeof(*metadata));
735
736 if (device->physical_device->rad_info.chip_class >= GFX9) {
737 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
738 } else {
739 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
740 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
741 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
742 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
743 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
744 metadata->u.legacy.bankw = surface->u.legacy.bankw;
745 metadata->u.legacy.bankh = surface->u.legacy.bankh;
746 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
747 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
748 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
749 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
750 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
751 }
752 radv_query_opaque_metadata(device, image, metadata);
753 }
754
755 /* The number of samples can be specified independently of the texture. */
756 static void
757 radv_image_get_fmask_info(struct radv_device *device,
758 struct radv_image *image,
759 unsigned nr_samples,
760 struct radv_fmask_info *out)
761 {
762 if (device->physical_device->rad_info.chip_class >= GFX9) {
763 out->alignment = image->surface.fmask_alignment;
764 out->size = image->surface.fmask_size;
765 out->tile_swizzle = image->surface.fmask_tile_swizzle;
766 return;
767 }
768
769 out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
770 out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
771 out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
772 out->bank_height = image->surface.u.legacy.fmask.bankh;
773 out->tile_swizzle = image->surface.fmask_tile_swizzle;
774 out->alignment = image->surface.fmask_alignment;
775 out->size = image->surface.fmask_size;
776
777 assert(!out->tile_swizzle || !image->shareable);
778 }
779
780 static void
781 radv_image_alloc_fmask(struct radv_device *device,
782 struct radv_image *image)
783 {
784 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
785
786 image->fmask.offset = align64(image->size, image->fmask.alignment);
787 image->size = image->fmask.offset + image->fmask.size;
788 image->alignment = MAX2(image->alignment, image->fmask.alignment);
789 }
790
791 static void
792 radv_image_get_cmask_info(struct radv_device *device,
793 struct radv_image *image,
794 struct radv_cmask_info *out)
795 {
796 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
797 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
798 unsigned cl_width, cl_height;
799
800 if (device->physical_device->rad_info.chip_class >= GFX9) {
801 out->alignment = image->surface.cmask_alignment;
802 out->size = image->surface.cmask_size;
803 return;
804 }
805
806 switch (num_pipes) {
807 case 2:
808 cl_width = 32;
809 cl_height = 16;
810 break;
811 case 4:
812 cl_width = 32;
813 cl_height = 32;
814 break;
815 case 8:
816 cl_width = 64;
817 cl_height = 32;
818 break;
819 case 16: /* Hawaii */
820 cl_width = 64;
821 cl_height = 64;
822 break;
823 default:
824 assert(0);
825 return;
826 }
827
828 unsigned base_align = num_pipes * pipe_interleave_bytes;
829
830 unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
831 unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
832 unsigned slice_elements = (width * height) / (8*8);
833
834 /* Each element of CMASK is a nibble. */
835 unsigned slice_bytes = slice_elements / 2;
836
837 out->slice_tile_max = (width * height) / (128*128);
838 if (out->slice_tile_max)
839 out->slice_tile_max -= 1;
840
841 out->alignment = MAX2(256, base_align);
842 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
843 align(slice_bytes, base_align);
844 }
845
846 static void
847 radv_image_alloc_cmask(struct radv_device *device,
848 struct radv_image *image)
849 {
850 uint32_t clear_value_size = 0;
851 radv_image_get_cmask_info(device, image, &image->cmask);
852
853 image->cmask.offset = align64(image->size, image->cmask.alignment);
854 /* + 8 for storing the clear values */
855 if (!image->clear_value_offset) {
856 image->clear_value_offset = image->cmask.offset + image->cmask.size;
857 clear_value_size = 8;
858 }
859 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
860 image->alignment = MAX2(image->alignment, image->cmask.alignment);
861 }
862
863 static void
864 radv_image_alloc_dcc(struct radv_image *image)
865 {
866 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
867 /* + 16 for storing the clear values + dcc pred */
868 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
869 image->fce_pred_offset = image->clear_value_offset + 8;
870 image->dcc_pred_offset = image->clear_value_offset + 16;
871 image->size = image->dcc_offset + image->surface.dcc_size + 24;
872 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
873 }
874
875 static void
876 radv_image_alloc_htile(struct radv_image *image)
877 {
878 image->htile_offset = align64(image->size, image->surface.htile_alignment);
879
880 /* + 8 for storing the clear values */
881 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
882 image->size = image->clear_value_offset + 8;
883 if (radv_image_is_tc_compat_htile(image)) {
884 /* Metadata for the TC-compatible HTILE hardware bug which
885 * have to be fixed by updating ZRANGE_PRECISION when doing
886 * fast depth clears to 0.0f.
887 */
888 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
889 image->size = image->clear_value_offset + 16;
890 }
891 image->alignment = align64(image->alignment, image->surface.htile_alignment);
892 }
893
894 static inline bool
895 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
896 {
897 if (image->info.samples <= 1 &&
898 image->info.width * image->info.height <= 512 * 512) {
899 /* Do not enable CMASK or DCC for small surfaces where the cost
900 * of the eliminate pass can be higher than the benefit of fast
901 * clear. RadeonSI does this, but the image threshold is
902 * different.
903 */
904 return false;
905 }
906
907 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
908 (image->exclusive || image->queue_family_mask == 1);
909 }
910
911 static inline bool
912 radv_image_can_enable_dcc(struct radv_image *image)
913 {
914 return radv_image_can_enable_dcc_or_cmask(image) &&
915 radv_image_has_dcc(image);
916 }
917
918 static inline bool
919 radv_image_can_enable_cmask(struct radv_image *image)
920 {
921 if (image->surface.bpe > 8 && image->info.samples == 1) {
922 /* Do not enable CMASK for non-MSAA images (fast color clear)
923 * because 128 bit formats are not supported, but FMASK might
924 * still be used.
925 */
926 return false;
927 }
928
929 return radv_image_can_enable_dcc_or_cmask(image) &&
930 image->info.levels == 1 &&
931 image->info.depth == 1 &&
932 !image->surface.is_linear;
933 }
934
935 static inline bool
936 radv_image_can_enable_fmask(struct radv_image *image)
937 {
938 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
939 }
940
941 static inline bool
942 radv_image_can_enable_htile(struct radv_image *image)
943 {
944 return radv_image_has_htile(image) &&
945 image->info.levels == 1 &&
946 image->info.width * image->info.height >= 8 * 8;
947 }
948
949 VkResult
950 radv_image_create(VkDevice _device,
951 const struct radv_image_create_info *create_info,
952 const VkAllocationCallbacks* alloc,
953 VkImage *pImage)
954 {
955 RADV_FROM_HANDLE(radv_device, device, _device);
956 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
957 struct radv_image *image = NULL;
958 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
959
960 radv_assert(pCreateInfo->mipLevels > 0);
961 radv_assert(pCreateInfo->arrayLayers > 0);
962 radv_assert(pCreateInfo->samples > 0);
963 radv_assert(pCreateInfo->extent.width > 0);
964 radv_assert(pCreateInfo->extent.height > 0);
965 radv_assert(pCreateInfo->extent.depth > 0);
966
967 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
968 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
969 if (!image)
970 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
971
972 image->type = pCreateInfo->imageType;
973 image->info.width = pCreateInfo->extent.width;
974 image->info.height = pCreateInfo->extent.height;
975 image->info.depth = pCreateInfo->extent.depth;
976 image->info.samples = pCreateInfo->samples;
977 image->info.storage_samples = pCreateInfo->samples;
978 image->info.array_size = pCreateInfo->arrayLayers;
979 image->info.levels = pCreateInfo->mipLevels;
980 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
981
982 image->vk_format = pCreateInfo->format;
983 image->tiling = pCreateInfo->tiling;
984 image->usage = pCreateInfo->usage;
985 image->flags = pCreateInfo->flags;
986
987 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
988 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
989 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
990 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
991 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
992 else
993 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
994 }
995
996 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
997 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
998 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
999 image->info.surf_index = &device->image_mrt_offset_counter;
1000 }
1001
1002 radv_init_surface(device, image, &image->surface, create_info);
1003
1004 device->ws->surface_init(device->ws, &image->info, &image->surface);
1005
1006 image->size = image->surface.surf_size;
1007 image->alignment = image->surface.surf_alignment;
1008
1009 if (!create_info->no_metadata_planes) {
1010 /* Try to enable DCC first. */
1011 if (radv_image_can_enable_dcc(image)) {
1012 radv_image_alloc_dcc(image);
1013 if (image->info.samples > 1) {
1014 /* CMASK should be enabled because DCC fast
1015 * clear with MSAA needs it.
1016 */
1017 assert(radv_image_can_enable_cmask(image));
1018 radv_image_alloc_cmask(device, image);
1019 }
1020 } else {
1021 /* When DCC cannot be enabled, try CMASK. */
1022 image->surface.dcc_size = 0;
1023 if (radv_image_can_enable_cmask(image)) {
1024 radv_image_alloc_cmask(device, image);
1025 }
1026 }
1027
1028 /* Try to enable FMASK for multisampled images. */
1029 if (radv_image_can_enable_fmask(image)) {
1030 radv_image_alloc_fmask(device, image);
1031 } else {
1032 /* Otherwise, try to enable HTILE for depth surfaces. */
1033 if (radv_image_can_enable_htile(image) &&
1034 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1035 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1036 radv_image_alloc_htile(image);
1037 } else {
1038 image->surface.htile_size = 0;
1039 }
1040 }
1041 } else {
1042 image->surface.dcc_size = 0;
1043 image->surface.htile_size = 0;
1044 }
1045
1046 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1047 image->alignment = MAX2(image->alignment, 4096);
1048 image->size = align64(image->size, image->alignment);
1049 image->offset = 0;
1050
1051 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1052 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1053 if (!image->bo) {
1054 vk_free2(&device->alloc, alloc, image);
1055 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1056 }
1057 }
1058
1059 *pImage = radv_image_to_handle(image);
1060
1061 return VK_SUCCESS;
1062 }
1063
1064 static void
1065 radv_image_view_make_descriptor(struct radv_image_view *iview,
1066 struct radv_device *device,
1067 const VkComponentMapping *components,
1068 bool is_storage_image)
1069 {
1070 struct radv_image *image = iview->image;
1071 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1072 uint32_t blk_w;
1073 uint32_t *descriptor;
1074 uint32_t hw_level = 0;
1075
1076 if (is_storage_image) {
1077 descriptor = iview->storage_descriptor;
1078 } else {
1079 descriptor = iview->descriptor;
1080 }
1081
1082 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
1083 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
1084
1085 if (device->physical_device->rad_info.chip_class >= GFX9)
1086 hw_level = iview->base_mip;
1087 si_make_texture_descriptor(device, image, is_storage_image,
1088 iview->type,
1089 iview->vk_format,
1090 components,
1091 hw_level, hw_level + iview->level_count - 1,
1092 iview->base_layer,
1093 iview->base_layer + iview->layer_count - 1,
1094 iview->extent.width,
1095 iview->extent.height,
1096 iview->extent.depth,
1097 descriptor,
1098 descriptor + 8);
1099
1100 const struct legacy_surf_level *base_level_info = NULL;
1101 if (device->physical_device->rad_info.chip_class <= GFX9) {
1102 if (is_stencil)
1103 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1104 else
1105 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1106 }
1107 si_set_mutable_tex_desc_fields(device, image,
1108 base_level_info,
1109 iview->base_mip,
1110 iview->base_mip,
1111 blk_w, is_stencil, is_storage_image, descriptor);
1112 }
1113
1114 void
1115 radv_image_view_init(struct radv_image_view *iview,
1116 struct radv_device *device,
1117 const VkImageViewCreateInfo* pCreateInfo)
1118 {
1119 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1120 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1121
1122 switch (image->type) {
1123 case VK_IMAGE_TYPE_1D:
1124 case VK_IMAGE_TYPE_2D:
1125 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1126 break;
1127 case VK_IMAGE_TYPE_3D:
1128 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1129 <= radv_minify(image->info.depth, range->baseMipLevel));
1130 break;
1131 default:
1132 unreachable("bad VkImageType");
1133 }
1134 iview->image = image;
1135 iview->bo = image->bo;
1136 iview->type = pCreateInfo->viewType;
1137 iview->vk_format = pCreateInfo->format;
1138 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1139
1140 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1141 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1142 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1143 iview->vk_format = vk_format_depth_only(iview->vk_format);
1144 }
1145
1146 if (device->physical_device->rad_info.chip_class >= GFX9) {
1147 iview->extent = (VkExtent3D) {
1148 .width = image->info.width,
1149 .height = image->info.height,
1150 .depth = image->info.depth,
1151 };
1152 } else {
1153 iview->extent = (VkExtent3D) {
1154 .width = radv_minify(image->info.width , range->baseMipLevel),
1155 .height = radv_minify(image->info.height, range->baseMipLevel),
1156 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1157 };
1158 }
1159
1160 if (iview->vk_format != image->vk_format) {
1161 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1162 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1163 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1164 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1165
1166 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1167 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1168
1169 /* Comment ported from amdvlk -
1170 * If we have the following image:
1171 * Uncompressed pixels Compressed block sizes (4x4)
1172 * mip0: 22 x 22 6 x 6
1173 * mip1: 11 x 11 3 x 3
1174 * mip2: 5 x 5 2 x 2
1175 * mip3: 2 x 2 1 x 1
1176 * mip4: 1 x 1 1 x 1
1177 *
1178 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1179 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1180 * divide-by-two integer math):
1181 * mip0: 6x6
1182 * mip1: 3x3
1183 * mip2: 1x1
1184 * mip3: 1x1
1185 *
1186 * This means that mip2 will be missing texels.
1187 *
1188 * Fix this by calculating the base mip's width and height, then convert that, and round it
1189 * back up to get the level 0 size.
1190 * Clamp the converted size between the original values, and next power of two, which
1191 * means we don't oversize the image.
1192 */
1193 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1194 vk_format_is_compressed(image->vk_format) &&
1195 !vk_format_is_compressed(iview->vk_format)) {
1196 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1197 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1198
1199 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1200 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1201
1202 lvl_width <<= range->baseMipLevel;
1203 lvl_height <<= range->baseMipLevel;
1204
1205 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->surface.u.gfx9.surf_pitch);
1206 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->surface.u.gfx9.surf_height);
1207 }
1208 }
1209
1210 iview->base_layer = range->baseArrayLayer;
1211 iview->layer_count = radv_get_layerCount(image, range);
1212 iview->base_mip = range->baseMipLevel;
1213 iview->level_count = radv_get_levelCount(image, range);
1214
1215 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1216 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1217 }
1218
1219 bool radv_layout_has_htile(const struct radv_image *image,
1220 VkImageLayout layout,
1221 unsigned queue_mask)
1222 {
1223 if (radv_image_is_tc_compat_htile(image))
1224 return layout != VK_IMAGE_LAYOUT_GENERAL;
1225
1226 return radv_image_has_htile(image) &&
1227 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1228 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1229 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1230 }
1231
1232 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1233 VkImageLayout layout,
1234 unsigned queue_mask)
1235 {
1236 if (radv_image_is_tc_compat_htile(image))
1237 return layout != VK_IMAGE_LAYOUT_GENERAL;
1238
1239 return radv_image_has_htile(image) &&
1240 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1241 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1242 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1243 }
1244
1245 bool radv_layout_can_fast_clear(const struct radv_image *image,
1246 VkImageLayout layout,
1247 unsigned queue_mask)
1248 {
1249 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1250 }
1251
1252 bool radv_layout_dcc_compressed(const struct radv_image *image,
1253 VkImageLayout layout,
1254 unsigned queue_mask)
1255 {
1256 /* Don't compress compute transfer dst, as image stores are not supported. */
1257 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1258 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1259 return false;
1260
1261 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1262 }
1263
1264
1265 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1266 {
1267 if (!image->exclusive)
1268 return image->queue_family_mask;
1269 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1270 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1271 if (family == VK_QUEUE_FAMILY_IGNORED)
1272 return 1u << queue_family;
1273 return 1u << family;
1274 }
1275
1276 VkResult
1277 radv_CreateImage(VkDevice device,
1278 const VkImageCreateInfo *pCreateInfo,
1279 const VkAllocationCallbacks *pAllocator,
1280 VkImage *pImage)
1281 {
1282 #ifdef ANDROID
1283 const VkNativeBufferANDROID *gralloc_info =
1284 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1285
1286 if (gralloc_info)
1287 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1288 pAllocator, pImage);
1289 #endif
1290
1291 const struct wsi_image_create_info *wsi_info =
1292 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1293 bool scanout = wsi_info && wsi_info->scanout;
1294
1295 return radv_image_create(device,
1296 &(struct radv_image_create_info) {
1297 .vk_info = pCreateInfo,
1298 .scanout = scanout,
1299 },
1300 pAllocator,
1301 pImage);
1302 }
1303
1304 void
1305 radv_DestroyImage(VkDevice _device, VkImage _image,
1306 const VkAllocationCallbacks *pAllocator)
1307 {
1308 RADV_FROM_HANDLE(radv_device, device, _device);
1309 RADV_FROM_HANDLE(radv_image, image, _image);
1310
1311 if (!image)
1312 return;
1313
1314 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1315 device->ws->buffer_destroy(image->bo);
1316
1317 if (image->owned_memory != VK_NULL_HANDLE)
1318 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1319
1320 vk_free2(&device->alloc, pAllocator, image);
1321 }
1322
1323 void radv_GetImageSubresourceLayout(
1324 VkDevice _device,
1325 VkImage _image,
1326 const VkImageSubresource* pSubresource,
1327 VkSubresourceLayout* pLayout)
1328 {
1329 RADV_FROM_HANDLE(radv_image, image, _image);
1330 RADV_FROM_HANDLE(radv_device, device, _device);
1331 int level = pSubresource->mipLevel;
1332 int layer = pSubresource->arrayLayer;
1333 struct radeon_surf *surface = &image->surface;
1334
1335 if (device->physical_device->rad_info.chip_class >= GFX9) {
1336 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1337 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1338 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1339 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1340 pLayout->size = surface->u.gfx9.surf_slice_size;
1341 if (image->type == VK_IMAGE_TYPE_3D)
1342 pLayout->size *= u_minify(image->info.depth, level);
1343 } else {
1344 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1345 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1346 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1347 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1348 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1349 if (image->type == VK_IMAGE_TYPE_3D)
1350 pLayout->size *= u_minify(image->info.depth, level);
1351 }
1352 }
1353
1354
1355 VkResult
1356 radv_CreateImageView(VkDevice _device,
1357 const VkImageViewCreateInfo *pCreateInfo,
1358 const VkAllocationCallbacks *pAllocator,
1359 VkImageView *pView)
1360 {
1361 RADV_FROM_HANDLE(radv_device, device, _device);
1362 struct radv_image_view *view;
1363
1364 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1365 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1366 if (view == NULL)
1367 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1368
1369 radv_image_view_init(view, device, pCreateInfo);
1370
1371 *pView = radv_image_view_to_handle(view);
1372
1373 return VK_SUCCESS;
1374 }
1375
1376 void
1377 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1378 const VkAllocationCallbacks *pAllocator)
1379 {
1380 RADV_FROM_HANDLE(radv_device, device, _device);
1381 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1382
1383 if (!iview)
1384 return;
1385 vk_free2(&device->alloc, pAllocator, iview);
1386 }
1387
1388 void radv_buffer_view_init(struct radv_buffer_view *view,
1389 struct radv_device *device,
1390 const VkBufferViewCreateInfo* pCreateInfo)
1391 {
1392 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1393
1394 view->bo = buffer->bo;
1395 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1396 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1397 view->vk_format = pCreateInfo->format;
1398
1399 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1400 pCreateInfo->offset, view->range, view->state);
1401 }
1402
1403 VkResult
1404 radv_CreateBufferView(VkDevice _device,
1405 const VkBufferViewCreateInfo *pCreateInfo,
1406 const VkAllocationCallbacks *pAllocator,
1407 VkBufferView *pView)
1408 {
1409 RADV_FROM_HANDLE(radv_device, device, _device);
1410 struct radv_buffer_view *view;
1411
1412 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1413 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1414 if (!view)
1415 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1416
1417 radv_buffer_view_init(view, device, pCreateInfo);
1418
1419 *pView = radv_buffer_view_to_handle(view);
1420
1421 return VK_SUCCESS;
1422 }
1423
1424 void
1425 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1426 const VkAllocationCallbacks *pAllocator)
1427 {
1428 RADV_FROM_HANDLE(radv_device, device, _device);
1429 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1430
1431 if (!view)
1432 return;
1433
1434 vk_free2(&device->alloc, pAllocator, view);
1435 }