2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
88 if (pCreateInfo
->samples
>= 2 &&
89 (pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
||
90 (pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT
&&
91 device
->physical_device
->rad_info
.chip_class
== GFX10
)))
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
98 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
99 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
100 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
103 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
104 const struct VkImageFormatListCreateInfoKHR
*format_list
=
105 (const struct VkImageFormatListCreateInfoKHR
*)
106 vk_find_struct_const(pCreateInfo
->pNext
,
107 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
109 /* We have to ignore the existence of the list if viewFormatCount = 0 */
110 if (format_list
&& format_list
->viewFormatCount
) {
111 /* compatibility is transitive, so we only need to check
112 * one format with everything else.
114 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
115 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
118 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
130 radv_surface_has_scanout(struct radv_device
*device
, const struct radv_image_create_info
*info
)
135 if (!info
->bo_metadata
)
138 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
139 return info
->bo_metadata
->u
.gfx9
.swizzle_mode
== 0 || info
->bo_metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
141 return info
->bo_metadata
->u
.legacy
.scanout
;
146 radv_use_dcc_for_image(struct radv_device
*device
,
147 const struct radv_image
*image
,
148 const struct radv_image_create_info
*create_info
,
149 const VkImageCreateInfo
*pCreateInfo
)
151 bool dcc_compatible_formats
;
154 /* DCC (Delta Color Compression) is only available for GFX8+. */
155 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
158 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
161 if (image
->shareable
)
164 /* TODO: Enable DCC for storage images. */
165 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
166 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
169 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
172 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
173 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
176 /* TODO: Enable DCC for mipmaps on GFX9+. */
177 if ((pCreateInfo
->arrayLayers
> 1 || pCreateInfo
->mipLevels
> 1) &&
178 device
->physical_device
->rad_info
.chip_class
>= GFX9
)
181 /* Do not enable DCC for mipmapped arrays because performance is worse. */
182 if (pCreateInfo
->arrayLayers
> 1 && pCreateInfo
->mipLevels
> 1)
185 if (radv_surface_has_scanout(device
, create_info
))
188 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
189 * 2x can be enabled with an option.
191 if (pCreateInfo
->samples
> 2 ||
192 (pCreateInfo
->samples
== 2 &&
193 !device
->physical_device
->dcc_msaa_allowed
))
196 /* Determine if the formats are DCC compatible. */
197 dcc_compatible_formats
=
198 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
201 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
202 const struct VkImageFormatListCreateInfoKHR
*format_list
=
203 (const struct VkImageFormatListCreateInfoKHR
*)
204 vk_find_struct_const(pCreateInfo
->pNext
,
205 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
207 /* We have to ignore the existence of the list if viewFormatCount = 0 */
208 if (format_list
&& format_list
->viewFormatCount
) {
209 /* compatibility is transitive, so we only need to check
210 * one format with everything else. */
211 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
212 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
215 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
216 format_list
->pViewFormats
[i
]))
217 dcc_compatible_formats
= false;
220 dcc_compatible_formats
= false;
224 if (!dcc_compatible_formats
)
231 radv_use_tc_compat_cmask_for_image(struct radv_device
*device
,
232 struct radv_image
*image
)
234 if (!(device
->instance
->perftest_flags
& RADV_PERFTEST_TC_COMPAT_CMASK
))
237 /* TC-compat CMASK is only available for GFX8+. */
238 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
241 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
244 if (radv_image_has_dcc(image
))
247 if (!radv_image_has_cmask(image
))
254 radv_prefill_surface_from_metadata(struct radv_device
*device
,
255 struct radeon_surf
*surface
,
256 const struct radv_image_create_info
*create_info
)
258 const struct radeon_bo_metadata
*md
= create_info
->bo_metadata
;
259 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
260 if (md
->u
.gfx9
.swizzle_mode
> 0)
261 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
263 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
265 surface
->u
.gfx9
.surf
.swizzle_mode
= md
->u
.gfx9
.swizzle_mode
;
267 surface
->u
.legacy
.pipe_config
= md
->u
.legacy
.pipe_config
;
268 surface
->u
.legacy
.bankw
= md
->u
.legacy
.bankw
;
269 surface
->u
.legacy
.bankh
= md
->u
.legacy
.bankh
;
270 surface
->u
.legacy
.tile_split
= md
->u
.legacy
.tile_split
;
271 surface
->u
.legacy
.mtilea
= md
->u
.legacy
.mtilea
;
272 surface
->u
.legacy
.num_banks
= md
->u
.legacy
.num_banks
;
274 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
275 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
276 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
277 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
279 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
285 radv_init_surface(struct radv_device
*device
,
286 const struct radv_image
*image
,
287 struct radeon_surf
*surface
,
289 const struct radv_image_create_info
*create_info
)
291 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
292 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
293 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
294 const struct vk_format_description
*desc
= vk_format_description(format
);
295 bool is_depth
, is_stencil
;
297 is_depth
= vk_format_has_depth(desc
);
298 is_stencil
= vk_format_has_stencil(desc
);
300 surface
->blk_w
= vk_format_get_blockwidth(format
);
301 surface
->blk_h
= vk_format_get_blockheight(format
);
303 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
304 /* align byte per element on dword */
305 if (surface
->bpe
== 3) {
308 if (create_info
->bo_metadata
) {
309 radv_prefill_surface_from_metadata(device
, surface
, create_info
);
311 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
314 switch (pCreateInfo
->imageType
){
315 case VK_IMAGE_TYPE_1D
:
316 if (pCreateInfo
->arrayLayers
> 1)
317 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
319 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
321 case VK_IMAGE_TYPE_2D
:
322 if (pCreateInfo
->arrayLayers
> 1)
323 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
325 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
327 case VK_IMAGE_TYPE_3D
:
328 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
331 unreachable("unhandled image type");
335 surface
->flags
|= RADEON_SURF_ZBUFFER
;
336 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
337 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
341 surface
->flags
|= RADEON_SURF_SBUFFER
;
343 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
344 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
345 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
346 vk_format_is_compressed(pCreateInfo
->format
))
347 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
349 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
351 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
352 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
354 if (radv_surface_has_scanout(device
, create_info
))
355 surface
->flags
|= RADEON_SURF_SCANOUT
;
360 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
362 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
365 static inline unsigned
366 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
369 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
371 return plane
->surface
.u
.legacy
.tiling_index
[level
];
374 static unsigned radv_map_swizzle(unsigned swizzle
)
378 return V_008F0C_SQ_SEL_Y
;
380 return V_008F0C_SQ_SEL_Z
;
382 return V_008F0C_SQ_SEL_W
;
384 return V_008F0C_SQ_SEL_0
;
386 return V_008F0C_SQ_SEL_1
;
387 default: /* VK_SWIZZLE_X */
388 return V_008F0C_SQ_SEL_X
;
393 radv_make_buffer_descriptor(struct radv_device
*device
,
394 struct radv_buffer
*buffer
,
400 const struct vk_format_description
*desc
;
402 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
403 uint64_t va
= gpu_address
+ buffer
->offset
;
404 unsigned num_format
, data_format
;
406 desc
= vk_format_description(vk_format
);
407 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
408 stride
= desc
->block
.bits
/ 8;
412 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
413 S_008F04_STRIDE(stride
);
415 if (device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
) {
420 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
421 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
422 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
423 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3]));
425 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
426 const struct gfx10_format
*fmt
= &gfx10_format_table
[vk_format
];
428 /* OOB_SELECT chooses the out-of-bounds check:
429 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
430 * - 1: index >= NUM_RECORDS
431 * - 2: NUM_RECORDS == 0
432 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
433 * else: swizzle_address >= NUM_RECORDS
435 state
[3] |= S_008F0C_FORMAT(fmt
->img_format
) |
436 S_008F0C_OOB_SELECT(0) |
437 S_008F0C_RESOURCE_LEVEL(1);
439 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
440 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
442 assert(data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
);
443 assert(num_format
!= ~0);
445 state
[3] |= S_008F0C_NUM_FORMAT(num_format
) |
446 S_008F0C_DATA_FORMAT(data_format
);
451 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
452 struct radv_image
*image
,
453 const struct legacy_surf_level
*base_level_info
,
455 unsigned base_level
, unsigned first_level
,
456 unsigned block_width
, bool is_stencil
,
457 bool is_storage_image
, uint32_t *state
)
459 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
460 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
461 uint64_t va
= gpu_address
+ plane
->offset
;
462 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
463 uint64_t meta_va
= 0;
464 if (chip_class
>= GFX9
) {
466 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
468 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
470 va
+= base_level_info
->offset
;
473 if (chip_class
>= GFX9
||
474 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
475 state
[0] |= plane
->surface
.tile_swizzle
;
476 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
477 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
479 if (chip_class
>= GFX8
) {
480 state
[6] &= C_008F28_COMPRESSION_EN
;
482 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
483 meta_va
= gpu_address
+ image
->dcc_offset
;
484 if (chip_class
<= GFX8
)
485 meta_va
+= base_level_info
->dcc_offset
;
486 } else if (!is_storage_image
&&
487 radv_image_is_tc_compat_htile(image
)) {
488 meta_va
= gpu_address
+ image
->htile_offset
;
492 state
[6] |= S_008F28_COMPRESSION_EN(1);
493 if (chip_class
<= GFX9
) {
494 state
[7] = meta_va
>> 8;
495 state
[7] |= plane
->surface
.tile_swizzle
;
500 if (chip_class
>= GFX10
) {
501 state
[3] &= C_00A00C_SW_MODE
;
504 state
[3] |= S_00A00C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
506 state
[3] |= S_00A00C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
509 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
&
510 C_00A018_META_PIPE_ALIGNED
;
513 struct gfx9_surf_meta_flags meta
;
515 if (image
->dcc_offset
)
516 meta
= plane
->surface
.u
.gfx9
.dcc
;
518 meta
= plane
->surface
.u
.gfx9
.htile
;
520 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
521 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
524 state
[7] = meta_va
>> 16;
525 } else if (chip_class
== GFX9
) {
526 state
[3] &= C_008F1C_SW_MODE
;
527 state
[4] &= C_008F20_PITCH
;
530 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
531 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.stencil
.epitch
);
533 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
534 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.surf
.epitch
);
537 state
[5] &= C_008F24_META_DATA_ADDRESS
&
538 C_008F24_META_PIPE_ALIGNED
&
539 C_008F24_META_RB_ALIGNED
;
541 struct gfx9_surf_meta_flags meta
;
543 if (image
->dcc_offset
)
544 meta
= plane
->surface
.u
.gfx9
.dcc
;
546 meta
= plane
->surface
.u
.gfx9
.htile
;
548 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
549 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
550 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
554 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
555 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
557 state
[3] &= C_008F1C_TILING_INDEX
;
558 state
[3] |= S_008F1C_TILING_INDEX(index
);
559 state
[4] &= C_008F20_PITCH
;
560 state
[4] |= S_008F20_PITCH(pitch
- 1);
564 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
565 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
567 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
568 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
570 /* GFX9 allocates 1D textures as 2D. */
571 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
572 image_type
= VK_IMAGE_TYPE_2D
;
573 switch (image_type
) {
574 case VK_IMAGE_TYPE_1D
:
575 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
576 case VK_IMAGE_TYPE_2D
:
578 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
580 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
581 case VK_IMAGE_TYPE_3D
:
582 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
583 return V_008F1C_SQ_RSRC_IMG_3D
;
585 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
587 unreachable("illegal image type");
591 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
593 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
595 if (swizzle
[3] == VK_SWIZZLE_X
) {
596 /* For the pre-defined border color values (white, opaque
597 * black, transparent black), the only thing that matters is
598 * that the alpha channel winds up in the correct place
599 * (because the RGB channels are all the same) so either of
600 * these enumerations will work.
602 if (swizzle
[2] == VK_SWIZZLE_Y
)
603 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
605 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
606 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
607 if (swizzle
[1] == VK_SWIZZLE_Y
)
608 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
610 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
611 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
612 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
613 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
614 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
620 static bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
)
622 const struct vk_format_description
*desc
= vk_format_description(format
);
624 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&& desc
->nr_channels
== 1)
625 return desc
->swizzle
[3] == VK_SWIZZLE_X
;
627 return radv_translate_colorswap(format
, false) <= 1;
630 * Build the sampler view descriptor for a texture (GFX10).
633 gfx10_make_texture_descriptor(struct radv_device
*device
,
634 struct radv_image
*image
,
635 bool is_storage_image
,
636 VkImageViewType view_type
,
638 const VkComponentMapping
*mapping
,
639 unsigned first_level
, unsigned last_level
,
640 unsigned first_layer
, unsigned last_layer
,
641 unsigned width
, unsigned height
, unsigned depth
,
643 uint32_t *fmask_state
)
645 const struct vk_format_description
*desc
;
646 enum vk_swizzle swizzle
[4];
650 desc
= vk_format_description(vk_format
);
651 img_format
= gfx10_format_table
[vk_format
].img_format
;
653 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
654 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
655 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
657 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
660 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
661 is_storage_image
, device
->physical_device
->rad_info
.chip_class
== GFX9
);
662 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
664 depth
= image
->info
.array_size
;
665 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
666 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
667 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
668 depth
= image
->info
.array_size
;
669 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
670 depth
= image
->info
.array_size
/ 6;
673 state
[1] = S_00A004_FORMAT(img_format
) |
674 S_00A004_WIDTH_LO(width
- 1);
675 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
676 S_00A008_HEIGHT(height
- 1) |
677 S_00A008_RESOURCE_LEVEL(1);
678 state
[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
679 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
680 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
681 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
682 S_00A00C_BASE_LEVEL(image
->info
.samples
> 1 ?
684 S_00A00C_LAST_LEVEL(image
->info
.samples
> 1 ?
685 util_logbase2(image
->info
.samples
) :
687 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle
)) |
689 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
690 * to know the total number of layers.
692 state
[4] = S_00A010_DEPTH(type
== V_008F1C_SQ_RSRC_IMG_3D
? depth
- 1 : last_layer
) |
693 S_00A010_BASE_ARRAY(first_layer
);
694 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
)) |
695 S_00A014_MAX_MIP(image
->info
.samples
> 1 ?
696 util_logbase2(image
->info
.samples
) :
697 image
->info
.levels
- 1) |
698 S_00A014_PERF_MOD(4);
702 if (radv_dcc_enabled(image
, first_level
)) {
703 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
704 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
705 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device
, vk_format
));
708 /* Initialize the sampler view for FMASK. */
709 if (radv_image_has_fmask(image
)) {
710 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
714 assert(image
->plane_count
== 1);
716 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
718 switch (image
->info
.samples
) {
720 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
723 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
726 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
729 unreachable("invalid nr_samples");
732 fmask_state
[0] = (va
>> 8) | image
->planes
[0].surface
.fmask_tile_swizzle
;
733 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
734 S_00A004_FORMAT(format
) |
735 S_00A004_WIDTH_LO(width
- 1);
736 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
737 S_00A008_HEIGHT(height
- 1) |
738 S_00A008_RESOURCE_LEVEL(1);
739 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
740 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
741 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
742 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
743 S_00A00C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
) |
744 S_00A00C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
745 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
746 S_00A010_BASE_ARRAY(first_layer
);
748 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
);
750 } else if (fmask_state
)
751 memset(fmask_state
, 0, 8 * 4);
755 * Build the sampler view descriptor for a texture (SI-GFX9)
758 si_make_texture_descriptor(struct radv_device
*device
,
759 struct radv_image
*image
,
760 bool is_storage_image
,
761 VkImageViewType view_type
,
763 const VkComponentMapping
*mapping
,
764 unsigned first_level
, unsigned last_level
,
765 unsigned first_layer
, unsigned last_layer
,
766 unsigned width
, unsigned height
, unsigned depth
,
768 uint32_t *fmask_state
)
770 const struct vk_format_description
*desc
;
771 enum vk_swizzle swizzle
[4];
773 unsigned num_format
, data_format
, type
;
775 desc
= vk_format_description(vk_format
);
777 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
778 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
779 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
781 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
784 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
786 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
787 if (num_format
== ~0) {
791 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
792 if (data_format
== ~0) {
796 /* S8 with either Z16 or Z32 HTILE need a special format. */
797 if (device
->physical_device
->rad_info
.chip_class
== GFX9
&&
798 vk_format
== VK_FORMAT_S8_UINT
&&
799 radv_image_is_tc_compat_htile(image
)) {
800 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
801 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
802 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
803 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
805 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
806 is_storage_image
, device
->physical_device
->rad_info
.chip_class
== GFX9
);
807 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
809 depth
= image
->info
.array_size
;
810 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
811 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
812 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
813 depth
= image
->info
.array_size
;
814 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
815 depth
= image
->info
.array_size
/ 6;
818 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
819 S_008F14_NUM_FORMAT(num_format
));
820 state
[2] = (S_008F18_WIDTH(width
- 1) |
821 S_008F18_HEIGHT(height
- 1) |
822 S_008F18_PERF_MOD(4));
823 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
824 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
825 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
826 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
827 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
829 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
830 util_logbase2(image
->info
.samples
) :
832 S_008F1C_TYPE(type
));
834 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
838 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
839 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
841 /* Depth is the last accessible layer on Gfx9.
842 * The hw doesn't need to know the total number of layers.
844 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
845 state
[4] |= S_008F20_DEPTH(depth
- 1);
847 state
[4] |= S_008F20_DEPTH(last_layer
);
849 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
850 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
851 util_logbase2(image
->info
.samples
) :
852 image
->info
.levels
- 1);
854 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
855 state
[4] |= S_008F20_DEPTH(depth
- 1);
856 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
858 if (image
->dcc_offset
) {
859 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device
, vk_format
));
861 /* The last dword is unused by hw. The shader uses it to clear
862 * bits in the first dword of sampler state.
864 if (device
->physical_device
->rad_info
.chip_class
<= GFX7
&& image
->info
.samples
<= 1) {
865 if (first_level
== last_level
)
866 state
[7] = C_008F30_MAX_ANISO_RATIO
;
868 state
[7] = 0xffffffff;
872 /* Initialize the sampler view for FMASK. */
873 if (radv_image_has_fmask(image
)) {
874 uint32_t fmask_format
, num_format
;
875 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
878 assert(image
->plane_count
== 1);
880 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
882 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
883 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
884 switch (image
->info
.samples
) {
886 num_format
= V_008F14_IMG_FMASK_8_2_2
;
889 num_format
= V_008F14_IMG_FMASK_8_4_4
;
892 num_format
= V_008F14_IMG_FMASK_32_8_8
;
895 unreachable("invalid nr_samples");
898 switch (image
->info
.samples
) {
900 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
903 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
906 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
910 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
912 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
915 fmask_state
[0] = va
>> 8;
916 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
917 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
918 S_008F14_DATA_FORMAT(fmask_format
) |
919 S_008F14_NUM_FORMAT(num_format
);
920 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
921 S_008F18_HEIGHT(height
- 1);
922 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
923 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
924 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
925 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
926 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
928 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
932 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
933 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
934 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
935 S_008F20_PITCH(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
936 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
937 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
939 if (radv_image_is_tc_compat_cmask(image
)) {
940 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
942 fmask_state
[5] |= S_008F24_META_DATA_ADDRESS(va
>> 40);
943 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
944 fmask_state
[7] |= va
>> 8;
947 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
948 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
949 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
950 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
952 if (radv_image_is_tc_compat_cmask(image
)) {
953 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
955 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
956 fmask_state
[7] |= va
>> 8;
959 } else if (fmask_state
)
960 memset(fmask_state
, 0, 8 * 4);
964 radv_make_texture_descriptor(struct radv_device
*device
,
965 struct radv_image
*image
,
966 bool is_storage_image
,
967 VkImageViewType view_type
,
969 const VkComponentMapping
*mapping
,
970 unsigned first_level
, unsigned last_level
,
971 unsigned first_layer
, unsigned last_layer
,
972 unsigned width
, unsigned height
, unsigned depth
,
974 uint32_t *fmask_state
)
976 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
977 gfx10_make_texture_descriptor(device
, image
, is_storage_image
,
978 view_type
, vk_format
, mapping
,
979 first_level
, last_level
,
980 first_layer
, last_layer
,
981 width
, height
, depth
,
984 si_make_texture_descriptor(device
, image
, is_storage_image
,
985 view_type
, vk_format
, mapping
,
986 first_level
, last_level
,
987 first_layer
, last_layer
,
988 width
, height
, depth
,
994 radv_query_opaque_metadata(struct radv_device
*device
,
995 struct radv_image
*image
,
996 struct radeon_bo_metadata
*md
)
998 static const VkComponentMapping fixedmapping
;
1001 assert(image
->plane_count
== 1);
1003 /* Metadata image format format version 1:
1004 * [0] = 1 (metadata format identifier)
1005 * [1] = (VENDOR_ID << 16) | PCI_ID
1006 * [2:9] = image descriptor for the whole resource
1007 * [2] is always 0, because the base address is cleared
1008 * [9] is the DCC offset bits [39:8] from the beginning of
1010 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1012 md
->metadata
[0] = 1; /* metadata image format version 1 */
1014 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1015 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
1018 radv_make_texture_descriptor(device
, image
, false,
1019 (VkImageViewType
)image
->type
, image
->vk_format
,
1020 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
1021 image
->info
.array_size
- 1,
1022 image
->info
.width
, image
->info
.height
,
1026 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
1027 image
->planes
[0].surface
.blk_w
, false, false, desc
);
1029 /* Clear the base address and set the relative DCC offset. */
1031 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
1032 desc
[7] = image
->dcc_offset
>> 8;
1034 /* Dwords [2:9] contain the image descriptor. */
1035 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
1037 /* Dwords [10:..] contain the mipmap level offsets. */
1038 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
1039 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
1040 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
1041 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
1046 radv_init_metadata(struct radv_device
*device
,
1047 struct radv_image
*image
,
1048 struct radeon_bo_metadata
*metadata
)
1050 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
1052 memset(metadata
, 0, sizeof(*metadata
));
1054 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1055 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
1057 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
1058 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
1059 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
1060 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
1061 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
1062 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
1063 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
1064 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
1065 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
1066 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
1067 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
1068 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
1070 radv_query_opaque_metadata(device
, image
, metadata
);
1074 radv_image_override_offset_stride(struct radv_device
*device
,
1075 struct radv_image
*image
,
1076 uint64_t offset
, uint32_t stride
)
1078 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
1079 unsigned bpe
= vk_format_get_blocksizebits(image
->vk_format
) / 8;
1081 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1083 surface
->u
.gfx9
.surf_pitch
= stride
;
1084 surface
->u
.gfx9
.surf_slice_size
=
1085 (uint64_t)stride
* surface
->u
.gfx9
.surf_height
* bpe
;
1087 surface
->u
.gfx9
.surf_offset
= offset
;
1089 surface
->u
.legacy
.level
[0].nblk_x
= stride
;
1090 surface
->u
.legacy
.level
[0].slice_size_dw
=
1091 ((uint64_t)stride
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
1094 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
1095 surface
->u
.legacy
.level
[i
].offset
+= offset
;
1101 /* The number of samples can be specified independently of the texture. */
1103 radv_image_get_fmask_info(struct radv_device
*device
,
1104 struct radv_image
*image
,
1105 unsigned nr_samples
,
1106 struct radv_fmask_info
*out
)
1108 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1109 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
1110 out
->size
= image
->planes
[0].surface
.fmask_size
;
1111 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
1115 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
1116 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
1117 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
1118 out
->slice_size
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_size
;
1119 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
1120 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
1121 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
1122 out
->size
= image
->planes
[0].surface
.fmask_size
;
1124 assert(!out
->tile_swizzle
|| !image
->shareable
);
1128 radv_image_alloc_fmask(struct radv_device
*device
,
1129 struct radv_image
*image
)
1131 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
1133 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
1134 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
1135 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
1139 radv_image_get_cmask_info(struct radv_device
*device
,
1140 struct radv_image
*image
,
1141 struct radv_cmask_info
*out
)
1143 assert(image
->plane_count
== 1);
1145 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1146 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
1147 out
->size
= image
->planes
[0].surface
.cmask_size
;
1151 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.cmask_slice_tile_max
;
1152 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
1153 out
->slice_size
= image
->planes
[0].surface
.cmask_slice_size
;
1154 out
->size
= image
->planes
[0].surface
.cmask_size
;
1158 radv_image_alloc_cmask(struct radv_device
*device
,
1159 struct radv_image
*image
)
1161 uint32_t clear_value_size
= 0;
1162 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
1164 if (!image
->cmask
.size
)
1167 assert(image
->cmask
.alignment
);
1169 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
1170 /* + 8 for storing the clear values */
1171 if (!image
->clear_value_offset
) {
1172 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
1173 clear_value_size
= 8;
1175 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
1176 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
1180 radv_image_alloc_dcc(struct radv_image
*image
)
1182 assert(image
->plane_count
== 1);
1184 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
1185 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1186 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
1187 image
->fce_pred_offset
= image
->clear_value_offset
+ 8 * image
->info
.levels
;
1188 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16 * image
->info
.levels
;
1189 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24 * image
->info
.levels
;
1190 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
1194 radv_image_alloc_htile(struct radv_device
*device
, struct radv_image
*image
)
1196 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
1198 /* + 8 for storing the clear values */
1199 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
1200 image
->size
= image
->clear_value_offset
+ 8;
1201 if (radv_image_is_tc_compat_htile(image
) &&
1202 device
->physical_device
->has_tc_compat_zrange_bug
) {
1203 /* Metadata for the TC-compatible HTILE hardware bug which
1204 * have to be fixed by updating ZRANGE_PRECISION when doing
1205 * fast depth clears to 0.0f.
1207 image
->tc_compat_zrange_offset
= image
->size
;
1208 image
->size
= image
->tc_compat_zrange_offset
+ 4;
1210 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
1214 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
1216 if (image
->info
.samples
<= 1 &&
1217 image
->info
.width
* image
->info
.height
<= 512 * 512) {
1218 /* Do not enable CMASK or DCC for small surfaces where the cost
1219 * of the eliminate pass can be higher than the benefit of fast
1220 * clear. RadeonSI does this, but the image threshold is
1226 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
1227 (image
->exclusive
|| image
->queue_family_mask
== 1);
1231 radv_image_can_enable_dcc(struct radv_device
*device
, struct radv_image
*image
)
1233 if (!radv_image_can_enable_dcc_or_cmask(image
) ||
1234 !radv_image_has_dcc(image
))
1237 /* On GFX8, DCC layers can be interleaved and it's currently only
1238 * enabled if slice size is equal to the per slice fast clear size
1239 * because the driver assumes that portions of multiple layers are
1240 * contiguous during fast clears.
1242 if (image
->info
.array_size
> 1) {
1243 const struct legacy_surf_level
*surf_level
=
1244 &image
->planes
[0].surface
.u
.legacy
.level
[0];
1246 assert(device
->physical_device
->rad_info
.chip_class
== GFX8
);
1248 if (image
->planes
[0].surface
.dcc_slice_size
!= surf_level
->dcc_fast_clear_size
)
1256 radv_image_can_enable_cmask(struct radv_image
*image
)
1258 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
1259 /* Do not enable CMASK for non-MSAA images (fast color clear)
1260 * because 128 bit formats are not supported, but FMASK might
1266 return radv_image_can_enable_dcc_or_cmask(image
) &&
1267 image
->info
.levels
== 1 &&
1268 image
->info
.depth
== 1 &&
1269 !image
->planes
[0].surface
.is_linear
;
1273 radv_image_can_enable_fmask(struct radv_image
*image
)
1275 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
1279 radv_image_can_enable_htile(struct radv_image
*image
)
1281 return radv_image_has_htile(image
) &&
1282 image
->info
.levels
== 1 &&
1283 image
->info
.width
* image
->info
.height
>= 8 * 8;
1286 static void radv_image_disable_dcc(struct radv_image
*image
)
1288 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1289 image
->planes
[i
].surface
.dcc_size
= 0;
1292 static void radv_image_disable_htile(struct radv_image
*image
)
1294 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1295 image
->planes
[i
].surface
.htile_size
= 0;
1299 radv_image_create(VkDevice _device
,
1300 const struct radv_image_create_info
*create_info
,
1301 const VkAllocationCallbacks
* alloc
,
1304 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1305 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
1306 struct radv_image
*image
= NULL
;
1307 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
1309 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
1310 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
1312 radv_assert(pCreateInfo
->mipLevels
> 0);
1313 radv_assert(pCreateInfo
->arrayLayers
> 0);
1314 radv_assert(pCreateInfo
->samples
> 0);
1315 radv_assert(pCreateInfo
->extent
.width
> 0);
1316 radv_assert(pCreateInfo
->extent
.height
> 0);
1317 radv_assert(pCreateInfo
->extent
.depth
> 0);
1319 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
1320 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1322 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1324 image
->type
= pCreateInfo
->imageType
;
1325 image
->info
.width
= pCreateInfo
->extent
.width
;
1326 image
->info
.height
= pCreateInfo
->extent
.height
;
1327 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1328 image
->info
.samples
= pCreateInfo
->samples
;
1329 image
->info
.storage_samples
= pCreateInfo
->samples
;
1330 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1331 image
->info
.levels
= pCreateInfo
->mipLevels
;
1332 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1334 image
->vk_format
= pCreateInfo
->format
;
1335 image
->tiling
= pCreateInfo
->tiling
;
1336 image
->usage
= pCreateInfo
->usage
;
1337 image
->flags
= pCreateInfo
->flags
;
1339 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1340 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1341 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1342 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
||
1343 pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_FOREIGN_EXT
)
1344 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1346 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1349 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1350 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1351 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) &&
1352 !radv_surface_has_scanout(device
, create_info
) && !image
->shareable
) {
1353 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1356 image
->plane_count
= plane_count
;
1358 image
->alignment
= 1;
1359 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1360 struct ac_surf_info info
= image
->info
;
1361 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1364 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1365 assert(info
.width
% desc
->width_divisor
== 0);
1366 assert(info
.height
% desc
->height_divisor
== 0);
1368 info
.width
/= desc
->width_divisor
;
1369 info
.height
/= desc
->height_divisor
;
1372 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1374 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1375 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1376 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1378 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1381 if (!create_info
->no_metadata_planes
) {
1382 /* Try to enable DCC first. */
1383 if (radv_image_can_enable_dcc(device
, image
)) {
1384 radv_image_alloc_dcc(image
);
1385 if (image
->info
.samples
> 1) {
1386 /* CMASK should be enabled because DCC fast
1387 * clear with MSAA needs it.
1389 assert(radv_image_can_enable_cmask(image
));
1390 radv_image_alloc_cmask(device
, image
);
1393 /* When DCC cannot be enabled, try CMASK. */
1394 radv_image_disable_dcc(image
);
1395 if (radv_image_can_enable_cmask(image
)) {
1396 radv_image_alloc_cmask(device
, image
);
1400 /* Try to enable FMASK for multisampled images. */
1401 if (radv_image_can_enable_fmask(image
)) {
1402 radv_image_alloc_fmask(device
, image
);
1404 if (radv_use_tc_compat_cmask_for_image(device
, image
))
1405 image
->tc_compatible_cmask
= true;
1407 /* Otherwise, try to enable HTILE for depth surfaces. */
1408 if (radv_image_can_enable_htile(image
) &&
1409 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1410 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1411 radv_image_alloc_htile(device
, image
);
1413 radv_image_disable_htile(image
);
1417 radv_image_disable_dcc(image
);
1418 radv_image_disable_htile(image
);
1421 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1422 image
->alignment
= MAX2(image
->alignment
, 4096);
1423 image
->size
= align64(image
->size
, image
->alignment
);
1426 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1427 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1429 vk_free2(&device
->alloc
, alloc
, image
);
1430 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1434 *pImage
= radv_image_to_handle(image
);
1440 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1441 struct radv_device
*device
,
1443 const VkComponentMapping
*components
,
1444 bool is_storage_image
, unsigned plane_id
,
1445 unsigned descriptor_plane_id
)
1447 struct radv_image
*image
= iview
->image
;
1448 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1449 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1450 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1452 union radv_descriptor
*descriptor
;
1453 uint32_t hw_level
= 0;
1455 if (is_storage_image
) {
1456 descriptor
= &iview
->storage_descriptor
;
1458 descriptor
= &iview
->descriptor
;
1461 assert(vk_format_get_plane_count(vk_format
) == 1);
1462 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1463 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1465 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1466 hw_level
= iview
->base_mip
;
1467 radv_make_texture_descriptor(device
, image
, is_storage_image
,
1471 hw_level
, hw_level
+ iview
->level_count
- 1,
1473 iview
->base_layer
+ iview
->layer_count
- 1,
1474 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1475 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1476 iview
->extent
.depth
,
1477 descriptor
->plane_descriptors
[descriptor_plane_id
],
1478 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1480 const struct legacy_surf_level
*base_level_info
= NULL
;
1481 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1483 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1485 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1487 si_set_mutable_tex_desc_fields(device
, image
,
1492 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1496 radv_plane_from_aspect(VkImageAspectFlags mask
)
1499 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1501 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1509 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1512 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1513 return image
->planes
[0].format
;
1514 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1515 return image
->planes
[1].format
;
1516 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1517 return image
->planes
[2].format
;
1518 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1519 return vk_format_stencil_only(image
->vk_format
);
1520 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1521 return vk_format_depth_only(image
->vk_format
);
1522 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1523 return vk_format_depth_only(image
->vk_format
);
1525 return image
->vk_format
;
1530 radv_image_view_init(struct radv_image_view
*iview
,
1531 struct radv_device
*device
,
1532 const VkImageViewCreateInfo
* pCreateInfo
)
1534 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1535 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1537 switch (image
->type
) {
1538 case VK_IMAGE_TYPE_1D
:
1539 case VK_IMAGE_TYPE_2D
:
1540 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1542 case VK_IMAGE_TYPE_3D
:
1543 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1544 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1547 unreachable("bad VkImageType");
1549 iview
->image
= image
;
1550 iview
->bo
= image
->bo
;
1551 iview
->type
= pCreateInfo
->viewType
;
1552 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1553 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1554 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1555 iview
->vk_format
= pCreateInfo
->format
;
1557 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1558 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1559 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1560 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1563 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1564 iview
->extent
= (VkExtent3D
) {
1565 .width
= image
->info
.width
,
1566 .height
= image
->info
.height
,
1567 .depth
= image
->info
.depth
,
1570 iview
->extent
= (VkExtent3D
) {
1571 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1572 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1573 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1577 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1578 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1579 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1580 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1581 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1583 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1584 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1586 /* Comment ported from amdvlk -
1587 * If we have the following image:
1588 * Uncompressed pixels Compressed block sizes (4x4)
1589 * mip0: 22 x 22 6 x 6
1590 * mip1: 11 x 11 3 x 3
1595 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1596 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1597 * divide-by-two integer math):
1603 * This means that mip2 will be missing texels.
1605 * Fix this by calculating the base mip's width and height, then convert that, and round it
1606 * back up to get the level 0 size.
1607 * Clamp the converted size between the original values, and next power of two, which
1608 * means we don't oversize the image.
1610 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1611 vk_format_is_compressed(image
->vk_format
) &&
1612 !vk_format_is_compressed(iview
->vk_format
)) {
1613 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1614 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1616 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1617 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1619 lvl_width
<<= range
->baseMipLevel
;
1620 lvl_height
<<= range
->baseMipLevel
;
1622 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1623 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1627 iview
->base_layer
= range
->baseArrayLayer
;
1628 iview
->layer_count
= radv_get_layerCount(image
, range
);
1629 iview
->base_mip
= range
->baseMipLevel
;
1630 iview
->level_count
= radv_get_levelCount(image
, range
);
1632 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1633 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1634 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1635 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1639 bool radv_layout_has_htile(const struct radv_image
*image
,
1640 VkImageLayout layout
,
1641 unsigned queue_mask
)
1643 if (radv_image_is_tc_compat_htile(image
))
1644 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1646 return radv_image_has_htile(image
) &&
1647 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1648 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1649 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1652 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1653 VkImageLayout layout
,
1654 unsigned queue_mask
)
1656 if (radv_image_is_tc_compat_htile(image
))
1657 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1659 return radv_image_has_htile(image
) &&
1660 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1661 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1662 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1665 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1666 VkImageLayout layout
,
1667 unsigned queue_mask
)
1669 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1672 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1673 VkImageLayout layout
,
1674 unsigned queue_mask
)
1676 /* Don't compress compute transfer dst, as image stores are not supported. */
1677 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1678 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1681 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1685 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1687 if (!image
->exclusive
)
1688 return image
->queue_family_mask
;
1689 if (family
== VK_QUEUE_FAMILY_EXTERNAL
||
1690 family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
1691 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1692 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1693 return 1u << queue_family
;
1694 return 1u << family
;
1698 radv_CreateImage(VkDevice device
,
1699 const VkImageCreateInfo
*pCreateInfo
,
1700 const VkAllocationCallbacks
*pAllocator
,
1704 const VkNativeBufferANDROID
*gralloc_info
=
1705 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1708 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1709 pAllocator
, pImage
);
1712 const struct wsi_image_create_info
*wsi_info
=
1713 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1714 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1716 return radv_image_create(device
,
1717 &(struct radv_image_create_info
) {
1718 .vk_info
= pCreateInfo
,
1726 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1727 const VkAllocationCallbacks
*pAllocator
)
1729 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1730 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1735 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1736 device
->ws
->buffer_destroy(image
->bo
);
1738 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1739 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1741 vk_free2(&device
->alloc
, pAllocator
, image
);
1744 void radv_GetImageSubresourceLayout(
1747 const VkImageSubresource
* pSubresource
,
1748 VkSubresourceLayout
* pLayout
)
1750 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1751 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1752 int level
= pSubresource
->mipLevel
;
1753 int layer
= pSubresource
->arrayLayer
;
1755 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1757 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1758 struct radeon_surf
*surface
= &plane
->surface
;
1760 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1761 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1762 if (image
->vk_format
== VK_FORMAT_R32G32B32_UINT
||
1763 image
->vk_format
== VK_FORMAT_R32G32B32_SINT
||
1764 image
->vk_format
== VK_FORMAT_R32G32B32_SFLOAT
) {
1765 /* Adjust the number of bytes between each row because
1766 * the pitch is actually the number of components per
1769 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
/ 3;
1771 assert(util_is_power_of_two_nonzero(surface
->bpe
));
1772 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1775 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1776 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1777 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1778 if (image
->type
== VK_IMAGE_TYPE_3D
)
1779 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1781 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1782 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1783 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1784 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1785 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1786 if (image
->type
== VK_IMAGE_TYPE_3D
)
1787 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1793 radv_CreateImageView(VkDevice _device
,
1794 const VkImageViewCreateInfo
*pCreateInfo
,
1795 const VkAllocationCallbacks
*pAllocator
,
1798 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1799 struct radv_image_view
*view
;
1801 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1802 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1804 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1806 radv_image_view_init(view
, device
, pCreateInfo
);
1808 *pView
= radv_image_view_to_handle(view
);
1814 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1815 const VkAllocationCallbacks
*pAllocator
)
1817 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1818 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1822 vk_free2(&device
->alloc
, pAllocator
, iview
);
1825 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1826 struct radv_device
*device
,
1827 const VkBufferViewCreateInfo
* pCreateInfo
)
1829 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1831 view
->bo
= buffer
->bo
;
1832 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1833 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1834 view
->vk_format
= pCreateInfo
->format
;
1836 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1837 pCreateInfo
->offset
, view
->range
, view
->state
);
1841 radv_CreateBufferView(VkDevice _device
,
1842 const VkBufferViewCreateInfo
*pCreateInfo
,
1843 const VkAllocationCallbacks
*pAllocator
,
1844 VkBufferView
*pView
)
1846 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1847 struct radv_buffer_view
*view
;
1849 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1850 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1852 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1854 radv_buffer_view_init(view
, device
, pCreateInfo
);
1856 *pView
= radv_buffer_view_to_handle(view
);
1862 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1863 const VkAllocationCallbacks
*pAllocator
)
1865 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1866 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1871 vk_free2(&device
->alloc
, pAllocator
, view
);