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radv: only account for tile_swizzle for color surfaces with DCC
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
87 */
88 if (pCreateInfo->samples >= 2 &&
89 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
90 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT &&
91 device->physical_device->rad_info.chip_class == GFX10)))
92 return false;
93
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
97 */
98 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
99 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
100 pCreateInfo->format != VK_FORMAT_D16_UNORM)
101 return false;
102
103 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
104 const struct VkImageFormatListCreateInfoKHR *format_list =
105 (const struct VkImageFormatListCreateInfoKHR *)
106 vk_find_struct_const(pCreateInfo->pNext,
107 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
108
109 /* We have to ignore the existence of the list if viewFormatCount = 0 */
110 if (format_list && format_list->viewFormatCount) {
111 /* compatibility is transitive, so we only need to check
112 * one format with everything else.
113 */
114 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
115 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
116 continue;
117
118 if (pCreateInfo->format != format_list->pViewFormats[i])
119 return false;
120 }
121 } else {
122 return false;
123 }
124 }
125
126 return true;
127 }
128
129 static bool
130 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
131 {
132 if (info->scanout)
133 return true;
134
135 if (!info->bo_metadata)
136 return false;
137
138 if (device->physical_device->rad_info.chip_class >= GFX9) {
139 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
140 } else {
141 return info->bo_metadata->u.legacy.scanout;
142 }
143 }
144
145 static bool
146 radv_use_dcc_for_image(struct radv_device *device,
147 const struct radv_image *image,
148 const struct radv_image_create_info *create_info,
149 const VkImageCreateInfo *pCreateInfo)
150 {
151 bool dcc_compatible_formats;
152 bool blendable;
153
154 /* DCC (Delta Color Compression) is only available for GFX8+. */
155 if (device->physical_device->rad_info.chip_class < GFX8)
156 return false;
157
158 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
159 return false;
160
161 if (image->shareable)
162 return false;
163
164 /* TODO: Enable DCC for storage images. */
165 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
166 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
167 return false;
168
169 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
170 return false;
171
172 if (vk_format_is_subsampled(pCreateInfo->format) ||
173 vk_format_get_plane_count(pCreateInfo->format) > 1)
174 return false;
175
176 /* TODO: Enable DCC for mipmaps on GFX9+. */
177 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
178 device->physical_device->rad_info.chip_class >= GFX9)
179 return false;
180
181 /* Do not enable DCC for mipmapped arrays because performance is worse. */
182 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
183 return false;
184
185 if (radv_surface_has_scanout(device, create_info))
186 return false;
187
188 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
189 * 2x can be enabled with an option.
190 */
191 if (pCreateInfo->samples > 2 ||
192 (pCreateInfo->samples == 2 &&
193 !device->physical_device->dcc_msaa_allowed))
194 return false;
195
196 /* Determine if the formats are DCC compatible. */
197 dcc_compatible_formats =
198 radv_is_colorbuffer_format_supported(pCreateInfo->format,
199 &blendable);
200
201 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
202 const struct VkImageFormatListCreateInfoKHR *format_list =
203 (const struct VkImageFormatListCreateInfoKHR *)
204 vk_find_struct_const(pCreateInfo->pNext,
205 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
206
207 /* We have to ignore the existence of the list if viewFormatCount = 0 */
208 if (format_list && format_list->viewFormatCount) {
209 /* compatibility is transitive, so we only need to check
210 * one format with everything else. */
211 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
212 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
213 continue;
214
215 if (!radv_dcc_formats_compatible(pCreateInfo->format,
216 format_list->pViewFormats[i]))
217 dcc_compatible_formats = false;
218 }
219 } else {
220 dcc_compatible_formats = false;
221 }
222 }
223
224 if (!dcc_compatible_formats)
225 return false;
226
227 return true;
228 }
229
230 static bool
231 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
232 struct radv_image *image)
233 {
234 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
235 return false;
236
237 /* TC-compat CMASK is only available for GFX8+. */
238 if (device->physical_device->rad_info.chip_class < GFX8)
239 return false;
240
241 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
242 return false;
243
244 if (radv_image_has_dcc(image))
245 return false;
246
247 if (!radv_image_has_cmask(image))
248 return false;
249
250 return true;
251 }
252
253 static void
254 radv_prefill_surface_from_metadata(struct radv_device *device,
255 struct radeon_surf *surface,
256 const struct radv_image_create_info *create_info)
257 {
258 const struct radeon_bo_metadata *md = create_info->bo_metadata;
259 if (device->physical_device->rad_info.chip_class >= GFX9) {
260 if (md->u.gfx9.swizzle_mode > 0)
261 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
262 else
263 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
264
265 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
266 } else {
267 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
268 surface->u.legacy.bankw = md->u.legacy.bankw;
269 surface->u.legacy.bankh = md->u.legacy.bankh;
270 surface->u.legacy.tile_split = md->u.legacy.tile_split;
271 surface->u.legacy.mtilea = md->u.legacy.mtilea;
272 surface->u.legacy.num_banks = md->u.legacy.num_banks;
273
274 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
276 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
277 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
278 else
279 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
280
281 }
282 }
283
284 static int
285 radv_init_surface(struct radv_device *device,
286 const struct radv_image *image,
287 struct radeon_surf *surface,
288 unsigned plane_id,
289 const struct radv_image_create_info *create_info)
290 {
291 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
292 unsigned array_mode = radv_choose_tiling(device, create_info);
293 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
294 const struct vk_format_description *desc = vk_format_description(format);
295 bool is_depth, is_stencil;
296
297 is_depth = vk_format_has_depth(desc);
298 is_stencil = vk_format_has_stencil(desc);
299
300 surface->blk_w = vk_format_get_blockwidth(format);
301 surface->blk_h = vk_format_get_blockheight(format);
302
303 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
304 /* align byte per element on dword */
305 if (surface->bpe == 3) {
306 surface->bpe = 4;
307 }
308 if (create_info->bo_metadata) {
309 radv_prefill_surface_from_metadata(device, surface, create_info);
310 } else {
311 surface->flags = RADEON_SURF_SET(array_mode, MODE);
312 }
313
314 switch (pCreateInfo->imageType){
315 case VK_IMAGE_TYPE_1D:
316 if (pCreateInfo->arrayLayers > 1)
317 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
318 else
319 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
320 break;
321 case VK_IMAGE_TYPE_2D:
322 if (pCreateInfo->arrayLayers > 1)
323 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
324 else
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
326 break;
327 case VK_IMAGE_TYPE_3D:
328 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
329 break;
330 default:
331 unreachable("unhandled image type");
332 }
333
334 if (is_depth) {
335 surface->flags |= RADEON_SURF_ZBUFFER;
336 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
337 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
338 }
339
340 if (is_stencil)
341 surface->flags |= RADEON_SURF_SBUFFER;
342
343 if (device->physical_device->rad_info.chip_class >= GFX9 &&
344 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
345 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
346 vk_format_is_compressed(pCreateInfo->format))
347 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
348
349 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
350
351 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
352 surface->flags |= RADEON_SURF_DISABLE_DCC;
353
354 if (radv_surface_has_scanout(device, create_info))
355 surface->flags |= RADEON_SURF_SCANOUT;
356
357 return 0;
358 }
359
360 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
361 {
362 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
363 }
364
365 static inline unsigned
366 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
367 {
368 if (stencil)
369 return plane->surface.u.legacy.stencil_tiling_index[level];
370 else
371 return plane->surface.u.legacy.tiling_index[level];
372 }
373
374 static unsigned radv_map_swizzle(unsigned swizzle)
375 {
376 switch (swizzle) {
377 case VK_SWIZZLE_Y:
378 return V_008F0C_SQ_SEL_Y;
379 case VK_SWIZZLE_Z:
380 return V_008F0C_SQ_SEL_Z;
381 case VK_SWIZZLE_W:
382 return V_008F0C_SQ_SEL_W;
383 case VK_SWIZZLE_0:
384 return V_008F0C_SQ_SEL_0;
385 case VK_SWIZZLE_1:
386 return V_008F0C_SQ_SEL_1;
387 default: /* VK_SWIZZLE_X */
388 return V_008F0C_SQ_SEL_X;
389 }
390 }
391
392 static void
393 radv_make_buffer_descriptor(struct radv_device *device,
394 struct radv_buffer *buffer,
395 VkFormat vk_format,
396 unsigned offset,
397 unsigned range,
398 uint32_t *state)
399 {
400 const struct vk_format_description *desc;
401 unsigned stride;
402 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
403 uint64_t va = gpu_address + buffer->offset;
404 unsigned num_format, data_format;
405 int first_non_void;
406 desc = vk_format_description(vk_format);
407 first_non_void = vk_format_get_first_non_void_channel(vk_format);
408 stride = desc->block.bits / 8;
409
410 va += offset;
411 state[0] = va;
412 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
413 S_008F04_STRIDE(stride);
414
415 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
416 range /= stride;
417 }
418
419 state[2] = range;
420 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
421 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
422 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
423 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
424
425 if (device->physical_device->rad_info.chip_class >= GFX10) {
426 const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
427
428 /* OOB_SELECT chooses the out-of-bounds check:
429 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
430 * - 1: index >= NUM_RECORDS
431 * - 2: NUM_RECORDS == 0
432 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
433 * else: swizzle_address >= NUM_RECORDS
434 */
435 state[3] |= S_008F0C_FORMAT(fmt->img_format) |
436 S_008F0C_OOB_SELECT(0) |
437 S_008F0C_RESOURCE_LEVEL(1);
438 } else {
439 num_format = radv_translate_buffer_numformat(desc, first_non_void);
440 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
441
442 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
443 assert(num_format != ~0);
444
445 state[3] |= S_008F0C_NUM_FORMAT(num_format) |
446 S_008F0C_DATA_FORMAT(data_format);
447 }
448 }
449
450 static void
451 si_set_mutable_tex_desc_fields(struct radv_device *device,
452 struct radv_image *image,
453 const struct legacy_surf_level *base_level_info,
454 unsigned plane_id,
455 unsigned base_level, unsigned first_level,
456 unsigned block_width, bool is_stencil,
457 bool is_storage_image, uint32_t *state)
458 {
459 struct radv_image_plane *plane = &image->planes[plane_id];
460 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
461 uint64_t va = gpu_address + plane->offset;
462 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
463 uint64_t meta_va = 0;
464 if (chip_class >= GFX9) {
465 if (is_stencil)
466 va += plane->surface.u.gfx9.stencil_offset;
467 else
468 va += plane->surface.u.gfx9.surf_offset;
469 } else
470 va += base_level_info->offset;
471
472 state[0] = va >> 8;
473 if (chip_class >= GFX9 ||
474 base_level_info->mode == RADEON_SURF_MODE_2D)
475 state[0] |= plane->surface.tile_swizzle;
476 state[1] &= C_008F14_BASE_ADDRESS_HI;
477 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
478
479 if (chip_class >= GFX8) {
480 state[6] &= C_008F28_COMPRESSION_EN;
481 state[7] = 0;
482 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
483 meta_va = gpu_address + image->dcc_offset;
484 if (chip_class <= GFX8)
485 meta_va += base_level_info->dcc_offset;
486
487 meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
488 } else if (!is_storage_image &&
489 radv_image_is_tc_compat_htile(image)) {
490 meta_va = gpu_address + image->htile_offset;
491 }
492
493 if (meta_va) {
494 state[6] |= S_008F28_COMPRESSION_EN(1);
495 if (chip_class <= GFX9)
496 state[7] = meta_va >> 8;
497 }
498 }
499
500 if (chip_class >= GFX10) {
501 state[3] &= C_00A00C_SW_MODE;
502
503 if (is_stencil) {
504 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
505 } else {
506 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
507 }
508
509 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
510 C_00A018_META_PIPE_ALIGNED;
511
512 if (meta_va) {
513 struct gfx9_surf_meta_flags meta;
514
515 if (image->dcc_offset)
516 meta = plane->surface.u.gfx9.dcc;
517 else
518 meta = plane->surface.u.gfx9.htile;
519
520 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
521 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
522 }
523
524 state[7] = meta_va >> 16;
525 } else if (chip_class == GFX9) {
526 state[3] &= C_008F1C_SW_MODE;
527 state[4] &= C_008F20_PITCH;
528
529 if (is_stencil) {
530 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
531 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
532 } else {
533 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
534 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
535 }
536
537 state[5] &= C_008F24_META_DATA_ADDRESS &
538 C_008F24_META_PIPE_ALIGNED &
539 C_008F24_META_RB_ALIGNED;
540 if (meta_va) {
541 struct gfx9_surf_meta_flags meta;
542
543 if (image->dcc_offset)
544 meta = plane->surface.u.gfx9.dcc;
545 else
546 meta = plane->surface.u.gfx9.htile;
547
548 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
549 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
550 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
551 }
552 } else {
553 /* GFX6-GFX8 */
554 unsigned pitch = base_level_info->nblk_x * block_width;
555 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
556
557 state[3] &= C_008F1C_TILING_INDEX;
558 state[3] |= S_008F1C_TILING_INDEX(index);
559 state[4] &= C_008F20_PITCH;
560 state[4] |= S_008F20_PITCH(pitch - 1);
561 }
562 }
563
564 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
565 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
566 {
567 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
568 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
569
570 /* GFX9 allocates 1D textures as 2D. */
571 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
572 image_type = VK_IMAGE_TYPE_2D;
573 switch (image_type) {
574 case VK_IMAGE_TYPE_1D:
575 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
576 case VK_IMAGE_TYPE_2D:
577 if (nr_samples > 1)
578 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
579 else
580 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
581 case VK_IMAGE_TYPE_3D:
582 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
583 return V_008F1C_SQ_RSRC_IMG_3D;
584 else
585 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
586 default:
587 unreachable("illegal image type");
588 }
589 }
590
591 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
592 {
593 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
594
595 if (swizzle[3] == VK_SWIZZLE_X) {
596 /* For the pre-defined border color values (white, opaque
597 * black, transparent black), the only thing that matters is
598 * that the alpha channel winds up in the correct place
599 * (because the RGB channels are all the same) so either of
600 * these enumerations will work.
601 */
602 if (swizzle[2] == VK_SWIZZLE_Y)
603 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
604 else
605 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
606 } else if (swizzle[0] == VK_SWIZZLE_X) {
607 if (swizzle[1] == VK_SWIZZLE_Y)
608 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
609 else
610 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
611 } else if (swizzle[1] == VK_SWIZZLE_X) {
612 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
613 } else if (swizzle[2] == VK_SWIZZLE_X) {
614 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
615 }
616
617 return bc_swizzle;
618 }
619
620 static bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
621 {
622 const struct vk_format_description *desc = vk_format_description(format);
623
624 if (device->physical_device->rad_info.chip_class >= GFX10 && desc->nr_channels == 1)
625 return desc->swizzle[3] == VK_SWIZZLE_X;
626
627 return radv_translate_colorswap(format, false) <= 1;
628 }
629 /**
630 * Build the sampler view descriptor for a texture (GFX10).
631 */
632 static void
633 gfx10_make_texture_descriptor(struct radv_device *device,
634 struct radv_image *image,
635 bool is_storage_image,
636 VkImageViewType view_type,
637 VkFormat vk_format,
638 const VkComponentMapping *mapping,
639 unsigned first_level, unsigned last_level,
640 unsigned first_layer, unsigned last_layer,
641 unsigned width, unsigned height, unsigned depth,
642 uint32_t *state,
643 uint32_t *fmask_state)
644 {
645 const struct vk_format_description *desc;
646 enum vk_swizzle swizzle[4];
647 unsigned img_format;
648 unsigned type;
649
650 desc = vk_format_description(vk_format);
651 img_format = gfx10_format_table[vk_format].img_format;
652
653 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
654 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
655 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
656 } else {
657 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
658 }
659
660 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
661 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
662 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
663 height = 1;
664 depth = image->info.array_size;
665 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
666 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
667 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
668 depth = image->info.array_size;
669 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
670 depth = image->info.array_size / 6;
671
672 state[0] = 0;
673 state[1] = S_00A004_FORMAT(img_format) |
674 S_00A004_WIDTH_LO(width - 1);
675 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
676 S_00A008_HEIGHT(height - 1) |
677 S_00A008_RESOURCE_LEVEL(1);
678 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
679 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
680 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
681 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
682 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
683 0 : first_level) |
684 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
685 util_logbase2(image->info.samples) :
686 last_level) |
687 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
688 S_00A00C_TYPE(type);
689 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
690 * to know the total number of layers.
691 */
692 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
693 S_00A010_BASE_ARRAY(first_layer);
694 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
695 S_00A014_MAX_MIP(image->info.samples > 1 ?
696 util_logbase2(image->info.samples) :
697 image->info.levels - 1) |
698 S_00A014_PERF_MOD(4);
699 state[6] = 0;
700 state[7] = 0;
701
702 if (radv_dcc_enabled(image, first_level)) {
703 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
704 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
705 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
706 }
707
708 /* Initialize the sampler view for FMASK. */
709 if (radv_image_has_fmask(image)) {
710 uint64_t gpu_address = radv_buffer_get_va(image->bo);
711 uint32_t format;
712 uint64_t va;
713
714 assert(image->plane_count == 1);
715
716 va = gpu_address + image->offset + image->fmask.offset;
717
718 switch (image->info.samples) {
719 case 2:
720 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
721 break;
722 case 4:
723 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
724 break;
725 case 8:
726 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
727 break;
728 default:
729 unreachable("invalid nr_samples");
730 }
731
732 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
733 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
734 S_00A004_FORMAT(format) |
735 S_00A004_WIDTH_LO(width - 1);
736 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
737 S_00A008_HEIGHT(height - 1) |
738 S_00A008_RESOURCE_LEVEL(1);
739 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
740 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
741 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
742 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
743 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
744 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
745 fmask_state[4] = S_00A010_DEPTH(last_layer) |
746 S_00A010_BASE_ARRAY(first_layer);
747 fmask_state[5] = 0;
748 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
749 fmask_state[7] = 0;
750 } else if (fmask_state)
751 memset(fmask_state, 0, 8 * 4);
752 }
753
754 /**
755 * Build the sampler view descriptor for a texture (SI-GFX9)
756 */
757 static void
758 si_make_texture_descriptor(struct radv_device *device,
759 struct radv_image *image,
760 bool is_storage_image,
761 VkImageViewType view_type,
762 VkFormat vk_format,
763 const VkComponentMapping *mapping,
764 unsigned first_level, unsigned last_level,
765 unsigned first_layer, unsigned last_layer,
766 unsigned width, unsigned height, unsigned depth,
767 uint32_t *state,
768 uint32_t *fmask_state)
769 {
770 const struct vk_format_description *desc;
771 enum vk_swizzle swizzle[4];
772 int first_non_void;
773 unsigned num_format, data_format, type;
774
775 desc = vk_format_description(vk_format);
776
777 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
778 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
779 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
780 } else {
781 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
782 }
783
784 first_non_void = vk_format_get_first_non_void_channel(vk_format);
785
786 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
787 if (num_format == ~0) {
788 num_format = 0;
789 }
790
791 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
792 if (data_format == ~0) {
793 data_format = 0;
794 }
795
796 /* S8 with either Z16 or Z32 HTILE need a special format. */
797 if (device->physical_device->rad_info.chip_class == GFX9 &&
798 vk_format == VK_FORMAT_S8_UINT &&
799 radv_image_is_tc_compat_htile(image)) {
800 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
801 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
802 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
803 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
804 }
805 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
806 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
807 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
808 height = 1;
809 depth = image->info.array_size;
810 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
811 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
812 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
813 depth = image->info.array_size;
814 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
815 depth = image->info.array_size / 6;
816
817 state[0] = 0;
818 state[1] = (S_008F14_DATA_FORMAT(data_format) |
819 S_008F14_NUM_FORMAT(num_format));
820 state[2] = (S_008F18_WIDTH(width - 1) |
821 S_008F18_HEIGHT(height - 1) |
822 S_008F18_PERF_MOD(4));
823 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
824 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
825 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
826 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
827 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
828 0 : first_level) |
829 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
830 util_logbase2(image->info.samples) :
831 last_level) |
832 S_008F1C_TYPE(type));
833 state[4] = 0;
834 state[5] = S_008F24_BASE_ARRAY(first_layer);
835 state[6] = 0;
836 state[7] = 0;
837
838 if (device->physical_device->rad_info.chip_class == GFX9) {
839 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
840
841 /* Depth is the last accessible layer on Gfx9.
842 * The hw doesn't need to know the total number of layers.
843 */
844 if (type == V_008F1C_SQ_RSRC_IMG_3D)
845 state[4] |= S_008F20_DEPTH(depth - 1);
846 else
847 state[4] |= S_008F20_DEPTH(last_layer);
848
849 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
850 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
851 util_logbase2(image->info.samples) :
852 image->info.levels - 1);
853 } else {
854 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
855 state[4] |= S_008F20_DEPTH(depth - 1);
856 state[5] |= S_008F24_LAST_ARRAY(last_layer);
857 }
858 if (image->dcc_offset) {
859 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
860 } else {
861 /* The last dword is unused by hw. The shader uses it to clear
862 * bits in the first dword of sampler state.
863 */
864 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
865 if (first_level == last_level)
866 state[7] = C_008F30_MAX_ANISO_RATIO;
867 else
868 state[7] = 0xffffffff;
869 }
870 }
871
872 /* Initialize the sampler view for FMASK. */
873 if (radv_image_has_fmask(image)) {
874 uint32_t fmask_format, num_format;
875 uint64_t gpu_address = radv_buffer_get_va(image->bo);
876 uint64_t va;
877
878 assert(image->plane_count == 1);
879
880 va = gpu_address + image->offset + image->fmask.offset;
881
882 if (device->physical_device->rad_info.chip_class == GFX9) {
883 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
884 switch (image->info.samples) {
885 case 2:
886 num_format = V_008F14_IMG_FMASK_8_2_2;
887 break;
888 case 4:
889 num_format = V_008F14_IMG_FMASK_8_4_4;
890 break;
891 case 8:
892 num_format = V_008F14_IMG_FMASK_32_8_8;
893 break;
894 default:
895 unreachable("invalid nr_samples");
896 }
897 } else {
898 switch (image->info.samples) {
899 case 2:
900 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
901 break;
902 case 4:
903 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
904 break;
905 case 8:
906 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
907 break;
908 default:
909 assert(0);
910 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
911 }
912 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
913 }
914
915 fmask_state[0] = va >> 8;
916 fmask_state[0] |= image->fmask.tile_swizzle;
917 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
918 S_008F14_DATA_FORMAT(fmask_format) |
919 S_008F14_NUM_FORMAT(num_format);
920 fmask_state[2] = S_008F18_WIDTH(width - 1) |
921 S_008F18_HEIGHT(height - 1);
922 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
923 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
924 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
925 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
926 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
927 fmask_state[4] = 0;
928 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
929 fmask_state[6] = 0;
930 fmask_state[7] = 0;
931
932 if (device->physical_device->rad_info.chip_class == GFX9) {
933 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
934 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
935 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
936 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
937 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
938
939 if (radv_image_is_tc_compat_cmask(image)) {
940 va = gpu_address + image->offset + image->cmask.offset;
941
942 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
943 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
944 fmask_state[7] |= va >> 8;
945 }
946 } else {
947 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
948 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
949 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
950 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
951
952 if (radv_image_is_tc_compat_cmask(image)) {
953 va = gpu_address + image->offset + image->cmask.offset;
954
955 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
956 fmask_state[7] |= va >> 8;
957 }
958 }
959 } else if (fmask_state)
960 memset(fmask_state, 0, 8 * 4);
961 }
962
963 static void
964 radv_make_texture_descriptor(struct radv_device *device,
965 struct radv_image *image,
966 bool is_storage_image,
967 VkImageViewType view_type,
968 VkFormat vk_format,
969 const VkComponentMapping *mapping,
970 unsigned first_level, unsigned last_level,
971 unsigned first_layer, unsigned last_layer,
972 unsigned width, unsigned height, unsigned depth,
973 uint32_t *state,
974 uint32_t *fmask_state)
975 {
976 if (device->physical_device->rad_info.chip_class >= GFX10) {
977 gfx10_make_texture_descriptor(device, image, is_storage_image,
978 view_type, vk_format, mapping,
979 first_level, last_level,
980 first_layer, last_layer,
981 width, height, depth,
982 state, fmask_state);
983 } else {
984 si_make_texture_descriptor(device, image, is_storage_image,
985 view_type, vk_format, mapping,
986 first_level, last_level,
987 first_layer, last_layer,
988 width, height, depth,
989 state, fmask_state);
990 }
991 }
992
993 static void
994 radv_query_opaque_metadata(struct radv_device *device,
995 struct radv_image *image,
996 struct radeon_bo_metadata *md)
997 {
998 static const VkComponentMapping fixedmapping;
999 uint32_t desc[8], i;
1000
1001 assert(image->plane_count == 1);
1002
1003 /* Metadata image format format version 1:
1004 * [0] = 1 (metadata format identifier)
1005 * [1] = (VENDOR_ID << 16) | PCI_ID
1006 * [2:9] = image descriptor for the whole resource
1007 * [2] is always 0, because the base address is cleared
1008 * [9] is the DCC offset bits [39:8] from the beginning of
1009 * the buffer
1010 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1011 */
1012 md->metadata[0] = 1; /* metadata image format version 1 */
1013
1014 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1015 md->metadata[1] = si_get_bo_metadata_word1(device);
1016
1017
1018 radv_make_texture_descriptor(device, image, false,
1019 (VkImageViewType)image->type, image->vk_format,
1020 &fixedmapping, 0, image->info.levels - 1, 0,
1021 image->info.array_size - 1,
1022 image->info.width, image->info.height,
1023 image->info.depth,
1024 desc, NULL);
1025
1026 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1027 image->planes[0].surface.blk_w, false, false, desc);
1028
1029 /* Clear the base address and set the relative DCC offset. */
1030 desc[0] = 0;
1031 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1032 desc[7] = image->dcc_offset >> 8;
1033
1034 /* Dwords [2:9] contain the image descriptor. */
1035 memcpy(&md->metadata[2], desc, sizeof(desc));
1036
1037 /* Dwords [10:..] contain the mipmap level offsets. */
1038 if (device->physical_device->rad_info.chip_class <= GFX8) {
1039 for (i = 0; i <= image->info.levels - 1; i++)
1040 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1041 md->size_metadata = (11 + image->info.levels - 1) * 4;
1042 } else
1043 md->size_metadata = 10 * 4;
1044 }
1045
1046 void
1047 radv_init_metadata(struct radv_device *device,
1048 struct radv_image *image,
1049 struct radeon_bo_metadata *metadata)
1050 {
1051 struct radeon_surf *surface = &image->planes[0].surface;
1052
1053 memset(metadata, 0, sizeof(*metadata));
1054
1055 if (device->physical_device->rad_info.chip_class >= GFX9) {
1056 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1057 } else {
1058 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1059 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1060 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1061 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1062 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1063 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1064 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1065 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1066 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1067 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1068 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1069 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1070 }
1071 radv_query_opaque_metadata(device, image, metadata);
1072 }
1073
1074 void
1075 radv_image_override_offset_stride(struct radv_device *device,
1076 struct radv_image *image,
1077 uint64_t offset, uint32_t stride)
1078 {
1079 struct radeon_surf *surface = &image->planes[0].surface;
1080 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1081
1082 if (device->physical_device->rad_info.chip_class >= GFX9) {
1083 if (stride) {
1084 surface->u.gfx9.surf_pitch = stride;
1085 surface->u.gfx9.surf_slice_size =
1086 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1087 }
1088 surface->u.gfx9.surf_offset = offset;
1089 } else {
1090 surface->u.legacy.level[0].nblk_x = stride;
1091 surface->u.legacy.level[0].slice_size_dw =
1092 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1093
1094 if (offset) {
1095 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1096 surface->u.legacy.level[i].offset += offset;
1097 }
1098
1099 }
1100 }
1101
1102 /* The number of samples can be specified independently of the texture. */
1103 static void
1104 radv_image_get_fmask_info(struct radv_device *device,
1105 struct radv_image *image,
1106 unsigned nr_samples,
1107 struct radv_fmask_info *out)
1108 {
1109 if (device->physical_device->rad_info.chip_class >= GFX9) {
1110 out->alignment = image->planes[0].surface.fmask_alignment;
1111 out->size = image->planes[0].surface.fmask_size;
1112 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1113 return;
1114 }
1115
1116 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
1117 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
1118 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
1119 out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
1120 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
1121 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1122 out->alignment = image->planes[0].surface.fmask_alignment;
1123 out->size = image->planes[0].surface.fmask_size;
1124
1125 assert(!out->tile_swizzle || !image->shareable);
1126 }
1127
1128 static void
1129 radv_image_alloc_fmask(struct radv_device *device,
1130 struct radv_image *image)
1131 {
1132 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
1133
1134 image->fmask.offset = align64(image->size, image->fmask.alignment);
1135 image->size = image->fmask.offset + image->fmask.size;
1136 image->alignment = MAX2(image->alignment, image->fmask.alignment);
1137 }
1138
1139 static void
1140 radv_image_get_cmask_info(struct radv_device *device,
1141 struct radv_image *image,
1142 struct radv_cmask_info *out)
1143 {
1144 assert(image->plane_count == 1);
1145
1146 if (device->physical_device->rad_info.chip_class >= GFX9) {
1147 out->alignment = image->planes[0].surface.cmask_alignment;
1148 out->size = image->planes[0].surface.cmask_size;
1149 return;
1150 }
1151
1152 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
1153 out->alignment = image->planes[0].surface.cmask_alignment;
1154 out->slice_size = image->planes[0].surface.cmask_slice_size;
1155 out->size = image->planes[0].surface.cmask_size;
1156 }
1157
1158 static void
1159 radv_image_alloc_cmask(struct radv_device *device,
1160 struct radv_image *image)
1161 {
1162 uint32_t clear_value_size = 0;
1163 radv_image_get_cmask_info(device, image, &image->cmask);
1164
1165 if (!image->cmask.size)
1166 return;
1167
1168 assert(image->cmask.alignment);
1169
1170 image->cmask.offset = align64(image->size, image->cmask.alignment);
1171 /* + 8 for storing the clear values */
1172 if (!image->clear_value_offset) {
1173 image->clear_value_offset = image->cmask.offset + image->cmask.size;
1174 clear_value_size = 8;
1175 }
1176 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
1177 image->alignment = MAX2(image->alignment, image->cmask.alignment);
1178 }
1179
1180 static void
1181 radv_image_alloc_dcc(struct radv_image *image)
1182 {
1183 assert(image->plane_count == 1);
1184
1185 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1186 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1187 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1188 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1189 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1190 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1191 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1192 }
1193
1194 static void
1195 radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
1196 {
1197 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1198
1199 /* + 8 for storing the clear values */
1200 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1201 image->size = image->clear_value_offset + 8;
1202 if (radv_image_is_tc_compat_htile(image) &&
1203 device->physical_device->has_tc_compat_zrange_bug) {
1204 /* Metadata for the TC-compatible HTILE hardware bug which
1205 * have to be fixed by updating ZRANGE_PRECISION when doing
1206 * fast depth clears to 0.0f.
1207 */
1208 image->tc_compat_zrange_offset = image->size;
1209 image->size = image->tc_compat_zrange_offset + 4;
1210 }
1211 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1212 }
1213
1214 static inline bool
1215 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1216 {
1217 if (image->info.samples <= 1 &&
1218 image->info.width * image->info.height <= 512 * 512) {
1219 /* Do not enable CMASK or DCC for small surfaces where the cost
1220 * of the eliminate pass can be higher than the benefit of fast
1221 * clear. RadeonSI does this, but the image threshold is
1222 * different.
1223 */
1224 return false;
1225 }
1226
1227 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1228 (image->exclusive || image->queue_family_mask == 1);
1229 }
1230
1231 static inline bool
1232 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1233 {
1234 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1235 !radv_image_has_dcc(image))
1236 return false;
1237
1238 /* On GFX8, DCC layers can be interleaved and it's currently only
1239 * enabled if slice size is equal to the per slice fast clear size
1240 * because the driver assumes that portions of multiple layers are
1241 * contiguous during fast clears.
1242 */
1243 if (image->info.array_size > 1) {
1244 const struct legacy_surf_level *surf_level =
1245 &image->planes[0].surface.u.legacy.level[0];
1246
1247 assert(device->physical_device->rad_info.chip_class == GFX8);
1248
1249 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1250 return false;
1251 }
1252
1253 return true;
1254 }
1255
1256 static inline bool
1257 radv_image_can_enable_cmask(struct radv_image *image)
1258 {
1259 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1260 /* Do not enable CMASK for non-MSAA images (fast color clear)
1261 * because 128 bit formats are not supported, but FMASK might
1262 * still be used.
1263 */
1264 return false;
1265 }
1266
1267 return radv_image_can_enable_dcc_or_cmask(image) &&
1268 image->info.levels == 1 &&
1269 image->info.depth == 1 &&
1270 !image->planes[0].surface.is_linear;
1271 }
1272
1273 static inline bool
1274 radv_image_can_enable_fmask(struct radv_image *image)
1275 {
1276 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1277 }
1278
1279 static inline bool
1280 radv_image_can_enable_htile(struct radv_image *image)
1281 {
1282 return radv_image_has_htile(image) &&
1283 image->info.levels == 1 &&
1284 image->info.width * image->info.height >= 8 * 8;
1285 }
1286
1287 static void radv_image_disable_dcc(struct radv_image *image)
1288 {
1289 for (unsigned i = 0; i < image->plane_count; ++i)
1290 image->planes[i].surface.dcc_size = 0;
1291 }
1292
1293 static void radv_image_disable_htile(struct radv_image *image)
1294 {
1295 for (unsigned i = 0; i < image->plane_count; ++i)
1296 image->planes[i].surface.htile_size = 0;
1297 }
1298
1299 VkResult
1300 radv_image_create(VkDevice _device,
1301 const struct radv_image_create_info *create_info,
1302 const VkAllocationCallbacks* alloc,
1303 VkImage *pImage)
1304 {
1305 RADV_FROM_HANDLE(radv_device, device, _device);
1306 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1307 struct radv_image *image = NULL;
1308 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1309
1310 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1311 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1312
1313 radv_assert(pCreateInfo->mipLevels > 0);
1314 radv_assert(pCreateInfo->arrayLayers > 0);
1315 radv_assert(pCreateInfo->samples > 0);
1316 radv_assert(pCreateInfo->extent.width > 0);
1317 radv_assert(pCreateInfo->extent.height > 0);
1318 radv_assert(pCreateInfo->extent.depth > 0);
1319
1320 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1321 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1322 if (!image)
1323 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1324
1325 image->type = pCreateInfo->imageType;
1326 image->info.width = pCreateInfo->extent.width;
1327 image->info.height = pCreateInfo->extent.height;
1328 image->info.depth = pCreateInfo->extent.depth;
1329 image->info.samples = pCreateInfo->samples;
1330 image->info.storage_samples = pCreateInfo->samples;
1331 image->info.array_size = pCreateInfo->arrayLayers;
1332 image->info.levels = pCreateInfo->mipLevels;
1333 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1334
1335 image->vk_format = pCreateInfo->format;
1336 image->tiling = pCreateInfo->tiling;
1337 image->usage = pCreateInfo->usage;
1338 image->flags = pCreateInfo->flags;
1339
1340 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1341 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1342 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1343 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1344 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1345 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1346 else
1347 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1348 }
1349
1350 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1351 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1352 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1353 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1354 image->info.surf_index = &device->image_mrt_offset_counter;
1355 }
1356
1357 image->plane_count = plane_count;
1358 image->size = 0;
1359 image->alignment = 1;
1360 for (unsigned plane = 0; plane < plane_count; ++plane) {
1361 struct ac_surf_info info = image->info;
1362 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1363
1364 if (plane) {
1365 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1366 assert(info.width % desc->width_divisor == 0);
1367 assert(info.height % desc->height_divisor == 0);
1368
1369 info.width /= desc->width_divisor;
1370 info.height /= desc->height_divisor;
1371 }
1372
1373 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1374
1375 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1376 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1377 image->alignment = image->planes[plane].surface.surf_alignment;
1378
1379 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1380 }
1381
1382 if (!create_info->no_metadata_planes) {
1383 /* Try to enable DCC first. */
1384 if (radv_image_can_enable_dcc(device, image)) {
1385 radv_image_alloc_dcc(image);
1386 if (image->info.samples > 1) {
1387 /* CMASK should be enabled because DCC fast
1388 * clear with MSAA needs it.
1389 */
1390 assert(radv_image_can_enable_cmask(image));
1391 radv_image_alloc_cmask(device, image);
1392 }
1393 } else {
1394 /* When DCC cannot be enabled, try CMASK. */
1395 radv_image_disable_dcc(image);
1396 if (radv_image_can_enable_cmask(image)) {
1397 radv_image_alloc_cmask(device, image);
1398 }
1399 }
1400
1401 /* Try to enable FMASK for multisampled images. */
1402 if (radv_image_can_enable_fmask(image)) {
1403 radv_image_alloc_fmask(device, image);
1404
1405 if (radv_use_tc_compat_cmask_for_image(device, image))
1406 image->tc_compatible_cmask = true;
1407 } else {
1408 /* Otherwise, try to enable HTILE for depth surfaces. */
1409 if (radv_image_can_enable_htile(image) &&
1410 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1411 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1412 radv_image_alloc_htile(device, image);
1413 } else {
1414 radv_image_disable_htile(image);
1415 }
1416 }
1417 } else {
1418 radv_image_disable_dcc(image);
1419 radv_image_disable_htile(image);
1420 }
1421
1422 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1423 image->alignment = MAX2(image->alignment, 4096);
1424 image->size = align64(image->size, image->alignment);
1425 image->offset = 0;
1426
1427 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1428 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1429 if (!image->bo) {
1430 vk_free2(&device->alloc, alloc, image);
1431 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1432 }
1433 }
1434
1435 *pImage = radv_image_to_handle(image);
1436
1437 return VK_SUCCESS;
1438 }
1439
1440 static void
1441 radv_image_view_make_descriptor(struct radv_image_view *iview,
1442 struct radv_device *device,
1443 VkFormat vk_format,
1444 const VkComponentMapping *components,
1445 bool is_storage_image, unsigned plane_id,
1446 unsigned descriptor_plane_id)
1447 {
1448 struct radv_image *image = iview->image;
1449 struct radv_image_plane *plane = &image->planes[plane_id];
1450 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1451 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1452 uint32_t blk_w;
1453 union radv_descriptor *descriptor;
1454 uint32_t hw_level = 0;
1455
1456 if (is_storage_image) {
1457 descriptor = &iview->storage_descriptor;
1458 } else {
1459 descriptor = &iview->descriptor;
1460 }
1461
1462 assert(vk_format_get_plane_count(vk_format) == 1);
1463 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1464 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1465
1466 if (device->physical_device->rad_info.chip_class >= GFX9)
1467 hw_level = iview->base_mip;
1468 radv_make_texture_descriptor(device, image, is_storage_image,
1469 iview->type,
1470 vk_format,
1471 components,
1472 hw_level, hw_level + iview->level_count - 1,
1473 iview->base_layer,
1474 iview->base_layer + iview->layer_count - 1,
1475 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1476 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1477 iview->extent.depth,
1478 descriptor->plane_descriptors[descriptor_plane_id],
1479 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1480
1481 const struct legacy_surf_level *base_level_info = NULL;
1482 if (device->physical_device->rad_info.chip_class <= GFX9) {
1483 if (is_stencil)
1484 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1485 else
1486 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1487 }
1488 si_set_mutable_tex_desc_fields(device, image,
1489 base_level_info,
1490 plane_id,
1491 iview->base_mip,
1492 iview->base_mip,
1493 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1494 }
1495
1496 static unsigned
1497 radv_plane_from_aspect(VkImageAspectFlags mask)
1498 {
1499 switch(mask) {
1500 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1501 return 1;
1502 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1503 return 2;
1504 default:
1505 return 0;
1506 }
1507 }
1508
1509 VkFormat
1510 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1511 {
1512 switch(mask) {
1513 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1514 return image->planes[0].format;
1515 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1516 return image->planes[1].format;
1517 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1518 return image->planes[2].format;
1519 case VK_IMAGE_ASPECT_STENCIL_BIT:
1520 return vk_format_stencil_only(image->vk_format);
1521 case VK_IMAGE_ASPECT_DEPTH_BIT:
1522 return vk_format_depth_only(image->vk_format);
1523 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1524 return vk_format_depth_only(image->vk_format);
1525 default:
1526 return image->vk_format;
1527 }
1528 }
1529
1530 void
1531 radv_image_view_init(struct radv_image_view *iview,
1532 struct radv_device *device,
1533 const VkImageViewCreateInfo* pCreateInfo)
1534 {
1535 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1536 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1537
1538 switch (image->type) {
1539 case VK_IMAGE_TYPE_1D:
1540 case VK_IMAGE_TYPE_2D:
1541 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1542 break;
1543 case VK_IMAGE_TYPE_3D:
1544 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1545 <= radv_minify(image->info.depth, range->baseMipLevel));
1546 break;
1547 default:
1548 unreachable("bad VkImageType");
1549 }
1550 iview->image = image;
1551 iview->bo = image->bo;
1552 iview->type = pCreateInfo->viewType;
1553 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1554 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1555 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1556 iview->vk_format = pCreateInfo->format;
1557
1558 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1559 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1560 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1561 iview->vk_format = vk_format_depth_only(iview->vk_format);
1562 }
1563
1564 if (device->physical_device->rad_info.chip_class >= GFX9) {
1565 iview->extent = (VkExtent3D) {
1566 .width = image->info.width,
1567 .height = image->info.height,
1568 .depth = image->info.depth,
1569 };
1570 } else {
1571 iview->extent = (VkExtent3D) {
1572 .width = radv_minify(image->info.width , range->baseMipLevel),
1573 .height = radv_minify(image->info.height, range->baseMipLevel),
1574 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1575 };
1576 }
1577
1578 if (iview->vk_format != image->planes[iview->plane_id].format) {
1579 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1580 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1581 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1582 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1583
1584 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1585 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1586
1587 /* Comment ported from amdvlk -
1588 * If we have the following image:
1589 * Uncompressed pixels Compressed block sizes (4x4)
1590 * mip0: 22 x 22 6 x 6
1591 * mip1: 11 x 11 3 x 3
1592 * mip2: 5 x 5 2 x 2
1593 * mip3: 2 x 2 1 x 1
1594 * mip4: 1 x 1 1 x 1
1595 *
1596 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1597 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1598 * divide-by-two integer math):
1599 * mip0: 6x6
1600 * mip1: 3x3
1601 * mip2: 1x1
1602 * mip3: 1x1
1603 *
1604 * This means that mip2 will be missing texels.
1605 *
1606 * Fix this by calculating the base mip's width and height, then convert that, and round it
1607 * back up to get the level 0 size.
1608 * Clamp the converted size between the original values, and next power of two, which
1609 * means we don't oversize the image.
1610 */
1611 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1612 vk_format_is_compressed(image->vk_format) &&
1613 !vk_format_is_compressed(iview->vk_format)) {
1614 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1615 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1616
1617 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1618 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1619
1620 lvl_width <<= range->baseMipLevel;
1621 lvl_height <<= range->baseMipLevel;
1622
1623 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1624 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1625 }
1626 }
1627
1628 iview->base_layer = range->baseArrayLayer;
1629 iview->layer_count = radv_get_layerCount(image, range);
1630 iview->base_mip = range->baseMipLevel;
1631 iview->level_count = radv_get_levelCount(image, range);
1632
1633 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1634 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1635 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1636 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1637 }
1638 }
1639
1640 bool radv_layout_has_htile(const struct radv_image *image,
1641 VkImageLayout layout,
1642 unsigned queue_mask)
1643 {
1644 if (radv_image_is_tc_compat_htile(image))
1645 return layout != VK_IMAGE_LAYOUT_GENERAL;
1646
1647 return radv_image_has_htile(image) &&
1648 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1649 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1650 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1651 }
1652
1653 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1654 VkImageLayout layout,
1655 unsigned queue_mask)
1656 {
1657 if (radv_image_is_tc_compat_htile(image))
1658 return layout != VK_IMAGE_LAYOUT_GENERAL;
1659
1660 return radv_image_has_htile(image) &&
1661 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1662 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1663 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1664 }
1665
1666 bool radv_layout_can_fast_clear(const struct radv_image *image,
1667 VkImageLayout layout,
1668 unsigned queue_mask)
1669 {
1670 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1671 }
1672
1673 bool radv_layout_dcc_compressed(const struct radv_image *image,
1674 VkImageLayout layout,
1675 unsigned queue_mask)
1676 {
1677 /* Don't compress compute transfer dst, as image stores are not supported. */
1678 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1679 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1680 return false;
1681
1682 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1683 }
1684
1685
1686 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1687 {
1688 if (!image->exclusive)
1689 return image->queue_family_mask;
1690 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1691 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1692 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1693 if (family == VK_QUEUE_FAMILY_IGNORED)
1694 return 1u << queue_family;
1695 return 1u << family;
1696 }
1697
1698 VkResult
1699 radv_CreateImage(VkDevice device,
1700 const VkImageCreateInfo *pCreateInfo,
1701 const VkAllocationCallbacks *pAllocator,
1702 VkImage *pImage)
1703 {
1704 #ifdef ANDROID
1705 const VkNativeBufferANDROID *gralloc_info =
1706 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1707
1708 if (gralloc_info)
1709 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1710 pAllocator, pImage);
1711 #endif
1712
1713 const struct wsi_image_create_info *wsi_info =
1714 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1715 bool scanout = wsi_info && wsi_info->scanout;
1716
1717 return radv_image_create(device,
1718 &(struct radv_image_create_info) {
1719 .vk_info = pCreateInfo,
1720 .scanout = scanout,
1721 },
1722 pAllocator,
1723 pImage);
1724 }
1725
1726 void
1727 radv_DestroyImage(VkDevice _device, VkImage _image,
1728 const VkAllocationCallbacks *pAllocator)
1729 {
1730 RADV_FROM_HANDLE(radv_device, device, _device);
1731 RADV_FROM_HANDLE(radv_image, image, _image);
1732
1733 if (!image)
1734 return;
1735
1736 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1737 device->ws->buffer_destroy(image->bo);
1738
1739 if (image->owned_memory != VK_NULL_HANDLE)
1740 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1741
1742 vk_free2(&device->alloc, pAllocator, image);
1743 }
1744
1745 void radv_GetImageSubresourceLayout(
1746 VkDevice _device,
1747 VkImage _image,
1748 const VkImageSubresource* pSubresource,
1749 VkSubresourceLayout* pLayout)
1750 {
1751 RADV_FROM_HANDLE(radv_image, image, _image);
1752 RADV_FROM_HANDLE(radv_device, device, _device);
1753 int level = pSubresource->mipLevel;
1754 int layer = pSubresource->arrayLayer;
1755
1756 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1757
1758 struct radv_image_plane *plane = &image->planes[plane_id];
1759 struct radeon_surf *surface = &plane->surface;
1760
1761 if (device->physical_device->rad_info.chip_class >= GFX9) {
1762 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1763 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1764 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1765 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1766 /* Adjust the number of bytes between each row because
1767 * the pitch is actually the number of components per
1768 * row.
1769 */
1770 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1771 } else {
1772 assert(util_is_power_of_two_nonzero(surface->bpe));
1773 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1774 }
1775
1776 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1777 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1778 pLayout->size = surface->u.gfx9.surf_slice_size;
1779 if (image->type == VK_IMAGE_TYPE_3D)
1780 pLayout->size *= u_minify(image->info.depth, level);
1781 } else {
1782 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1783 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1784 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1785 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1786 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1787 if (image->type == VK_IMAGE_TYPE_3D)
1788 pLayout->size *= u_minify(image->info.depth, level);
1789 }
1790 }
1791
1792
1793 VkResult
1794 radv_CreateImageView(VkDevice _device,
1795 const VkImageViewCreateInfo *pCreateInfo,
1796 const VkAllocationCallbacks *pAllocator,
1797 VkImageView *pView)
1798 {
1799 RADV_FROM_HANDLE(radv_device, device, _device);
1800 struct radv_image_view *view;
1801
1802 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1803 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1804 if (view == NULL)
1805 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1806
1807 radv_image_view_init(view, device, pCreateInfo);
1808
1809 *pView = radv_image_view_to_handle(view);
1810
1811 return VK_SUCCESS;
1812 }
1813
1814 void
1815 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1816 const VkAllocationCallbacks *pAllocator)
1817 {
1818 RADV_FROM_HANDLE(radv_device, device, _device);
1819 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1820
1821 if (!iview)
1822 return;
1823 vk_free2(&device->alloc, pAllocator, iview);
1824 }
1825
1826 void radv_buffer_view_init(struct radv_buffer_view *view,
1827 struct radv_device *device,
1828 const VkBufferViewCreateInfo* pCreateInfo)
1829 {
1830 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1831
1832 view->bo = buffer->bo;
1833 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1834 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1835 view->vk_format = pCreateInfo->format;
1836
1837 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1838 pCreateInfo->offset, view->range, view->state);
1839 }
1840
1841 VkResult
1842 radv_CreateBufferView(VkDevice _device,
1843 const VkBufferViewCreateInfo *pCreateInfo,
1844 const VkAllocationCallbacks *pAllocator,
1845 VkBufferView *pView)
1846 {
1847 RADV_FROM_HANDLE(radv_device, device, _device);
1848 struct radv_buffer_view *view;
1849
1850 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1851 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1852 if (!view)
1853 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1854
1855 radv_buffer_view_init(view, device, pCreateInfo);
1856
1857 *pView = radv_buffer_view_to_handle(view);
1858
1859 return VK_SUCCESS;
1860 }
1861
1862 void
1863 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1864 const VkAllocationCallbacks *pAllocator)
1865 {
1866 RADV_FROM_HANDLE(radv_device, device, _device);
1867 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1868
1869 if (!view)
1870 return;
1871
1872 vk_free2(&device->alloc, pAllocator, view);
1873 }