projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/gfx10: add gfx10_make_texture_descriptor
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
175 device->physical_device->rad_info.chip_class >= GFX9)
176 return false;
177
178 /* Do not enable DCC for mipmapped arrays because performance is worse. */
179 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
180 return false;
181
182 if (radv_surface_has_scanout(device, create_info))
183 return false;
184
185 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
186 * 2x can be enabled with an option.
187 */
188 if (pCreateInfo->samples > 2 ||
189 (pCreateInfo->samples == 2 &&
190 !device->physical_device->dcc_msaa_allowed))
191 return false;
192
193 /* Determine if the formats are DCC compatible. */
194 dcc_compatible_formats =
195 radv_is_colorbuffer_format_supported(pCreateInfo->format,
196 &blendable);
197
198 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
199 const struct VkImageFormatListCreateInfoKHR *format_list =
200 (const struct VkImageFormatListCreateInfoKHR *)
201 vk_find_struct_const(pCreateInfo->pNext,
202 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
203
204 /* We have to ignore the existence of the list if viewFormatCount = 0 */
205 if (format_list && format_list->viewFormatCount) {
206 /* compatibility is transitive, so we only need to check
207 * one format with everything else. */
208 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
209 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
210 continue;
211
212 if (!radv_dcc_formats_compatible(pCreateInfo->format,
213 format_list->pViewFormats[i]))
214 dcc_compatible_formats = false;
215 }
216 } else {
217 dcc_compatible_formats = false;
218 }
219 }
220
221 if (!dcc_compatible_formats)
222 return false;
223
224 return true;
225 }
226
227 static bool
228 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
229 struct radv_image *image)
230 {
231 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
232 return false;
233
234 /* TC-compat CMASK is only available for GFX8+. */
235 if (device->physical_device->rad_info.chip_class < GFX8)
236 return false;
237
238 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
239 return false;
240
241 if (radv_image_has_dcc(image))
242 return false;
243
244 if (!radv_image_has_cmask(image))
245 return false;
246
247 return true;
248 }
249
250 static void
251 radv_prefill_surface_from_metadata(struct radv_device *device,
252 struct radeon_surf *surface,
253 const struct radv_image_create_info *create_info)
254 {
255 const struct radeon_bo_metadata *md = create_info->bo_metadata;
256 if (device->physical_device->rad_info.chip_class >= GFX9) {
257 if (md->u.gfx9.swizzle_mode > 0)
258 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
259 else
260 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
261
262 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
263 } else {
264 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
265 surface->u.legacy.bankw = md->u.legacy.bankw;
266 surface->u.legacy.bankh = md->u.legacy.bankh;
267 surface->u.legacy.tile_split = md->u.legacy.tile_split;
268 surface->u.legacy.mtilea = md->u.legacy.mtilea;
269 surface->u.legacy.num_banks = md->u.legacy.num_banks;
270
271 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
272 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
273 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
274 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
275 else
276 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
277
278 }
279 }
280
281 static int
282 radv_init_surface(struct radv_device *device,
283 const struct radv_image *image,
284 struct radeon_surf *surface,
285 unsigned plane_id,
286 const struct radv_image_create_info *create_info)
287 {
288 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
289 unsigned array_mode = radv_choose_tiling(device, create_info);
290 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
291 const struct vk_format_description *desc = vk_format_description(format);
292 bool is_depth, is_stencil;
293
294 is_depth = vk_format_has_depth(desc);
295 is_stencil = vk_format_has_stencil(desc);
296
297 surface->blk_w = vk_format_get_blockwidth(format);
298 surface->blk_h = vk_format_get_blockheight(format);
299
300 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
301 /* align byte per element on dword */
302 if (surface->bpe == 3) {
303 surface->bpe = 4;
304 }
305 if (create_info->bo_metadata) {
306 radv_prefill_surface_from_metadata(device, surface, create_info);
307 } else {
308 surface->flags = RADEON_SURF_SET(array_mode, MODE);
309 }
310
311 switch (pCreateInfo->imageType){
312 case VK_IMAGE_TYPE_1D:
313 if (pCreateInfo->arrayLayers > 1)
314 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
315 else
316 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
317 break;
318 case VK_IMAGE_TYPE_2D:
319 if (pCreateInfo->arrayLayers > 1)
320 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
321 else
322 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
323 break;
324 case VK_IMAGE_TYPE_3D:
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
326 break;
327 default:
328 unreachable("unhandled image type");
329 }
330
331 if (is_depth) {
332 surface->flags |= RADEON_SURF_ZBUFFER;
333 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
334 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
335 }
336
337 if (is_stencil)
338 surface->flags |= RADEON_SURF_SBUFFER;
339
340 if (device->physical_device->rad_info.chip_class >= GFX9 &&
341 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
342 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
343 vk_format_is_compressed(pCreateInfo->format))
344 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
345
346 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
347
348 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
349 surface->flags |= RADEON_SURF_DISABLE_DCC;
350
351 if (radv_surface_has_scanout(device, create_info))
352 surface->flags |= RADEON_SURF_SCANOUT;
353
354 return 0;
355 }
356
357 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
358 {
359 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
360 }
361
362 static inline unsigned
363 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
364 {
365 if (stencil)
366 return plane->surface.u.legacy.stencil_tiling_index[level];
367 else
368 return plane->surface.u.legacy.tiling_index[level];
369 }
370
371 static unsigned radv_map_swizzle(unsigned swizzle)
372 {
373 switch (swizzle) {
374 case VK_SWIZZLE_Y:
375 return V_008F0C_SQ_SEL_Y;
376 case VK_SWIZZLE_Z:
377 return V_008F0C_SQ_SEL_Z;
378 case VK_SWIZZLE_W:
379 return V_008F0C_SQ_SEL_W;
380 case VK_SWIZZLE_0:
381 return V_008F0C_SQ_SEL_0;
382 case VK_SWIZZLE_1:
383 return V_008F0C_SQ_SEL_1;
384 default: /* VK_SWIZZLE_X */
385 return V_008F0C_SQ_SEL_X;
386 }
387 }
388
389 static void
390 radv_make_buffer_descriptor(struct radv_device *device,
391 struct radv_buffer *buffer,
392 VkFormat vk_format,
393 unsigned offset,
394 unsigned range,
395 uint32_t *state)
396 {
397 const struct vk_format_description *desc;
398 unsigned stride;
399 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
400 uint64_t va = gpu_address + buffer->offset;
401 unsigned num_format, data_format;
402 int first_non_void;
403 desc = vk_format_description(vk_format);
404 first_non_void = vk_format_get_first_non_void_channel(vk_format);
405 stride = desc->block.bits / 8;
406
407 num_format = radv_translate_buffer_numformat(desc, first_non_void);
408 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
409
410 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
411 assert(num_format != ~0);
412
413 va += offset;
414 state[0] = va;
415 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
416 S_008F04_STRIDE(stride);
417
418 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
419 range /= stride;
420 }
421
422 state[2] = range;
423 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
424 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
425 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
426 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
427 S_008F0C_NUM_FORMAT(num_format) |
428 S_008F0C_DATA_FORMAT(data_format);
429 }
430
431 static void
432 si_set_mutable_tex_desc_fields(struct radv_device *device,
433 struct radv_image *image,
434 const struct legacy_surf_level *base_level_info,
435 unsigned plane_id,
436 unsigned base_level, unsigned first_level,
437 unsigned block_width, bool is_stencil,
438 bool is_storage_image, uint32_t *state)
439 {
440 struct radv_image_plane *plane = &image->planes[plane_id];
441 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
442 uint64_t va = gpu_address + plane->offset;
443 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
444 uint64_t meta_va = 0;
445 if (chip_class >= GFX9) {
446 if (is_stencil)
447 va += plane->surface.u.gfx9.stencil_offset;
448 else
449 va += plane->surface.u.gfx9.surf_offset;
450 } else
451 va += base_level_info->offset;
452
453 state[0] = va >> 8;
454 if (chip_class >= GFX9 ||
455 base_level_info->mode == RADEON_SURF_MODE_2D)
456 state[0] |= plane->surface.tile_swizzle;
457 state[1] &= C_008F14_BASE_ADDRESS_HI;
458 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
459
460 if (chip_class >= GFX8) {
461 state[6] &= C_008F28_COMPRESSION_EN;
462 state[7] = 0;
463 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
464 meta_va = gpu_address + image->dcc_offset;
465 if (chip_class <= GFX8)
466 meta_va += base_level_info->dcc_offset;
467 } else if (!is_storage_image &&
468 radv_image_is_tc_compat_htile(image)) {
469 meta_va = gpu_address + image->htile_offset;
470 }
471
472 if (meta_va) {
473 state[6] |= S_008F28_COMPRESSION_EN(1);
474 state[7] = meta_va >> 8;
475 state[7] |= plane->surface.tile_swizzle;
476 }
477 }
478
479 if (chip_class >= GFX9) {
480 state[3] &= C_008F1C_SW_MODE;
481 state[4] &= C_008F20_PITCH;
482
483 if (is_stencil) {
484 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
485 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
486 } else {
487 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
488 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
489 }
490
491 state[5] &= C_008F24_META_DATA_ADDRESS &
492 C_008F24_META_PIPE_ALIGNED &
493 C_008F24_META_RB_ALIGNED;
494 if (meta_va) {
495 struct gfx9_surf_meta_flags meta;
496
497 if (image->dcc_offset)
498 meta = plane->surface.u.gfx9.dcc;
499 else
500 meta = plane->surface.u.gfx9.htile;
501
502 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
503 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
504 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
505 }
506 } else {
507 /* GFX6-GFX8 */
508 unsigned pitch = base_level_info->nblk_x * block_width;
509 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
510
511 state[3] &= C_008F1C_TILING_INDEX;
512 state[3] |= S_008F1C_TILING_INDEX(index);
513 state[4] &= C_008F20_PITCH;
514 state[4] |= S_008F20_PITCH(pitch - 1);
515 }
516 }
517
518 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
519 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
520 {
521 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
522 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
523
524 /* GFX9 allocates 1D textures as 2D. */
525 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
526 image_type = VK_IMAGE_TYPE_2D;
527 switch (image_type) {
528 case VK_IMAGE_TYPE_1D:
529 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
530 case VK_IMAGE_TYPE_2D:
531 if (nr_samples > 1)
532 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
533 else
534 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
535 case VK_IMAGE_TYPE_3D:
536 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
537 return V_008F1C_SQ_RSRC_IMG_3D;
538 else
539 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
540 default:
541 unreachable("illegal image type");
542 }
543 }
544
545 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
546 {
547 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
548
549 if (swizzle[3] == VK_SWIZZLE_X) {
550 /* For the pre-defined border color values (white, opaque
551 * black, transparent black), the only thing that matters is
552 * that the alpha channel winds up in the correct place
553 * (because the RGB channels are all the same) so either of
554 * these enumerations will work.
555 */
556 if (swizzle[2] == VK_SWIZZLE_Y)
557 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
558 else
559 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
560 } else if (swizzle[0] == VK_SWIZZLE_X) {
561 if (swizzle[1] == VK_SWIZZLE_Y)
562 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
563 else
564 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
565 } else if (swizzle[1] == VK_SWIZZLE_X) {
566 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
567 } else if (swizzle[2] == VK_SWIZZLE_X) {
568 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
569 }
570
571 return bc_swizzle;
572 }
573
574 /**
575 * Build the sampler view descriptor for a texture (GFX10).
576 */
577 static void
578 gfx10_make_texture_descriptor(struct radv_device *device,
579 struct radv_image *image,
580 bool is_storage_image,
581 VkImageViewType view_type,
582 VkFormat vk_format,
583 const VkComponentMapping *mapping,
584 unsigned first_level, unsigned last_level,
585 unsigned first_layer, unsigned last_layer,
586 unsigned width, unsigned height, unsigned depth,
587 uint32_t *state,
588 uint32_t *fmask_state)
589 {
590 const struct vk_format_description *desc;
591 enum vk_swizzle swizzle[4];
592 unsigned img_format;
593 unsigned type;
594
595 desc = vk_format_description(vk_format);
596 img_format = gfx10_format_table[vk_format].img_format;
597
598 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
599 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
600 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
601 } else {
602 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
603 }
604
605 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
606 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
607 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
608 height = 1;
609 depth = image->info.array_size;
610 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
611 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
612 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
613 depth = image->info.array_size;
614 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
615 depth = image->info.array_size / 6;
616
617 state[0] = 0;
618 state[1] = S_00A004_FORMAT(img_format) |
619 S_00A004_WIDTH_LO(width - 1);
620 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
621 S_00A008_HEIGHT(height - 1) |
622 S_00A008_RESOURCE_LEVEL(1);
623 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
624 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
625 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
626 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
627 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
628 0 : first_level) |
629 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
630 util_logbase2(image->info.samples) :
631 last_level) |
632 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
633 S_00A00C_TYPE(type);
634 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
635 * to know the total number of layers.
636 */
637 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
638 S_00A010_BASE_ARRAY(first_layer);
639 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
640 S_00A014_MAX_MIP(image->info.samples > 1 ?
641 util_logbase2(image->info.samples) :
642 image->info.levels - 1) |
643 S_00A014_PERF_MOD(4);
644 state[6] = 0;
645 state[7] = 0;
646
647 if (radv_dcc_enabled(image, first_level)) {
648 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
649
650 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
651 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
652 S_00A018_ALPHA_IS_ON_MSB(swap <= 1);
653 }
654
655 /* Initialize the sampler view for FMASK. */
656 if (radv_image_has_fmask(image)) {
657 uint64_t gpu_address = radv_buffer_get_va(image->bo);
658 uint32_t format;
659 uint64_t va;
660
661 assert(image->plane_count == 1);
662
663 va = gpu_address + image->offset + image->fmask.offset;
664
665 switch (image->info.samples) {
666 case 2:
667 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
668 break;
669 case 4:
670 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
671 break;
672 case 8:
673 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
674 break;
675 default:
676 unreachable("invalid nr_samples");
677 }
678
679 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
680 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
681 S_00A004_FORMAT(format) |
682 S_00A004_WIDTH_LO(width - 1);
683 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
684 S_00A008_HEIGHT(height - 1) |
685 S_00A008_RESOURCE_LEVEL(1);
686 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
687 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
688 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
689 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
690 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
691 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
692 fmask_state[4] = S_00A010_DEPTH(last_layer) |
693 S_00A010_BASE_ARRAY(first_layer);
694 fmask_state[5] = 0;
695 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
696 fmask_state[7] = 0;
697 } else if (fmask_state)
698 memset(fmask_state, 0, 8 * 4);
699 }
700
701 /**
702 * Build the sampler view descriptor for a texture (SI-GFX9)
703 */
704 static void
705 si_make_texture_descriptor(struct radv_device *device,
706 struct radv_image *image,
707 bool is_storage_image,
708 VkImageViewType view_type,
709 VkFormat vk_format,
710 const VkComponentMapping *mapping,
711 unsigned first_level, unsigned last_level,
712 unsigned first_layer, unsigned last_layer,
713 unsigned width, unsigned height, unsigned depth,
714 uint32_t *state,
715 uint32_t *fmask_state)
716 {
717 const struct vk_format_description *desc;
718 enum vk_swizzle swizzle[4];
719 int first_non_void;
720 unsigned num_format, data_format, type;
721
722 desc = vk_format_description(vk_format);
723
724 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
725 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
726 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
727 } else {
728 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
729 }
730
731 first_non_void = vk_format_get_first_non_void_channel(vk_format);
732
733 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
734 if (num_format == ~0) {
735 num_format = 0;
736 }
737
738 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
739 if (data_format == ~0) {
740 data_format = 0;
741 }
742
743 /* S8 with either Z16 or Z32 HTILE need a special format. */
744 if (device->physical_device->rad_info.chip_class >= GFX9 &&
745 vk_format == VK_FORMAT_S8_UINT &&
746 radv_image_is_tc_compat_htile(image)) {
747 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
748 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
749 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
750 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
751 }
752 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
753 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
754 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
755 height = 1;
756 depth = image->info.array_size;
757 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
758 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
759 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
760 depth = image->info.array_size;
761 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
762 depth = image->info.array_size / 6;
763
764 state[0] = 0;
765 state[1] = (S_008F14_DATA_FORMAT(data_format) |
766 S_008F14_NUM_FORMAT(num_format));
767 state[2] = (S_008F18_WIDTH(width - 1) |
768 S_008F18_HEIGHT(height - 1) |
769 S_008F18_PERF_MOD(4));
770 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
771 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
772 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
773 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
774 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
775 0 : first_level) |
776 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
777 util_logbase2(image->info.samples) :
778 last_level) |
779 S_008F1C_TYPE(type));
780 state[4] = 0;
781 state[5] = S_008F24_BASE_ARRAY(first_layer);
782 state[6] = 0;
783 state[7] = 0;
784
785 if (device->physical_device->rad_info.chip_class >= GFX9) {
786 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
787
788 /* Depth is the last accessible layer on Gfx9.
789 * The hw doesn't need to know the total number of layers.
790 */
791 if (type == V_008F1C_SQ_RSRC_IMG_3D)
792 state[4] |= S_008F20_DEPTH(depth - 1);
793 else
794 state[4] |= S_008F20_DEPTH(last_layer);
795
796 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
797 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
798 util_logbase2(image->info.samples) :
799 image->info.levels - 1);
800 } else {
801 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
802 state[4] |= S_008F20_DEPTH(depth - 1);
803 state[5] |= S_008F24_LAST_ARRAY(last_layer);
804 }
805 if (image->dcc_offset) {
806 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
807
808 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
809 } else {
810 /* The last dword is unused by hw. The shader uses it to clear
811 * bits in the first dword of sampler state.
812 */
813 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
814 if (first_level == last_level)
815 state[7] = C_008F30_MAX_ANISO_RATIO;
816 else
817 state[7] = 0xffffffff;
818 }
819 }
820
821 /* Initialize the sampler view for FMASK. */
822 if (radv_image_has_fmask(image)) {
823 uint32_t fmask_format, num_format;
824 uint64_t gpu_address = radv_buffer_get_va(image->bo);
825 uint64_t va;
826
827 assert(image->plane_count == 1);
828
829 va = gpu_address + image->offset + image->fmask.offset;
830
831 if (device->physical_device->rad_info.chip_class >= GFX9) {
832 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
833 switch (image->info.samples) {
834 case 2:
835 num_format = V_008F14_IMG_FMASK_8_2_2;
836 break;
837 case 4:
838 num_format = V_008F14_IMG_FMASK_8_4_4;
839 break;
840 case 8:
841 num_format = V_008F14_IMG_FMASK_32_8_8;
842 break;
843 default:
844 unreachable("invalid nr_samples");
845 }
846 } else {
847 switch (image->info.samples) {
848 case 2:
849 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
850 break;
851 case 4:
852 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
853 break;
854 case 8:
855 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
856 break;
857 default:
858 assert(0);
859 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
860 }
861 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
862 }
863
864 fmask_state[0] = va >> 8;
865 fmask_state[0] |= image->fmask.tile_swizzle;
866 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
867 S_008F14_DATA_FORMAT(fmask_format) |
868 S_008F14_NUM_FORMAT(num_format);
869 fmask_state[2] = S_008F18_WIDTH(width - 1) |
870 S_008F18_HEIGHT(height - 1);
871 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
872 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
873 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
874 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
875 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
876 fmask_state[4] = 0;
877 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
878 fmask_state[6] = 0;
879 fmask_state[7] = 0;
880
881 if (device->physical_device->rad_info.chip_class >= GFX9) {
882 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
883 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
884 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
885 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
886 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
887
888 if (radv_image_is_tc_compat_cmask(image)) {
889 va = gpu_address + image->offset + image->cmask.offset;
890
891 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
892 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
893 fmask_state[7] |= va >> 8;
894 }
895 } else {
896 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
897 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
898 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
899 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
900
901 if (radv_image_is_tc_compat_cmask(image)) {
902 va = gpu_address + image->offset + image->cmask.offset;
903
904 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
905 fmask_state[7] |= va >> 8;
906 }
907 }
908 } else if (fmask_state)
909 memset(fmask_state, 0, 8 * 4);
910 }
911
912 static void
913 radv_make_texture_descriptor(struct radv_device *device,
914 struct radv_image *image,
915 bool is_storage_image,
916 VkImageViewType view_type,
917 VkFormat vk_format,
918 const VkComponentMapping *mapping,
919 unsigned first_level, unsigned last_level,
920 unsigned first_layer, unsigned last_layer,
921 unsigned width, unsigned height, unsigned depth,
922 uint32_t *state,
923 uint32_t *fmask_state)
924 {
925 if (device->physical_device->rad_info.chip_class >= GFX10) {
926 gfx10_make_texture_descriptor(device, image, is_storage_image,
927 view_type, vk_format, mapping,
928 first_level, last_level,
929 first_layer, last_layer,
930 width, height, depth,
931 state, fmask_state);
932 } else {
933 si_make_texture_descriptor(device, image, is_storage_image,
934 view_type, vk_format, mapping,
935 first_level, last_level,
936 first_layer, last_layer,
937 width, height, depth,
938 state, fmask_state);
939 }
940 }
941
942 static void
943 radv_query_opaque_metadata(struct radv_device *device,
944 struct radv_image *image,
945 struct radeon_bo_metadata *md)
946 {
947 static const VkComponentMapping fixedmapping;
948 uint32_t desc[8], i;
949
950 assert(image->plane_count == 1);
951
952 /* Metadata image format format version 1:
953 * [0] = 1 (metadata format identifier)
954 * [1] = (VENDOR_ID << 16) | PCI_ID
955 * [2:9] = image descriptor for the whole resource
956 * [2] is always 0, because the base address is cleared
957 * [9] is the DCC offset bits [39:8] from the beginning of
958 * the buffer
959 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
960 */
961 md->metadata[0] = 1; /* metadata image format version 1 */
962
963 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
964 md->metadata[1] = si_get_bo_metadata_word1(device);
965
966
967 radv_make_texture_descriptor(device, image, false,
968 (VkImageViewType)image->type, image->vk_format,
969 &fixedmapping, 0, image->info.levels - 1, 0,
970 image->info.array_size - 1,
971 image->info.width, image->info.height,
972 image->info.depth,
973 desc, NULL);
974
975 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
976 image->planes[0].surface.blk_w, false, false, desc);
977
978 /* Clear the base address and set the relative DCC offset. */
979 desc[0] = 0;
980 desc[1] &= C_008F14_BASE_ADDRESS_HI;
981 desc[7] = image->dcc_offset >> 8;
982
983 /* Dwords [2:9] contain the image descriptor. */
984 memcpy(&md->metadata[2], desc, sizeof(desc));
985
986 /* Dwords [10:..] contain the mipmap level offsets. */
987 if (device->physical_device->rad_info.chip_class <= GFX8) {
988 for (i = 0; i <= image->info.levels - 1; i++)
989 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
990 md->size_metadata = (11 + image->info.levels - 1) * 4;
991 }
992 }
993
994 void
995 radv_init_metadata(struct radv_device *device,
996 struct radv_image *image,
997 struct radeon_bo_metadata *metadata)
998 {
999 struct radeon_surf *surface = &image->planes[0].surface;
1000
1001 memset(metadata, 0, sizeof(*metadata));
1002
1003 if (device->physical_device->rad_info.chip_class >= GFX9) {
1004 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1005 } else {
1006 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1007 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1008 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1009 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1010 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1011 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1012 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1013 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1014 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1015 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1016 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1017 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1018 }
1019 radv_query_opaque_metadata(device, image, metadata);
1020 }
1021
1022 void
1023 radv_image_override_offset_stride(struct radv_device *device,
1024 struct radv_image *image,
1025 uint64_t offset, uint32_t stride)
1026 {
1027 struct radeon_surf *surface = &image->planes[0].surface;
1028 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1029
1030 if (device->physical_device->rad_info.chip_class >= GFX9) {
1031 if (stride) {
1032 surface->u.gfx9.surf_pitch = stride;
1033 surface->u.gfx9.surf_slice_size =
1034 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1035 }
1036 surface->u.gfx9.surf_offset = offset;
1037 } else {
1038 surface->u.legacy.level[0].nblk_x = stride;
1039 surface->u.legacy.level[0].slice_size_dw =
1040 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1041
1042 if (offset) {
1043 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1044 surface->u.legacy.level[i].offset += offset;
1045 }
1046
1047 }
1048 }
1049
1050 /* The number of samples can be specified independently of the texture. */
1051 static void
1052 radv_image_get_fmask_info(struct radv_device *device,
1053 struct radv_image *image,
1054 unsigned nr_samples,
1055 struct radv_fmask_info *out)
1056 {
1057 if (device->physical_device->rad_info.chip_class >= GFX9) {
1058 out->alignment = image->planes[0].surface.fmask_alignment;
1059 out->size = image->planes[0].surface.fmask_size;
1060 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1061 return;
1062 }
1063
1064 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
1065 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
1066 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
1067 out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
1068 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
1069 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1070 out->alignment = image->planes[0].surface.fmask_alignment;
1071 out->size = image->planes[0].surface.fmask_size;
1072
1073 assert(!out->tile_swizzle || !image->shareable);
1074 }
1075
1076 static void
1077 radv_image_alloc_fmask(struct radv_device *device,
1078 struct radv_image *image)
1079 {
1080 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
1081
1082 image->fmask.offset = align64(image->size, image->fmask.alignment);
1083 image->size = image->fmask.offset + image->fmask.size;
1084 image->alignment = MAX2(image->alignment, image->fmask.alignment);
1085 }
1086
1087 static void
1088 radv_image_get_cmask_info(struct radv_device *device,
1089 struct radv_image *image,
1090 struct radv_cmask_info *out)
1091 {
1092 assert(image->plane_count == 1);
1093
1094 if (device->physical_device->rad_info.chip_class >= GFX9) {
1095 out->alignment = image->planes[0].surface.cmask_alignment;
1096 out->size = image->planes[0].surface.cmask_size;
1097 return;
1098 }
1099
1100 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
1101 out->alignment = image->planes[0].surface.cmask_alignment;
1102 out->slice_size = image->planes[0].surface.cmask_slice_size;
1103 out->size = image->planes[0].surface.cmask_size;
1104 }
1105
1106 static void
1107 radv_image_alloc_cmask(struct radv_device *device,
1108 struct radv_image *image)
1109 {
1110 uint32_t clear_value_size = 0;
1111 radv_image_get_cmask_info(device, image, &image->cmask);
1112
1113 image->cmask.offset = align64(image->size, image->cmask.alignment);
1114 /* + 8 for storing the clear values */
1115 if (!image->clear_value_offset) {
1116 image->clear_value_offset = image->cmask.offset + image->cmask.size;
1117 clear_value_size = 8;
1118 }
1119 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
1120 image->alignment = MAX2(image->alignment, image->cmask.alignment);
1121 }
1122
1123 static void
1124 radv_image_alloc_dcc(struct radv_image *image)
1125 {
1126 assert(image->plane_count == 1);
1127
1128 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1129 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1130 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1131 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1132 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1133 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1134 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1135 }
1136
1137 static void
1138 radv_image_alloc_htile(struct radv_image *image)
1139 {
1140 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1141
1142 /* + 8 for storing the clear values */
1143 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1144 image->size = image->clear_value_offset + 8;
1145 if (radv_image_is_tc_compat_htile(image)) {
1146 /* Metadata for the TC-compatible HTILE hardware bug which
1147 * have to be fixed by updating ZRANGE_PRECISION when doing
1148 * fast depth clears to 0.0f.
1149 */
1150 image->tc_compat_zrange_offset = image->size;
1151 image->size = image->tc_compat_zrange_offset + 4;
1152 }
1153 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1154 }
1155
1156 static inline bool
1157 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1158 {
1159 if (image->info.samples <= 1 &&
1160 image->info.width * image->info.height <= 512 * 512) {
1161 /* Do not enable CMASK or DCC for small surfaces where the cost
1162 * of the eliminate pass can be higher than the benefit of fast
1163 * clear. RadeonSI does this, but the image threshold is
1164 * different.
1165 */
1166 return false;
1167 }
1168
1169 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1170 (image->exclusive || image->queue_family_mask == 1);
1171 }
1172
1173 static inline bool
1174 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1175 {
1176 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1177 !radv_image_has_dcc(image))
1178 return false;
1179
1180 /* On GFX8, DCC layers can be interleaved and it's currently only
1181 * enabled if slice size is equal to the per slice fast clear size
1182 * because the driver assumes that portions of multiple layers are
1183 * contiguous during fast clears.
1184 */
1185 if (image->info.array_size > 1) {
1186 const struct legacy_surf_level *surf_level =
1187 &image->planes[0].surface.u.legacy.level[0];
1188
1189 assert(device->physical_device->rad_info.chip_class == GFX8);
1190
1191 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1192 return false;
1193 }
1194
1195 return true;
1196 }
1197
1198 static inline bool
1199 radv_image_can_enable_cmask(struct radv_image *image)
1200 {
1201 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1202 /* Do not enable CMASK for non-MSAA images (fast color clear)
1203 * because 128 bit formats are not supported, but FMASK might
1204 * still be used.
1205 */
1206 return false;
1207 }
1208
1209 return radv_image_can_enable_dcc_or_cmask(image) &&
1210 image->info.levels == 1 &&
1211 image->info.depth == 1 &&
1212 !image->planes[0].surface.is_linear;
1213 }
1214
1215 static inline bool
1216 radv_image_can_enable_fmask(struct radv_image *image)
1217 {
1218 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1219 }
1220
1221 static inline bool
1222 radv_image_can_enable_htile(struct radv_image *image)
1223 {
1224 return radv_image_has_htile(image) &&
1225 image->info.levels == 1 &&
1226 image->info.width * image->info.height >= 8 * 8;
1227 }
1228
1229 static void radv_image_disable_dcc(struct radv_image *image)
1230 {
1231 for (unsigned i = 0; i < image->plane_count; ++i)
1232 image->planes[i].surface.dcc_size = 0;
1233 }
1234
1235 static void radv_image_disable_htile(struct radv_image *image)
1236 {
1237 for (unsigned i = 0; i < image->plane_count; ++i)
1238 image->planes[i].surface.htile_size = 0;
1239 }
1240
1241 VkResult
1242 radv_image_create(VkDevice _device,
1243 const struct radv_image_create_info *create_info,
1244 const VkAllocationCallbacks* alloc,
1245 VkImage *pImage)
1246 {
1247 RADV_FROM_HANDLE(radv_device, device, _device);
1248 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1249 struct radv_image *image = NULL;
1250 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1251
1252 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1253 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1254
1255 radv_assert(pCreateInfo->mipLevels > 0);
1256 radv_assert(pCreateInfo->arrayLayers > 0);
1257 radv_assert(pCreateInfo->samples > 0);
1258 radv_assert(pCreateInfo->extent.width > 0);
1259 radv_assert(pCreateInfo->extent.height > 0);
1260 radv_assert(pCreateInfo->extent.depth > 0);
1261
1262 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1264 if (!image)
1265 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1266
1267 image->type = pCreateInfo->imageType;
1268 image->info.width = pCreateInfo->extent.width;
1269 image->info.height = pCreateInfo->extent.height;
1270 image->info.depth = pCreateInfo->extent.depth;
1271 image->info.samples = pCreateInfo->samples;
1272 image->info.storage_samples = pCreateInfo->samples;
1273 image->info.array_size = pCreateInfo->arrayLayers;
1274 image->info.levels = pCreateInfo->mipLevels;
1275 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1276
1277 image->vk_format = pCreateInfo->format;
1278 image->tiling = pCreateInfo->tiling;
1279 image->usage = pCreateInfo->usage;
1280 image->flags = pCreateInfo->flags;
1281
1282 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1283 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1284 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1285 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1286 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1287 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1288 else
1289 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1290 }
1291
1292 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1293 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1294 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1295 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1296 image->info.surf_index = &device->image_mrt_offset_counter;
1297 }
1298
1299 image->plane_count = plane_count;
1300 image->size = 0;
1301 image->alignment = 1;
1302 for (unsigned plane = 0; plane < plane_count; ++plane) {
1303 struct ac_surf_info info = image->info;
1304 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1305
1306 if (plane) {
1307 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1308 assert(info.width % desc->width_divisor == 0);
1309 assert(info.height % desc->height_divisor == 0);
1310
1311 info.width /= desc->width_divisor;
1312 info.height /= desc->height_divisor;
1313 }
1314
1315 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1316
1317 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1318 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1319 image->alignment = image->planes[plane].surface.surf_alignment;
1320
1321 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1322 }
1323
1324 if (!create_info->no_metadata_planes) {
1325 /* Try to enable DCC first. */
1326 if (radv_image_can_enable_dcc(device, image)) {
1327 radv_image_alloc_dcc(image);
1328 if (image->info.samples > 1) {
1329 /* CMASK should be enabled because DCC fast
1330 * clear with MSAA needs it.
1331 */
1332 assert(radv_image_can_enable_cmask(image));
1333 radv_image_alloc_cmask(device, image);
1334 }
1335 } else {
1336 /* When DCC cannot be enabled, try CMASK. */
1337 radv_image_disable_dcc(image);
1338 if (radv_image_can_enable_cmask(image)) {
1339 radv_image_alloc_cmask(device, image);
1340 }
1341 }
1342
1343 /* Try to enable FMASK for multisampled images. */
1344 if (radv_image_can_enable_fmask(image)) {
1345 radv_image_alloc_fmask(device, image);
1346
1347 if (radv_use_tc_compat_cmask_for_image(device, image))
1348 image->tc_compatible_cmask = true;
1349 } else {
1350 /* Otherwise, try to enable HTILE for depth surfaces. */
1351 if (radv_image_can_enable_htile(image) &&
1352 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1353 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1354 radv_image_alloc_htile(image);
1355 } else {
1356 radv_image_disable_htile(image);
1357 }
1358 }
1359 } else {
1360 radv_image_disable_dcc(image);
1361 radv_image_disable_htile(image);
1362 }
1363
1364 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1365 image->alignment = MAX2(image->alignment, 4096);
1366 image->size = align64(image->size, image->alignment);
1367 image->offset = 0;
1368
1369 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1370 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1371 if (!image->bo) {
1372 vk_free2(&device->alloc, alloc, image);
1373 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1374 }
1375 }
1376
1377 *pImage = radv_image_to_handle(image);
1378
1379 return VK_SUCCESS;
1380 }
1381
1382 static void
1383 radv_image_view_make_descriptor(struct radv_image_view *iview,
1384 struct radv_device *device,
1385 VkFormat vk_format,
1386 const VkComponentMapping *components,
1387 bool is_storage_image, unsigned plane_id,
1388 unsigned descriptor_plane_id)
1389 {
1390 struct radv_image *image = iview->image;
1391 struct radv_image_plane *plane = &image->planes[plane_id];
1392 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1393 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1394 uint32_t blk_w;
1395 union radv_descriptor *descriptor;
1396 uint32_t hw_level = 0;
1397
1398 if (is_storage_image) {
1399 descriptor = &iview->storage_descriptor;
1400 } else {
1401 descriptor = &iview->descriptor;
1402 }
1403
1404 assert(vk_format_get_plane_count(vk_format) == 1);
1405 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1406 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1407
1408 if (device->physical_device->rad_info.chip_class >= GFX9)
1409 hw_level = iview->base_mip;
1410 radv_make_texture_descriptor(device, image, is_storage_image,
1411 iview->type,
1412 vk_format,
1413 components,
1414 hw_level, hw_level + iview->level_count - 1,
1415 iview->base_layer,
1416 iview->base_layer + iview->layer_count - 1,
1417 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1418 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1419 iview->extent.depth,
1420 descriptor->plane_descriptors[descriptor_plane_id],
1421 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1422
1423 const struct legacy_surf_level *base_level_info = NULL;
1424 if (device->physical_device->rad_info.chip_class <= GFX9) {
1425 if (is_stencil)
1426 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1427 else
1428 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1429 }
1430 si_set_mutable_tex_desc_fields(device, image,
1431 base_level_info,
1432 plane_id,
1433 iview->base_mip,
1434 iview->base_mip,
1435 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1436 }
1437
1438 static unsigned
1439 radv_plane_from_aspect(VkImageAspectFlags mask)
1440 {
1441 switch(mask) {
1442 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1443 return 1;
1444 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1445 return 2;
1446 default:
1447 return 0;
1448 }
1449 }
1450
1451 VkFormat
1452 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1453 {
1454 switch(mask) {
1455 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1456 return image->planes[0].format;
1457 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1458 return image->planes[1].format;
1459 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1460 return image->planes[2].format;
1461 case VK_IMAGE_ASPECT_STENCIL_BIT:
1462 return vk_format_stencil_only(image->vk_format);
1463 case VK_IMAGE_ASPECT_DEPTH_BIT:
1464 return vk_format_depth_only(image->vk_format);
1465 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1466 return vk_format_depth_only(image->vk_format);
1467 default:
1468 return image->vk_format;
1469 }
1470 }
1471
1472 void
1473 radv_image_view_init(struct radv_image_view *iview,
1474 struct radv_device *device,
1475 const VkImageViewCreateInfo* pCreateInfo)
1476 {
1477 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1478 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1479
1480 switch (image->type) {
1481 case VK_IMAGE_TYPE_1D:
1482 case VK_IMAGE_TYPE_2D:
1483 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1484 break;
1485 case VK_IMAGE_TYPE_3D:
1486 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1487 <= radv_minify(image->info.depth, range->baseMipLevel));
1488 break;
1489 default:
1490 unreachable("bad VkImageType");
1491 }
1492 iview->image = image;
1493 iview->bo = image->bo;
1494 iview->type = pCreateInfo->viewType;
1495 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1496 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1497 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1498 iview->vk_format = pCreateInfo->format;
1499
1500 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1501 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1502 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1503 iview->vk_format = vk_format_depth_only(iview->vk_format);
1504 }
1505
1506 if (device->physical_device->rad_info.chip_class >= GFX9) {
1507 iview->extent = (VkExtent3D) {
1508 .width = image->info.width,
1509 .height = image->info.height,
1510 .depth = image->info.depth,
1511 };
1512 } else {
1513 iview->extent = (VkExtent3D) {
1514 .width = radv_minify(image->info.width , range->baseMipLevel),
1515 .height = radv_minify(image->info.height, range->baseMipLevel),
1516 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1517 };
1518 }
1519
1520 if (iview->vk_format != image->planes[iview->plane_id].format) {
1521 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1522 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1523 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1524 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1525
1526 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1527 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1528
1529 /* Comment ported from amdvlk -
1530 * If we have the following image:
1531 * Uncompressed pixels Compressed block sizes (4x4)
1532 * mip0: 22 x 22 6 x 6
1533 * mip1: 11 x 11 3 x 3
1534 * mip2: 5 x 5 2 x 2
1535 * mip3: 2 x 2 1 x 1
1536 * mip4: 1 x 1 1 x 1
1537 *
1538 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1539 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1540 * divide-by-two integer math):
1541 * mip0: 6x6
1542 * mip1: 3x3
1543 * mip2: 1x1
1544 * mip3: 1x1
1545 *
1546 * This means that mip2 will be missing texels.
1547 *
1548 * Fix this by calculating the base mip's width and height, then convert that, and round it
1549 * back up to get the level 0 size.
1550 * Clamp the converted size between the original values, and next power of two, which
1551 * means we don't oversize the image.
1552 */
1553 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1554 vk_format_is_compressed(image->vk_format) &&
1555 !vk_format_is_compressed(iview->vk_format)) {
1556 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1557 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1558
1559 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1560 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1561
1562 lvl_width <<= range->baseMipLevel;
1563 lvl_height <<= range->baseMipLevel;
1564
1565 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1566 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1567 }
1568 }
1569
1570 iview->base_layer = range->baseArrayLayer;
1571 iview->layer_count = radv_get_layerCount(image, range);
1572 iview->base_mip = range->baseMipLevel;
1573 iview->level_count = radv_get_levelCount(image, range);
1574
1575 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1576 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1577 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1578 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1579 }
1580 }
1581
1582 bool radv_layout_has_htile(const struct radv_image *image,
1583 VkImageLayout layout,
1584 unsigned queue_mask)
1585 {
1586 if (radv_image_is_tc_compat_htile(image))
1587 return layout != VK_IMAGE_LAYOUT_GENERAL;
1588
1589 return radv_image_has_htile(image) &&
1590 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1591 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1592 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1593 }
1594
1595 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1596 VkImageLayout layout,
1597 unsigned queue_mask)
1598 {
1599 if (radv_image_is_tc_compat_htile(image))
1600 return layout != VK_IMAGE_LAYOUT_GENERAL;
1601
1602 return radv_image_has_htile(image) &&
1603 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1604 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1605 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1606 }
1607
1608 bool radv_layout_can_fast_clear(const struct radv_image *image,
1609 VkImageLayout layout,
1610 unsigned queue_mask)
1611 {
1612 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1613 }
1614
1615 bool radv_layout_dcc_compressed(const struct radv_image *image,
1616 VkImageLayout layout,
1617 unsigned queue_mask)
1618 {
1619 /* Don't compress compute transfer dst, as image stores are not supported. */
1620 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1621 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1622 return false;
1623
1624 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1625 }
1626
1627
1628 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1629 {
1630 if (!image->exclusive)
1631 return image->queue_family_mask;
1632 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1633 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1634 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1635 if (family == VK_QUEUE_FAMILY_IGNORED)
1636 return 1u << queue_family;
1637 return 1u << family;
1638 }
1639
1640 VkResult
1641 radv_CreateImage(VkDevice device,
1642 const VkImageCreateInfo *pCreateInfo,
1643 const VkAllocationCallbacks *pAllocator,
1644 VkImage *pImage)
1645 {
1646 #ifdef ANDROID
1647 const VkNativeBufferANDROID *gralloc_info =
1648 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1649
1650 if (gralloc_info)
1651 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1652 pAllocator, pImage);
1653 #endif
1654
1655 const struct wsi_image_create_info *wsi_info =
1656 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1657 bool scanout = wsi_info && wsi_info->scanout;
1658
1659 return radv_image_create(device,
1660 &(struct radv_image_create_info) {
1661 .vk_info = pCreateInfo,
1662 .scanout = scanout,
1663 },
1664 pAllocator,
1665 pImage);
1666 }
1667
1668 void
1669 radv_DestroyImage(VkDevice _device, VkImage _image,
1670 const VkAllocationCallbacks *pAllocator)
1671 {
1672 RADV_FROM_HANDLE(radv_device, device, _device);
1673 RADV_FROM_HANDLE(radv_image, image, _image);
1674
1675 if (!image)
1676 return;
1677
1678 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1679 device->ws->buffer_destroy(image->bo);
1680
1681 if (image->owned_memory != VK_NULL_HANDLE)
1682 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1683
1684 vk_free2(&device->alloc, pAllocator, image);
1685 }
1686
1687 void radv_GetImageSubresourceLayout(
1688 VkDevice _device,
1689 VkImage _image,
1690 const VkImageSubresource* pSubresource,
1691 VkSubresourceLayout* pLayout)
1692 {
1693 RADV_FROM_HANDLE(radv_image, image, _image);
1694 RADV_FROM_HANDLE(radv_device, device, _device);
1695 int level = pSubresource->mipLevel;
1696 int layer = pSubresource->arrayLayer;
1697
1698 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1699
1700 struct radv_image_plane *plane = &image->planes[plane_id];
1701 struct radeon_surf *surface = &plane->surface;
1702
1703 if (device->physical_device->rad_info.chip_class >= GFX9) {
1704 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1705 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1706 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1707 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1708 /* Adjust the number of bytes between each row because
1709 * the pitch is actually the number of components per
1710 * row.
1711 */
1712 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1713 } else {
1714 assert(util_is_power_of_two_nonzero(surface->bpe));
1715 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1716 }
1717
1718 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1719 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1720 pLayout->size = surface->u.gfx9.surf_slice_size;
1721 if (image->type == VK_IMAGE_TYPE_3D)
1722 pLayout->size *= u_minify(image->info.depth, level);
1723 } else {
1724 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1725 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1726 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1727 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1728 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1729 if (image->type == VK_IMAGE_TYPE_3D)
1730 pLayout->size *= u_minify(image->info.depth, level);
1731 }
1732 }
1733
1734
1735 VkResult
1736 radv_CreateImageView(VkDevice _device,
1737 const VkImageViewCreateInfo *pCreateInfo,
1738 const VkAllocationCallbacks *pAllocator,
1739 VkImageView *pView)
1740 {
1741 RADV_FROM_HANDLE(radv_device, device, _device);
1742 struct radv_image_view *view;
1743
1744 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1745 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1746 if (view == NULL)
1747 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1748
1749 radv_image_view_init(view, device, pCreateInfo);
1750
1751 *pView = radv_image_view_to_handle(view);
1752
1753 return VK_SUCCESS;
1754 }
1755
1756 void
1757 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1758 const VkAllocationCallbacks *pAllocator)
1759 {
1760 RADV_FROM_HANDLE(radv_device, device, _device);
1761 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1762
1763 if (!iview)
1764 return;
1765 vk_free2(&device->alloc, pAllocator, iview);
1766 }
1767
1768 void radv_buffer_view_init(struct radv_buffer_view *view,
1769 struct radv_device *device,
1770 const VkBufferViewCreateInfo* pCreateInfo)
1771 {
1772 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1773
1774 view->bo = buffer->bo;
1775 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1776 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1777 view->vk_format = pCreateInfo->format;
1778
1779 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1780 pCreateInfo->offset, view->range, view->state);
1781 }
1782
1783 VkResult
1784 radv_CreateBufferView(VkDevice _device,
1785 const VkBufferViewCreateInfo *pCreateInfo,
1786 const VkAllocationCallbacks *pAllocator,
1787 VkBufferView *pView)
1788 {
1789 RADV_FROM_HANDLE(radv_device, device, _device);
1790 struct radv_buffer_view *view;
1791
1792 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1793 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1794 if (!view)
1795 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1796
1797 radv_buffer_view_init(view, device, pCreateInfo);
1798
1799 *pView = radv_buffer_view_to_handle(view);
1800
1801 return VK_SUCCESS;
1802 }
1803
1804 void
1805 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1806 const VkAllocationCallbacks *pAllocator)
1807 {
1808 RADV_FROM_HANDLE(radv_device, device, _device);
1809 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1810
1811 if (!view)
1812 return;
1813
1814 vk_free2(&device->alloc, pAllocator, view);
1815 }