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radv/gfx10: implement radv_make_buffer_descriptor()
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
175 device->physical_device->rad_info.chip_class >= GFX9)
176 return false;
177
178 /* Do not enable DCC for mipmapped arrays because performance is worse. */
179 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
180 return false;
181
182 if (radv_surface_has_scanout(device, create_info))
183 return false;
184
185 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
186 * 2x can be enabled with an option.
187 */
188 if (pCreateInfo->samples > 2 ||
189 (pCreateInfo->samples == 2 &&
190 !device->physical_device->dcc_msaa_allowed))
191 return false;
192
193 /* Determine if the formats are DCC compatible. */
194 dcc_compatible_formats =
195 radv_is_colorbuffer_format_supported(pCreateInfo->format,
196 &blendable);
197
198 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
199 const struct VkImageFormatListCreateInfoKHR *format_list =
200 (const struct VkImageFormatListCreateInfoKHR *)
201 vk_find_struct_const(pCreateInfo->pNext,
202 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
203
204 /* We have to ignore the existence of the list if viewFormatCount = 0 */
205 if (format_list && format_list->viewFormatCount) {
206 /* compatibility is transitive, so we only need to check
207 * one format with everything else. */
208 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
209 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
210 continue;
211
212 if (!radv_dcc_formats_compatible(pCreateInfo->format,
213 format_list->pViewFormats[i]))
214 dcc_compatible_formats = false;
215 }
216 } else {
217 dcc_compatible_formats = false;
218 }
219 }
220
221 if (!dcc_compatible_formats)
222 return false;
223
224 return true;
225 }
226
227 static bool
228 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
229 struct radv_image *image)
230 {
231 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
232 return false;
233
234 /* TC-compat CMASK is only available for GFX8+. */
235 if (device->physical_device->rad_info.chip_class < GFX8)
236 return false;
237
238 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
239 return false;
240
241 if (radv_image_has_dcc(image))
242 return false;
243
244 if (!radv_image_has_cmask(image))
245 return false;
246
247 return true;
248 }
249
250 static void
251 radv_prefill_surface_from_metadata(struct radv_device *device,
252 struct radeon_surf *surface,
253 const struct radv_image_create_info *create_info)
254 {
255 const struct radeon_bo_metadata *md = create_info->bo_metadata;
256 if (device->physical_device->rad_info.chip_class >= GFX9) {
257 if (md->u.gfx9.swizzle_mode > 0)
258 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
259 else
260 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
261
262 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
263 } else {
264 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
265 surface->u.legacy.bankw = md->u.legacy.bankw;
266 surface->u.legacy.bankh = md->u.legacy.bankh;
267 surface->u.legacy.tile_split = md->u.legacy.tile_split;
268 surface->u.legacy.mtilea = md->u.legacy.mtilea;
269 surface->u.legacy.num_banks = md->u.legacy.num_banks;
270
271 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
272 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
273 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
274 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
275 else
276 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
277
278 }
279 }
280
281 static int
282 radv_init_surface(struct radv_device *device,
283 const struct radv_image *image,
284 struct radeon_surf *surface,
285 unsigned plane_id,
286 const struct radv_image_create_info *create_info)
287 {
288 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
289 unsigned array_mode = radv_choose_tiling(device, create_info);
290 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
291 const struct vk_format_description *desc = vk_format_description(format);
292 bool is_depth, is_stencil;
293
294 is_depth = vk_format_has_depth(desc);
295 is_stencil = vk_format_has_stencil(desc);
296
297 surface->blk_w = vk_format_get_blockwidth(format);
298 surface->blk_h = vk_format_get_blockheight(format);
299
300 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
301 /* align byte per element on dword */
302 if (surface->bpe == 3) {
303 surface->bpe = 4;
304 }
305 if (create_info->bo_metadata) {
306 radv_prefill_surface_from_metadata(device, surface, create_info);
307 } else {
308 surface->flags = RADEON_SURF_SET(array_mode, MODE);
309 }
310
311 switch (pCreateInfo->imageType){
312 case VK_IMAGE_TYPE_1D:
313 if (pCreateInfo->arrayLayers > 1)
314 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
315 else
316 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
317 break;
318 case VK_IMAGE_TYPE_2D:
319 if (pCreateInfo->arrayLayers > 1)
320 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
321 else
322 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
323 break;
324 case VK_IMAGE_TYPE_3D:
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
326 break;
327 default:
328 unreachable("unhandled image type");
329 }
330
331 if (is_depth) {
332 surface->flags |= RADEON_SURF_ZBUFFER;
333 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
334 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
335 }
336
337 if (is_stencil)
338 surface->flags |= RADEON_SURF_SBUFFER;
339
340 if (device->physical_device->rad_info.chip_class >= GFX9 &&
341 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
342 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
343 vk_format_is_compressed(pCreateInfo->format))
344 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
345
346 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
347
348 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
349 surface->flags |= RADEON_SURF_DISABLE_DCC;
350
351 if (radv_surface_has_scanout(device, create_info))
352 surface->flags |= RADEON_SURF_SCANOUT;
353
354 return 0;
355 }
356
357 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
358 {
359 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
360 }
361
362 static inline unsigned
363 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
364 {
365 if (stencil)
366 return plane->surface.u.legacy.stencil_tiling_index[level];
367 else
368 return plane->surface.u.legacy.tiling_index[level];
369 }
370
371 static unsigned radv_map_swizzle(unsigned swizzle)
372 {
373 switch (swizzle) {
374 case VK_SWIZZLE_Y:
375 return V_008F0C_SQ_SEL_Y;
376 case VK_SWIZZLE_Z:
377 return V_008F0C_SQ_SEL_Z;
378 case VK_SWIZZLE_W:
379 return V_008F0C_SQ_SEL_W;
380 case VK_SWIZZLE_0:
381 return V_008F0C_SQ_SEL_0;
382 case VK_SWIZZLE_1:
383 return V_008F0C_SQ_SEL_1;
384 default: /* VK_SWIZZLE_X */
385 return V_008F0C_SQ_SEL_X;
386 }
387 }
388
389 static void
390 radv_make_buffer_descriptor(struct radv_device *device,
391 struct radv_buffer *buffer,
392 VkFormat vk_format,
393 unsigned offset,
394 unsigned range,
395 uint32_t *state)
396 {
397 const struct vk_format_description *desc;
398 unsigned stride;
399 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
400 uint64_t va = gpu_address + buffer->offset;
401 unsigned num_format, data_format;
402 int first_non_void;
403 desc = vk_format_description(vk_format);
404 first_non_void = vk_format_get_first_non_void_channel(vk_format);
405 stride = desc->block.bits / 8;
406
407 va += offset;
408 state[0] = va;
409 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
410 S_008F04_STRIDE(stride);
411
412 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
413 range /= stride;
414 }
415
416 state[2] = range;
417 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
418 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
419 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
420 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
421
422 if (device->physical_device->rad_info.chip_class >= GFX10) {
423 const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
424
425 /* OOB_SELECT chooses the out-of-bounds check:
426 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
427 * - 1: index >= NUM_RECORDS
428 * - 2: NUM_RECORDS == 0
429 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
430 * else: swizzle_address >= NUM_RECORDS
431 */
432 state[3] |= S_008F0C_FORMAT(fmt->img_format) |
433 S_008F0C_OOB_SELECT(0) |
434 S_008F0C_RESOURCE_LEVEL(1);
435 } else {
436 num_format = radv_translate_buffer_numformat(desc, first_non_void);
437 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
438
439 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
440 assert(num_format != ~0);
441
442 state[3] |= S_008F0C_NUM_FORMAT(num_format) |
443 S_008F0C_DATA_FORMAT(data_format);
444 }
445 }
446
447 static void
448 si_set_mutable_tex_desc_fields(struct radv_device *device,
449 struct radv_image *image,
450 const struct legacy_surf_level *base_level_info,
451 unsigned plane_id,
452 unsigned base_level, unsigned first_level,
453 unsigned block_width, bool is_stencil,
454 bool is_storage_image, uint32_t *state)
455 {
456 struct radv_image_plane *plane = &image->planes[plane_id];
457 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
458 uint64_t va = gpu_address + plane->offset;
459 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
460 uint64_t meta_va = 0;
461 if (chip_class >= GFX9) {
462 if (is_stencil)
463 va += plane->surface.u.gfx9.stencil_offset;
464 else
465 va += plane->surface.u.gfx9.surf_offset;
466 } else
467 va += base_level_info->offset;
468
469 state[0] = va >> 8;
470 if (chip_class >= GFX9 ||
471 base_level_info->mode == RADEON_SURF_MODE_2D)
472 state[0] |= plane->surface.tile_swizzle;
473 state[1] &= C_008F14_BASE_ADDRESS_HI;
474 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
475
476 if (chip_class >= GFX8) {
477 state[6] &= C_008F28_COMPRESSION_EN;
478 state[7] = 0;
479 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
480 meta_va = gpu_address + image->dcc_offset;
481 if (chip_class <= GFX8)
482 meta_va += base_level_info->dcc_offset;
483 } else if (!is_storage_image &&
484 radv_image_is_tc_compat_htile(image)) {
485 meta_va = gpu_address + image->htile_offset;
486 }
487
488 if (meta_va) {
489 state[6] |= S_008F28_COMPRESSION_EN(1);
490 if (chip_class <= GFX9) {
491 state[7] = meta_va >> 8;
492 state[7] |= plane->surface.tile_swizzle;
493 }
494 }
495 }
496
497 if (chip_class >= GFX10) {
498 state[3] &= C_00A00C_SW_MODE;
499
500 if (is_stencil) {
501 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
502 } else {
503 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
504 }
505
506 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
507 C_00A018_META_PIPE_ALIGNED;
508
509 if (meta_va) {
510 struct gfx9_surf_meta_flags meta;
511
512 if (image->dcc_offset)
513 meta = plane->surface.u.gfx9.dcc;
514 else
515 meta = plane->surface.u.gfx9.htile;
516
517 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
518 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
519 }
520
521 state[7] = meta_va >> 16;
522 } else if (chip_class >= GFX9) {
523 state[3] &= C_008F1C_SW_MODE;
524 state[4] &= C_008F20_PITCH;
525
526 if (is_stencil) {
527 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
528 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
529 } else {
530 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
531 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
532 }
533
534 state[5] &= C_008F24_META_DATA_ADDRESS &
535 C_008F24_META_PIPE_ALIGNED &
536 C_008F24_META_RB_ALIGNED;
537 if (meta_va) {
538 struct gfx9_surf_meta_flags meta;
539
540 if (image->dcc_offset)
541 meta = plane->surface.u.gfx9.dcc;
542 else
543 meta = plane->surface.u.gfx9.htile;
544
545 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
546 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
547 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
548 }
549 } else {
550 /* GFX6-GFX8 */
551 unsigned pitch = base_level_info->nblk_x * block_width;
552 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
553
554 state[3] &= C_008F1C_TILING_INDEX;
555 state[3] |= S_008F1C_TILING_INDEX(index);
556 state[4] &= C_008F20_PITCH;
557 state[4] |= S_008F20_PITCH(pitch - 1);
558 }
559 }
560
561 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
562 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
563 {
564 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
565 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
566
567 /* GFX9 allocates 1D textures as 2D. */
568 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
569 image_type = VK_IMAGE_TYPE_2D;
570 switch (image_type) {
571 case VK_IMAGE_TYPE_1D:
572 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
573 case VK_IMAGE_TYPE_2D:
574 if (nr_samples > 1)
575 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
576 else
577 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
578 case VK_IMAGE_TYPE_3D:
579 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
580 return V_008F1C_SQ_RSRC_IMG_3D;
581 else
582 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
583 default:
584 unreachable("illegal image type");
585 }
586 }
587
588 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
589 {
590 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
591
592 if (swizzle[3] == VK_SWIZZLE_X) {
593 /* For the pre-defined border color values (white, opaque
594 * black, transparent black), the only thing that matters is
595 * that the alpha channel winds up in the correct place
596 * (because the RGB channels are all the same) so either of
597 * these enumerations will work.
598 */
599 if (swizzle[2] == VK_SWIZZLE_Y)
600 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
601 else
602 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
603 } else if (swizzle[0] == VK_SWIZZLE_X) {
604 if (swizzle[1] == VK_SWIZZLE_Y)
605 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
606 else
607 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
608 } else if (swizzle[1] == VK_SWIZZLE_X) {
609 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
610 } else if (swizzle[2] == VK_SWIZZLE_X) {
611 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
612 }
613
614 return bc_swizzle;
615 }
616
617 /**
618 * Build the sampler view descriptor for a texture (GFX10).
619 */
620 static void
621 gfx10_make_texture_descriptor(struct radv_device *device,
622 struct radv_image *image,
623 bool is_storage_image,
624 VkImageViewType view_type,
625 VkFormat vk_format,
626 const VkComponentMapping *mapping,
627 unsigned first_level, unsigned last_level,
628 unsigned first_layer, unsigned last_layer,
629 unsigned width, unsigned height, unsigned depth,
630 uint32_t *state,
631 uint32_t *fmask_state)
632 {
633 const struct vk_format_description *desc;
634 enum vk_swizzle swizzle[4];
635 unsigned img_format;
636 unsigned type;
637
638 desc = vk_format_description(vk_format);
639 img_format = gfx10_format_table[vk_format].img_format;
640
641 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
642 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
643 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
644 } else {
645 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
646 }
647
648 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
649 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
650 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
651 height = 1;
652 depth = image->info.array_size;
653 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
654 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
655 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
656 depth = image->info.array_size;
657 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
658 depth = image->info.array_size / 6;
659
660 state[0] = 0;
661 state[1] = S_00A004_FORMAT(img_format) |
662 S_00A004_WIDTH_LO(width - 1);
663 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
664 S_00A008_HEIGHT(height - 1) |
665 S_00A008_RESOURCE_LEVEL(1);
666 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
667 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
668 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
669 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
670 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
671 0 : first_level) |
672 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
673 util_logbase2(image->info.samples) :
674 last_level) |
675 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
676 S_00A00C_TYPE(type);
677 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
678 * to know the total number of layers.
679 */
680 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
681 S_00A010_BASE_ARRAY(first_layer);
682 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
683 S_00A014_MAX_MIP(image->info.samples > 1 ?
684 util_logbase2(image->info.samples) :
685 image->info.levels - 1) |
686 S_00A014_PERF_MOD(4);
687 state[6] = 0;
688 state[7] = 0;
689
690 if (radv_dcc_enabled(image, first_level)) {
691 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
692
693 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
694 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
695 S_00A018_ALPHA_IS_ON_MSB(swap <= 1);
696 }
697
698 /* Initialize the sampler view for FMASK. */
699 if (radv_image_has_fmask(image)) {
700 uint64_t gpu_address = radv_buffer_get_va(image->bo);
701 uint32_t format;
702 uint64_t va;
703
704 assert(image->plane_count == 1);
705
706 va = gpu_address + image->offset + image->fmask.offset;
707
708 switch (image->info.samples) {
709 case 2:
710 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
711 break;
712 case 4:
713 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
714 break;
715 case 8:
716 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
717 break;
718 default:
719 unreachable("invalid nr_samples");
720 }
721
722 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
723 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
724 S_00A004_FORMAT(format) |
725 S_00A004_WIDTH_LO(width - 1);
726 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
727 S_00A008_HEIGHT(height - 1) |
728 S_00A008_RESOURCE_LEVEL(1);
729 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
730 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
731 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
732 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
733 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
734 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
735 fmask_state[4] = S_00A010_DEPTH(last_layer) |
736 S_00A010_BASE_ARRAY(first_layer);
737 fmask_state[5] = 0;
738 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
739 fmask_state[7] = 0;
740 } else if (fmask_state)
741 memset(fmask_state, 0, 8 * 4);
742 }
743
744 /**
745 * Build the sampler view descriptor for a texture (SI-GFX9)
746 */
747 static void
748 si_make_texture_descriptor(struct radv_device *device,
749 struct radv_image *image,
750 bool is_storage_image,
751 VkImageViewType view_type,
752 VkFormat vk_format,
753 const VkComponentMapping *mapping,
754 unsigned first_level, unsigned last_level,
755 unsigned first_layer, unsigned last_layer,
756 unsigned width, unsigned height, unsigned depth,
757 uint32_t *state,
758 uint32_t *fmask_state)
759 {
760 const struct vk_format_description *desc;
761 enum vk_swizzle swizzle[4];
762 int first_non_void;
763 unsigned num_format, data_format, type;
764
765 desc = vk_format_description(vk_format);
766
767 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
768 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
769 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
770 } else {
771 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
772 }
773
774 first_non_void = vk_format_get_first_non_void_channel(vk_format);
775
776 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
777 if (num_format == ~0) {
778 num_format = 0;
779 }
780
781 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
782 if (data_format == ~0) {
783 data_format = 0;
784 }
785
786 /* S8 with either Z16 or Z32 HTILE need a special format. */
787 if (device->physical_device->rad_info.chip_class >= GFX9 &&
788 vk_format == VK_FORMAT_S8_UINT &&
789 radv_image_is_tc_compat_htile(image)) {
790 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
791 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
792 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
793 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
794 }
795 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
796 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
797 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
798 height = 1;
799 depth = image->info.array_size;
800 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
801 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
802 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
803 depth = image->info.array_size;
804 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
805 depth = image->info.array_size / 6;
806
807 state[0] = 0;
808 state[1] = (S_008F14_DATA_FORMAT(data_format) |
809 S_008F14_NUM_FORMAT(num_format));
810 state[2] = (S_008F18_WIDTH(width - 1) |
811 S_008F18_HEIGHT(height - 1) |
812 S_008F18_PERF_MOD(4));
813 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
814 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
815 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
816 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
817 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
818 0 : first_level) |
819 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
820 util_logbase2(image->info.samples) :
821 last_level) |
822 S_008F1C_TYPE(type));
823 state[4] = 0;
824 state[5] = S_008F24_BASE_ARRAY(first_layer);
825 state[6] = 0;
826 state[7] = 0;
827
828 if (device->physical_device->rad_info.chip_class >= GFX9) {
829 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
830
831 /* Depth is the last accessible layer on Gfx9.
832 * The hw doesn't need to know the total number of layers.
833 */
834 if (type == V_008F1C_SQ_RSRC_IMG_3D)
835 state[4] |= S_008F20_DEPTH(depth - 1);
836 else
837 state[4] |= S_008F20_DEPTH(last_layer);
838
839 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
840 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
841 util_logbase2(image->info.samples) :
842 image->info.levels - 1);
843 } else {
844 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
845 state[4] |= S_008F20_DEPTH(depth - 1);
846 state[5] |= S_008F24_LAST_ARRAY(last_layer);
847 }
848 if (image->dcc_offset) {
849 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
850
851 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
852 } else {
853 /* The last dword is unused by hw. The shader uses it to clear
854 * bits in the first dword of sampler state.
855 */
856 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
857 if (first_level == last_level)
858 state[7] = C_008F30_MAX_ANISO_RATIO;
859 else
860 state[7] = 0xffffffff;
861 }
862 }
863
864 /* Initialize the sampler view for FMASK. */
865 if (radv_image_has_fmask(image)) {
866 uint32_t fmask_format, num_format;
867 uint64_t gpu_address = radv_buffer_get_va(image->bo);
868 uint64_t va;
869
870 assert(image->plane_count == 1);
871
872 va = gpu_address + image->offset + image->fmask.offset;
873
874 if (device->physical_device->rad_info.chip_class >= GFX9) {
875 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
876 switch (image->info.samples) {
877 case 2:
878 num_format = V_008F14_IMG_FMASK_8_2_2;
879 break;
880 case 4:
881 num_format = V_008F14_IMG_FMASK_8_4_4;
882 break;
883 case 8:
884 num_format = V_008F14_IMG_FMASK_32_8_8;
885 break;
886 default:
887 unreachable("invalid nr_samples");
888 }
889 } else {
890 switch (image->info.samples) {
891 case 2:
892 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
893 break;
894 case 4:
895 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
896 break;
897 case 8:
898 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
899 break;
900 default:
901 assert(0);
902 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
903 }
904 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
905 }
906
907 fmask_state[0] = va >> 8;
908 fmask_state[0] |= image->fmask.tile_swizzle;
909 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
910 S_008F14_DATA_FORMAT(fmask_format) |
911 S_008F14_NUM_FORMAT(num_format);
912 fmask_state[2] = S_008F18_WIDTH(width - 1) |
913 S_008F18_HEIGHT(height - 1);
914 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
915 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
916 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
917 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
918 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
919 fmask_state[4] = 0;
920 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
921 fmask_state[6] = 0;
922 fmask_state[7] = 0;
923
924 if (device->physical_device->rad_info.chip_class >= GFX9) {
925 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
926 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
927 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
928 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
929 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
930
931 if (radv_image_is_tc_compat_cmask(image)) {
932 va = gpu_address + image->offset + image->cmask.offset;
933
934 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
935 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
936 fmask_state[7] |= va >> 8;
937 }
938 } else {
939 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
940 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
941 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
942 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
943
944 if (radv_image_is_tc_compat_cmask(image)) {
945 va = gpu_address + image->offset + image->cmask.offset;
946
947 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
948 fmask_state[7] |= va >> 8;
949 }
950 }
951 } else if (fmask_state)
952 memset(fmask_state, 0, 8 * 4);
953 }
954
955 static void
956 radv_make_texture_descriptor(struct radv_device *device,
957 struct radv_image *image,
958 bool is_storage_image,
959 VkImageViewType view_type,
960 VkFormat vk_format,
961 const VkComponentMapping *mapping,
962 unsigned first_level, unsigned last_level,
963 unsigned first_layer, unsigned last_layer,
964 unsigned width, unsigned height, unsigned depth,
965 uint32_t *state,
966 uint32_t *fmask_state)
967 {
968 if (device->physical_device->rad_info.chip_class >= GFX10) {
969 gfx10_make_texture_descriptor(device, image, is_storage_image,
970 view_type, vk_format, mapping,
971 first_level, last_level,
972 first_layer, last_layer,
973 width, height, depth,
974 state, fmask_state);
975 } else {
976 si_make_texture_descriptor(device, image, is_storage_image,
977 view_type, vk_format, mapping,
978 first_level, last_level,
979 first_layer, last_layer,
980 width, height, depth,
981 state, fmask_state);
982 }
983 }
984
985 static void
986 radv_query_opaque_metadata(struct radv_device *device,
987 struct radv_image *image,
988 struct radeon_bo_metadata *md)
989 {
990 static const VkComponentMapping fixedmapping;
991 uint32_t desc[8], i;
992
993 assert(image->plane_count == 1);
994
995 /* Metadata image format format version 1:
996 * [0] = 1 (metadata format identifier)
997 * [1] = (VENDOR_ID << 16) | PCI_ID
998 * [2:9] = image descriptor for the whole resource
999 * [2] is always 0, because the base address is cleared
1000 * [9] is the DCC offset bits [39:8] from the beginning of
1001 * the buffer
1002 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1003 */
1004 md->metadata[0] = 1; /* metadata image format version 1 */
1005
1006 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1007 md->metadata[1] = si_get_bo_metadata_word1(device);
1008
1009
1010 radv_make_texture_descriptor(device, image, false,
1011 (VkImageViewType)image->type, image->vk_format,
1012 &fixedmapping, 0, image->info.levels - 1, 0,
1013 image->info.array_size - 1,
1014 image->info.width, image->info.height,
1015 image->info.depth,
1016 desc, NULL);
1017
1018 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1019 image->planes[0].surface.blk_w, false, false, desc);
1020
1021 /* Clear the base address and set the relative DCC offset. */
1022 desc[0] = 0;
1023 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1024 desc[7] = image->dcc_offset >> 8;
1025
1026 /* Dwords [2:9] contain the image descriptor. */
1027 memcpy(&md->metadata[2], desc, sizeof(desc));
1028
1029 /* Dwords [10:..] contain the mipmap level offsets. */
1030 if (device->physical_device->rad_info.chip_class <= GFX8) {
1031 for (i = 0; i <= image->info.levels - 1; i++)
1032 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1033 md->size_metadata = (11 + image->info.levels - 1) * 4;
1034 }
1035 }
1036
1037 void
1038 radv_init_metadata(struct radv_device *device,
1039 struct radv_image *image,
1040 struct radeon_bo_metadata *metadata)
1041 {
1042 struct radeon_surf *surface = &image->planes[0].surface;
1043
1044 memset(metadata, 0, sizeof(*metadata));
1045
1046 if (device->physical_device->rad_info.chip_class >= GFX9) {
1047 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1048 } else {
1049 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1050 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1051 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1052 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1053 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1054 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1055 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1056 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1057 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1058 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1059 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1060 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1061 }
1062 radv_query_opaque_metadata(device, image, metadata);
1063 }
1064
1065 void
1066 radv_image_override_offset_stride(struct radv_device *device,
1067 struct radv_image *image,
1068 uint64_t offset, uint32_t stride)
1069 {
1070 struct radeon_surf *surface = &image->planes[0].surface;
1071 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1072
1073 if (device->physical_device->rad_info.chip_class >= GFX9) {
1074 if (stride) {
1075 surface->u.gfx9.surf_pitch = stride;
1076 surface->u.gfx9.surf_slice_size =
1077 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1078 }
1079 surface->u.gfx9.surf_offset = offset;
1080 } else {
1081 surface->u.legacy.level[0].nblk_x = stride;
1082 surface->u.legacy.level[0].slice_size_dw =
1083 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1084
1085 if (offset) {
1086 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1087 surface->u.legacy.level[i].offset += offset;
1088 }
1089
1090 }
1091 }
1092
1093 /* The number of samples can be specified independently of the texture. */
1094 static void
1095 radv_image_get_fmask_info(struct radv_device *device,
1096 struct radv_image *image,
1097 unsigned nr_samples,
1098 struct radv_fmask_info *out)
1099 {
1100 if (device->physical_device->rad_info.chip_class >= GFX9) {
1101 out->alignment = image->planes[0].surface.fmask_alignment;
1102 out->size = image->planes[0].surface.fmask_size;
1103 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1104 return;
1105 }
1106
1107 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
1108 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
1109 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
1110 out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
1111 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
1112 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1113 out->alignment = image->planes[0].surface.fmask_alignment;
1114 out->size = image->planes[0].surface.fmask_size;
1115
1116 assert(!out->tile_swizzle || !image->shareable);
1117 }
1118
1119 static void
1120 radv_image_alloc_fmask(struct radv_device *device,
1121 struct radv_image *image)
1122 {
1123 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
1124
1125 image->fmask.offset = align64(image->size, image->fmask.alignment);
1126 image->size = image->fmask.offset + image->fmask.size;
1127 image->alignment = MAX2(image->alignment, image->fmask.alignment);
1128 }
1129
1130 static void
1131 radv_image_get_cmask_info(struct radv_device *device,
1132 struct radv_image *image,
1133 struct radv_cmask_info *out)
1134 {
1135 assert(image->plane_count == 1);
1136
1137 if (device->physical_device->rad_info.chip_class >= GFX9) {
1138 out->alignment = image->planes[0].surface.cmask_alignment;
1139 out->size = image->planes[0].surface.cmask_size;
1140 return;
1141 }
1142
1143 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
1144 out->alignment = image->planes[0].surface.cmask_alignment;
1145 out->slice_size = image->planes[0].surface.cmask_slice_size;
1146 out->size = image->planes[0].surface.cmask_size;
1147 }
1148
1149 static void
1150 radv_image_alloc_cmask(struct radv_device *device,
1151 struct radv_image *image)
1152 {
1153 uint32_t clear_value_size = 0;
1154 radv_image_get_cmask_info(device, image, &image->cmask);
1155
1156 image->cmask.offset = align64(image->size, image->cmask.alignment);
1157 /* + 8 for storing the clear values */
1158 if (!image->clear_value_offset) {
1159 image->clear_value_offset = image->cmask.offset + image->cmask.size;
1160 clear_value_size = 8;
1161 }
1162 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
1163 image->alignment = MAX2(image->alignment, image->cmask.alignment);
1164 }
1165
1166 static void
1167 radv_image_alloc_dcc(struct radv_image *image)
1168 {
1169 assert(image->plane_count == 1);
1170
1171 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1172 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1173 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1174 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1175 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1176 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1177 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1178 }
1179
1180 static void
1181 radv_image_alloc_htile(struct radv_image *image)
1182 {
1183 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1184
1185 /* + 8 for storing the clear values */
1186 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1187 image->size = image->clear_value_offset + 8;
1188 if (radv_image_is_tc_compat_htile(image)) {
1189 /* Metadata for the TC-compatible HTILE hardware bug which
1190 * have to be fixed by updating ZRANGE_PRECISION when doing
1191 * fast depth clears to 0.0f.
1192 */
1193 image->tc_compat_zrange_offset = image->size;
1194 image->size = image->tc_compat_zrange_offset + 4;
1195 }
1196 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1197 }
1198
1199 static inline bool
1200 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1201 {
1202 if (image->info.samples <= 1 &&
1203 image->info.width * image->info.height <= 512 * 512) {
1204 /* Do not enable CMASK or DCC for small surfaces where the cost
1205 * of the eliminate pass can be higher than the benefit of fast
1206 * clear. RadeonSI does this, but the image threshold is
1207 * different.
1208 */
1209 return false;
1210 }
1211
1212 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1213 (image->exclusive || image->queue_family_mask == 1);
1214 }
1215
1216 static inline bool
1217 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1218 {
1219 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1220 !radv_image_has_dcc(image))
1221 return false;
1222
1223 /* On GFX8, DCC layers can be interleaved and it's currently only
1224 * enabled if slice size is equal to the per slice fast clear size
1225 * because the driver assumes that portions of multiple layers are
1226 * contiguous during fast clears.
1227 */
1228 if (image->info.array_size > 1) {
1229 const struct legacy_surf_level *surf_level =
1230 &image->planes[0].surface.u.legacy.level[0];
1231
1232 assert(device->physical_device->rad_info.chip_class == GFX8);
1233
1234 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1235 return false;
1236 }
1237
1238 return true;
1239 }
1240
1241 static inline bool
1242 radv_image_can_enable_cmask(struct radv_image *image)
1243 {
1244 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1245 /* Do not enable CMASK for non-MSAA images (fast color clear)
1246 * because 128 bit formats are not supported, but FMASK might
1247 * still be used.
1248 */
1249 return false;
1250 }
1251
1252 return radv_image_can_enable_dcc_or_cmask(image) &&
1253 image->info.levels == 1 &&
1254 image->info.depth == 1 &&
1255 !image->planes[0].surface.is_linear;
1256 }
1257
1258 static inline bool
1259 radv_image_can_enable_fmask(struct radv_image *image)
1260 {
1261 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1262 }
1263
1264 static inline bool
1265 radv_image_can_enable_htile(struct radv_image *image)
1266 {
1267 return radv_image_has_htile(image) &&
1268 image->info.levels == 1 &&
1269 image->info.width * image->info.height >= 8 * 8;
1270 }
1271
1272 static void radv_image_disable_dcc(struct radv_image *image)
1273 {
1274 for (unsigned i = 0; i < image->plane_count; ++i)
1275 image->planes[i].surface.dcc_size = 0;
1276 }
1277
1278 static void radv_image_disable_htile(struct radv_image *image)
1279 {
1280 for (unsigned i = 0; i < image->plane_count; ++i)
1281 image->planes[i].surface.htile_size = 0;
1282 }
1283
1284 VkResult
1285 radv_image_create(VkDevice _device,
1286 const struct radv_image_create_info *create_info,
1287 const VkAllocationCallbacks* alloc,
1288 VkImage *pImage)
1289 {
1290 RADV_FROM_HANDLE(radv_device, device, _device);
1291 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1292 struct radv_image *image = NULL;
1293 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1294
1295 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1296 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1297
1298 radv_assert(pCreateInfo->mipLevels > 0);
1299 radv_assert(pCreateInfo->arrayLayers > 0);
1300 radv_assert(pCreateInfo->samples > 0);
1301 radv_assert(pCreateInfo->extent.width > 0);
1302 radv_assert(pCreateInfo->extent.height > 0);
1303 radv_assert(pCreateInfo->extent.depth > 0);
1304
1305 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1306 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1307 if (!image)
1308 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1309
1310 image->type = pCreateInfo->imageType;
1311 image->info.width = pCreateInfo->extent.width;
1312 image->info.height = pCreateInfo->extent.height;
1313 image->info.depth = pCreateInfo->extent.depth;
1314 image->info.samples = pCreateInfo->samples;
1315 image->info.storage_samples = pCreateInfo->samples;
1316 image->info.array_size = pCreateInfo->arrayLayers;
1317 image->info.levels = pCreateInfo->mipLevels;
1318 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1319
1320 image->vk_format = pCreateInfo->format;
1321 image->tiling = pCreateInfo->tiling;
1322 image->usage = pCreateInfo->usage;
1323 image->flags = pCreateInfo->flags;
1324
1325 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1326 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1327 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1328 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1329 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1330 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1331 else
1332 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1333 }
1334
1335 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1336 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1337 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1338 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1339 image->info.surf_index = &device->image_mrt_offset_counter;
1340 }
1341
1342 image->plane_count = plane_count;
1343 image->size = 0;
1344 image->alignment = 1;
1345 for (unsigned plane = 0; plane < plane_count; ++plane) {
1346 struct ac_surf_info info = image->info;
1347 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1348
1349 if (plane) {
1350 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1351 assert(info.width % desc->width_divisor == 0);
1352 assert(info.height % desc->height_divisor == 0);
1353
1354 info.width /= desc->width_divisor;
1355 info.height /= desc->height_divisor;
1356 }
1357
1358 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1359
1360 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1361 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1362 image->alignment = image->planes[plane].surface.surf_alignment;
1363
1364 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1365 }
1366
1367 if (!create_info->no_metadata_planes) {
1368 /* Try to enable DCC first. */
1369 if (radv_image_can_enable_dcc(device, image)) {
1370 radv_image_alloc_dcc(image);
1371 if (image->info.samples > 1) {
1372 /* CMASK should be enabled because DCC fast
1373 * clear with MSAA needs it.
1374 */
1375 assert(radv_image_can_enable_cmask(image));
1376 radv_image_alloc_cmask(device, image);
1377 }
1378 } else {
1379 /* When DCC cannot be enabled, try CMASK. */
1380 radv_image_disable_dcc(image);
1381 if (radv_image_can_enable_cmask(image)) {
1382 radv_image_alloc_cmask(device, image);
1383 }
1384 }
1385
1386 /* Try to enable FMASK for multisampled images. */
1387 if (radv_image_can_enable_fmask(image)) {
1388 radv_image_alloc_fmask(device, image);
1389
1390 if (radv_use_tc_compat_cmask_for_image(device, image))
1391 image->tc_compatible_cmask = true;
1392 } else {
1393 /* Otherwise, try to enable HTILE for depth surfaces. */
1394 if (radv_image_can_enable_htile(image) &&
1395 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1396 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1397 radv_image_alloc_htile(image);
1398 } else {
1399 radv_image_disable_htile(image);
1400 }
1401 }
1402 } else {
1403 radv_image_disable_dcc(image);
1404 radv_image_disable_htile(image);
1405 }
1406
1407 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1408 image->alignment = MAX2(image->alignment, 4096);
1409 image->size = align64(image->size, image->alignment);
1410 image->offset = 0;
1411
1412 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1413 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1414 if (!image->bo) {
1415 vk_free2(&device->alloc, alloc, image);
1416 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1417 }
1418 }
1419
1420 *pImage = radv_image_to_handle(image);
1421
1422 return VK_SUCCESS;
1423 }
1424
1425 static void
1426 radv_image_view_make_descriptor(struct radv_image_view *iview,
1427 struct radv_device *device,
1428 VkFormat vk_format,
1429 const VkComponentMapping *components,
1430 bool is_storage_image, unsigned plane_id,
1431 unsigned descriptor_plane_id)
1432 {
1433 struct radv_image *image = iview->image;
1434 struct radv_image_plane *plane = &image->planes[plane_id];
1435 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1436 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1437 uint32_t blk_w;
1438 union radv_descriptor *descriptor;
1439 uint32_t hw_level = 0;
1440
1441 if (is_storage_image) {
1442 descriptor = &iview->storage_descriptor;
1443 } else {
1444 descriptor = &iview->descriptor;
1445 }
1446
1447 assert(vk_format_get_plane_count(vk_format) == 1);
1448 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1449 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1450
1451 if (device->physical_device->rad_info.chip_class >= GFX9)
1452 hw_level = iview->base_mip;
1453 radv_make_texture_descriptor(device, image, is_storage_image,
1454 iview->type,
1455 vk_format,
1456 components,
1457 hw_level, hw_level + iview->level_count - 1,
1458 iview->base_layer,
1459 iview->base_layer + iview->layer_count - 1,
1460 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1461 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1462 iview->extent.depth,
1463 descriptor->plane_descriptors[descriptor_plane_id],
1464 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1465
1466 const struct legacy_surf_level *base_level_info = NULL;
1467 if (device->physical_device->rad_info.chip_class <= GFX9) {
1468 if (is_stencil)
1469 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1470 else
1471 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1472 }
1473 si_set_mutable_tex_desc_fields(device, image,
1474 base_level_info,
1475 plane_id,
1476 iview->base_mip,
1477 iview->base_mip,
1478 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1479 }
1480
1481 static unsigned
1482 radv_plane_from_aspect(VkImageAspectFlags mask)
1483 {
1484 switch(mask) {
1485 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1486 return 1;
1487 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1488 return 2;
1489 default:
1490 return 0;
1491 }
1492 }
1493
1494 VkFormat
1495 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1496 {
1497 switch(mask) {
1498 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1499 return image->planes[0].format;
1500 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1501 return image->planes[1].format;
1502 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1503 return image->planes[2].format;
1504 case VK_IMAGE_ASPECT_STENCIL_BIT:
1505 return vk_format_stencil_only(image->vk_format);
1506 case VK_IMAGE_ASPECT_DEPTH_BIT:
1507 return vk_format_depth_only(image->vk_format);
1508 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1509 return vk_format_depth_only(image->vk_format);
1510 default:
1511 return image->vk_format;
1512 }
1513 }
1514
1515 void
1516 radv_image_view_init(struct radv_image_view *iview,
1517 struct radv_device *device,
1518 const VkImageViewCreateInfo* pCreateInfo)
1519 {
1520 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1521 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1522
1523 switch (image->type) {
1524 case VK_IMAGE_TYPE_1D:
1525 case VK_IMAGE_TYPE_2D:
1526 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1527 break;
1528 case VK_IMAGE_TYPE_3D:
1529 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1530 <= radv_minify(image->info.depth, range->baseMipLevel));
1531 break;
1532 default:
1533 unreachable("bad VkImageType");
1534 }
1535 iview->image = image;
1536 iview->bo = image->bo;
1537 iview->type = pCreateInfo->viewType;
1538 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1539 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1540 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1541 iview->vk_format = pCreateInfo->format;
1542
1543 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1544 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1545 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1546 iview->vk_format = vk_format_depth_only(iview->vk_format);
1547 }
1548
1549 if (device->physical_device->rad_info.chip_class >= GFX9) {
1550 iview->extent = (VkExtent3D) {
1551 .width = image->info.width,
1552 .height = image->info.height,
1553 .depth = image->info.depth,
1554 };
1555 } else {
1556 iview->extent = (VkExtent3D) {
1557 .width = radv_minify(image->info.width , range->baseMipLevel),
1558 .height = radv_minify(image->info.height, range->baseMipLevel),
1559 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1560 };
1561 }
1562
1563 if (iview->vk_format != image->planes[iview->plane_id].format) {
1564 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1565 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1566 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1567 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1568
1569 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1570 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1571
1572 /* Comment ported from amdvlk -
1573 * If we have the following image:
1574 * Uncompressed pixels Compressed block sizes (4x4)
1575 * mip0: 22 x 22 6 x 6
1576 * mip1: 11 x 11 3 x 3
1577 * mip2: 5 x 5 2 x 2
1578 * mip3: 2 x 2 1 x 1
1579 * mip4: 1 x 1 1 x 1
1580 *
1581 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1582 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1583 * divide-by-two integer math):
1584 * mip0: 6x6
1585 * mip1: 3x3
1586 * mip2: 1x1
1587 * mip3: 1x1
1588 *
1589 * This means that mip2 will be missing texels.
1590 *
1591 * Fix this by calculating the base mip's width and height, then convert that, and round it
1592 * back up to get the level 0 size.
1593 * Clamp the converted size between the original values, and next power of two, which
1594 * means we don't oversize the image.
1595 */
1596 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1597 vk_format_is_compressed(image->vk_format) &&
1598 !vk_format_is_compressed(iview->vk_format)) {
1599 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1600 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1601
1602 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1603 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1604
1605 lvl_width <<= range->baseMipLevel;
1606 lvl_height <<= range->baseMipLevel;
1607
1608 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1609 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1610 }
1611 }
1612
1613 iview->base_layer = range->baseArrayLayer;
1614 iview->layer_count = radv_get_layerCount(image, range);
1615 iview->base_mip = range->baseMipLevel;
1616 iview->level_count = radv_get_levelCount(image, range);
1617
1618 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1619 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1620 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1621 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1622 }
1623 }
1624
1625 bool radv_layout_has_htile(const struct radv_image *image,
1626 VkImageLayout layout,
1627 unsigned queue_mask)
1628 {
1629 if (radv_image_is_tc_compat_htile(image))
1630 return layout != VK_IMAGE_LAYOUT_GENERAL;
1631
1632 return radv_image_has_htile(image) &&
1633 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1634 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1635 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1636 }
1637
1638 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1639 VkImageLayout layout,
1640 unsigned queue_mask)
1641 {
1642 if (radv_image_is_tc_compat_htile(image))
1643 return layout != VK_IMAGE_LAYOUT_GENERAL;
1644
1645 return radv_image_has_htile(image) &&
1646 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1647 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1648 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1649 }
1650
1651 bool radv_layout_can_fast_clear(const struct radv_image *image,
1652 VkImageLayout layout,
1653 unsigned queue_mask)
1654 {
1655 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1656 }
1657
1658 bool radv_layout_dcc_compressed(const struct radv_image *image,
1659 VkImageLayout layout,
1660 unsigned queue_mask)
1661 {
1662 /* Don't compress compute transfer dst, as image stores are not supported. */
1663 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1664 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1665 return false;
1666
1667 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1668 }
1669
1670
1671 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1672 {
1673 if (!image->exclusive)
1674 return image->queue_family_mask;
1675 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1676 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1677 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1678 if (family == VK_QUEUE_FAMILY_IGNORED)
1679 return 1u << queue_family;
1680 return 1u << family;
1681 }
1682
1683 VkResult
1684 radv_CreateImage(VkDevice device,
1685 const VkImageCreateInfo *pCreateInfo,
1686 const VkAllocationCallbacks *pAllocator,
1687 VkImage *pImage)
1688 {
1689 #ifdef ANDROID
1690 const VkNativeBufferANDROID *gralloc_info =
1691 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1692
1693 if (gralloc_info)
1694 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1695 pAllocator, pImage);
1696 #endif
1697
1698 const struct wsi_image_create_info *wsi_info =
1699 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1700 bool scanout = wsi_info && wsi_info->scanout;
1701
1702 return radv_image_create(device,
1703 &(struct radv_image_create_info) {
1704 .vk_info = pCreateInfo,
1705 .scanout = scanout,
1706 },
1707 pAllocator,
1708 pImage);
1709 }
1710
1711 void
1712 radv_DestroyImage(VkDevice _device, VkImage _image,
1713 const VkAllocationCallbacks *pAllocator)
1714 {
1715 RADV_FROM_HANDLE(radv_device, device, _device);
1716 RADV_FROM_HANDLE(radv_image, image, _image);
1717
1718 if (!image)
1719 return;
1720
1721 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1722 device->ws->buffer_destroy(image->bo);
1723
1724 if (image->owned_memory != VK_NULL_HANDLE)
1725 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1726
1727 vk_free2(&device->alloc, pAllocator, image);
1728 }
1729
1730 void radv_GetImageSubresourceLayout(
1731 VkDevice _device,
1732 VkImage _image,
1733 const VkImageSubresource* pSubresource,
1734 VkSubresourceLayout* pLayout)
1735 {
1736 RADV_FROM_HANDLE(radv_image, image, _image);
1737 RADV_FROM_HANDLE(radv_device, device, _device);
1738 int level = pSubresource->mipLevel;
1739 int layer = pSubresource->arrayLayer;
1740
1741 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1742
1743 struct radv_image_plane *plane = &image->planes[plane_id];
1744 struct radeon_surf *surface = &plane->surface;
1745
1746 if (device->physical_device->rad_info.chip_class >= GFX9) {
1747 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1748 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1749 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1750 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1751 /* Adjust the number of bytes between each row because
1752 * the pitch is actually the number of components per
1753 * row.
1754 */
1755 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1756 } else {
1757 assert(util_is_power_of_two_nonzero(surface->bpe));
1758 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1759 }
1760
1761 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1762 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1763 pLayout->size = surface->u.gfx9.surf_slice_size;
1764 if (image->type == VK_IMAGE_TYPE_3D)
1765 pLayout->size *= u_minify(image->info.depth, level);
1766 } else {
1767 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1768 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1769 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1770 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1771 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1772 if (image->type == VK_IMAGE_TYPE_3D)
1773 pLayout->size *= u_minify(image->info.depth, level);
1774 }
1775 }
1776
1777
1778 VkResult
1779 radv_CreateImageView(VkDevice _device,
1780 const VkImageViewCreateInfo *pCreateInfo,
1781 const VkAllocationCallbacks *pAllocator,
1782 VkImageView *pView)
1783 {
1784 RADV_FROM_HANDLE(radv_device, device, _device);
1785 struct radv_image_view *view;
1786
1787 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1788 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1789 if (view == NULL)
1790 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1791
1792 radv_image_view_init(view, device, pCreateInfo);
1793
1794 *pView = radv_image_view_to_handle(view);
1795
1796 return VK_SUCCESS;
1797 }
1798
1799 void
1800 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1801 const VkAllocationCallbacks *pAllocator)
1802 {
1803 RADV_FROM_HANDLE(radv_device, device, _device);
1804 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1805
1806 if (!iview)
1807 return;
1808 vk_free2(&device->alloc, pAllocator, iview);
1809 }
1810
1811 void radv_buffer_view_init(struct radv_buffer_view *view,
1812 struct radv_device *device,
1813 const VkBufferViewCreateInfo* pCreateInfo)
1814 {
1815 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1816
1817 view->bo = buffer->bo;
1818 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1819 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1820 view->vk_format = pCreateInfo->format;
1821
1822 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1823 pCreateInfo->offset, view->range, view->state);
1824 }
1825
1826 VkResult
1827 radv_CreateBufferView(VkDevice _device,
1828 const VkBufferViewCreateInfo *pCreateInfo,
1829 const VkAllocationCallbacks *pAllocator,
1830 VkBufferView *pView)
1831 {
1832 RADV_FROM_HANDLE(radv_device, device, _device);
1833 struct radv_buffer_view *view;
1834
1835 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1836 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1837 if (!view)
1838 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1839
1840 radv_buffer_view_init(view, device, pCreateInfo);
1841
1842 *pView = radv_buffer_view_to_handle(view);
1843
1844 return VK_SUCCESS;
1845 }
1846
1847 void
1848 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1849 const VkAllocationCallbacks *pAllocator)
1850 {
1851 RADV_FROM_HANDLE(radv_device, device, _device);
1852 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1853
1854 if (!view)
1855 return;
1856
1857 vk_free2(&device->alloc, pAllocator, view);
1858 }