2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo
->samples
>= 2 &&
88 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
95 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
96 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
97 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
100 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
101 const struct VkImageFormatListCreateInfoKHR
*format_list
=
102 (const struct VkImageFormatListCreateInfoKHR
*)
103 vk_find_struct_const(pCreateInfo
->pNext
,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list
&& format_list
->viewFormatCount
) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
111 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
112 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
115 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
127 radv_surface_has_scanout(struct radv_device
*device
, const struct radv_image_create_info
*info
)
132 if (!info
->bo_metadata
)
135 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
136 return info
->bo_metadata
->u
.gfx9
.swizzle_mode
== 0 || info
->bo_metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
138 return info
->bo_metadata
->u
.legacy
.scanout
;
143 radv_use_dcc_for_image(struct radv_device
*device
,
144 const struct radv_image
*image
,
145 const struct radv_image_create_info
*create_info
,
146 const VkImageCreateInfo
*pCreateInfo
)
148 bool dcc_compatible_formats
;
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
155 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
158 if (image
->shareable
)
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
163 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
166 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
169 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
170 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
173 /* TODO: Enable DCC for mipmaps and array layers. */
174 if (pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1)
177 if (radv_surface_has_scanout(device
, create_info
))
180 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
181 * 2x can be enabled with an option.
183 if (pCreateInfo
->samples
> 2 ||
184 (pCreateInfo
->samples
== 2 &&
185 !device
->physical_device
->dcc_msaa_allowed
))
188 /* Determine if the formats are DCC compatible. */
189 dcc_compatible_formats
=
190 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
193 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
194 const struct VkImageFormatListCreateInfoKHR
*format_list
=
195 (const struct VkImageFormatListCreateInfoKHR
*)
196 vk_find_struct_const(pCreateInfo
->pNext
,
197 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
199 /* We have to ignore the existence of the list if viewFormatCount = 0 */
200 if (format_list
&& format_list
->viewFormatCount
) {
201 /* compatibility is transitive, so we only need to check
202 * one format with everything else. */
203 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
204 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
207 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
208 format_list
->pViewFormats
[i
]))
209 dcc_compatible_formats
= false;
212 dcc_compatible_formats
= false;
216 if (!dcc_compatible_formats
)
223 radv_prefill_surface_from_metadata(struct radv_device
*device
,
224 struct radeon_surf
*surface
,
225 const struct radv_image_create_info
*create_info
)
227 const struct radeon_bo_metadata
*md
= create_info
->bo_metadata
;
228 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
229 if (md
->u
.gfx9
.swizzle_mode
> 0)
230 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
232 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
234 surface
->u
.gfx9
.surf
.swizzle_mode
= md
->u
.gfx9
.swizzle_mode
;
236 surface
->u
.legacy
.pipe_config
= md
->u
.legacy
.pipe_config
;
237 surface
->u
.legacy
.bankw
= md
->u
.legacy
.bankw
;
238 surface
->u
.legacy
.bankh
= md
->u
.legacy
.bankh
;
239 surface
->u
.legacy
.tile_split
= md
->u
.legacy
.tile_split
;
240 surface
->u
.legacy
.mtilea
= md
->u
.legacy
.mtilea
;
241 surface
->u
.legacy
.num_banks
= md
->u
.legacy
.num_banks
;
243 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
244 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
245 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
246 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
248 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
254 radv_init_surface(struct radv_device
*device
,
255 const struct radv_image
*image
,
256 struct radeon_surf
*surface
,
258 const struct radv_image_create_info
*create_info
)
260 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
261 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
262 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
263 const struct vk_format_description
*desc
= vk_format_description(format
);
264 bool is_depth
, is_stencil
;
266 is_depth
= vk_format_has_depth(desc
);
267 is_stencil
= vk_format_has_stencil(desc
);
269 surface
->blk_w
= vk_format_get_blockwidth(format
);
270 surface
->blk_h
= vk_format_get_blockheight(format
);
272 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
273 /* align byte per element on dword */
274 if (surface
->bpe
== 3) {
277 if (create_info
->bo_metadata
) {
278 radv_prefill_surface_from_metadata(device
, surface
, create_info
);
280 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
283 switch (pCreateInfo
->imageType
){
284 case VK_IMAGE_TYPE_1D
:
285 if (pCreateInfo
->arrayLayers
> 1)
286 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
288 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
290 case VK_IMAGE_TYPE_2D
:
291 if (pCreateInfo
->arrayLayers
> 1)
292 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
294 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
296 case VK_IMAGE_TYPE_3D
:
297 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
300 unreachable("unhandled image type");
304 surface
->flags
|= RADEON_SURF_ZBUFFER
;
305 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
306 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
310 surface
->flags
|= RADEON_SURF_SBUFFER
;
312 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
313 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
314 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
315 vk_format_is_compressed(pCreateInfo
->format
))
316 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
318 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
320 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
321 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
323 if (radv_surface_has_scanout(device
, create_info
))
324 surface
->flags
|= RADEON_SURF_SCANOUT
;
329 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
331 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
334 static inline unsigned
335 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
338 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
340 return plane
->surface
.u
.legacy
.tiling_index
[level
];
343 static unsigned radv_map_swizzle(unsigned swizzle
)
347 return V_008F0C_SQ_SEL_Y
;
349 return V_008F0C_SQ_SEL_Z
;
351 return V_008F0C_SQ_SEL_W
;
353 return V_008F0C_SQ_SEL_0
;
355 return V_008F0C_SQ_SEL_1
;
356 default: /* VK_SWIZZLE_X */
357 return V_008F0C_SQ_SEL_X
;
362 radv_make_buffer_descriptor(struct radv_device
*device
,
363 struct radv_buffer
*buffer
,
369 const struct vk_format_description
*desc
;
371 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
372 uint64_t va
= gpu_address
+ buffer
->offset
;
373 unsigned num_format
, data_format
;
375 desc
= vk_format_description(vk_format
);
376 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
377 stride
= desc
->block
.bits
/ 8;
379 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
380 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
384 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
385 S_008F04_STRIDE(stride
);
387 if (device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
) {
392 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
393 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
394 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
395 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
396 S_008F0C_NUM_FORMAT(num_format
) |
397 S_008F0C_DATA_FORMAT(data_format
);
401 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
402 struct radv_image
*image
,
403 const struct legacy_surf_level
*base_level_info
,
405 unsigned base_level
, unsigned first_level
,
406 unsigned block_width
, bool is_stencil
,
407 bool is_storage_image
, uint32_t *state
)
409 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
410 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
411 uint64_t va
= gpu_address
+ plane
->offset
;
412 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
413 uint64_t meta_va
= 0;
414 if (chip_class
>= GFX9
) {
416 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
418 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
420 va
+= base_level_info
->offset
;
423 if (chip_class
>= GFX9
||
424 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
425 state
[0] |= plane
->surface
.tile_swizzle
;
426 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
427 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
429 if (chip_class
>= GFX8
) {
430 state
[6] &= C_008F28_COMPRESSION_EN
;
432 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
433 meta_va
= gpu_address
+ image
->dcc_offset
;
434 if (chip_class
<= GFX8
)
435 meta_va
+= base_level_info
->dcc_offset
;
436 } else if (!is_storage_image
&&
437 radv_image_is_tc_compat_htile(image
)) {
438 meta_va
= gpu_address
+ image
->htile_offset
;
442 state
[6] |= S_008F28_COMPRESSION_EN(1);
443 state
[7] = meta_va
>> 8;
444 state
[7] |= plane
->surface
.tile_swizzle
;
448 if (chip_class
>= GFX9
) {
449 state
[3] &= C_008F1C_SW_MODE
;
450 state
[4] &= C_008F20_PITCH
;
453 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
454 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.stencil
.epitch
);
456 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
457 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.surf
.epitch
);
460 state
[5] &= C_008F24_META_DATA_ADDRESS
&
461 C_008F24_META_PIPE_ALIGNED
&
462 C_008F24_META_RB_ALIGNED
;
464 struct gfx9_surf_meta_flags meta
;
466 if (image
->dcc_offset
)
467 meta
= plane
->surface
.u
.gfx9
.dcc
;
469 meta
= plane
->surface
.u
.gfx9
.htile
;
471 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
472 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
473 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
477 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
478 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
480 state
[3] &= C_008F1C_TILING_INDEX
;
481 state
[3] |= S_008F1C_TILING_INDEX(index
);
482 state
[4] &= C_008F20_PITCH
;
483 state
[4] |= S_008F20_PITCH(pitch
- 1);
487 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
488 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
490 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
491 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
493 /* GFX9 allocates 1D textures as 2D. */
494 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
495 image_type
= VK_IMAGE_TYPE_2D
;
496 switch (image_type
) {
497 case VK_IMAGE_TYPE_1D
:
498 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
499 case VK_IMAGE_TYPE_2D
:
501 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
503 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
504 case VK_IMAGE_TYPE_3D
:
505 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
506 return V_008F1C_SQ_RSRC_IMG_3D
;
508 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
510 unreachable("illegal image type");
514 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
516 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
518 if (swizzle
[3] == VK_SWIZZLE_X
) {
519 /* For the pre-defined border color values (white, opaque
520 * black, transparent black), the only thing that matters is
521 * that the alpha channel winds up in the correct place
522 * (because the RGB channels are all the same) so either of
523 * these enumerations will work.
525 if (swizzle
[2] == VK_SWIZZLE_Y
)
526 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
528 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
529 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
530 if (swizzle
[1] == VK_SWIZZLE_Y
)
531 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
533 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
534 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
535 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
536 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
537 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
544 * Build the sampler view descriptor for a texture.
547 si_make_texture_descriptor(struct radv_device
*device
,
548 struct radv_image
*image
,
549 bool is_storage_image
,
550 VkImageViewType view_type
,
552 const VkComponentMapping
*mapping
,
553 unsigned first_level
, unsigned last_level
,
554 unsigned first_layer
, unsigned last_layer
,
555 unsigned width
, unsigned height
, unsigned depth
,
557 uint32_t *fmask_state
)
559 const struct vk_format_description
*desc
;
560 enum vk_swizzle swizzle
[4];
562 unsigned num_format
, data_format
, type
;
564 desc
= vk_format_description(vk_format
);
566 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
567 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
568 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
570 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
573 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
575 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
576 if (num_format
== ~0) {
580 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
581 if (data_format
== ~0) {
585 /* S8 with either Z16 or Z32 HTILE need a special format. */
586 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
587 vk_format
== VK_FORMAT_S8_UINT
&&
588 radv_image_is_tc_compat_htile(image
)) {
589 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
590 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
591 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
592 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
594 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
595 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
596 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
598 depth
= image
->info
.array_size
;
599 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
600 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
601 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
602 depth
= image
->info
.array_size
;
603 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
604 depth
= image
->info
.array_size
/ 6;
607 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
608 S_008F14_NUM_FORMAT(num_format
));
609 state
[2] = (S_008F18_WIDTH(width
- 1) |
610 S_008F18_HEIGHT(height
- 1) |
611 S_008F18_PERF_MOD(4));
612 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
613 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
614 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
615 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
616 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
618 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
619 util_logbase2(image
->info
.samples
) :
621 S_008F1C_TYPE(type
));
623 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
627 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
628 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
630 /* Depth is the last accessible layer on Gfx9.
631 * The hw doesn't need to know the total number of layers.
633 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
634 state
[4] |= S_008F20_DEPTH(depth
- 1);
636 state
[4] |= S_008F20_DEPTH(last_layer
);
638 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
639 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
640 util_logbase2(image
->info
.samples
) :
641 image
->info
.levels
- 1);
643 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
644 state
[4] |= S_008F20_DEPTH(depth
- 1);
645 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
647 if (image
->dcc_offset
) {
648 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
650 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
652 /* The last dword is unused by hw. The shader uses it to clear
653 * bits in the first dword of sampler state.
655 if (device
->physical_device
->rad_info
.chip_class
<= GFX7
&& image
->info
.samples
<= 1) {
656 if (first_level
== last_level
)
657 state
[7] = C_008F30_MAX_ANISO_RATIO
;
659 state
[7] = 0xffffffff;
663 /* Initialize the sampler view for FMASK. */
664 if (radv_image_has_fmask(image
)) {
665 uint32_t fmask_format
, num_format
;
666 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
669 assert(image
->plane_count
== 1);
671 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
673 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
674 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
675 switch (image
->info
.samples
) {
677 num_format
= V_008F14_IMG_FMASK_8_2_2
;
680 num_format
= V_008F14_IMG_FMASK_8_4_4
;
683 num_format
= V_008F14_IMG_FMASK_32_8_8
;
686 unreachable("invalid nr_samples");
689 switch (image
->info
.samples
) {
691 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
694 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
697 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
701 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
703 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
706 fmask_state
[0] = va
>> 8;
707 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
708 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
709 S_008F14_DATA_FORMAT(fmask_format
) |
710 S_008F14_NUM_FORMAT(num_format
);
711 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
712 S_008F18_HEIGHT(height
- 1);
713 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
714 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
715 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
716 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
717 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
719 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
723 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
724 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
725 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
726 S_008F20_PITCH(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
727 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
728 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
730 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
731 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
732 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
733 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
735 } else if (fmask_state
)
736 memset(fmask_state
, 0, 8 * 4);
740 radv_query_opaque_metadata(struct radv_device
*device
,
741 struct radv_image
*image
,
742 struct radeon_bo_metadata
*md
)
744 static const VkComponentMapping fixedmapping
;
747 assert(image
->plane_count
== 1);
749 /* Metadata image format format version 1:
750 * [0] = 1 (metadata format identifier)
751 * [1] = (VENDOR_ID << 16) | PCI_ID
752 * [2:9] = image descriptor for the whole resource
753 * [2] is always 0, because the base address is cleared
754 * [9] is the DCC offset bits [39:8] from the beginning of
756 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
758 md
->metadata
[0] = 1; /* metadata image format version 1 */
760 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
761 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
764 si_make_texture_descriptor(device
, image
, false,
765 (VkImageViewType
)image
->type
, image
->vk_format
,
766 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
767 image
->info
.array_size
- 1,
768 image
->info
.width
, image
->info
.height
,
772 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
773 image
->planes
[0].surface
.blk_w
, false, false, desc
);
775 /* Clear the base address and set the relative DCC offset. */
777 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
778 desc
[7] = image
->dcc_offset
>> 8;
780 /* Dwords [2:9] contain the image descriptor. */
781 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
783 /* Dwords [10:..] contain the mipmap level offsets. */
784 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
785 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
786 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
787 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
792 radv_init_metadata(struct radv_device
*device
,
793 struct radv_image
*image
,
794 struct radeon_bo_metadata
*metadata
)
796 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
798 memset(metadata
, 0, sizeof(*metadata
));
800 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
801 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
803 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
804 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
805 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
806 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
807 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
808 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
809 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
810 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
811 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
812 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
813 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
814 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
816 radv_query_opaque_metadata(device
, image
, metadata
);
820 radv_image_override_offset_stride(struct radv_device
*device
,
821 struct radv_image
*image
,
822 uint64_t offset
, uint32_t stride
)
824 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
825 unsigned bpe
= vk_format_get_blocksizebits(image
->vk_format
) / 8;
827 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
829 surface
->u
.gfx9
.surf_pitch
= stride
;
830 surface
->u
.gfx9
.surf_slice_size
=
831 (uint64_t)stride
* surface
->u
.gfx9
.surf_height
* bpe
;
833 surface
->u
.gfx9
.surf_offset
= offset
;
835 surface
->u
.legacy
.level
[0].nblk_x
= stride
;
836 surface
->u
.legacy
.level
[0].slice_size_dw
=
837 ((uint64_t)stride
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
840 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
841 surface
->u
.legacy
.level
[i
].offset
+= offset
;
847 /* The number of samples can be specified independently of the texture. */
849 radv_image_get_fmask_info(struct radv_device
*device
,
850 struct radv_image
*image
,
852 struct radv_fmask_info
*out
)
854 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
855 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
856 out
->size
= image
->planes
[0].surface
.fmask_size
;
857 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
861 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
862 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
863 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
864 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
865 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
866 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
867 out
->size
= image
->planes
[0].surface
.fmask_size
;
869 assert(!out
->tile_swizzle
|| !image
->shareable
);
873 radv_image_alloc_fmask(struct radv_device
*device
,
874 struct radv_image
*image
)
876 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
878 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
879 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
880 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
884 radv_image_get_cmask_info(struct radv_device
*device
,
885 struct radv_image
*image
,
886 struct radv_cmask_info
*out
)
888 assert(image
->plane_count
== 1);
890 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
891 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
892 out
->size
= image
->planes
[0].surface
.cmask_size
;
896 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.cmask_slice_tile_max
;
897 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
898 out
->size
= image
->planes
[0].surface
.cmask_size
;
902 radv_image_alloc_cmask(struct radv_device
*device
,
903 struct radv_image
*image
)
905 uint32_t clear_value_size
= 0;
906 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
908 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
909 /* + 8 for storing the clear values */
910 if (!image
->clear_value_offset
) {
911 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
912 clear_value_size
= 8;
914 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
915 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
919 radv_image_alloc_dcc(struct radv_image
*image
)
921 assert(image
->plane_count
== 1);
923 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
924 /* + 16 for storing the clear values + dcc pred */
925 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
926 image
->fce_pred_offset
= image
->clear_value_offset
+ 8;
927 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16;
928 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24;
929 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
933 radv_image_alloc_htile(struct radv_image
*image
)
935 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
937 /* + 8 for storing the clear values */
938 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
939 image
->size
= image
->clear_value_offset
+ 8;
940 if (radv_image_is_tc_compat_htile(image
)) {
941 /* Metadata for the TC-compatible HTILE hardware bug which
942 * have to be fixed by updating ZRANGE_PRECISION when doing
943 * fast depth clears to 0.0f.
945 image
->tc_compat_zrange_offset
= image
->clear_value_offset
+ 8;
946 image
->size
= image
->clear_value_offset
+ 16;
948 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
952 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
954 if (image
->info
.samples
<= 1 &&
955 image
->info
.width
* image
->info
.height
<= 512 * 512) {
956 /* Do not enable CMASK or DCC for small surfaces where the cost
957 * of the eliminate pass can be higher than the benefit of fast
958 * clear. RadeonSI does this, but the image threshold is
964 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
965 (image
->exclusive
|| image
->queue_family_mask
== 1);
969 radv_image_can_enable_dcc(struct radv_image
*image
)
971 return radv_image_can_enable_dcc_or_cmask(image
) &&
972 radv_image_has_dcc(image
);
976 radv_image_can_enable_cmask(struct radv_image
*image
)
978 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
979 /* Do not enable CMASK for non-MSAA images (fast color clear)
980 * because 128 bit formats are not supported, but FMASK might
986 return radv_image_can_enable_dcc_or_cmask(image
) &&
987 image
->info
.levels
== 1 &&
988 image
->info
.depth
== 1 &&
989 !image
->planes
[0].surface
.is_linear
;
993 radv_image_can_enable_fmask(struct radv_image
*image
)
995 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
999 radv_image_can_enable_htile(struct radv_image
*image
)
1001 return radv_image_has_htile(image
) &&
1002 image
->info
.levels
== 1 &&
1003 image
->info
.width
* image
->info
.height
>= 8 * 8;
1006 static void radv_image_disable_dcc(struct radv_image
*image
)
1008 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1009 image
->planes
[i
].surface
.dcc_size
= 0;
1012 static void radv_image_disable_htile(struct radv_image
*image
)
1014 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1015 image
->planes
[i
].surface
.htile_size
= 0;
1019 radv_image_create(VkDevice _device
,
1020 const struct radv_image_create_info
*create_info
,
1021 const VkAllocationCallbacks
* alloc
,
1024 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1025 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
1026 struct radv_image
*image
= NULL
;
1027 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
1029 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
1030 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
1032 radv_assert(pCreateInfo
->mipLevels
> 0);
1033 radv_assert(pCreateInfo
->arrayLayers
> 0);
1034 radv_assert(pCreateInfo
->samples
> 0);
1035 radv_assert(pCreateInfo
->extent
.width
> 0);
1036 radv_assert(pCreateInfo
->extent
.height
> 0);
1037 radv_assert(pCreateInfo
->extent
.depth
> 0);
1039 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
1040 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1042 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1044 image
->type
= pCreateInfo
->imageType
;
1045 image
->info
.width
= pCreateInfo
->extent
.width
;
1046 image
->info
.height
= pCreateInfo
->extent
.height
;
1047 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1048 image
->info
.samples
= pCreateInfo
->samples
;
1049 image
->info
.storage_samples
= pCreateInfo
->samples
;
1050 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1051 image
->info
.levels
= pCreateInfo
->mipLevels
;
1052 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1054 image
->vk_format
= pCreateInfo
->format
;
1055 image
->tiling
= pCreateInfo
->tiling
;
1056 image
->usage
= pCreateInfo
->usage
;
1057 image
->flags
= pCreateInfo
->flags
;
1059 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1060 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1061 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1062 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
)
1063 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1065 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1068 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1069 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1070 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) &&
1071 !radv_surface_has_scanout(device
, create_info
) && !image
->shareable
) {
1072 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1075 image
->plane_count
= plane_count
;
1077 image
->alignment
= 1;
1078 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1079 struct ac_surf_info info
= image
->info
;
1080 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1083 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1084 assert(info
.width
% desc
->width_divisor
== 0);
1085 assert(info
.height
% desc
->height_divisor
== 0);
1087 info
.width
/= desc
->width_divisor
;
1088 info
.height
/= desc
->height_divisor
;
1091 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1093 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1094 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1095 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1097 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1100 if (!create_info
->no_metadata_planes
) {
1101 /* Try to enable DCC first. */
1102 if (radv_image_can_enable_dcc(image
)) {
1103 radv_image_alloc_dcc(image
);
1104 if (image
->info
.samples
> 1) {
1105 /* CMASK should be enabled because DCC fast
1106 * clear with MSAA needs it.
1108 assert(radv_image_can_enable_cmask(image
));
1109 radv_image_alloc_cmask(device
, image
);
1112 /* When DCC cannot be enabled, try CMASK. */
1113 radv_image_disable_dcc(image
);
1114 if (radv_image_can_enable_cmask(image
)) {
1115 radv_image_alloc_cmask(device
, image
);
1119 /* Try to enable FMASK for multisampled images. */
1120 if (radv_image_can_enable_fmask(image
)) {
1121 radv_image_alloc_fmask(device
, image
);
1123 /* Otherwise, try to enable HTILE for depth surfaces. */
1124 if (radv_image_can_enable_htile(image
) &&
1125 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1126 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1127 radv_image_alloc_htile(image
);
1129 radv_image_disable_htile(image
);
1133 radv_image_disable_dcc(image
);
1134 radv_image_disable_htile(image
);
1137 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1138 image
->alignment
= MAX2(image
->alignment
, 4096);
1139 image
->size
= align64(image
->size
, image
->alignment
);
1142 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1143 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1145 vk_free2(&device
->alloc
, alloc
, image
);
1146 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1150 *pImage
= radv_image_to_handle(image
);
1156 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1157 struct radv_device
*device
,
1159 const VkComponentMapping
*components
,
1160 bool is_storage_image
, unsigned plane_id
,
1161 unsigned descriptor_plane_id
)
1163 struct radv_image
*image
= iview
->image
;
1164 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1165 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1166 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1168 union radv_descriptor
*descriptor
;
1169 uint32_t hw_level
= 0;
1171 if (is_storage_image
) {
1172 descriptor
= &iview
->storage_descriptor
;
1174 descriptor
= &iview
->descriptor
;
1177 assert(vk_format_get_plane_count(vk_format
) == 1);
1178 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1179 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1181 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1182 hw_level
= iview
->base_mip
;
1183 si_make_texture_descriptor(device
, image
, is_storage_image
,
1187 hw_level
, hw_level
+ iview
->level_count
- 1,
1189 iview
->base_layer
+ iview
->layer_count
- 1,
1190 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1191 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1192 iview
->extent
.depth
,
1193 descriptor
->plane_descriptors
[descriptor_plane_id
],
1194 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1196 const struct legacy_surf_level
*base_level_info
= NULL
;
1197 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1199 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1201 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1203 si_set_mutable_tex_desc_fields(device
, image
,
1208 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1212 radv_plane_from_aspect(VkImageAspectFlags mask
)
1215 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1217 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1225 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1228 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1229 return image
->planes
[0].format
;
1230 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1231 return image
->planes
[1].format
;
1232 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1233 return image
->planes
[2].format
;
1234 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1235 return vk_format_stencil_only(image
->vk_format
);
1236 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1237 return vk_format_depth_only(image
->vk_format
);
1238 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1239 return vk_format_depth_only(image
->vk_format
);
1241 return image
->vk_format
;
1246 radv_image_view_init(struct radv_image_view
*iview
,
1247 struct radv_device
*device
,
1248 const VkImageViewCreateInfo
* pCreateInfo
)
1250 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1251 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1253 switch (image
->type
) {
1254 case VK_IMAGE_TYPE_1D
:
1255 case VK_IMAGE_TYPE_2D
:
1256 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1258 case VK_IMAGE_TYPE_3D
:
1259 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1260 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1263 unreachable("bad VkImageType");
1265 iview
->image
= image
;
1266 iview
->bo
= image
->bo
;
1267 iview
->type
= pCreateInfo
->viewType
;
1268 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1269 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1270 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1271 iview
->vk_format
= pCreateInfo
->format
;
1273 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1274 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1275 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1276 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1279 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1280 iview
->extent
= (VkExtent3D
) {
1281 .width
= image
->info
.width
,
1282 .height
= image
->info
.height
,
1283 .depth
= image
->info
.depth
,
1286 iview
->extent
= (VkExtent3D
) {
1287 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1288 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1289 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1293 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1294 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1295 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1296 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1297 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1299 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1300 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1302 /* Comment ported from amdvlk -
1303 * If we have the following image:
1304 * Uncompressed pixels Compressed block sizes (4x4)
1305 * mip0: 22 x 22 6 x 6
1306 * mip1: 11 x 11 3 x 3
1311 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1312 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1313 * divide-by-two integer math):
1319 * This means that mip2 will be missing texels.
1321 * Fix this by calculating the base mip's width and height, then convert that, and round it
1322 * back up to get the level 0 size.
1323 * Clamp the converted size between the original values, and next power of two, which
1324 * means we don't oversize the image.
1326 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1327 vk_format_is_compressed(image
->vk_format
) &&
1328 !vk_format_is_compressed(iview
->vk_format
)) {
1329 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1330 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1332 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1333 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1335 lvl_width
<<= range
->baseMipLevel
;
1336 lvl_height
<<= range
->baseMipLevel
;
1338 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1339 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1343 iview
->base_layer
= range
->baseArrayLayer
;
1344 iview
->layer_count
= radv_get_layerCount(image
, range
);
1345 iview
->base_mip
= range
->baseMipLevel
;
1346 iview
->level_count
= radv_get_levelCount(image
, range
);
1348 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1349 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1350 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1351 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1355 bool radv_layout_has_htile(const struct radv_image
*image
,
1356 VkImageLayout layout
,
1357 unsigned queue_mask
)
1359 if (radv_image_is_tc_compat_htile(image
))
1360 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1362 return radv_image_has_htile(image
) &&
1363 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1364 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1365 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1368 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1369 VkImageLayout layout
,
1370 unsigned queue_mask
)
1372 if (radv_image_is_tc_compat_htile(image
))
1373 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1375 return radv_image_has_htile(image
) &&
1376 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1377 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1378 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1381 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1382 VkImageLayout layout
,
1383 unsigned queue_mask
)
1385 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1388 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1389 VkImageLayout layout
,
1390 unsigned queue_mask
)
1392 /* Don't compress compute transfer dst, as image stores are not supported. */
1393 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1394 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1397 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1401 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1403 if (!image
->exclusive
)
1404 return image
->queue_family_mask
;
1405 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
1406 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1407 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1408 return 1u << queue_family
;
1409 return 1u << family
;
1413 radv_CreateImage(VkDevice device
,
1414 const VkImageCreateInfo
*pCreateInfo
,
1415 const VkAllocationCallbacks
*pAllocator
,
1419 const VkNativeBufferANDROID
*gralloc_info
=
1420 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1423 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1424 pAllocator
, pImage
);
1427 const struct wsi_image_create_info
*wsi_info
=
1428 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1429 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1431 return radv_image_create(device
,
1432 &(struct radv_image_create_info
) {
1433 .vk_info
= pCreateInfo
,
1441 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1442 const VkAllocationCallbacks
*pAllocator
)
1444 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1445 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1450 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1451 device
->ws
->buffer_destroy(image
->bo
);
1453 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1454 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1456 vk_free2(&device
->alloc
, pAllocator
, image
);
1459 void radv_GetImageSubresourceLayout(
1462 const VkImageSubresource
* pSubresource
,
1463 VkSubresourceLayout
* pLayout
)
1465 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1466 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1467 int level
= pSubresource
->mipLevel
;
1468 int layer
= pSubresource
->arrayLayer
;
1470 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1472 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1473 struct radeon_surf
*surface
= &plane
->surface
;
1475 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1476 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1477 if (image
->vk_format
== VK_FORMAT_R32G32B32_UINT
||
1478 image
->vk_format
== VK_FORMAT_R32G32B32_SINT
||
1479 image
->vk_format
== VK_FORMAT_R32G32B32_SFLOAT
) {
1480 /* Adjust the number of bytes between each row because
1481 * the pitch is actually the number of components per
1484 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
/ 3;
1486 assert(util_is_power_of_two_nonzero(surface
->bpe
));
1487 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1490 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1491 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1492 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1493 if (image
->type
== VK_IMAGE_TYPE_3D
)
1494 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1496 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1497 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1498 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1499 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1500 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1501 if (image
->type
== VK_IMAGE_TYPE_3D
)
1502 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1508 radv_CreateImageView(VkDevice _device
,
1509 const VkImageViewCreateInfo
*pCreateInfo
,
1510 const VkAllocationCallbacks
*pAllocator
,
1513 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1514 struct radv_image_view
*view
;
1516 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1517 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1519 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1521 radv_image_view_init(view
, device
, pCreateInfo
);
1523 *pView
= radv_image_view_to_handle(view
);
1529 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1530 const VkAllocationCallbacks
*pAllocator
)
1532 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1533 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1537 vk_free2(&device
->alloc
, pAllocator
, iview
);
1540 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1541 struct radv_device
*device
,
1542 const VkBufferViewCreateInfo
* pCreateInfo
)
1544 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1546 view
->bo
= buffer
->bo
;
1547 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1548 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1549 view
->vk_format
= pCreateInfo
->format
;
1551 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1552 pCreateInfo
->offset
, view
->range
, view
->state
);
1556 radv_CreateBufferView(VkDevice _device
,
1557 const VkBufferViewCreateInfo
*pCreateInfo
,
1558 const VkAllocationCallbacks
*pAllocator
,
1559 VkBufferView
*pView
)
1561 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1562 struct radv_buffer_view
*view
;
1564 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1565 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1567 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1569 radv_buffer_view_init(view
, device
, pCreateInfo
);
1571 *pView
= radv_buffer_view_to_handle(view
);
1577 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1578 const VkAllocationCallbacks
*pAllocator
)
1580 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1581 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1586 vk_free2(&device
->alloc
, pAllocator
, view
);