2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo
->samples
>= 2 &&
88 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
95 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
96 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
97 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
100 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
101 const struct VkImageFormatListCreateInfoKHR
*format_list
=
102 (const struct VkImageFormatListCreateInfoKHR
*)
103 vk_find_struct_const(pCreateInfo
->pNext
,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list
&& format_list
->viewFormatCount
) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
111 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
112 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
115 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
127 radv_surface_has_scanout(struct radv_device
*device
, const struct radv_image_create_info
*info
)
132 if (!info
->bo_metadata
)
135 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
136 return info
->bo_metadata
->u
.gfx9
.swizzle_mode
== 0 || info
->bo_metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
138 return info
->bo_metadata
->u
.legacy
.scanout
;
143 radv_use_dcc_for_image(struct radv_device
*device
,
144 const struct radv_image
*image
,
145 const struct radv_image_create_info
*create_info
,
146 const VkImageCreateInfo
*pCreateInfo
)
148 bool dcc_compatible_formats
;
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
155 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
158 if (image
->shareable
)
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
163 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
166 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
169 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
170 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if ((pCreateInfo
->arrayLayers
> 1 || pCreateInfo
->mipLevels
> 1) &&
175 device
->physical_device
->rad_info
.chip_class
>= GFX9
)
178 /* Do not enable DCC for mipmapped arrays because performance is worse. */
179 if (pCreateInfo
->arrayLayers
> 1 && pCreateInfo
->mipLevels
> 1)
182 if (radv_surface_has_scanout(device
, create_info
))
185 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
186 * 2x can be enabled with an option.
188 if (pCreateInfo
->samples
> 2 ||
189 (pCreateInfo
->samples
== 2 &&
190 !device
->physical_device
->dcc_msaa_allowed
))
193 /* Determine if the formats are DCC compatible. */
194 dcc_compatible_formats
=
195 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
198 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
199 const struct VkImageFormatListCreateInfoKHR
*format_list
=
200 (const struct VkImageFormatListCreateInfoKHR
*)
201 vk_find_struct_const(pCreateInfo
->pNext
,
202 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
204 /* We have to ignore the existence of the list if viewFormatCount = 0 */
205 if (format_list
&& format_list
->viewFormatCount
) {
206 /* compatibility is transitive, so we only need to check
207 * one format with everything else. */
208 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
209 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
212 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
213 format_list
->pViewFormats
[i
]))
214 dcc_compatible_formats
= false;
217 dcc_compatible_formats
= false;
221 if (!dcc_compatible_formats
)
228 radv_use_tc_compat_cmask_for_image(struct radv_device
*device
,
229 struct radv_image
*image
)
231 if (!(device
->instance
->perftest_flags
& RADV_PERFTEST_TC_COMPAT_CMASK
))
234 /* TC-compat CMASK is only available for GFX8+. */
235 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
238 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
241 if (radv_image_has_dcc(image
))
244 if (!radv_image_has_cmask(image
))
251 radv_prefill_surface_from_metadata(struct radv_device
*device
,
252 struct radeon_surf
*surface
,
253 const struct radv_image_create_info
*create_info
)
255 const struct radeon_bo_metadata
*md
= create_info
->bo_metadata
;
256 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
257 if (md
->u
.gfx9
.swizzle_mode
> 0)
258 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
260 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
262 surface
->u
.gfx9
.surf
.swizzle_mode
= md
->u
.gfx9
.swizzle_mode
;
264 surface
->u
.legacy
.pipe_config
= md
->u
.legacy
.pipe_config
;
265 surface
->u
.legacy
.bankw
= md
->u
.legacy
.bankw
;
266 surface
->u
.legacy
.bankh
= md
->u
.legacy
.bankh
;
267 surface
->u
.legacy
.tile_split
= md
->u
.legacy
.tile_split
;
268 surface
->u
.legacy
.mtilea
= md
->u
.legacy
.mtilea
;
269 surface
->u
.legacy
.num_banks
= md
->u
.legacy
.num_banks
;
271 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
272 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
273 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
274 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
276 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
282 radv_init_surface(struct radv_device
*device
,
283 const struct radv_image
*image
,
284 struct radeon_surf
*surface
,
286 const struct radv_image_create_info
*create_info
)
288 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
289 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
290 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
291 const struct vk_format_description
*desc
= vk_format_description(format
);
292 bool is_depth
, is_stencil
;
294 is_depth
= vk_format_has_depth(desc
);
295 is_stencil
= vk_format_has_stencil(desc
);
297 surface
->blk_w
= vk_format_get_blockwidth(format
);
298 surface
->blk_h
= vk_format_get_blockheight(format
);
300 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
301 /* align byte per element on dword */
302 if (surface
->bpe
== 3) {
305 if (create_info
->bo_metadata
) {
306 radv_prefill_surface_from_metadata(device
, surface
, create_info
);
308 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
311 switch (pCreateInfo
->imageType
){
312 case VK_IMAGE_TYPE_1D
:
313 if (pCreateInfo
->arrayLayers
> 1)
314 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
316 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
318 case VK_IMAGE_TYPE_2D
:
319 if (pCreateInfo
->arrayLayers
> 1)
320 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
322 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
324 case VK_IMAGE_TYPE_3D
:
325 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
328 unreachable("unhandled image type");
332 surface
->flags
|= RADEON_SURF_ZBUFFER
;
333 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
334 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
338 surface
->flags
|= RADEON_SURF_SBUFFER
;
340 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
341 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
342 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
343 vk_format_is_compressed(pCreateInfo
->format
))
344 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
346 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
348 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
349 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
351 if (radv_surface_has_scanout(device
, create_info
))
352 surface
->flags
|= RADEON_SURF_SCANOUT
;
357 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
359 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
362 static inline unsigned
363 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
366 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
368 return plane
->surface
.u
.legacy
.tiling_index
[level
];
371 static unsigned radv_map_swizzle(unsigned swizzle
)
375 return V_008F0C_SQ_SEL_Y
;
377 return V_008F0C_SQ_SEL_Z
;
379 return V_008F0C_SQ_SEL_W
;
381 return V_008F0C_SQ_SEL_0
;
383 return V_008F0C_SQ_SEL_1
;
384 default: /* VK_SWIZZLE_X */
385 return V_008F0C_SQ_SEL_X
;
390 radv_make_buffer_descriptor(struct radv_device
*device
,
391 struct radv_buffer
*buffer
,
397 const struct vk_format_description
*desc
;
399 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
400 uint64_t va
= gpu_address
+ buffer
->offset
;
401 unsigned num_format
, data_format
;
403 desc
= vk_format_description(vk_format
);
404 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
405 stride
= desc
->block
.bits
/ 8;
409 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
410 S_008F04_STRIDE(stride
);
412 if (device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
) {
417 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
418 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
419 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
420 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3]));
422 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
423 const struct gfx10_format
*fmt
= &gfx10_format_table
[vk_format
];
425 /* OOB_SELECT chooses the out-of-bounds check:
426 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
427 * - 1: index >= NUM_RECORDS
428 * - 2: NUM_RECORDS == 0
429 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
430 * else: swizzle_address >= NUM_RECORDS
432 state
[3] |= S_008F0C_FORMAT(fmt
->img_format
) |
433 S_008F0C_OOB_SELECT(0) |
434 S_008F0C_RESOURCE_LEVEL(1);
436 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
437 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
439 assert(data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
);
440 assert(num_format
!= ~0);
442 state
[3] |= S_008F0C_NUM_FORMAT(num_format
) |
443 S_008F0C_DATA_FORMAT(data_format
);
448 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
449 struct radv_image
*image
,
450 const struct legacy_surf_level
*base_level_info
,
452 unsigned base_level
, unsigned first_level
,
453 unsigned block_width
, bool is_stencil
,
454 bool is_storage_image
, uint32_t *state
)
456 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
457 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
458 uint64_t va
= gpu_address
+ plane
->offset
;
459 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
460 uint64_t meta_va
= 0;
461 if (chip_class
>= GFX9
) {
463 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
465 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
467 va
+= base_level_info
->offset
;
470 if (chip_class
>= GFX9
||
471 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
472 state
[0] |= plane
->surface
.tile_swizzle
;
473 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
474 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
476 if (chip_class
>= GFX8
) {
477 state
[6] &= C_008F28_COMPRESSION_EN
;
479 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
480 meta_va
= gpu_address
+ image
->dcc_offset
;
481 if (chip_class
<= GFX8
)
482 meta_va
+= base_level_info
->dcc_offset
;
483 } else if (!is_storage_image
&&
484 radv_image_is_tc_compat_htile(image
)) {
485 meta_va
= gpu_address
+ image
->htile_offset
;
489 state
[6] |= S_008F28_COMPRESSION_EN(1);
490 if (chip_class
<= GFX9
) {
491 state
[7] = meta_va
>> 8;
492 state
[7] |= plane
->surface
.tile_swizzle
;
497 if (chip_class
>= GFX10
) {
498 state
[3] &= C_00A00C_SW_MODE
;
501 state
[3] |= S_00A00C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
503 state
[3] |= S_00A00C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
506 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
&
507 C_00A018_META_PIPE_ALIGNED
;
510 struct gfx9_surf_meta_flags meta
;
512 if (image
->dcc_offset
)
513 meta
= plane
->surface
.u
.gfx9
.dcc
;
515 meta
= plane
->surface
.u
.gfx9
.htile
;
517 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
518 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
521 state
[7] = meta_va
>> 16;
522 } else if (chip_class
>= GFX9
) {
523 state
[3] &= C_008F1C_SW_MODE
;
524 state
[4] &= C_008F20_PITCH
;
527 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
528 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.stencil
.epitch
);
530 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
531 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.surf
.epitch
);
534 state
[5] &= C_008F24_META_DATA_ADDRESS
&
535 C_008F24_META_PIPE_ALIGNED
&
536 C_008F24_META_RB_ALIGNED
;
538 struct gfx9_surf_meta_flags meta
;
540 if (image
->dcc_offset
)
541 meta
= plane
->surface
.u
.gfx9
.dcc
;
543 meta
= plane
->surface
.u
.gfx9
.htile
;
545 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
546 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
547 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
551 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
552 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
554 state
[3] &= C_008F1C_TILING_INDEX
;
555 state
[3] |= S_008F1C_TILING_INDEX(index
);
556 state
[4] &= C_008F20_PITCH
;
557 state
[4] |= S_008F20_PITCH(pitch
- 1);
561 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
562 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
564 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
565 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
567 /* GFX9 allocates 1D textures as 2D. */
568 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
569 image_type
= VK_IMAGE_TYPE_2D
;
570 switch (image_type
) {
571 case VK_IMAGE_TYPE_1D
:
572 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
573 case VK_IMAGE_TYPE_2D
:
575 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
577 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
578 case VK_IMAGE_TYPE_3D
:
579 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
580 return V_008F1C_SQ_RSRC_IMG_3D
;
582 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
584 unreachable("illegal image type");
588 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
590 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
592 if (swizzle
[3] == VK_SWIZZLE_X
) {
593 /* For the pre-defined border color values (white, opaque
594 * black, transparent black), the only thing that matters is
595 * that the alpha channel winds up in the correct place
596 * (because the RGB channels are all the same) so either of
597 * these enumerations will work.
599 if (swizzle
[2] == VK_SWIZZLE_Y
)
600 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
602 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
603 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
604 if (swizzle
[1] == VK_SWIZZLE_Y
)
605 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
607 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
608 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
609 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
610 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
611 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
618 * Build the sampler view descriptor for a texture (GFX10).
621 gfx10_make_texture_descriptor(struct radv_device
*device
,
622 struct radv_image
*image
,
623 bool is_storage_image
,
624 VkImageViewType view_type
,
626 const VkComponentMapping
*mapping
,
627 unsigned first_level
, unsigned last_level
,
628 unsigned first_layer
, unsigned last_layer
,
629 unsigned width
, unsigned height
, unsigned depth
,
631 uint32_t *fmask_state
)
633 const struct vk_format_description
*desc
;
634 enum vk_swizzle swizzle
[4];
638 desc
= vk_format_description(vk_format
);
639 img_format
= gfx10_format_table
[vk_format
].img_format
;
641 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
642 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
643 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
645 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
648 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
649 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
650 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
652 depth
= image
->info
.array_size
;
653 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
654 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
655 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
656 depth
= image
->info
.array_size
;
657 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
658 depth
= image
->info
.array_size
/ 6;
661 state
[1] = S_00A004_FORMAT(img_format
) |
662 S_00A004_WIDTH_LO(width
- 1);
663 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
664 S_00A008_HEIGHT(height
- 1) |
665 S_00A008_RESOURCE_LEVEL(1);
666 state
[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
667 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
668 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
669 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
670 S_00A00C_BASE_LEVEL(image
->info
.samples
> 1 ?
672 S_00A00C_LAST_LEVEL(image
->info
.samples
> 1 ?
673 util_logbase2(image
->info
.samples
) :
675 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle
)) |
677 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
678 * to know the total number of layers.
680 state
[4] = S_00A010_DEPTH(type
== V_008F1C_SQ_RSRC_IMG_3D
? depth
- 1 : last_layer
) |
681 S_00A010_BASE_ARRAY(first_layer
);
682 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
)) |
683 S_00A014_MAX_MIP(image
->info
.samples
> 1 ?
684 util_logbase2(image
->info
.samples
) :
685 image
->info
.levels
- 1) |
686 S_00A014_PERF_MOD(4);
690 if (radv_dcc_enabled(image
, first_level
)) {
691 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
693 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
694 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
695 S_00A018_ALPHA_IS_ON_MSB(swap
<= 1);
698 /* Initialize the sampler view for FMASK. */
699 if (radv_image_has_fmask(image
)) {
700 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
704 assert(image
->plane_count
== 1);
706 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
708 switch (image
->info
.samples
) {
710 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
713 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
716 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
719 unreachable("invalid nr_samples");
722 fmask_state
[0] = (va
>> 8) | image
->planes
[0].surface
.fmask_tile_swizzle
;
723 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
724 S_00A004_FORMAT(format
) |
725 S_00A004_WIDTH_LO(width
- 1);
726 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
727 S_00A008_HEIGHT(height
- 1) |
728 S_00A008_RESOURCE_LEVEL(1);
729 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
730 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
731 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
732 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
733 S_00A00C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
) |
734 S_00A00C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
735 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
736 S_00A010_BASE_ARRAY(first_layer
);
738 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
);
740 } else if (fmask_state
)
741 memset(fmask_state
, 0, 8 * 4);
745 * Build the sampler view descriptor for a texture (SI-GFX9)
748 si_make_texture_descriptor(struct radv_device
*device
,
749 struct radv_image
*image
,
750 bool is_storage_image
,
751 VkImageViewType view_type
,
753 const VkComponentMapping
*mapping
,
754 unsigned first_level
, unsigned last_level
,
755 unsigned first_layer
, unsigned last_layer
,
756 unsigned width
, unsigned height
, unsigned depth
,
758 uint32_t *fmask_state
)
760 const struct vk_format_description
*desc
;
761 enum vk_swizzle swizzle
[4];
763 unsigned num_format
, data_format
, type
;
765 desc
= vk_format_description(vk_format
);
767 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
768 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
769 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
771 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
774 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
776 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
777 if (num_format
== ~0) {
781 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
782 if (data_format
== ~0) {
786 /* S8 with either Z16 or Z32 HTILE need a special format. */
787 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
788 vk_format
== VK_FORMAT_S8_UINT
&&
789 radv_image_is_tc_compat_htile(image
)) {
790 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
791 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
792 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
793 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
795 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
796 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
797 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
799 depth
= image
->info
.array_size
;
800 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
801 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
802 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
803 depth
= image
->info
.array_size
;
804 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
805 depth
= image
->info
.array_size
/ 6;
808 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
809 S_008F14_NUM_FORMAT(num_format
));
810 state
[2] = (S_008F18_WIDTH(width
- 1) |
811 S_008F18_HEIGHT(height
- 1) |
812 S_008F18_PERF_MOD(4));
813 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
814 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
815 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
816 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
817 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
819 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
820 util_logbase2(image
->info
.samples
) :
822 S_008F1C_TYPE(type
));
824 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
828 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
829 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
831 /* Depth is the last accessible layer on Gfx9.
832 * The hw doesn't need to know the total number of layers.
834 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
835 state
[4] |= S_008F20_DEPTH(depth
- 1);
837 state
[4] |= S_008F20_DEPTH(last_layer
);
839 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
840 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
841 util_logbase2(image
->info
.samples
) :
842 image
->info
.levels
- 1);
844 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
845 state
[4] |= S_008F20_DEPTH(depth
- 1);
846 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
848 if (image
->dcc_offset
) {
849 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
851 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
853 /* The last dword is unused by hw. The shader uses it to clear
854 * bits in the first dword of sampler state.
856 if (device
->physical_device
->rad_info
.chip_class
<= GFX7
&& image
->info
.samples
<= 1) {
857 if (first_level
== last_level
)
858 state
[7] = C_008F30_MAX_ANISO_RATIO
;
860 state
[7] = 0xffffffff;
864 /* Initialize the sampler view for FMASK. */
865 if (radv_image_has_fmask(image
)) {
866 uint32_t fmask_format
, num_format
;
867 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
870 assert(image
->plane_count
== 1);
872 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
874 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
875 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
876 switch (image
->info
.samples
) {
878 num_format
= V_008F14_IMG_FMASK_8_2_2
;
881 num_format
= V_008F14_IMG_FMASK_8_4_4
;
884 num_format
= V_008F14_IMG_FMASK_32_8_8
;
887 unreachable("invalid nr_samples");
890 switch (image
->info
.samples
) {
892 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
895 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
898 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
902 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
904 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
907 fmask_state
[0] = va
>> 8;
908 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
909 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
910 S_008F14_DATA_FORMAT(fmask_format
) |
911 S_008F14_NUM_FORMAT(num_format
);
912 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
913 S_008F18_HEIGHT(height
- 1);
914 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
915 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
916 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
917 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
918 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
920 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
924 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
925 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
926 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
927 S_008F20_PITCH(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
928 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
929 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
931 if (radv_image_is_tc_compat_cmask(image
)) {
932 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
934 fmask_state
[5] |= S_008F24_META_DATA_ADDRESS(va
>> 40);
935 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
936 fmask_state
[7] |= va
>> 8;
939 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
940 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
941 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
942 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
944 if (radv_image_is_tc_compat_cmask(image
)) {
945 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
947 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
948 fmask_state
[7] |= va
>> 8;
951 } else if (fmask_state
)
952 memset(fmask_state
, 0, 8 * 4);
956 radv_make_texture_descriptor(struct radv_device
*device
,
957 struct radv_image
*image
,
958 bool is_storage_image
,
959 VkImageViewType view_type
,
961 const VkComponentMapping
*mapping
,
962 unsigned first_level
, unsigned last_level
,
963 unsigned first_layer
, unsigned last_layer
,
964 unsigned width
, unsigned height
, unsigned depth
,
966 uint32_t *fmask_state
)
968 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
969 gfx10_make_texture_descriptor(device
, image
, is_storage_image
,
970 view_type
, vk_format
, mapping
,
971 first_level
, last_level
,
972 first_layer
, last_layer
,
973 width
, height
, depth
,
976 si_make_texture_descriptor(device
, image
, is_storage_image
,
977 view_type
, vk_format
, mapping
,
978 first_level
, last_level
,
979 first_layer
, last_layer
,
980 width
, height
, depth
,
986 radv_query_opaque_metadata(struct radv_device
*device
,
987 struct radv_image
*image
,
988 struct radeon_bo_metadata
*md
)
990 static const VkComponentMapping fixedmapping
;
993 assert(image
->plane_count
== 1);
995 /* Metadata image format format version 1:
996 * [0] = 1 (metadata format identifier)
997 * [1] = (VENDOR_ID << 16) | PCI_ID
998 * [2:9] = image descriptor for the whole resource
999 * [2] is always 0, because the base address is cleared
1000 * [9] is the DCC offset bits [39:8] from the beginning of
1002 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1004 md
->metadata
[0] = 1; /* metadata image format version 1 */
1006 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1007 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
1010 radv_make_texture_descriptor(device
, image
, false,
1011 (VkImageViewType
)image
->type
, image
->vk_format
,
1012 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
1013 image
->info
.array_size
- 1,
1014 image
->info
.width
, image
->info
.height
,
1018 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
1019 image
->planes
[0].surface
.blk_w
, false, false, desc
);
1021 /* Clear the base address and set the relative DCC offset. */
1023 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
1024 desc
[7] = image
->dcc_offset
>> 8;
1026 /* Dwords [2:9] contain the image descriptor. */
1027 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
1029 /* Dwords [10:..] contain the mipmap level offsets. */
1030 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
1031 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
1032 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
1033 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
1038 radv_init_metadata(struct radv_device
*device
,
1039 struct radv_image
*image
,
1040 struct radeon_bo_metadata
*metadata
)
1042 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
1044 memset(metadata
, 0, sizeof(*metadata
));
1046 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1047 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
1049 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
1050 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
1051 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
1052 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
1053 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
1054 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
1055 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
1056 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
1057 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
1058 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
1059 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
1060 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
1062 radv_query_opaque_metadata(device
, image
, metadata
);
1066 radv_image_override_offset_stride(struct radv_device
*device
,
1067 struct radv_image
*image
,
1068 uint64_t offset
, uint32_t stride
)
1070 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
1071 unsigned bpe
= vk_format_get_blocksizebits(image
->vk_format
) / 8;
1073 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1075 surface
->u
.gfx9
.surf_pitch
= stride
;
1076 surface
->u
.gfx9
.surf_slice_size
=
1077 (uint64_t)stride
* surface
->u
.gfx9
.surf_height
* bpe
;
1079 surface
->u
.gfx9
.surf_offset
= offset
;
1081 surface
->u
.legacy
.level
[0].nblk_x
= stride
;
1082 surface
->u
.legacy
.level
[0].slice_size_dw
=
1083 ((uint64_t)stride
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
1086 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
1087 surface
->u
.legacy
.level
[i
].offset
+= offset
;
1093 /* The number of samples can be specified independently of the texture. */
1095 radv_image_get_fmask_info(struct radv_device
*device
,
1096 struct radv_image
*image
,
1097 unsigned nr_samples
,
1098 struct radv_fmask_info
*out
)
1100 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1101 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
1102 out
->size
= image
->planes
[0].surface
.fmask_size
;
1103 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
1107 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
1108 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
1109 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
1110 out
->slice_size
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_size
;
1111 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
1112 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
1113 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
1114 out
->size
= image
->planes
[0].surface
.fmask_size
;
1116 assert(!out
->tile_swizzle
|| !image
->shareable
);
1120 radv_image_alloc_fmask(struct radv_device
*device
,
1121 struct radv_image
*image
)
1123 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
1125 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
1126 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
1127 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
1131 radv_image_get_cmask_info(struct radv_device
*device
,
1132 struct radv_image
*image
,
1133 struct radv_cmask_info
*out
)
1135 assert(image
->plane_count
== 1);
1137 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1138 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
1139 out
->size
= image
->planes
[0].surface
.cmask_size
;
1143 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.cmask_slice_tile_max
;
1144 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
1145 out
->slice_size
= image
->planes
[0].surface
.cmask_slice_size
;
1146 out
->size
= image
->planes
[0].surface
.cmask_size
;
1150 radv_image_alloc_cmask(struct radv_device
*device
,
1151 struct radv_image
*image
)
1153 uint32_t clear_value_size
= 0;
1154 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
1156 if (!image
->cmask
.size
)
1159 assert(image
->cmask
.alignment
);
1161 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
1162 /* + 8 for storing the clear values */
1163 if (!image
->clear_value_offset
) {
1164 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
1165 clear_value_size
= 8;
1167 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
1168 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
1172 radv_image_alloc_dcc(struct radv_image
*image
)
1174 assert(image
->plane_count
== 1);
1176 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
1177 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1178 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
1179 image
->fce_pred_offset
= image
->clear_value_offset
+ 8 * image
->info
.levels
;
1180 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16 * image
->info
.levels
;
1181 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24 * image
->info
.levels
;
1182 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
1186 radv_image_alloc_htile(struct radv_image
*image
)
1188 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
1190 /* + 8 for storing the clear values */
1191 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
1192 image
->size
= image
->clear_value_offset
+ 8;
1193 if (radv_image_is_tc_compat_htile(image
)) {
1194 /* Metadata for the TC-compatible HTILE hardware bug which
1195 * have to be fixed by updating ZRANGE_PRECISION when doing
1196 * fast depth clears to 0.0f.
1198 image
->tc_compat_zrange_offset
= image
->size
;
1199 image
->size
= image
->tc_compat_zrange_offset
+ 4;
1201 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
1205 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
1207 if (image
->info
.samples
<= 1 &&
1208 image
->info
.width
* image
->info
.height
<= 512 * 512) {
1209 /* Do not enable CMASK or DCC for small surfaces where the cost
1210 * of the eliminate pass can be higher than the benefit of fast
1211 * clear. RadeonSI does this, but the image threshold is
1217 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
1218 (image
->exclusive
|| image
->queue_family_mask
== 1);
1222 radv_image_can_enable_dcc(struct radv_device
*device
, struct radv_image
*image
)
1224 if (!radv_image_can_enable_dcc_or_cmask(image
) ||
1225 !radv_image_has_dcc(image
))
1228 /* On GFX8, DCC layers can be interleaved and it's currently only
1229 * enabled if slice size is equal to the per slice fast clear size
1230 * because the driver assumes that portions of multiple layers are
1231 * contiguous during fast clears.
1233 if (image
->info
.array_size
> 1) {
1234 const struct legacy_surf_level
*surf_level
=
1235 &image
->planes
[0].surface
.u
.legacy
.level
[0];
1237 assert(device
->physical_device
->rad_info
.chip_class
== GFX8
);
1239 if (image
->planes
[0].surface
.dcc_slice_size
!= surf_level
->dcc_fast_clear_size
)
1247 radv_image_can_enable_cmask(struct radv_image
*image
)
1249 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
1250 /* Do not enable CMASK for non-MSAA images (fast color clear)
1251 * because 128 bit formats are not supported, but FMASK might
1257 return radv_image_can_enable_dcc_or_cmask(image
) &&
1258 image
->info
.levels
== 1 &&
1259 image
->info
.depth
== 1 &&
1260 !image
->planes
[0].surface
.is_linear
;
1264 radv_image_can_enable_fmask(struct radv_image
*image
)
1266 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
1270 radv_image_can_enable_htile(struct radv_image
*image
)
1272 return radv_image_has_htile(image
) &&
1273 image
->info
.levels
== 1 &&
1274 image
->info
.width
* image
->info
.height
>= 8 * 8;
1277 static void radv_image_disable_dcc(struct radv_image
*image
)
1279 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1280 image
->planes
[i
].surface
.dcc_size
= 0;
1283 static void radv_image_disable_htile(struct radv_image
*image
)
1285 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1286 image
->planes
[i
].surface
.htile_size
= 0;
1290 radv_image_create(VkDevice _device
,
1291 const struct radv_image_create_info
*create_info
,
1292 const VkAllocationCallbacks
* alloc
,
1295 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1296 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
1297 struct radv_image
*image
= NULL
;
1298 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
1300 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
1301 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
1303 radv_assert(pCreateInfo
->mipLevels
> 0);
1304 radv_assert(pCreateInfo
->arrayLayers
> 0);
1305 radv_assert(pCreateInfo
->samples
> 0);
1306 radv_assert(pCreateInfo
->extent
.width
> 0);
1307 radv_assert(pCreateInfo
->extent
.height
> 0);
1308 radv_assert(pCreateInfo
->extent
.depth
> 0);
1310 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
1311 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1313 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1315 image
->type
= pCreateInfo
->imageType
;
1316 image
->info
.width
= pCreateInfo
->extent
.width
;
1317 image
->info
.height
= pCreateInfo
->extent
.height
;
1318 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1319 image
->info
.samples
= pCreateInfo
->samples
;
1320 image
->info
.storage_samples
= pCreateInfo
->samples
;
1321 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1322 image
->info
.levels
= pCreateInfo
->mipLevels
;
1323 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1325 image
->vk_format
= pCreateInfo
->format
;
1326 image
->tiling
= pCreateInfo
->tiling
;
1327 image
->usage
= pCreateInfo
->usage
;
1328 image
->flags
= pCreateInfo
->flags
;
1330 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1331 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1332 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1333 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
||
1334 pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_FOREIGN_EXT
)
1335 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1337 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1340 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1341 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1342 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) &&
1343 !radv_surface_has_scanout(device
, create_info
) && !image
->shareable
) {
1344 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1347 image
->plane_count
= plane_count
;
1349 image
->alignment
= 1;
1350 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1351 struct ac_surf_info info
= image
->info
;
1352 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1355 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1356 assert(info
.width
% desc
->width_divisor
== 0);
1357 assert(info
.height
% desc
->height_divisor
== 0);
1359 info
.width
/= desc
->width_divisor
;
1360 info
.height
/= desc
->height_divisor
;
1363 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1365 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1366 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1367 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1369 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1372 if (!create_info
->no_metadata_planes
) {
1373 /* Try to enable DCC first. */
1374 if (radv_image_can_enable_dcc(device
, image
)) {
1375 radv_image_alloc_dcc(image
);
1376 if (image
->info
.samples
> 1) {
1377 /* CMASK should be enabled because DCC fast
1378 * clear with MSAA needs it.
1380 assert(radv_image_can_enable_cmask(image
));
1381 radv_image_alloc_cmask(device
, image
);
1384 /* When DCC cannot be enabled, try CMASK. */
1385 radv_image_disable_dcc(image
);
1386 if (radv_image_can_enable_cmask(image
)) {
1387 radv_image_alloc_cmask(device
, image
);
1391 /* Try to enable FMASK for multisampled images. */
1392 if (radv_image_can_enable_fmask(image
)) {
1393 radv_image_alloc_fmask(device
, image
);
1395 if (radv_use_tc_compat_cmask_for_image(device
, image
))
1396 image
->tc_compatible_cmask
= true;
1398 /* Otherwise, try to enable HTILE for depth surfaces. */
1399 if (radv_image_can_enable_htile(image
) &&
1400 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1401 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1402 radv_image_alloc_htile(image
);
1404 radv_image_disable_htile(image
);
1408 radv_image_disable_dcc(image
);
1409 radv_image_disable_htile(image
);
1412 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1413 image
->alignment
= MAX2(image
->alignment
, 4096);
1414 image
->size
= align64(image
->size
, image
->alignment
);
1417 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1418 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1420 vk_free2(&device
->alloc
, alloc
, image
);
1421 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1425 *pImage
= radv_image_to_handle(image
);
1431 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1432 struct radv_device
*device
,
1434 const VkComponentMapping
*components
,
1435 bool is_storage_image
, unsigned plane_id
,
1436 unsigned descriptor_plane_id
)
1438 struct radv_image
*image
= iview
->image
;
1439 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1440 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1441 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1443 union radv_descriptor
*descriptor
;
1444 uint32_t hw_level
= 0;
1446 if (is_storage_image
) {
1447 descriptor
= &iview
->storage_descriptor
;
1449 descriptor
= &iview
->descriptor
;
1452 assert(vk_format_get_plane_count(vk_format
) == 1);
1453 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1454 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1456 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1457 hw_level
= iview
->base_mip
;
1458 radv_make_texture_descriptor(device
, image
, is_storage_image
,
1462 hw_level
, hw_level
+ iview
->level_count
- 1,
1464 iview
->base_layer
+ iview
->layer_count
- 1,
1465 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1466 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1467 iview
->extent
.depth
,
1468 descriptor
->plane_descriptors
[descriptor_plane_id
],
1469 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1471 const struct legacy_surf_level
*base_level_info
= NULL
;
1472 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1474 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1476 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1478 si_set_mutable_tex_desc_fields(device
, image
,
1483 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1487 radv_plane_from_aspect(VkImageAspectFlags mask
)
1490 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1492 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1500 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1503 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1504 return image
->planes
[0].format
;
1505 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1506 return image
->planes
[1].format
;
1507 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1508 return image
->planes
[2].format
;
1509 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1510 return vk_format_stencil_only(image
->vk_format
);
1511 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1512 return vk_format_depth_only(image
->vk_format
);
1513 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1514 return vk_format_depth_only(image
->vk_format
);
1516 return image
->vk_format
;
1521 radv_image_view_init(struct radv_image_view
*iview
,
1522 struct radv_device
*device
,
1523 const VkImageViewCreateInfo
* pCreateInfo
)
1525 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1526 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1528 switch (image
->type
) {
1529 case VK_IMAGE_TYPE_1D
:
1530 case VK_IMAGE_TYPE_2D
:
1531 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1533 case VK_IMAGE_TYPE_3D
:
1534 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1535 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1538 unreachable("bad VkImageType");
1540 iview
->image
= image
;
1541 iview
->bo
= image
->bo
;
1542 iview
->type
= pCreateInfo
->viewType
;
1543 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1544 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1545 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1546 iview
->vk_format
= pCreateInfo
->format
;
1548 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1549 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1550 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1551 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1554 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1555 iview
->extent
= (VkExtent3D
) {
1556 .width
= image
->info
.width
,
1557 .height
= image
->info
.height
,
1558 .depth
= image
->info
.depth
,
1561 iview
->extent
= (VkExtent3D
) {
1562 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1563 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1564 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1568 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1569 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1570 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1571 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1572 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1574 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1575 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1577 /* Comment ported from amdvlk -
1578 * If we have the following image:
1579 * Uncompressed pixels Compressed block sizes (4x4)
1580 * mip0: 22 x 22 6 x 6
1581 * mip1: 11 x 11 3 x 3
1586 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1587 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1588 * divide-by-two integer math):
1594 * This means that mip2 will be missing texels.
1596 * Fix this by calculating the base mip's width and height, then convert that, and round it
1597 * back up to get the level 0 size.
1598 * Clamp the converted size between the original values, and next power of two, which
1599 * means we don't oversize the image.
1601 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1602 vk_format_is_compressed(image
->vk_format
) &&
1603 !vk_format_is_compressed(iview
->vk_format
)) {
1604 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1605 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1607 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1608 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1610 lvl_width
<<= range
->baseMipLevel
;
1611 lvl_height
<<= range
->baseMipLevel
;
1613 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1614 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1618 iview
->base_layer
= range
->baseArrayLayer
;
1619 iview
->layer_count
= radv_get_layerCount(image
, range
);
1620 iview
->base_mip
= range
->baseMipLevel
;
1621 iview
->level_count
= radv_get_levelCount(image
, range
);
1623 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1624 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1625 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1626 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1630 bool radv_layout_has_htile(const struct radv_image
*image
,
1631 VkImageLayout layout
,
1632 unsigned queue_mask
)
1634 if (radv_image_is_tc_compat_htile(image
))
1635 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1637 return radv_image_has_htile(image
) &&
1638 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1639 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1640 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1643 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1644 VkImageLayout layout
,
1645 unsigned queue_mask
)
1647 if (radv_image_is_tc_compat_htile(image
))
1648 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1650 return radv_image_has_htile(image
) &&
1651 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1652 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1653 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1656 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1657 VkImageLayout layout
,
1658 unsigned queue_mask
)
1660 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1663 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1664 VkImageLayout layout
,
1665 unsigned queue_mask
)
1667 /* Don't compress compute transfer dst, as image stores are not supported. */
1668 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1669 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1672 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1676 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1678 if (!image
->exclusive
)
1679 return image
->queue_family_mask
;
1680 if (family
== VK_QUEUE_FAMILY_EXTERNAL
||
1681 family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
1682 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1683 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1684 return 1u << queue_family
;
1685 return 1u << family
;
1689 radv_CreateImage(VkDevice device
,
1690 const VkImageCreateInfo
*pCreateInfo
,
1691 const VkAllocationCallbacks
*pAllocator
,
1695 const VkNativeBufferANDROID
*gralloc_info
=
1696 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1699 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1700 pAllocator
, pImage
);
1703 const struct wsi_image_create_info
*wsi_info
=
1704 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1705 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1707 return radv_image_create(device
,
1708 &(struct radv_image_create_info
) {
1709 .vk_info
= pCreateInfo
,
1717 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1718 const VkAllocationCallbacks
*pAllocator
)
1720 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1721 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1726 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1727 device
->ws
->buffer_destroy(image
->bo
);
1729 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1730 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1732 vk_free2(&device
->alloc
, pAllocator
, image
);
1735 void radv_GetImageSubresourceLayout(
1738 const VkImageSubresource
* pSubresource
,
1739 VkSubresourceLayout
* pLayout
)
1741 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1742 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1743 int level
= pSubresource
->mipLevel
;
1744 int layer
= pSubresource
->arrayLayer
;
1746 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1748 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1749 struct radeon_surf
*surface
= &plane
->surface
;
1751 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1752 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1753 if (image
->vk_format
== VK_FORMAT_R32G32B32_UINT
||
1754 image
->vk_format
== VK_FORMAT_R32G32B32_SINT
||
1755 image
->vk_format
== VK_FORMAT_R32G32B32_SFLOAT
) {
1756 /* Adjust the number of bytes between each row because
1757 * the pitch is actually the number of components per
1760 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
/ 3;
1762 assert(util_is_power_of_two_nonzero(surface
->bpe
));
1763 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1766 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1767 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1768 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1769 if (image
->type
== VK_IMAGE_TYPE_3D
)
1770 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1772 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1773 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1774 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1775 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1776 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1777 if (image
->type
== VK_IMAGE_TYPE_3D
)
1778 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1784 radv_CreateImageView(VkDevice _device
,
1785 const VkImageViewCreateInfo
*pCreateInfo
,
1786 const VkAllocationCallbacks
*pAllocator
,
1789 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1790 struct radv_image_view
*view
;
1792 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1793 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1795 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1797 radv_image_view_init(view
, device
, pCreateInfo
);
1799 *pView
= radv_image_view_to_handle(view
);
1805 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1806 const VkAllocationCallbacks
*pAllocator
)
1808 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1809 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1813 vk_free2(&device
->alloc
, pAllocator
, iview
);
1816 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1817 struct radv_device
*device
,
1818 const VkBufferViewCreateInfo
* pCreateInfo
)
1820 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1822 view
->bo
= buffer
->bo
;
1823 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1824 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1825 view
->vk_format
= pCreateInfo
->format
;
1827 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1828 pCreateInfo
->offset
, view
->range
, view
->state
);
1832 radv_CreateBufferView(VkDevice _device
,
1833 const VkBufferViewCreateInfo
*pCreateInfo
,
1834 const VkAllocationCallbacks
*pAllocator
,
1835 VkBufferView
*pView
)
1837 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1838 struct radv_buffer_view
*view
;
1840 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1841 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1843 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1845 radv_buffer_view_init(view
, device
, pCreateInfo
);
1847 *pView
= radv_buffer_view_to_handle(view
);
1853 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1854 const VkAllocationCallbacks
*pAllocator
)
1856 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1857 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1862 vk_free2(&device
->alloc
, pAllocator
, view
);