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radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps and array layers. */
174 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
175 return false;
176
177 if (radv_surface_has_scanout(device, create_info))
178 return false;
179
180 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
181 * 2x can be enabled with an option.
182 */
183 if (pCreateInfo->samples > 2 ||
184 (pCreateInfo->samples == 2 &&
185 !device->physical_device->dcc_msaa_allowed))
186 return false;
187
188 /* Determine if the formats are DCC compatible. */
189 dcc_compatible_formats =
190 radv_is_colorbuffer_format_supported(pCreateInfo->format,
191 &blendable);
192
193 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
194 const struct VkImageFormatListCreateInfoKHR *format_list =
195 (const struct VkImageFormatListCreateInfoKHR *)
196 vk_find_struct_const(pCreateInfo->pNext,
197 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
198
199 /* We have to ignore the existence of the list if viewFormatCount = 0 */
200 if (format_list && format_list->viewFormatCount) {
201 /* compatibility is transitive, so we only need to check
202 * one format with everything else. */
203 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
204 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
205 continue;
206
207 if (!radv_dcc_formats_compatible(pCreateInfo->format,
208 format_list->pViewFormats[i]))
209 dcc_compatible_formats = false;
210 }
211 } else {
212 dcc_compatible_formats = false;
213 }
214 }
215
216 if (!dcc_compatible_formats)
217 return false;
218
219 return true;
220 }
221
222 static bool
223 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
224 struct radv_image *image)
225 {
226 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
227 return false;
228
229 /* TC-compat CMASK is only available for GFX8+. */
230 if (device->physical_device->rad_info.chip_class < GFX8)
231 return false;
232
233 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
234 return false;
235
236 if (radv_image_has_dcc(image))
237 return false;
238
239 if (!radv_image_has_cmask(image))
240 return false;
241
242 return true;
243 }
244
245 static void
246 radv_prefill_surface_from_metadata(struct radv_device *device,
247 struct radeon_surf *surface,
248 const struct radv_image_create_info *create_info)
249 {
250 const struct radeon_bo_metadata *md = create_info->bo_metadata;
251 if (device->physical_device->rad_info.chip_class >= GFX9) {
252 if (md->u.gfx9.swizzle_mode > 0)
253 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
254 else
255 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
256
257 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
258 } else {
259 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
260 surface->u.legacy.bankw = md->u.legacy.bankw;
261 surface->u.legacy.bankh = md->u.legacy.bankh;
262 surface->u.legacy.tile_split = md->u.legacy.tile_split;
263 surface->u.legacy.mtilea = md->u.legacy.mtilea;
264 surface->u.legacy.num_banks = md->u.legacy.num_banks;
265
266 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
267 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
268 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
269 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
270 else
271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
272
273 }
274 }
275
276 static int
277 radv_init_surface(struct radv_device *device,
278 const struct radv_image *image,
279 struct radeon_surf *surface,
280 unsigned plane_id,
281 const struct radv_image_create_info *create_info)
282 {
283 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
284 unsigned array_mode = radv_choose_tiling(device, create_info);
285 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
286 const struct vk_format_description *desc = vk_format_description(format);
287 bool is_depth, is_stencil;
288
289 is_depth = vk_format_has_depth(desc);
290 is_stencil = vk_format_has_stencil(desc);
291
292 surface->blk_w = vk_format_get_blockwidth(format);
293 surface->blk_h = vk_format_get_blockheight(format);
294
295 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
296 /* align byte per element on dword */
297 if (surface->bpe == 3) {
298 surface->bpe = 4;
299 }
300 if (create_info->bo_metadata) {
301 radv_prefill_surface_from_metadata(device, surface, create_info);
302 } else {
303 surface->flags = RADEON_SURF_SET(array_mode, MODE);
304 }
305
306 switch (pCreateInfo->imageType){
307 case VK_IMAGE_TYPE_1D:
308 if (pCreateInfo->arrayLayers > 1)
309 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
310 else
311 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
312 break;
313 case VK_IMAGE_TYPE_2D:
314 if (pCreateInfo->arrayLayers > 1)
315 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
316 else
317 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
318 break;
319 case VK_IMAGE_TYPE_3D:
320 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
321 break;
322 default:
323 unreachable("unhandled image type");
324 }
325
326 if (is_depth) {
327 surface->flags |= RADEON_SURF_ZBUFFER;
328 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
329 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
330 }
331
332 if (is_stencil)
333 surface->flags |= RADEON_SURF_SBUFFER;
334
335 if (device->physical_device->rad_info.chip_class >= GFX9 &&
336 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
337 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
338 vk_format_is_compressed(pCreateInfo->format))
339 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
340
341 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
342
343 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
344 surface->flags |= RADEON_SURF_DISABLE_DCC;
345
346 if (radv_surface_has_scanout(device, create_info))
347 surface->flags |= RADEON_SURF_SCANOUT;
348
349 return 0;
350 }
351
352 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
353 {
354 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
355 }
356
357 static inline unsigned
358 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
359 {
360 if (stencil)
361 return plane->surface.u.legacy.stencil_tiling_index[level];
362 else
363 return plane->surface.u.legacy.tiling_index[level];
364 }
365
366 static unsigned radv_map_swizzle(unsigned swizzle)
367 {
368 switch (swizzle) {
369 case VK_SWIZZLE_Y:
370 return V_008F0C_SQ_SEL_Y;
371 case VK_SWIZZLE_Z:
372 return V_008F0C_SQ_SEL_Z;
373 case VK_SWIZZLE_W:
374 return V_008F0C_SQ_SEL_W;
375 case VK_SWIZZLE_0:
376 return V_008F0C_SQ_SEL_0;
377 case VK_SWIZZLE_1:
378 return V_008F0C_SQ_SEL_1;
379 default: /* VK_SWIZZLE_X */
380 return V_008F0C_SQ_SEL_X;
381 }
382 }
383
384 static void
385 radv_make_buffer_descriptor(struct radv_device *device,
386 struct radv_buffer *buffer,
387 VkFormat vk_format,
388 unsigned offset,
389 unsigned range,
390 uint32_t *state)
391 {
392 const struct vk_format_description *desc;
393 unsigned stride;
394 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
395 uint64_t va = gpu_address + buffer->offset;
396 unsigned num_format, data_format;
397 int first_non_void;
398 desc = vk_format_description(vk_format);
399 first_non_void = vk_format_get_first_non_void_channel(vk_format);
400 stride = desc->block.bits / 8;
401
402 num_format = radv_translate_buffer_numformat(desc, first_non_void);
403 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
404
405 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
406 assert(num_format != ~0);
407
408 va += offset;
409 state[0] = va;
410 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
411 S_008F04_STRIDE(stride);
412
413 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
414 range /= stride;
415 }
416
417 state[2] = range;
418 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
419 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
420 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
421 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
422 S_008F0C_NUM_FORMAT(num_format) |
423 S_008F0C_DATA_FORMAT(data_format);
424 }
425
426 static void
427 si_set_mutable_tex_desc_fields(struct radv_device *device,
428 struct radv_image *image,
429 const struct legacy_surf_level *base_level_info,
430 unsigned plane_id,
431 unsigned base_level, unsigned first_level,
432 unsigned block_width, bool is_stencil,
433 bool is_storage_image, uint32_t *state)
434 {
435 struct radv_image_plane *plane = &image->planes[plane_id];
436 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
437 uint64_t va = gpu_address + plane->offset;
438 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
439 uint64_t meta_va = 0;
440 if (chip_class >= GFX9) {
441 if (is_stencil)
442 va += plane->surface.u.gfx9.stencil_offset;
443 else
444 va += plane->surface.u.gfx9.surf_offset;
445 } else
446 va += base_level_info->offset;
447
448 state[0] = va >> 8;
449 if (chip_class >= GFX9 ||
450 base_level_info->mode == RADEON_SURF_MODE_2D)
451 state[0] |= plane->surface.tile_swizzle;
452 state[1] &= C_008F14_BASE_ADDRESS_HI;
453 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
454
455 if (chip_class >= GFX8) {
456 state[6] &= C_008F28_COMPRESSION_EN;
457 state[7] = 0;
458 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
459 meta_va = gpu_address + image->dcc_offset;
460 if (chip_class <= GFX8)
461 meta_va += base_level_info->dcc_offset;
462 } else if (!is_storage_image &&
463 radv_image_is_tc_compat_htile(image)) {
464 meta_va = gpu_address + image->htile_offset;
465 }
466
467 if (meta_va) {
468 state[6] |= S_008F28_COMPRESSION_EN(1);
469 state[7] = meta_va >> 8;
470 state[7] |= plane->surface.tile_swizzle;
471 }
472 }
473
474 if (chip_class >= GFX9) {
475 state[3] &= C_008F1C_SW_MODE;
476 state[4] &= C_008F20_PITCH;
477
478 if (is_stencil) {
479 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
480 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
481 } else {
482 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
483 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
484 }
485
486 state[5] &= C_008F24_META_DATA_ADDRESS &
487 C_008F24_META_PIPE_ALIGNED &
488 C_008F24_META_RB_ALIGNED;
489 if (meta_va) {
490 struct gfx9_surf_meta_flags meta;
491
492 if (image->dcc_offset)
493 meta = plane->surface.u.gfx9.dcc;
494 else
495 meta = plane->surface.u.gfx9.htile;
496
497 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
498 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
499 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
500 }
501 } else {
502 /* GFX6-GFX8 */
503 unsigned pitch = base_level_info->nblk_x * block_width;
504 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
505
506 state[3] &= C_008F1C_TILING_INDEX;
507 state[3] |= S_008F1C_TILING_INDEX(index);
508 state[4] &= C_008F20_PITCH;
509 state[4] |= S_008F20_PITCH(pitch - 1);
510 }
511 }
512
513 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
514 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
515 {
516 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
517 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
518
519 /* GFX9 allocates 1D textures as 2D. */
520 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
521 image_type = VK_IMAGE_TYPE_2D;
522 switch (image_type) {
523 case VK_IMAGE_TYPE_1D:
524 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
525 case VK_IMAGE_TYPE_2D:
526 if (nr_samples > 1)
527 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
528 else
529 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
530 case VK_IMAGE_TYPE_3D:
531 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
532 return V_008F1C_SQ_RSRC_IMG_3D;
533 else
534 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
535 default:
536 unreachable("illegal image type");
537 }
538 }
539
540 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
541 {
542 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
543
544 if (swizzle[3] == VK_SWIZZLE_X) {
545 /* For the pre-defined border color values (white, opaque
546 * black, transparent black), the only thing that matters is
547 * that the alpha channel winds up in the correct place
548 * (because the RGB channels are all the same) so either of
549 * these enumerations will work.
550 */
551 if (swizzle[2] == VK_SWIZZLE_Y)
552 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
553 else
554 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
555 } else if (swizzle[0] == VK_SWIZZLE_X) {
556 if (swizzle[1] == VK_SWIZZLE_Y)
557 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
558 else
559 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
560 } else if (swizzle[1] == VK_SWIZZLE_X) {
561 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
562 } else if (swizzle[2] == VK_SWIZZLE_X) {
563 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
564 }
565
566 return bc_swizzle;
567 }
568
569 /**
570 * Build the sampler view descriptor for a texture.
571 */
572 static void
573 si_make_texture_descriptor(struct radv_device *device,
574 struct radv_image *image,
575 bool is_storage_image,
576 VkImageViewType view_type,
577 VkFormat vk_format,
578 const VkComponentMapping *mapping,
579 unsigned first_level, unsigned last_level,
580 unsigned first_layer, unsigned last_layer,
581 unsigned width, unsigned height, unsigned depth,
582 uint32_t *state,
583 uint32_t *fmask_state)
584 {
585 const struct vk_format_description *desc;
586 enum vk_swizzle swizzle[4];
587 int first_non_void;
588 unsigned num_format, data_format, type;
589
590 desc = vk_format_description(vk_format);
591
592 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
593 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
594 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
595 } else {
596 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
597 }
598
599 first_non_void = vk_format_get_first_non_void_channel(vk_format);
600
601 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
602 if (num_format == ~0) {
603 num_format = 0;
604 }
605
606 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
607 if (data_format == ~0) {
608 data_format = 0;
609 }
610
611 /* S8 with either Z16 or Z32 HTILE need a special format. */
612 if (device->physical_device->rad_info.chip_class >= GFX9 &&
613 vk_format == VK_FORMAT_S8_UINT &&
614 radv_image_is_tc_compat_htile(image)) {
615 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
616 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
617 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
618 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
619 }
620 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
621 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
622 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
623 height = 1;
624 depth = image->info.array_size;
625 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
626 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
627 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
628 depth = image->info.array_size;
629 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
630 depth = image->info.array_size / 6;
631
632 state[0] = 0;
633 state[1] = (S_008F14_DATA_FORMAT(data_format) |
634 S_008F14_NUM_FORMAT(num_format));
635 state[2] = (S_008F18_WIDTH(width - 1) |
636 S_008F18_HEIGHT(height - 1) |
637 S_008F18_PERF_MOD(4));
638 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
639 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
640 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
641 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
642 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
643 0 : first_level) |
644 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
645 util_logbase2(image->info.samples) :
646 last_level) |
647 S_008F1C_TYPE(type));
648 state[4] = 0;
649 state[5] = S_008F24_BASE_ARRAY(first_layer);
650 state[6] = 0;
651 state[7] = 0;
652
653 if (device->physical_device->rad_info.chip_class >= GFX9) {
654 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
655
656 /* Depth is the last accessible layer on Gfx9.
657 * The hw doesn't need to know the total number of layers.
658 */
659 if (type == V_008F1C_SQ_RSRC_IMG_3D)
660 state[4] |= S_008F20_DEPTH(depth - 1);
661 else
662 state[4] |= S_008F20_DEPTH(last_layer);
663
664 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
665 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
666 util_logbase2(image->info.samples) :
667 image->info.levels - 1);
668 } else {
669 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
670 state[4] |= S_008F20_DEPTH(depth - 1);
671 state[5] |= S_008F24_LAST_ARRAY(last_layer);
672 }
673 if (image->dcc_offset) {
674 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
675
676 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
677 } else {
678 /* The last dword is unused by hw. The shader uses it to clear
679 * bits in the first dword of sampler state.
680 */
681 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
682 if (first_level == last_level)
683 state[7] = C_008F30_MAX_ANISO_RATIO;
684 else
685 state[7] = 0xffffffff;
686 }
687 }
688
689 /* Initialize the sampler view for FMASK. */
690 if (radv_image_has_fmask(image)) {
691 uint32_t fmask_format, num_format;
692 uint64_t gpu_address = radv_buffer_get_va(image->bo);
693 uint64_t va;
694
695 assert(image->plane_count == 1);
696
697 va = gpu_address + image->offset + image->fmask.offset;
698
699 if (device->physical_device->rad_info.chip_class >= GFX9) {
700 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
701 switch (image->info.samples) {
702 case 2:
703 num_format = V_008F14_IMG_FMASK_8_2_2;
704 break;
705 case 4:
706 num_format = V_008F14_IMG_FMASK_8_4_4;
707 break;
708 case 8:
709 num_format = V_008F14_IMG_FMASK_32_8_8;
710 break;
711 default:
712 unreachable("invalid nr_samples");
713 }
714 } else {
715 switch (image->info.samples) {
716 case 2:
717 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
718 break;
719 case 4:
720 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
721 break;
722 case 8:
723 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
724 break;
725 default:
726 assert(0);
727 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
728 }
729 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
730 }
731
732 fmask_state[0] = va >> 8;
733 fmask_state[0] |= image->fmask.tile_swizzle;
734 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
735 S_008F14_DATA_FORMAT(fmask_format) |
736 S_008F14_NUM_FORMAT(num_format);
737 fmask_state[2] = S_008F18_WIDTH(width - 1) |
738 S_008F18_HEIGHT(height - 1);
739 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
740 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
741 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
742 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
743 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
744 fmask_state[4] = 0;
745 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
746 fmask_state[6] = 0;
747 fmask_state[7] = 0;
748
749 if (device->physical_device->rad_info.chip_class >= GFX9) {
750 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
751 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
752 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
753 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
754 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
755
756 if (radv_image_is_tc_compat_cmask(image)) {
757 va = gpu_address + image->offset + image->cmask.offset;
758
759 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
760 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
761 fmask_state[7] |= va >> 8;
762 }
763 } else {
764 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
765 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
766 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
767 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
768
769 if (radv_image_is_tc_compat_cmask(image)) {
770 va = gpu_address + image->offset + image->cmask.offset;
771
772 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
773 fmask_state[7] |= va >> 8;
774 }
775 }
776 } else if (fmask_state)
777 memset(fmask_state, 0, 8 * 4);
778 }
779
780 static void
781 radv_query_opaque_metadata(struct radv_device *device,
782 struct radv_image *image,
783 struct radeon_bo_metadata *md)
784 {
785 static const VkComponentMapping fixedmapping;
786 uint32_t desc[8], i;
787
788 assert(image->plane_count == 1);
789
790 /* Metadata image format format version 1:
791 * [0] = 1 (metadata format identifier)
792 * [1] = (VENDOR_ID << 16) | PCI_ID
793 * [2:9] = image descriptor for the whole resource
794 * [2] is always 0, because the base address is cleared
795 * [9] is the DCC offset bits [39:8] from the beginning of
796 * the buffer
797 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
798 */
799 md->metadata[0] = 1; /* metadata image format version 1 */
800
801 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
802 md->metadata[1] = si_get_bo_metadata_word1(device);
803
804
805 si_make_texture_descriptor(device, image, false,
806 (VkImageViewType)image->type, image->vk_format,
807 &fixedmapping, 0, image->info.levels - 1, 0,
808 image->info.array_size - 1,
809 image->info.width, image->info.height,
810 image->info.depth,
811 desc, NULL);
812
813 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
814 image->planes[0].surface.blk_w, false, false, desc);
815
816 /* Clear the base address and set the relative DCC offset. */
817 desc[0] = 0;
818 desc[1] &= C_008F14_BASE_ADDRESS_HI;
819 desc[7] = image->dcc_offset >> 8;
820
821 /* Dwords [2:9] contain the image descriptor. */
822 memcpy(&md->metadata[2], desc, sizeof(desc));
823
824 /* Dwords [10:..] contain the mipmap level offsets. */
825 if (device->physical_device->rad_info.chip_class <= GFX8) {
826 for (i = 0; i <= image->info.levels - 1; i++)
827 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
828 md->size_metadata = (11 + image->info.levels - 1) * 4;
829 }
830 }
831
832 void
833 radv_init_metadata(struct radv_device *device,
834 struct radv_image *image,
835 struct radeon_bo_metadata *metadata)
836 {
837 struct radeon_surf *surface = &image->planes[0].surface;
838
839 memset(metadata, 0, sizeof(*metadata));
840
841 if (device->physical_device->rad_info.chip_class >= GFX9) {
842 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
843 } else {
844 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
845 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
846 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
847 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
848 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
849 metadata->u.legacy.bankw = surface->u.legacy.bankw;
850 metadata->u.legacy.bankh = surface->u.legacy.bankh;
851 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
852 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
853 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
854 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
855 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
856 }
857 radv_query_opaque_metadata(device, image, metadata);
858 }
859
860 void
861 radv_image_override_offset_stride(struct radv_device *device,
862 struct radv_image *image,
863 uint64_t offset, uint32_t stride)
864 {
865 struct radeon_surf *surface = &image->planes[0].surface;
866 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
867
868 if (device->physical_device->rad_info.chip_class >= GFX9) {
869 if (stride) {
870 surface->u.gfx9.surf_pitch = stride;
871 surface->u.gfx9.surf_slice_size =
872 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
873 }
874 surface->u.gfx9.surf_offset = offset;
875 } else {
876 surface->u.legacy.level[0].nblk_x = stride;
877 surface->u.legacy.level[0].slice_size_dw =
878 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
879
880 if (offset) {
881 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
882 surface->u.legacy.level[i].offset += offset;
883 }
884
885 }
886 }
887
888 /* The number of samples can be specified independently of the texture. */
889 static void
890 radv_image_get_fmask_info(struct radv_device *device,
891 struct radv_image *image,
892 unsigned nr_samples,
893 struct radv_fmask_info *out)
894 {
895 if (device->physical_device->rad_info.chip_class >= GFX9) {
896 out->alignment = image->planes[0].surface.fmask_alignment;
897 out->size = image->planes[0].surface.fmask_size;
898 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
899 return;
900 }
901
902 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
903 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
904 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
905 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
906 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
907 out->alignment = image->planes[0].surface.fmask_alignment;
908 out->size = image->planes[0].surface.fmask_size;
909
910 assert(!out->tile_swizzle || !image->shareable);
911 }
912
913 static void
914 radv_image_alloc_fmask(struct radv_device *device,
915 struct radv_image *image)
916 {
917 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
918
919 image->fmask.offset = align64(image->size, image->fmask.alignment);
920 image->size = image->fmask.offset + image->fmask.size;
921 image->alignment = MAX2(image->alignment, image->fmask.alignment);
922 }
923
924 static void
925 radv_image_get_cmask_info(struct radv_device *device,
926 struct radv_image *image,
927 struct radv_cmask_info *out)
928 {
929 assert(image->plane_count == 1);
930
931 if (device->physical_device->rad_info.chip_class >= GFX9) {
932 out->alignment = image->planes[0].surface.cmask_alignment;
933 out->size = image->planes[0].surface.cmask_size;
934 return;
935 }
936
937 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
938 out->alignment = image->planes[0].surface.cmask_alignment;
939 out->size = image->planes[0].surface.cmask_size;
940 }
941
942 static void
943 radv_image_alloc_cmask(struct radv_device *device,
944 struct radv_image *image)
945 {
946 uint32_t clear_value_size = 0;
947 radv_image_get_cmask_info(device, image, &image->cmask);
948
949 image->cmask.offset = align64(image->size, image->cmask.alignment);
950 /* + 8 for storing the clear values */
951 if (!image->clear_value_offset) {
952 image->clear_value_offset = image->cmask.offset + image->cmask.size;
953 clear_value_size = 8;
954 }
955 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
956 image->alignment = MAX2(image->alignment, image->cmask.alignment);
957 }
958
959 static void
960 radv_image_alloc_dcc(struct radv_image *image)
961 {
962 assert(image->plane_count == 1);
963
964 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
965 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
966 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
967 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
968 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
969 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
970 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
971 }
972
973 static void
974 radv_image_alloc_htile(struct radv_image *image)
975 {
976 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
977
978 /* + 8 for storing the clear values */
979 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
980 image->size = image->clear_value_offset + 8;
981 if (radv_image_is_tc_compat_htile(image)) {
982 /* Metadata for the TC-compatible HTILE hardware bug which
983 * have to be fixed by updating ZRANGE_PRECISION when doing
984 * fast depth clears to 0.0f.
985 */
986 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
987 image->size = image->clear_value_offset + 16;
988 }
989 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
990 }
991
992 static inline bool
993 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
994 {
995 if (image->info.samples <= 1 &&
996 image->info.width * image->info.height <= 512 * 512) {
997 /* Do not enable CMASK or DCC for small surfaces where the cost
998 * of the eliminate pass can be higher than the benefit of fast
999 * clear. RadeonSI does this, but the image threshold is
1000 * different.
1001 */
1002 return false;
1003 }
1004
1005 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1006 (image->exclusive || image->queue_family_mask == 1);
1007 }
1008
1009 static inline bool
1010 radv_image_can_enable_dcc(struct radv_image *image)
1011 {
1012 return radv_image_can_enable_dcc_or_cmask(image) &&
1013 radv_image_has_dcc(image);
1014 }
1015
1016 static inline bool
1017 radv_image_can_enable_cmask(struct radv_image *image)
1018 {
1019 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1020 /* Do not enable CMASK for non-MSAA images (fast color clear)
1021 * because 128 bit formats are not supported, but FMASK might
1022 * still be used.
1023 */
1024 return false;
1025 }
1026
1027 return radv_image_can_enable_dcc_or_cmask(image) &&
1028 image->info.levels == 1 &&
1029 image->info.depth == 1 &&
1030 !image->planes[0].surface.is_linear;
1031 }
1032
1033 static inline bool
1034 radv_image_can_enable_fmask(struct radv_image *image)
1035 {
1036 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1037 }
1038
1039 static inline bool
1040 radv_image_can_enable_htile(struct radv_image *image)
1041 {
1042 return radv_image_has_htile(image) &&
1043 image->info.levels == 1 &&
1044 image->info.width * image->info.height >= 8 * 8;
1045 }
1046
1047 static void radv_image_disable_dcc(struct radv_image *image)
1048 {
1049 for (unsigned i = 0; i < image->plane_count; ++i)
1050 image->planes[i].surface.dcc_size = 0;
1051 }
1052
1053 static void radv_image_disable_htile(struct radv_image *image)
1054 {
1055 for (unsigned i = 0; i < image->plane_count; ++i)
1056 image->planes[i].surface.htile_size = 0;
1057 }
1058
1059 VkResult
1060 radv_image_create(VkDevice _device,
1061 const struct radv_image_create_info *create_info,
1062 const VkAllocationCallbacks* alloc,
1063 VkImage *pImage)
1064 {
1065 RADV_FROM_HANDLE(radv_device, device, _device);
1066 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1067 struct radv_image *image = NULL;
1068 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1069
1070 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1071 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1072
1073 radv_assert(pCreateInfo->mipLevels > 0);
1074 radv_assert(pCreateInfo->arrayLayers > 0);
1075 radv_assert(pCreateInfo->samples > 0);
1076 radv_assert(pCreateInfo->extent.width > 0);
1077 radv_assert(pCreateInfo->extent.height > 0);
1078 radv_assert(pCreateInfo->extent.depth > 0);
1079
1080 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1081 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1082 if (!image)
1083 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1084
1085 image->type = pCreateInfo->imageType;
1086 image->info.width = pCreateInfo->extent.width;
1087 image->info.height = pCreateInfo->extent.height;
1088 image->info.depth = pCreateInfo->extent.depth;
1089 image->info.samples = pCreateInfo->samples;
1090 image->info.storage_samples = pCreateInfo->samples;
1091 image->info.array_size = pCreateInfo->arrayLayers;
1092 image->info.levels = pCreateInfo->mipLevels;
1093 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1094
1095 image->vk_format = pCreateInfo->format;
1096 image->tiling = pCreateInfo->tiling;
1097 image->usage = pCreateInfo->usage;
1098 image->flags = pCreateInfo->flags;
1099
1100 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1101 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1102 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1103 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
1104 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1105 else
1106 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1107 }
1108
1109 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1110 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1111 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1112 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1113 image->info.surf_index = &device->image_mrt_offset_counter;
1114 }
1115
1116 image->plane_count = plane_count;
1117 image->size = 0;
1118 image->alignment = 1;
1119 for (unsigned plane = 0; plane < plane_count; ++plane) {
1120 struct ac_surf_info info = image->info;
1121 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1122
1123 if (plane) {
1124 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1125 assert(info.width % desc->width_divisor == 0);
1126 assert(info.height % desc->height_divisor == 0);
1127
1128 info.width /= desc->width_divisor;
1129 info.height /= desc->height_divisor;
1130 }
1131
1132 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1133
1134 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1135 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1136 image->alignment = image->planes[plane].surface.surf_alignment;
1137
1138 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1139 }
1140
1141 if (!create_info->no_metadata_planes) {
1142 /* Try to enable DCC first. */
1143 if (radv_image_can_enable_dcc(image)) {
1144 radv_image_alloc_dcc(image);
1145 if (image->info.samples > 1) {
1146 /* CMASK should be enabled because DCC fast
1147 * clear with MSAA needs it.
1148 */
1149 assert(radv_image_can_enable_cmask(image));
1150 radv_image_alloc_cmask(device, image);
1151 }
1152 } else {
1153 /* When DCC cannot be enabled, try CMASK. */
1154 radv_image_disable_dcc(image);
1155 if (radv_image_can_enable_cmask(image)) {
1156 radv_image_alloc_cmask(device, image);
1157 }
1158 }
1159
1160 /* Try to enable FMASK for multisampled images. */
1161 if (radv_image_can_enable_fmask(image)) {
1162 radv_image_alloc_fmask(device, image);
1163
1164 if (radv_use_tc_compat_cmask_for_image(device, image))
1165 image->tc_compatible_cmask = true;
1166 } else {
1167 /* Otherwise, try to enable HTILE for depth surfaces. */
1168 if (radv_image_can_enable_htile(image) &&
1169 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1170 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1171 radv_image_alloc_htile(image);
1172 } else {
1173 radv_image_disable_htile(image);
1174 }
1175 }
1176 } else {
1177 radv_image_disable_dcc(image);
1178 radv_image_disable_htile(image);
1179 }
1180
1181 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1182 image->alignment = MAX2(image->alignment, 4096);
1183 image->size = align64(image->size, image->alignment);
1184 image->offset = 0;
1185
1186 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1187 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1188 if (!image->bo) {
1189 vk_free2(&device->alloc, alloc, image);
1190 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1191 }
1192 }
1193
1194 *pImage = radv_image_to_handle(image);
1195
1196 return VK_SUCCESS;
1197 }
1198
1199 static void
1200 radv_image_view_make_descriptor(struct radv_image_view *iview,
1201 struct radv_device *device,
1202 VkFormat vk_format,
1203 const VkComponentMapping *components,
1204 bool is_storage_image, unsigned plane_id,
1205 unsigned descriptor_plane_id)
1206 {
1207 struct radv_image *image = iview->image;
1208 struct radv_image_plane *plane = &image->planes[plane_id];
1209 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1210 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1211 uint32_t blk_w;
1212 union radv_descriptor *descriptor;
1213 uint32_t hw_level = 0;
1214
1215 if (is_storage_image) {
1216 descriptor = &iview->storage_descriptor;
1217 } else {
1218 descriptor = &iview->descriptor;
1219 }
1220
1221 assert(vk_format_get_plane_count(vk_format) == 1);
1222 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1223 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1224
1225 if (device->physical_device->rad_info.chip_class >= GFX9)
1226 hw_level = iview->base_mip;
1227 si_make_texture_descriptor(device, image, is_storage_image,
1228 iview->type,
1229 vk_format,
1230 components,
1231 hw_level, hw_level + iview->level_count - 1,
1232 iview->base_layer,
1233 iview->base_layer + iview->layer_count - 1,
1234 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1235 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1236 iview->extent.depth,
1237 descriptor->plane_descriptors[descriptor_plane_id],
1238 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1239
1240 const struct legacy_surf_level *base_level_info = NULL;
1241 if (device->physical_device->rad_info.chip_class <= GFX9) {
1242 if (is_stencil)
1243 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1244 else
1245 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1246 }
1247 si_set_mutable_tex_desc_fields(device, image,
1248 base_level_info,
1249 plane_id,
1250 iview->base_mip,
1251 iview->base_mip,
1252 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1253 }
1254
1255 static unsigned
1256 radv_plane_from_aspect(VkImageAspectFlags mask)
1257 {
1258 switch(mask) {
1259 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1260 return 1;
1261 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1262 return 2;
1263 default:
1264 return 0;
1265 }
1266 }
1267
1268 VkFormat
1269 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1270 {
1271 switch(mask) {
1272 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1273 return image->planes[0].format;
1274 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1275 return image->planes[1].format;
1276 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1277 return image->planes[2].format;
1278 case VK_IMAGE_ASPECT_STENCIL_BIT:
1279 return vk_format_stencil_only(image->vk_format);
1280 case VK_IMAGE_ASPECT_DEPTH_BIT:
1281 return vk_format_depth_only(image->vk_format);
1282 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1283 return vk_format_depth_only(image->vk_format);
1284 default:
1285 return image->vk_format;
1286 }
1287 }
1288
1289 void
1290 radv_image_view_init(struct radv_image_view *iview,
1291 struct radv_device *device,
1292 const VkImageViewCreateInfo* pCreateInfo)
1293 {
1294 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1295 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1296
1297 switch (image->type) {
1298 case VK_IMAGE_TYPE_1D:
1299 case VK_IMAGE_TYPE_2D:
1300 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1301 break;
1302 case VK_IMAGE_TYPE_3D:
1303 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1304 <= radv_minify(image->info.depth, range->baseMipLevel));
1305 break;
1306 default:
1307 unreachable("bad VkImageType");
1308 }
1309 iview->image = image;
1310 iview->bo = image->bo;
1311 iview->type = pCreateInfo->viewType;
1312 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1313 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1314 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1315 iview->vk_format = pCreateInfo->format;
1316
1317 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1318 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1319 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1320 iview->vk_format = vk_format_depth_only(iview->vk_format);
1321 }
1322
1323 if (device->physical_device->rad_info.chip_class >= GFX9) {
1324 iview->extent = (VkExtent3D) {
1325 .width = image->info.width,
1326 .height = image->info.height,
1327 .depth = image->info.depth,
1328 };
1329 } else {
1330 iview->extent = (VkExtent3D) {
1331 .width = radv_minify(image->info.width , range->baseMipLevel),
1332 .height = radv_minify(image->info.height, range->baseMipLevel),
1333 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1334 };
1335 }
1336
1337 if (iview->vk_format != image->planes[iview->plane_id].format) {
1338 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1339 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1340 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1341 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1342
1343 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1344 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1345
1346 /* Comment ported from amdvlk -
1347 * If we have the following image:
1348 * Uncompressed pixels Compressed block sizes (4x4)
1349 * mip0: 22 x 22 6 x 6
1350 * mip1: 11 x 11 3 x 3
1351 * mip2: 5 x 5 2 x 2
1352 * mip3: 2 x 2 1 x 1
1353 * mip4: 1 x 1 1 x 1
1354 *
1355 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1356 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1357 * divide-by-two integer math):
1358 * mip0: 6x6
1359 * mip1: 3x3
1360 * mip2: 1x1
1361 * mip3: 1x1
1362 *
1363 * This means that mip2 will be missing texels.
1364 *
1365 * Fix this by calculating the base mip's width and height, then convert that, and round it
1366 * back up to get the level 0 size.
1367 * Clamp the converted size between the original values, and next power of two, which
1368 * means we don't oversize the image.
1369 */
1370 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1371 vk_format_is_compressed(image->vk_format) &&
1372 !vk_format_is_compressed(iview->vk_format)) {
1373 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1374 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1375
1376 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1377 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1378
1379 lvl_width <<= range->baseMipLevel;
1380 lvl_height <<= range->baseMipLevel;
1381
1382 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1383 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1384 }
1385 }
1386
1387 iview->base_layer = range->baseArrayLayer;
1388 iview->layer_count = radv_get_layerCount(image, range);
1389 iview->base_mip = range->baseMipLevel;
1390 iview->level_count = radv_get_levelCount(image, range);
1391
1392 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1393 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1394 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1395 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1396 }
1397 }
1398
1399 bool radv_layout_has_htile(const struct radv_image *image,
1400 VkImageLayout layout,
1401 unsigned queue_mask)
1402 {
1403 if (radv_image_is_tc_compat_htile(image))
1404 return layout != VK_IMAGE_LAYOUT_GENERAL;
1405
1406 return radv_image_has_htile(image) &&
1407 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1408 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1409 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1410 }
1411
1412 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1413 VkImageLayout layout,
1414 unsigned queue_mask)
1415 {
1416 if (radv_image_is_tc_compat_htile(image))
1417 return layout != VK_IMAGE_LAYOUT_GENERAL;
1418
1419 return radv_image_has_htile(image) &&
1420 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1421 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1422 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1423 }
1424
1425 bool radv_layout_can_fast_clear(const struct radv_image *image,
1426 VkImageLayout layout,
1427 unsigned queue_mask)
1428 {
1429 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1430 }
1431
1432 bool radv_layout_dcc_compressed(const struct radv_image *image,
1433 VkImageLayout layout,
1434 unsigned queue_mask)
1435 {
1436 /* Don't compress compute transfer dst, as image stores are not supported. */
1437 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1438 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1439 return false;
1440
1441 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1442 }
1443
1444
1445 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1446 {
1447 if (!image->exclusive)
1448 return image->queue_family_mask;
1449 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1450 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1451 if (family == VK_QUEUE_FAMILY_IGNORED)
1452 return 1u << queue_family;
1453 return 1u << family;
1454 }
1455
1456 VkResult
1457 radv_CreateImage(VkDevice device,
1458 const VkImageCreateInfo *pCreateInfo,
1459 const VkAllocationCallbacks *pAllocator,
1460 VkImage *pImage)
1461 {
1462 #ifdef ANDROID
1463 const VkNativeBufferANDROID *gralloc_info =
1464 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1465
1466 if (gralloc_info)
1467 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1468 pAllocator, pImage);
1469 #endif
1470
1471 const struct wsi_image_create_info *wsi_info =
1472 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1473 bool scanout = wsi_info && wsi_info->scanout;
1474
1475 return radv_image_create(device,
1476 &(struct radv_image_create_info) {
1477 .vk_info = pCreateInfo,
1478 .scanout = scanout,
1479 },
1480 pAllocator,
1481 pImage);
1482 }
1483
1484 void
1485 radv_DestroyImage(VkDevice _device, VkImage _image,
1486 const VkAllocationCallbacks *pAllocator)
1487 {
1488 RADV_FROM_HANDLE(radv_device, device, _device);
1489 RADV_FROM_HANDLE(radv_image, image, _image);
1490
1491 if (!image)
1492 return;
1493
1494 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1495 device->ws->buffer_destroy(image->bo);
1496
1497 if (image->owned_memory != VK_NULL_HANDLE)
1498 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1499
1500 vk_free2(&device->alloc, pAllocator, image);
1501 }
1502
1503 void radv_GetImageSubresourceLayout(
1504 VkDevice _device,
1505 VkImage _image,
1506 const VkImageSubresource* pSubresource,
1507 VkSubresourceLayout* pLayout)
1508 {
1509 RADV_FROM_HANDLE(radv_image, image, _image);
1510 RADV_FROM_HANDLE(radv_device, device, _device);
1511 int level = pSubresource->mipLevel;
1512 int layer = pSubresource->arrayLayer;
1513
1514 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1515
1516 struct radv_image_plane *plane = &image->planes[plane_id];
1517 struct radeon_surf *surface = &plane->surface;
1518
1519 if (device->physical_device->rad_info.chip_class >= GFX9) {
1520 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1521 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1522 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1523 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1524 /* Adjust the number of bytes between each row because
1525 * the pitch is actually the number of components per
1526 * row.
1527 */
1528 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1529 } else {
1530 assert(util_is_power_of_two_nonzero(surface->bpe));
1531 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1532 }
1533
1534 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1535 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1536 pLayout->size = surface->u.gfx9.surf_slice_size;
1537 if (image->type == VK_IMAGE_TYPE_3D)
1538 pLayout->size *= u_minify(image->info.depth, level);
1539 } else {
1540 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1541 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1542 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1543 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1544 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1545 if (image->type == VK_IMAGE_TYPE_3D)
1546 pLayout->size *= u_minify(image->info.depth, level);
1547 }
1548 }
1549
1550
1551 VkResult
1552 radv_CreateImageView(VkDevice _device,
1553 const VkImageViewCreateInfo *pCreateInfo,
1554 const VkAllocationCallbacks *pAllocator,
1555 VkImageView *pView)
1556 {
1557 RADV_FROM_HANDLE(radv_device, device, _device);
1558 struct radv_image_view *view;
1559
1560 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1561 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1562 if (view == NULL)
1563 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1564
1565 radv_image_view_init(view, device, pCreateInfo);
1566
1567 *pView = radv_image_view_to_handle(view);
1568
1569 return VK_SUCCESS;
1570 }
1571
1572 void
1573 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1574 const VkAllocationCallbacks *pAllocator)
1575 {
1576 RADV_FROM_HANDLE(radv_device, device, _device);
1577 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1578
1579 if (!iview)
1580 return;
1581 vk_free2(&device->alloc, pAllocator, iview);
1582 }
1583
1584 void radv_buffer_view_init(struct radv_buffer_view *view,
1585 struct radv_device *device,
1586 const VkBufferViewCreateInfo* pCreateInfo)
1587 {
1588 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1589
1590 view->bo = buffer->bo;
1591 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1592 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1593 view->vk_format = pCreateInfo->format;
1594
1595 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1596 pCreateInfo->offset, view->range, view->state);
1597 }
1598
1599 VkResult
1600 radv_CreateBufferView(VkDevice _device,
1601 const VkBufferViewCreateInfo *pCreateInfo,
1602 const VkAllocationCallbacks *pAllocator,
1603 VkBufferView *pView)
1604 {
1605 RADV_FROM_HANDLE(radv_device, device, _device);
1606 struct radv_buffer_view *view;
1607
1608 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1609 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1610 if (!view)
1611 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1612
1613 radv_buffer_view_init(view, device, pCreateInfo);
1614
1615 *pView = radv_buffer_view_to_handle(view);
1616
1617 return VK_SUCCESS;
1618 }
1619
1620 void
1621 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1622 const VkAllocationCallbacks *pAllocator)
1623 {
1624 RADV_FROM_HANDLE(radv_device, device, _device);
1625 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1626
1627 if (!view)
1628 return;
1629
1630 vk_free2(&device->alloc, pAllocator, view);
1631 }