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radv/gfx10: disable TC-compat HTILE for multisampled D32_SFLOAT format
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
87 */
88 if (pCreateInfo->samples >= 2 &&
89 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
90 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT &&
91 device->physical_device->rad_info.chip_class == GFX10)))
92 return false;
93
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
97 */
98 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
99 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
100 pCreateInfo->format != VK_FORMAT_D16_UNORM)
101 return false;
102
103 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
104 const struct VkImageFormatListCreateInfoKHR *format_list =
105 (const struct VkImageFormatListCreateInfoKHR *)
106 vk_find_struct_const(pCreateInfo->pNext,
107 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
108
109 /* We have to ignore the existence of the list if viewFormatCount = 0 */
110 if (format_list && format_list->viewFormatCount) {
111 /* compatibility is transitive, so we only need to check
112 * one format with everything else.
113 */
114 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
115 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
116 continue;
117
118 if (pCreateInfo->format != format_list->pViewFormats[i])
119 return false;
120 }
121 } else {
122 return false;
123 }
124 }
125
126 return true;
127 }
128
129 static bool
130 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
131 {
132 if (info->scanout)
133 return true;
134
135 if (!info->bo_metadata)
136 return false;
137
138 if (device->physical_device->rad_info.chip_class >= GFX9) {
139 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
140 } else {
141 return info->bo_metadata->u.legacy.scanout;
142 }
143 }
144
145 static bool
146 radv_use_dcc_for_image(struct radv_device *device,
147 const struct radv_image *image,
148 const struct radv_image_create_info *create_info,
149 const VkImageCreateInfo *pCreateInfo)
150 {
151 bool dcc_compatible_formats;
152 bool blendable;
153
154 /* DCC (Delta Color Compression) is only available for GFX8+. */
155 if (device->physical_device->rad_info.chip_class < GFX8)
156 return false;
157
158 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
159 return false;
160
161 if (image->shareable)
162 return false;
163
164 /* TODO: Enable DCC for storage images. */
165 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
166 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
167 return false;
168
169 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
170 return false;
171
172 if (vk_format_is_subsampled(pCreateInfo->format) ||
173 vk_format_get_plane_count(pCreateInfo->format) > 1)
174 return false;
175
176 /* TODO: Enable DCC for mipmaps on GFX9+. */
177 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
178 device->physical_device->rad_info.chip_class >= GFX9)
179 return false;
180
181 /* Do not enable DCC for mipmapped arrays because performance is worse. */
182 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
183 return false;
184
185 if (radv_surface_has_scanout(device, create_info))
186 return false;
187
188 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
189 * 2x can be enabled with an option.
190 */
191 if (pCreateInfo->samples > 2 ||
192 (pCreateInfo->samples == 2 &&
193 !device->physical_device->dcc_msaa_allowed))
194 return false;
195
196 /* Determine if the formats are DCC compatible. */
197 dcc_compatible_formats =
198 radv_is_colorbuffer_format_supported(pCreateInfo->format,
199 &blendable);
200
201 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
202 const struct VkImageFormatListCreateInfoKHR *format_list =
203 (const struct VkImageFormatListCreateInfoKHR *)
204 vk_find_struct_const(pCreateInfo->pNext,
205 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
206
207 /* We have to ignore the existence of the list if viewFormatCount = 0 */
208 if (format_list && format_list->viewFormatCount) {
209 /* compatibility is transitive, so we only need to check
210 * one format with everything else. */
211 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
212 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
213 continue;
214
215 if (!radv_dcc_formats_compatible(pCreateInfo->format,
216 format_list->pViewFormats[i]))
217 dcc_compatible_formats = false;
218 }
219 } else {
220 dcc_compatible_formats = false;
221 }
222 }
223
224 if (!dcc_compatible_formats)
225 return false;
226
227 return true;
228 }
229
230 static bool
231 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
232 struct radv_image *image)
233 {
234 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
235 return false;
236
237 /* TC-compat CMASK is only available for GFX8+. */
238 if (device->physical_device->rad_info.chip_class < GFX8)
239 return false;
240
241 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
242 return false;
243
244 if (radv_image_has_dcc(image))
245 return false;
246
247 if (!radv_image_has_cmask(image))
248 return false;
249
250 return true;
251 }
252
253 static void
254 radv_prefill_surface_from_metadata(struct radv_device *device,
255 struct radeon_surf *surface,
256 const struct radv_image_create_info *create_info)
257 {
258 const struct radeon_bo_metadata *md = create_info->bo_metadata;
259 if (device->physical_device->rad_info.chip_class >= GFX9) {
260 if (md->u.gfx9.swizzle_mode > 0)
261 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
262 else
263 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
264
265 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
266 } else {
267 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
268 surface->u.legacy.bankw = md->u.legacy.bankw;
269 surface->u.legacy.bankh = md->u.legacy.bankh;
270 surface->u.legacy.tile_split = md->u.legacy.tile_split;
271 surface->u.legacy.mtilea = md->u.legacy.mtilea;
272 surface->u.legacy.num_banks = md->u.legacy.num_banks;
273
274 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
276 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
277 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
278 else
279 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
280
281 }
282 }
283
284 static int
285 radv_init_surface(struct radv_device *device,
286 const struct radv_image *image,
287 struct radeon_surf *surface,
288 unsigned plane_id,
289 const struct radv_image_create_info *create_info)
290 {
291 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
292 unsigned array_mode = radv_choose_tiling(device, create_info);
293 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
294 const struct vk_format_description *desc = vk_format_description(format);
295 bool is_depth, is_stencil;
296
297 is_depth = vk_format_has_depth(desc);
298 is_stencil = vk_format_has_stencil(desc);
299
300 surface->blk_w = vk_format_get_blockwidth(format);
301 surface->blk_h = vk_format_get_blockheight(format);
302
303 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
304 /* align byte per element on dword */
305 if (surface->bpe == 3) {
306 surface->bpe = 4;
307 }
308 if (create_info->bo_metadata) {
309 radv_prefill_surface_from_metadata(device, surface, create_info);
310 } else {
311 surface->flags = RADEON_SURF_SET(array_mode, MODE);
312 }
313
314 switch (pCreateInfo->imageType){
315 case VK_IMAGE_TYPE_1D:
316 if (pCreateInfo->arrayLayers > 1)
317 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
318 else
319 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
320 break;
321 case VK_IMAGE_TYPE_2D:
322 if (pCreateInfo->arrayLayers > 1)
323 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
324 else
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
326 break;
327 case VK_IMAGE_TYPE_3D:
328 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
329 break;
330 default:
331 unreachable("unhandled image type");
332 }
333
334 if (is_depth) {
335 surface->flags |= RADEON_SURF_ZBUFFER;
336 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
337 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
338 }
339
340 if (is_stencil)
341 surface->flags |= RADEON_SURF_SBUFFER;
342
343 if (device->physical_device->rad_info.chip_class >= GFX9 &&
344 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
345 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
346 vk_format_is_compressed(pCreateInfo->format))
347 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
348
349 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
350
351 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
352 surface->flags |= RADEON_SURF_DISABLE_DCC;
353
354 if (radv_surface_has_scanout(device, create_info))
355 surface->flags |= RADEON_SURF_SCANOUT;
356
357 return 0;
358 }
359
360 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
361 {
362 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
363 }
364
365 static inline unsigned
366 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
367 {
368 if (stencil)
369 return plane->surface.u.legacy.stencil_tiling_index[level];
370 else
371 return plane->surface.u.legacy.tiling_index[level];
372 }
373
374 static unsigned radv_map_swizzle(unsigned swizzle)
375 {
376 switch (swizzle) {
377 case VK_SWIZZLE_Y:
378 return V_008F0C_SQ_SEL_Y;
379 case VK_SWIZZLE_Z:
380 return V_008F0C_SQ_SEL_Z;
381 case VK_SWIZZLE_W:
382 return V_008F0C_SQ_SEL_W;
383 case VK_SWIZZLE_0:
384 return V_008F0C_SQ_SEL_0;
385 case VK_SWIZZLE_1:
386 return V_008F0C_SQ_SEL_1;
387 default: /* VK_SWIZZLE_X */
388 return V_008F0C_SQ_SEL_X;
389 }
390 }
391
392 static void
393 radv_make_buffer_descriptor(struct radv_device *device,
394 struct radv_buffer *buffer,
395 VkFormat vk_format,
396 unsigned offset,
397 unsigned range,
398 uint32_t *state)
399 {
400 const struct vk_format_description *desc;
401 unsigned stride;
402 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
403 uint64_t va = gpu_address + buffer->offset;
404 unsigned num_format, data_format;
405 int first_non_void;
406 desc = vk_format_description(vk_format);
407 first_non_void = vk_format_get_first_non_void_channel(vk_format);
408 stride = desc->block.bits / 8;
409
410 va += offset;
411 state[0] = va;
412 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
413 S_008F04_STRIDE(stride);
414
415 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
416 range /= stride;
417 }
418
419 state[2] = range;
420 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
421 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
422 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
423 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
424
425 if (device->physical_device->rad_info.chip_class >= GFX10) {
426 const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
427
428 /* OOB_SELECT chooses the out-of-bounds check:
429 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
430 * - 1: index >= NUM_RECORDS
431 * - 2: NUM_RECORDS == 0
432 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
433 * else: swizzle_address >= NUM_RECORDS
434 */
435 state[3] |= S_008F0C_FORMAT(fmt->img_format) |
436 S_008F0C_OOB_SELECT(0) |
437 S_008F0C_RESOURCE_LEVEL(1);
438 } else {
439 num_format = radv_translate_buffer_numformat(desc, first_non_void);
440 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
441
442 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
443 assert(num_format != ~0);
444
445 state[3] |= S_008F0C_NUM_FORMAT(num_format) |
446 S_008F0C_DATA_FORMAT(data_format);
447 }
448 }
449
450 static void
451 si_set_mutable_tex_desc_fields(struct radv_device *device,
452 struct radv_image *image,
453 const struct legacy_surf_level *base_level_info,
454 unsigned plane_id,
455 unsigned base_level, unsigned first_level,
456 unsigned block_width, bool is_stencil,
457 bool is_storage_image, uint32_t *state)
458 {
459 struct radv_image_plane *plane = &image->planes[plane_id];
460 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
461 uint64_t va = gpu_address + plane->offset;
462 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
463 uint64_t meta_va = 0;
464 if (chip_class >= GFX9) {
465 if (is_stencil)
466 va += plane->surface.u.gfx9.stencil_offset;
467 else
468 va += plane->surface.u.gfx9.surf_offset;
469 } else
470 va += base_level_info->offset;
471
472 state[0] = va >> 8;
473 if (chip_class >= GFX9 ||
474 base_level_info->mode == RADEON_SURF_MODE_2D)
475 state[0] |= plane->surface.tile_swizzle;
476 state[1] &= C_008F14_BASE_ADDRESS_HI;
477 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
478
479 if (chip_class >= GFX8) {
480 state[6] &= C_008F28_COMPRESSION_EN;
481 state[7] = 0;
482 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
483 meta_va = gpu_address + image->dcc_offset;
484 if (chip_class <= GFX8)
485 meta_va += base_level_info->dcc_offset;
486 } else if (!is_storage_image &&
487 radv_image_is_tc_compat_htile(image)) {
488 meta_va = gpu_address + image->htile_offset;
489 }
490
491 if (meta_va) {
492 state[6] |= S_008F28_COMPRESSION_EN(1);
493 if (chip_class <= GFX9) {
494 state[7] = meta_va >> 8;
495 state[7] |= plane->surface.tile_swizzle;
496 }
497 }
498 }
499
500 if (chip_class >= GFX10) {
501 state[3] &= C_00A00C_SW_MODE;
502
503 if (is_stencil) {
504 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
505 } else {
506 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
507 }
508
509 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
510 C_00A018_META_PIPE_ALIGNED;
511
512 if (meta_va) {
513 struct gfx9_surf_meta_flags meta;
514
515 if (image->dcc_offset)
516 meta = plane->surface.u.gfx9.dcc;
517 else
518 meta = plane->surface.u.gfx9.htile;
519
520 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
521 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
522 }
523
524 state[7] = meta_va >> 16;
525 } else if (chip_class >= GFX9) {
526 state[3] &= C_008F1C_SW_MODE;
527 state[4] &= C_008F20_PITCH;
528
529 if (is_stencil) {
530 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
531 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
532 } else {
533 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
534 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
535 }
536
537 state[5] &= C_008F24_META_DATA_ADDRESS &
538 C_008F24_META_PIPE_ALIGNED &
539 C_008F24_META_RB_ALIGNED;
540 if (meta_va) {
541 struct gfx9_surf_meta_flags meta;
542
543 if (image->dcc_offset)
544 meta = plane->surface.u.gfx9.dcc;
545 else
546 meta = plane->surface.u.gfx9.htile;
547
548 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
549 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
550 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
551 }
552 } else {
553 /* GFX6-GFX8 */
554 unsigned pitch = base_level_info->nblk_x * block_width;
555 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
556
557 state[3] &= C_008F1C_TILING_INDEX;
558 state[3] |= S_008F1C_TILING_INDEX(index);
559 state[4] &= C_008F20_PITCH;
560 state[4] |= S_008F20_PITCH(pitch - 1);
561 }
562 }
563
564 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
565 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
566 {
567 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
568 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
569
570 /* GFX9 allocates 1D textures as 2D. */
571 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
572 image_type = VK_IMAGE_TYPE_2D;
573 switch (image_type) {
574 case VK_IMAGE_TYPE_1D:
575 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
576 case VK_IMAGE_TYPE_2D:
577 if (nr_samples > 1)
578 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
579 else
580 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
581 case VK_IMAGE_TYPE_3D:
582 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
583 return V_008F1C_SQ_RSRC_IMG_3D;
584 else
585 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
586 default:
587 unreachable("illegal image type");
588 }
589 }
590
591 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
592 {
593 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
594
595 if (swizzle[3] == VK_SWIZZLE_X) {
596 /* For the pre-defined border color values (white, opaque
597 * black, transparent black), the only thing that matters is
598 * that the alpha channel winds up in the correct place
599 * (because the RGB channels are all the same) so either of
600 * these enumerations will work.
601 */
602 if (swizzle[2] == VK_SWIZZLE_Y)
603 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
604 else
605 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
606 } else if (swizzle[0] == VK_SWIZZLE_X) {
607 if (swizzle[1] == VK_SWIZZLE_Y)
608 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
609 else
610 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
611 } else if (swizzle[1] == VK_SWIZZLE_X) {
612 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
613 } else if (swizzle[2] == VK_SWIZZLE_X) {
614 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
615 }
616
617 return bc_swizzle;
618 }
619
620 /**
621 * Build the sampler view descriptor for a texture (GFX10).
622 */
623 static void
624 gfx10_make_texture_descriptor(struct radv_device *device,
625 struct radv_image *image,
626 bool is_storage_image,
627 VkImageViewType view_type,
628 VkFormat vk_format,
629 const VkComponentMapping *mapping,
630 unsigned first_level, unsigned last_level,
631 unsigned first_layer, unsigned last_layer,
632 unsigned width, unsigned height, unsigned depth,
633 uint32_t *state,
634 uint32_t *fmask_state)
635 {
636 const struct vk_format_description *desc;
637 enum vk_swizzle swizzle[4];
638 unsigned img_format;
639 unsigned type;
640
641 desc = vk_format_description(vk_format);
642 img_format = gfx10_format_table[vk_format].img_format;
643
644 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
645 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
646 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
647 } else {
648 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
649 }
650
651 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
652 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
653 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
654 height = 1;
655 depth = image->info.array_size;
656 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
657 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
658 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
659 depth = image->info.array_size;
660 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
661 depth = image->info.array_size / 6;
662
663 state[0] = 0;
664 state[1] = S_00A004_FORMAT(img_format) |
665 S_00A004_WIDTH_LO(width - 1);
666 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
667 S_00A008_HEIGHT(height - 1) |
668 S_00A008_RESOURCE_LEVEL(1);
669 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
670 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
671 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
672 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
673 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
674 0 : first_level) |
675 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
676 util_logbase2(image->info.samples) :
677 last_level) |
678 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
679 S_00A00C_TYPE(type);
680 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
681 * to know the total number of layers.
682 */
683 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
684 S_00A010_BASE_ARRAY(first_layer);
685 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
686 S_00A014_MAX_MIP(image->info.samples > 1 ?
687 util_logbase2(image->info.samples) :
688 image->info.levels - 1) |
689 S_00A014_PERF_MOD(4);
690 state[6] = 0;
691 state[7] = 0;
692
693 if (radv_dcc_enabled(image, first_level)) {
694 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
695
696 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
697 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
698 S_00A018_ALPHA_IS_ON_MSB(swap <= 1);
699 }
700
701 /* Initialize the sampler view for FMASK. */
702 if (radv_image_has_fmask(image)) {
703 uint64_t gpu_address = radv_buffer_get_va(image->bo);
704 uint32_t format;
705 uint64_t va;
706
707 assert(image->plane_count == 1);
708
709 va = gpu_address + image->offset + image->fmask.offset;
710
711 switch (image->info.samples) {
712 case 2:
713 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
714 break;
715 case 4:
716 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
717 break;
718 case 8:
719 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
720 break;
721 default:
722 unreachable("invalid nr_samples");
723 }
724
725 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
726 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
727 S_00A004_FORMAT(format) |
728 S_00A004_WIDTH_LO(width - 1);
729 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
730 S_00A008_HEIGHT(height - 1) |
731 S_00A008_RESOURCE_LEVEL(1);
732 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
733 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
734 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
735 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
736 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
737 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
738 fmask_state[4] = S_00A010_DEPTH(last_layer) |
739 S_00A010_BASE_ARRAY(first_layer);
740 fmask_state[5] = 0;
741 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
742 fmask_state[7] = 0;
743 } else if (fmask_state)
744 memset(fmask_state, 0, 8 * 4);
745 }
746
747 /**
748 * Build the sampler view descriptor for a texture (SI-GFX9)
749 */
750 static void
751 si_make_texture_descriptor(struct radv_device *device,
752 struct radv_image *image,
753 bool is_storage_image,
754 VkImageViewType view_type,
755 VkFormat vk_format,
756 const VkComponentMapping *mapping,
757 unsigned first_level, unsigned last_level,
758 unsigned first_layer, unsigned last_layer,
759 unsigned width, unsigned height, unsigned depth,
760 uint32_t *state,
761 uint32_t *fmask_state)
762 {
763 const struct vk_format_description *desc;
764 enum vk_swizzle swizzle[4];
765 int first_non_void;
766 unsigned num_format, data_format, type;
767
768 desc = vk_format_description(vk_format);
769
770 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
771 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
772 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
773 } else {
774 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
775 }
776
777 first_non_void = vk_format_get_first_non_void_channel(vk_format);
778
779 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
780 if (num_format == ~0) {
781 num_format = 0;
782 }
783
784 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
785 if (data_format == ~0) {
786 data_format = 0;
787 }
788
789 /* S8 with either Z16 or Z32 HTILE need a special format. */
790 if (device->physical_device->rad_info.chip_class >= GFX9 &&
791 vk_format == VK_FORMAT_S8_UINT &&
792 radv_image_is_tc_compat_htile(image)) {
793 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
794 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
795 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
796 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
797 }
798 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
799 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
800 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
801 height = 1;
802 depth = image->info.array_size;
803 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
804 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
805 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
806 depth = image->info.array_size;
807 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
808 depth = image->info.array_size / 6;
809
810 state[0] = 0;
811 state[1] = (S_008F14_DATA_FORMAT(data_format) |
812 S_008F14_NUM_FORMAT(num_format));
813 state[2] = (S_008F18_WIDTH(width - 1) |
814 S_008F18_HEIGHT(height - 1) |
815 S_008F18_PERF_MOD(4));
816 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
817 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
818 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
819 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
820 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
821 0 : first_level) |
822 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
823 util_logbase2(image->info.samples) :
824 last_level) |
825 S_008F1C_TYPE(type));
826 state[4] = 0;
827 state[5] = S_008F24_BASE_ARRAY(first_layer);
828 state[6] = 0;
829 state[7] = 0;
830
831 if (device->physical_device->rad_info.chip_class >= GFX9) {
832 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
833
834 /* Depth is the last accessible layer on Gfx9.
835 * The hw doesn't need to know the total number of layers.
836 */
837 if (type == V_008F1C_SQ_RSRC_IMG_3D)
838 state[4] |= S_008F20_DEPTH(depth - 1);
839 else
840 state[4] |= S_008F20_DEPTH(last_layer);
841
842 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
843 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
844 util_logbase2(image->info.samples) :
845 image->info.levels - 1);
846 } else {
847 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
848 state[4] |= S_008F20_DEPTH(depth - 1);
849 state[5] |= S_008F24_LAST_ARRAY(last_layer);
850 }
851 if (image->dcc_offset) {
852 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
853
854 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
855 } else {
856 /* The last dword is unused by hw. The shader uses it to clear
857 * bits in the first dword of sampler state.
858 */
859 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
860 if (first_level == last_level)
861 state[7] = C_008F30_MAX_ANISO_RATIO;
862 else
863 state[7] = 0xffffffff;
864 }
865 }
866
867 /* Initialize the sampler view for FMASK. */
868 if (radv_image_has_fmask(image)) {
869 uint32_t fmask_format, num_format;
870 uint64_t gpu_address = radv_buffer_get_va(image->bo);
871 uint64_t va;
872
873 assert(image->plane_count == 1);
874
875 va = gpu_address + image->offset + image->fmask.offset;
876
877 if (device->physical_device->rad_info.chip_class >= GFX9) {
878 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
879 switch (image->info.samples) {
880 case 2:
881 num_format = V_008F14_IMG_FMASK_8_2_2;
882 break;
883 case 4:
884 num_format = V_008F14_IMG_FMASK_8_4_4;
885 break;
886 case 8:
887 num_format = V_008F14_IMG_FMASK_32_8_8;
888 break;
889 default:
890 unreachable("invalid nr_samples");
891 }
892 } else {
893 switch (image->info.samples) {
894 case 2:
895 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
896 break;
897 case 4:
898 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
899 break;
900 case 8:
901 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
902 break;
903 default:
904 assert(0);
905 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
906 }
907 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
908 }
909
910 fmask_state[0] = va >> 8;
911 fmask_state[0] |= image->fmask.tile_swizzle;
912 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
913 S_008F14_DATA_FORMAT(fmask_format) |
914 S_008F14_NUM_FORMAT(num_format);
915 fmask_state[2] = S_008F18_WIDTH(width - 1) |
916 S_008F18_HEIGHT(height - 1);
917 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
918 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
919 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
920 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
921 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
922 fmask_state[4] = 0;
923 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
924 fmask_state[6] = 0;
925 fmask_state[7] = 0;
926
927 if (device->physical_device->rad_info.chip_class >= GFX9) {
928 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
929 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
930 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
931 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
932 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
933
934 if (radv_image_is_tc_compat_cmask(image)) {
935 va = gpu_address + image->offset + image->cmask.offset;
936
937 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
938 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
939 fmask_state[7] |= va >> 8;
940 }
941 } else {
942 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
943 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
944 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
945 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
946
947 if (radv_image_is_tc_compat_cmask(image)) {
948 va = gpu_address + image->offset + image->cmask.offset;
949
950 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
951 fmask_state[7] |= va >> 8;
952 }
953 }
954 } else if (fmask_state)
955 memset(fmask_state, 0, 8 * 4);
956 }
957
958 static void
959 radv_make_texture_descriptor(struct radv_device *device,
960 struct radv_image *image,
961 bool is_storage_image,
962 VkImageViewType view_type,
963 VkFormat vk_format,
964 const VkComponentMapping *mapping,
965 unsigned first_level, unsigned last_level,
966 unsigned first_layer, unsigned last_layer,
967 unsigned width, unsigned height, unsigned depth,
968 uint32_t *state,
969 uint32_t *fmask_state)
970 {
971 if (device->physical_device->rad_info.chip_class >= GFX10) {
972 gfx10_make_texture_descriptor(device, image, is_storage_image,
973 view_type, vk_format, mapping,
974 first_level, last_level,
975 first_layer, last_layer,
976 width, height, depth,
977 state, fmask_state);
978 } else {
979 si_make_texture_descriptor(device, image, is_storage_image,
980 view_type, vk_format, mapping,
981 first_level, last_level,
982 first_layer, last_layer,
983 width, height, depth,
984 state, fmask_state);
985 }
986 }
987
988 static void
989 radv_query_opaque_metadata(struct radv_device *device,
990 struct radv_image *image,
991 struct radeon_bo_metadata *md)
992 {
993 static const VkComponentMapping fixedmapping;
994 uint32_t desc[8], i;
995
996 assert(image->plane_count == 1);
997
998 /* Metadata image format format version 1:
999 * [0] = 1 (metadata format identifier)
1000 * [1] = (VENDOR_ID << 16) | PCI_ID
1001 * [2:9] = image descriptor for the whole resource
1002 * [2] is always 0, because the base address is cleared
1003 * [9] is the DCC offset bits [39:8] from the beginning of
1004 * the buffer
1005 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1006 */
1007 md->metadata[0] = 1; /* metadata image format version 1 */
1008
1009 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1010 md->metadata[1] = si_get_bo_metadata_word1(device);
1011
1012
1013 radv_make_texture_descriptor(device, image, false,
1014 (VkImageViewType)image->type, image->vk_format,
1015 &fixedmapping, 0, image->info.levels - 1, 0,
1016 image->info.array_size - 1,
1017 image->info.width, image->info.height,
1018 image->info.depth,
1019 desc, NULL);
1020
1021 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1022 image->planes[0].surface.blk_w, false, false, desc);
1023
1024 /* Clear the base address and set the relative DCC offset. */
1025 desc[0] = 0;
1026 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1027 desc[7] = image->dcc_offset >> 8;
1028
1029 /* Dwords [2:9] contain the image descriptor. */
1030 memcpy(&md->metadata[2], desc, sizeof(desc));
1031
1032 /* Dwords [10:..] contain the mipmap level offsets. */
1033 if (device->physical_device->rad_info.chip_class <= GFX8) {
1034 for (i = 0; i <= image->info.levels - 1; i++)
1035 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1036 md->size_metadata = (11 + image->info.levels - 1) * 4;
1037 }
1038 }
1039
1040 void
1041 radv_init_metadata(struct radv_device *device,
1042 struct radv_image *image,
1043 struct radeon_bo_metadata *metadata)
1044 {
1045 struct radeon_surf *surface = &image->planes[0].surface;
1046
1047 memset(metadata, 0, sizeof(*metadata));
1048
1049 if (device->physical_device->rad_info.chip_class >= GFX9) {
1050 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1051 } else {
1052 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1053 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1054 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1055 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1056 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1057 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1058 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1059 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1060 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1061 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1062 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1063 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1064 }
1065 radv_query_opaque_metadata(device, image, metadata);
1066 }
1067
1068 void
1069 radv_image_override_offset_stride(struct radv_device *device,
1070 struct radv_image *image,
1071 uint64_t offset, uint32_t stride)
1072 {
1073 struct radeon_surf *surface = &image->planes[0].surface;
1074 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1075
1076 if (device->physical_device->rad_info.chip_class >= GFX9) {
1077 if (stride) {
1078 surface->u.gfx9.surf_pitch = stride;
1079 surface->u.gfx9.surf_slice_size =
1080 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1081 }
1082 surface->u.gfx9.surf_offset = offset;
1083 } else {
1084 surface->u.legacy.level[0].nblk_x = stride;
1085 surface->u.legacy.level[0].slice_size_dw =
1086 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1087
1088 if (offset) {
1089 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1090 surface->u.legacy.level[i].offset += offset;
1091 }
1092
1093 }
1094 }
1095
1096 /* The number of samples can be specified independently of the texture. */
1097 static void
1098 radv_image_get_fmask_info(struct radv_device *device,
1099 struct radv_image *image,
1100 unsigned nr_samples,
1101 struct radv_fmask_info *out)
1102 {
1103 if (device->physical_device->rad_info.chip_class >= GFX9) {
1104 out->alignment = image->planes[0].surface.fmask_alignment;
1105 out->size = image->planes[0].surface.fmask_size;
1106 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1107 return;
1108 }
1109
1110 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
1111 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
1112 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
1113 out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
1114 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
1115 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1116 out->alignment = image->planes[0].surface.fmask_alignment;
1117 out->size = image->planes[0].surface.fmask_size;
1118
1119 assert(!out->tile_swizzle || !image->shareable);
1120 }
1121
1122 static void
1123 radv_image_alloc_fmask(struct radv_device *device,
1124 struct radv_image *image)
1125 {
1126 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
1127
1128 image->fmask.offset = align64(image->size, image->fmask.alignment);
1129 image->size = image->fmask.offset + image->fmask.size;
1130 image->alignment = MAX2(image->alignment, image->fmask.alignment);
1131 }
1132
1133 static void
1134 radv_image_get_cmask_info(struct radv_device *device,
1135 struct radv_image *image,
1136 struct radv_cmask_info *out)
1137 {
1138 assert(image->plane_count == 1);
1139
1140 if (device->physical_device->rad_info.chip_class >= GFX9) {
1141 out->alignment = image->planes[0].surface.cmask_alignment;
1142 out->size = image->planes[0].surface.cmask_size;
1143 return;
1144 }
1145
1146 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
1147 out->alignment = image->planes[0].surface.cmask_alignment;
1148 out->slice_size = image->planes[0].surface.cmask_slice_size;
1149 out->size = image->planes[0].surface.cmask_size;
1150 }
1151
1152 static void
1153 radv_image_alloc_cmask(struct radv_device *device,
1154 struct radv_image *image)
1155 {
1156 uint32_t clear_value_size = 0;
1157 radv_image_get_cmask_info(device, image, &image->cmask);
1158
1159 if (!image->cmask.size)
1160 return;
1161
1162 assert(image->cmask.alignment);
1163
1164 image->cmask.offset = align64(image->size, image->cmask.alignment);
1165 /* + 8 for storing the clear values */
1166 if (!image->clear_value_offset) {
1167 image->clear_value_offset = image->cmask.offset + image->cmask.size;
1168 clear_value_size = 8;
1169 }
1170 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
1171 image->alignment = MAX2(image->alignment, image->cmask.alignment);
1172 }
1173
1174 static void
1175 radv_image_alloc_dcc(struct radv_image *image)
1176 {
1177 assert(image->plane_count == 1);
1178
1179 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1180 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1181 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1182 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1183 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1184 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1185 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1186 }
1187
1188 static void
1189 radv_image_alloc_htile(struct radv_image *image)
1190 {
1191 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1192
1193 /* + 8 for storing the clear values */
1194 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1195 image->size = image->clear_value_offset + 8;
1196 if (radv_image_is_tc_compat_htile(image)) {
1197 /* Metadata for the TC-compatible HTILE hardware bug which
1198 * have to be fixed by updating ZRANGE_PRECISION when doing
1199 * fast depth clears to 0.0f.
1200 */
1201 image->tc_compat_zrange_offset = image->size;
1202 image->size = image->tc_compat_zrange_offset + 4;
1203 }
1204 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1205 }
1206
1207 static inline bool
1208 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1209 {
1210 if (image->info.samples <= 1 &&
1211 image->info.width * image->info.height <= 512 * 512) {
1212 /* Do not enable CMASK or DCC for small surfaces where the cost
1213 * of the eliminate pass can be higher than the benefit of fast
1214 * clear. RadeonSI does this, but the image threshold is
1215 * different.
1216 */
1217 return false;
1218 }
1219
1220 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1221 (image->exclusive || image->queue_family_mask == 1);
1222 }
1223
1224 static inline bool
1225 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1226 {
1227 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1228 !radv_image_has_dcc(image))
1229 return false;
1230
1231 /* On GFX8, DCC layers can be interleaved and it's currently only
1232 * enabled if slice size is equal to the per slice fast clear size
1233 * because the driver assumes that portions of multiple layers are
1234 * contiguous during fast clears.
1235 */
1236 if (image->info.array_size > 1) {
1237 const struct legacy_surf_level *surf_level =
1238 &image->planes[0].surface.u.legacy.level[0];
1239
1240 assert(device->physical_device->rad_info.chip_class == GFX8);
1241
1242 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1243 return false;
1244 }
1245
1246 return true;
1247 }
1248
1249 static inline bool
1250 radv_image_can_enable_cmask(struct radv_image *image)
1251 {
1252 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1253 /* Do not enable CMASK for non-MSAA images (fast color clear)
1254 * because 128 bit formats are not supported, but FMASK might
1255 * still be used.
1256 */
1257 return false;
1258 }
1259
1260 return radv_image_can_enable_dcc_or_cmask(image) &&
1261 image->info.levels == 1 &&
1262 image->info.depth == 1 &&
1263 !image->planes[0].surface.is_linear;
1264 }
1265
1266 static inline bool
1267 radv_image_can_enable_fmask(struct radv_image *image)
1268 {
1269 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1270 }
1271
1272 static inline bool
1273 radv_image_can_enable_htile(struct radv_image *image)
1274 {
1275 return radv_image_has_htile(image) &&
1276 image->info.levels == 1 &&
1277 image->info.width * image->info.height >= 8 * 8;
1278 }
1279
1280 static void radv_image_disable_dcc(struct radv_image *image)
1281 {
1282 for (unsigned i = 0; i < image->plane_count; ++i)
1283 image->planes[i].surface.dcc_size = 0;
1284 }
1285
1286 static void radv_image_disable_htile(struct radv_image *image)
1287 {
1288 for (unsigned i = 0; i < image->plane_count; ++i)
1289 image->planes[i].surface.htile_size = 0;
1290 }
1291
1292 VkResult
1293 radv_image_create(VkDevice _device,
1294 const struct radv_image_create_info *create_info,
1295 const VkAllocationCallbacks* alloc,
1296 VkImage *pImage)
1297 {
1298 RADV_FROM_HANDLE(radv_device, device, _device);
1299 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1300 struct radv_image *image = NULL;
1301 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1302
1303 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1304 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1305
1306 radv_assert(pCreateInfo->mipLevels > 0);
1307 radv_assert(pCreateInfo->arrayLayers > 0);
1308 radv_assert(pCreateInfo->samples > 0);
1309 radv_assert(pCreateInfo->extent.width > 0);
1310 radv_assert(pCreateInfo->extent.height > 0);
1311 radv_assert(pCreateInfo->extent.depth > 0);
1312
1313 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1314 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1315 if (!image)
1316 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1317
1318 image->type = pCreateInfo->imageType;
1319 image->info.width = pCreateInfo->extent.width;
1320 image->info.height = pCreateInfo->extent.height;
1321 image->info.depth = pCreateInfo->extent.depth;
1322 image->info.samples = pCreateInfo->samples;
1323 image->info.storage_samples = pCreateInfo->samples;
1324 image->info.array_size = pCreateInfo->arrayLayers;
1325 image->info.levels = pCreateInfo->mipLevels;
1326 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1327
1328 image->vk_format = pCreateInfo->format;
1329 image->tiling = pCreateInfo->tiling;
1330 image->usage = pCreateInfo->usage;
1331 image->flags = pCreateInfo->flags;
1332
1333 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1334 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1335 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1336 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1337 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1338 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1339 else
1340 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1341 }
1342
1343 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1344 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1345 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1346 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1347 image->info.surf_index = &device->image_mrt_offset_counter;
1348 }
1349
1350 image->plane_count = plane_count;
1351 image->size = 0;
1352 image->alignment = 1;
1353 for (unsigned plane = 0; plane < plane_count; ++plane) {
1354 struct ac_surf_info info = image->info;
1355 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1356
1357 if (plane) {
1358 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1359 assert(info.width % desc->width_divisor == 0);
1360 assert(info.height % desc->height_divisor == 0);
1361
1362 info.width /= desc->width_divisor;
1363 info.height /= desc->height_divisor;
1364 }
1365
1366 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1367
1368 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1369 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1370 image->alignment = image->planes[plane].surface.surf_alignment;
1371
1372 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1373 }
1374
1375 if (!create_info->no_metadata_planes) {
1376 /* Try to enable DCC first. */
1377 if (radv_image_can_enable_dcc(device, image)) {
1378 radv_image_alloc_dcc(image);
1379 if (image->info.samples > 1) {
1380 /* CMASK should be enabled because DCC fast
1381 * clear with MSAA needs it.
1382 */
1383 assert(radv_image_can_enable_cmask(image));
1384 radv_image_alloc_cmask(device, image);
1385 }
1386 } else {
1387 /* When DCC cannot be enabled, try CMASK. */
1388 radv_image_disable_dcc(image);
1389 if (radv_image_can_enable_cmask(image)) {
1390 radv_image_alloc_cmask(device, image);
1391 }
1392 }
1393
1394 /* Try to enable FMASK for multisampled images. */
1395 if (radv_image_can_enable_fmask(image)) {
1396 radv_image_alloc_fmask(device, image);
1397
1398 if (radv_use_tc_compat_cmask_for_image(device, image))
1399 image->tc_compatible_cmask = true;
1400 } else {
1401 /* Otherwise, try to enable HTILE for depth surfaces. */
1402 if (radv_image_can_enable_htile(image) &&
1403 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1404 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1405 radv_image_alloc_htile(image);
1406 } else {
1407 radv_image_disable_htile(image);
1408 }
1409 }
1410 } else {
1411 radv_image_disable_dcc(image);
1412 radv_image_disable_htile(image);
1413 }
1414
1415 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1416 image->alignment = MAX2(image->alignment, 4096);
1417 image->size = align64(image->size, image->alignment);
1418 image->offset = 0;
1419
1420 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1421 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1422 if (!image->bo) {
1423 vk_free2(&device->alloc, alloc, image);
1424 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1425 }
1426 }
1427
1428 *pImage = radv_image_to_handle(image);
1429
1430 return VK_SUCCESS;
1431 }
1432
1433 static void
1434 radv_image_view_make_descriptor(struct radv_image_view *iview,
1435 struct radv_device *device,
1436 VkFormat vk_format,
1437 const VkComponentMapping *components,
1438 bool is_storage_image, unsigned plane_id,
1439 unsigned descriptor_plane_id)
1440 {
1441 struct radv_image *image = iview->image;
1442 struct radv_image_plane *plane = &image->planes[plane_id];
1443 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1444 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1445 uint32_t blk_w;
1446 union radv_descriptor *descriptor;
1447 uint32_t hw_level = 0;
1448
1449 if (is_storage_image) {
1450 descriptor = &iview->storage_descriptor;
1451 } else {
1452 descriptor = &iview->descriptor;
1453 }
1454
1455 assert(vk_format_get_plane_count(vk_format) == 1);
1456 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1457 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1458
1459 if (device->physical_device->rad_info.chip_class >= GFX9)
1460 hw_level = iview->base_mip;
1461 radv_make_texture_descriptor(device, image, is_storage_image,
1462 iview->type,
1463 vk_format,
1464 components,
1465 hw_level, hw_level + iview->level_count - 1,
1466 iview->base_layer,
1467 iview->base_layer + iview->layer_count - 1,
1468 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1469 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1470 iview->extent.depth,
1471 descriptor->plane_descriptors[descriptor_plane_id],
1472 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1473
1474 const struct legacy_surf_level *base_level_info = NULL;
1475 if (device->physical_device->rad_info.chip_class <= GFX9) {
1476 if (is_stencil)
1477 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1478 else
1479 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1480 }
1481 si_set_mutable_tex_desc_fields(device, image,
1482 base_level_info,
1483 plane_id,
1484 iview->base_mip,
1485 iview->base_mip,
1486 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1487 }
1488
1489 static unsigned
1490 radv_plane_from_aspect(VkImageAspectFlags mask)
1491 {
1492 switch(mask) {
1493 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1494 return 1;
1495 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1496 return 2;
1497 default:
1498 return 0;
1499 }
1500 }
1501
1502 VkFormat
1503 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1504 {
1505 switch(mask) {
1506 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1507 return image->planes[0].format;
1508 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1509 return image->planes[1].format;
1510 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1511 return image->planes[2].format;
1512 case VK_IMAGE_ASPECT_STENCIL_BIT:
1513 return vk_format_stencil_only(image->vk_format);
1514 case VK_IMAGE_ASPECT_DEPTH_BIT:
1515 return vk_format_depth_only(image->vk_format);
1516 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1517 return vk_format_depth_only(image->vk_format);
1518 default:
1519 return image->vk_format;
1520 }
1521 }
1522
1523 void
1524 radv_image_view_init(struct radv_image_view *iview,
1525 struct radv_device *device,
1526 const VkImageViewCreateInfo* pCreateInfo)
1527 {
1528 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1529 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1530
1531 switch (image->type) {
1532 case VK_IMAGE_TYPE_1D:
1533 case VK_IMAGE_TYPE_2D:
1534 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1535 break;
1536 case VK_IMAGE_TYPE_3D:
1537 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1538 <= radv_minify(image->info.depth, range->baseMipLevel));
1539 break;
1540 default:
1541 unreachable("bad VkImageType");
1542 }
1543 iview->image = image;
1544 iview->bo = image->bo;
1545 iview->type = pCreateInfo->viewType;
1546 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1547 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1548 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1549 iview->vk_format = pCreateInfo->format;
1550
1551 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1552 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1553 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1554 iview->vk_format = vk_format_depth_only(iview->vk_format);
1555 }
1556
1557 if (device->physical_device->rad_info.chip_class >= GFX9) {
1558 iview->extent = (VkExtent3D) {
1559 .width = image->info.width,
1560 .height = image->info.height,
1561 .depth = image->info.depth,
1562 };
1563 } else {
1564 iview->extent = (VkExtent3D) {
1565 .width = radv_minify(image->info.width , range->baseMipLevel),
1566 .height = radv_minify(image->info.height, range->baseMipLevel),
1567 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1568 };
1569 }
1570
1571 if (iview->vk_format != image->planes[iview->plane_id].format) {
1572 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1573 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1574 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1575 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1576
1577 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1578 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1579
1580 /* Comment ported from amdvlk -
1581 * If we have the following image:
1582 * Uncompressed pixels Compressed block sizes (4x4)
1583 * mip0: 22 x 22 6 x 6
1584 * mip1: 11 x 11 3 x 3
1585 * mip2: 5 x 5 2 x 2
1586 * mip3: 2 x 2 1 x 1
1587 * mip4: 1 x 1 1 x 1
1588 *
1589 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1590 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1591 * divide-by-two integer math):
1592 * mip0: 6x6
1593 * mip1: 3x3
1594 * mip2: 1x1
1595 * mip3: 1x1
1596 *
1597 * This means that mip2 will be missing texels.
1598 *
1599 * Fix this by calculating the base mip's width and height, then convert that, and round it
1600 * back up to get the level 0 size.
1601 * Clamp the converted size between the original values, and next power of two, which
1602 * means we don't oversize the image.
1603 */
1604 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1605 vk_format_is_compressed(image->vk_format) &&
1606 !vk_format_is_compressed(iview->vk_format)) {
1607 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1608 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1609
1610 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1611 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1612
1613 lvl_width <<= range->baseMipLevel;
1614 lvl_height <<= range->baseMipLevel;
1615
1616 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1617 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1618 }
1619 }
1620
1621 iview->base_layer = range->baseArrayLayer;
1622 iview->layer_count = radv_get_layerCount(image, range);
1623 iview->base_mip = range->baseMipLevel;
1624 iview->level_count = radv_get_levelCount(image, range);
1625
1626 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1627 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1628 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1629 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1630 }
1631 }
1632
1633 bool radv_layout_has_htile(const struct radv_image *image,
1634 VkImageLayout layout,
1635 unsigned queue_mask)
1636 {
1637 if (radv_image_is_tc_compat_htile(image))
1638 return layout != VK_IMAGE_LAYOUT_GENERAL;
1639
1640 return radv_image_has_htile(image) &&
1641 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1642 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1643 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1644 }
1645
1646 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1647 VkImageLayout layout,
1648 unsigned queue_mask)
1649 {
1650 if (radv_image_is_tc_compat_htile(image))
1651 return layout != VK_IMAGE_LAYOUT_GENERAL;
1652
1653 return radv_image_has_htile(image) &&
1654 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1655 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1656 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1657 }
1658
1659 bool radv_layout_can_fast_clear(const struct radv_image *image,
1660 VkImageLayout layout,
1661 unsigned queue_mask)
1662 {
1663 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1664 }
1665
1666 bool radv_layout_dcc_compressed(const struct radv_image *image,
1667 VkImageLayout layout,
1668 unsigned queue_mask)
1669 {
1670 /* Don't compress compute transfer dst, as image stores are not supported. */
1671 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1672 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1673 return false;
1674
1675 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1676 }
1677
1678
1679 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1680 {
1681 if (!image->exclusive)
1682 return image->queue_family_mask;
1683 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1684 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1685 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1686 if (family == VK_QUEUE_FAMILY_IGNORED)
1687 return 1u << queue_family;
1688 return 1u << family;
1689 }
1690
1691 VkResult
1692 radv_CreateImage(VkDevice device,
1693 const VkImageCreateInfo *pCreateInfo,
1694 const VkAllocationCallbacks *pAllocator,
1695 VkImage *pImage)
1696 {
1697 #ifdef ANDROID
1698 const VkNativeBufferANDROID *gralloc_info =
1699 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1700
1701 if (gralloc_info)
1702 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1703 pAllocator, pImage);
1704 #endif
1705
1706 const struct wsi_image_create_info *wsi_info =
1707 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1708 bool scanout = wsi_info && wsi_info->scanout;
1709
1710 return radv_image_create(device,
1711 &(struct radv_image_create_info) {
1712 .vk_info = pCreateInfo,
1713 .scanout = scanout,
1714 },
1715 pAllocator,
1716 pImage);
1717 }
1718
1719 void
1720 radv_DestroyImage(VkDevice _device, VkImage _image,
1721 const VkAllocationCallbacks *pAllocator)
1722 {
1723 RADV_FROM_HANDLE(radv_device, device, _device);
1724 RADV_FROM_HANDLE(radv_image, image, _image);
1725
1726 if (!image)
1727 return;
1728
1729 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1730 device->ws->buffer_destroy(image->bo);
1731
1732 if (image->owned_memory != VK_NULL_HANDLE)
1733 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1734
1735 vk_free2(&device->alloc, pAllocator, image);
1736 }
1737
1738 void radv_GetImageSubresourceLayout(
1739 VkDevice _device,
1740 VkImage _image,
1741 const VkImageSubresource* pSubresource,
1742 VkSubresourceLayout* pLayout)
1743 {
1744 RADV_FROM_HANDLE(radv_image, image, _image);
1745 RADV_FROM_HANDLE(radv_device, device, _device);
1746 int level = pSubresource->mipLevel;
1747 int layer = pSubresource->arrayLayer;
1748
1749 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1750
1751 struct radv_image_plane *plane = &image->planes[plane_id];
1752 struct radeon_surf *surface = &plane->surface;
1753
1754 if (device->physical_device->rad_info.chip_class >= GFX9) {
1755 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1756 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1757 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1758 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1759 /* Adjust the number of bytes between each row because
1760 * the pitch is actually the number of components per
1761 * row.
1762 */
1763 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1764 } else {
1765 assert(util_is_power_of_two_nonzero(surface->bpe));
1766 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1767 }
1768
1769 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1770 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1771 pLayout->size = surface->u.gfx9.surf_slice_size;
1772 if (image->type == VK_IMAGE_TYPE_3D)
1773 pLayout->size *= u_minify(image->info.depth, level);
1774 } else {
1775 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1776 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1777 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1778 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1779 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1780 if (image->type == VK_IMAGE_TYPE_3D)
1781 pLayout->size *= u_minify(image->info.depth, level);
1782 }
1783 }
1784
1785
1786 VkResult
1787 radv_CreateImageView(VkDevice _device,
1788 const VkImageViewCreateInfo *pCreateInfo,
1789 const VkAllocationCallbacks *pAllocator,
1790 VkImageView *pView)
1791 {
1792 RADV_FROM_HANDLE(radv_device, device, _device);
1793 struct radv_image_view *view;
1794
1795 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1796 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1797 if (view == NULL)
1798 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1799
1800 radv_image_view_init(view, device, pCreateInfo);
1801
1802 *pView = radv_image_view_to_handle(view);
1803
1804 return VK_SUCCESS;
1805 }
1806
1807 void
1808 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1809 const VkAllocationCallbacks *pAllocator)
1810 {
1811 RADV_FROM_HANDLE(radv_device, device, _device);
1812 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1813
1814 if (!iview)
1815 return;
1816 vk_free2(&device->alloc, pAllocator, iview);
1817 }
1818
1819 void radv_buffer_view_init(struct radv_buffer_view *view,
1820 struct radv_device *device,
1821 const VkBufferViewCreateInfo* pCreateInfo)
1822 {
1823 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1824
1825 view->bo = buffer->bo;
1826 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1827 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1828 view->vk_format = pCreateInfo->format;
1829
1830 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1831 pCreateInfo->offset, view->range, view->state);
1832 }
1833
1834 VkResult
1835 radv_CreateBufferView(VkDevice _device,
1836 const VkBufferViewCreateInfo *pCreateInfo,
1837 const VkAllocationCallbacks *pAllocator,
1838 VkBufferView *pView)
1839 {
1840 RADV_FROM_HANDLE(radv_device, device, _device);
1841 struct radv_buffer_view *view;
1842
1843 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1844 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1845 if (!view)
1846 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1847
1848 radv_buffer_view_init(view, device, pCreateInfo);
1849
1850 *pView = radv_buffer_view_to_handle(view);
1851
1852 return VK_SUCCESS;
1853 }
1854
1855 void
1856 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1857 const VkAllocationCallbacks *pAllocator)
1858 {
1859 RADV_FROM_HANDLE(radv_device, device, _device);
1860 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1861
1862 if (!view)
1863 return;
1864
1865 vk_free2(&device->alloc, pAllocator, view);
1866 }