radv: add initial non-conformant radv vulkan driver
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
44 vec4, "a_pos");
45 pos_in->data.location = VERT_ATTRIB_GENERIC0;
46 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
47 vec4, "gl_Position");
48 pos_out->data.location = VARYING_SLOT_POS;
49 nir_copy_var(&b, pos_out, pos_in);
50
51 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
52 vec4, "a_tex_pos");
53 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
54 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
55 vec4, "v_tex_pos");
56 tex_pos_out->data.location = VARYING_SLOT_VAR0;
57 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
58 nir_copy_var(&b, tex_pos_out, tex_pos_in);
59
60 return b.shader;
61 }
62
63 static nir_shader *
64 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
65 {
66 char shader_name[64];
67 const struct glsl_type *vec4 = glsl_vec4_type();
68 nir_builder b;
69
70 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
71
72 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
73 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
74
75 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
76 vec4, "v_tex_pos");
77 tex_pos_in->data.location = VARYING_SLOT_VAR0;
78
79 /* Swizzle the array index which comes in as Z coordinate into the right
80 * position.
81 */
82 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
83 nir_ssa_def *const tex_pos =
84 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
85 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
86
87 const struct glsl_type *sampler_type =
88 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
89 glsl_get_base_type(vec4));
90 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
91 sampler_type, "s_tex");
92 sampler->data.descriptor_set = 0;
93 sampler->data.binding = 0;
94
95 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
96 tex->sampler_dim = tex_dim;
97 tex->op = nir_texop_tex;
98 tex->src[0].src_type = nir_tex_src_coord;
99 tex->src[0].src = nir_src_for_ssa(tex_pos);
100 tex->dest_type = nir_type_float; /* TODO */
101 tex->is_array = glsl_sampler_type_is_array(sampler_type);
102 tex->coord_components = tex_pos->num_components;
103 tex->texture = nir_deref_var_create(tex, sampler);
104 tex->sampler = nir_deref_var_create(tex, sampler);
105
106 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
107 nir_builder_instr_insert(&b, &tex->instr);
108
109 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
110 vec4, "f_color");
111 color_out->data.location = FRAG_RESULT_DATA0;
112 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
113
114 return b.shader;
115 }
116
117 static nir_shader *
118 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
119 {
120 char shader_name[64];
121 const struct glsl_type *vec4 = glsl_vec4_type();
122 nir_builder b;
123
124 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
125
126 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
127 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
128
129 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
130 vec4, "v_tex_pos");
131 tex_pos_in->data.location = VARYING_SLOT_VAR0;
132
133 /* Swizzle the array index which comes in as Z coordinate into the right
134 * position.
135 */
136 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
137 nir_ssa_def *const tex_pos =
138 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
139 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
140
141 const struct glsl_type *sampler_type =
142 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
143 glsl_get_base_type(vec4));
144 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
145 sampler_type, "s_tex");
146 sampler->data.descriptor_set = 0;
147 sampler->data.binding = 0;
148
149 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
150 tex->sampler_dim = tex_dim;
151 tex->op = nir_texop_tex;
152 tex->src[0].src_type = nir_tex_src_coord;
153 tex->src[0].src = nir_src_for_ssa(tex_pos);
154 tex->dest_type = nir_type_float; /* TODO */
155 tex->is_array = glsl_sampler_type_is_array(sampler_type);
156 tex->coord_components = tex_pos->num_components;
157 tex->texture = nir_deref_var_create(tex, sampler);
158 tex->sampler = nir_deref_var_create(tex, sampler);
159
160 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
161 nir_builder_instr_insert(&b, &tex->instr);
162
163 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
164 vec4, "f_color");
165 color_out->data.location = FRAG_RESULT_DEPTH;
166 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
167
168 return b.shader;
169 }
170
171 static nir_shader *
172 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
173 {
174 char shader_name[64];
175 const struct glsl_type *vec4 = glsl_vec4_type();
176 nir_builder b;
177
178 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
179
180 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
181 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
182
183 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
184 vec4, "v_tex_pos");
185 tex_pos_in->data.location = VARYING_SLOT_VAR0;
186
187 /* Swizzle the array index which comes in as Z coordinate into the right
188 * position.
189 */
190 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
191 nir_ssa_def *const tex_pos =
192 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
193 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
194
195 const struct glsl_type *sampler_type =
196 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
197 glsl_get_base_type(vec4));
198 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
199 sampler_type, "s_tex");
200 sampler->data.descriptor_set = 0;
201 sampler->data.binding = 0;
202
203 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
204 tex->sampler_dim = tex_dim;
205 tex->op = nir_texop_tex;
206 tex->src[0].src_type = nir_tex_src_coord;
207 tex->src[0].src = nir_src_for_ssa(tex_pos);
208 tex->dest_type = nir_type_float; /* TODO */
209 tex->is_array = glsl_sampler_type_is_array(sampler_type);
210 tex->coord_components = tex_pos->num_components;
211 tex->texture = nir_deref_var_create(tex, sampler);
212 tex->sampler = nir_deref_var_create(tex, sampler);
213
214 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
215 nir_builder_instr_insert(&b, &tex->instr);
216
217 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
218 vec4, "f_color");
219 color_out->data.location = FRAG_RESULT_STENCIL;
220 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
221
222 return b.shader;
223 }
224
225 static void
226 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
227 struct radv_image *src_image,
228 struct radv_image_view *src_iview,
229 VkOffset3D src_offset,
230 VkExtent3D src_extent,
231 struct radv_image *dest_image,
232 struct radv_image_view *dest_iview,
233 VkOffset3D dest_offset,
234 VkExtent3D dest_extent,
235 VkFilter blit_filter)
236 {
237 struct radv_device *device = cmd_buffer->device;
238 unsigned offset = 0;
239 struct blit_vb_data {
240 float pos[2];
241 float tex_coord[3];
242 } vb_data[3];
243
244 assert(src_image->samples == dest_image->samples);
245 unsigned vb_size = 3 * sizeof(*vb_data);
246 vb_data[0] = (struct blit_vb_data) {
247 .pos = {
248 dest_offset.x,
249 dest_offset.y,
250 },
251 .tex_coord = {
252 (float)(src_offset.x) / (float)src_iview->extent.width,
253 (float)(src_offset.y) / (float)src_iview->extent.height,
254 (float)src_offset.z / (float)src_iview->extent.depth,
255 },
256 };
257
258 vb_data[1] = (struct blit_vb_data) {
259 .pos = {
260 dest_offset.x,
261 dest_offset.y + dest_extent.height,
262 },
263 .tex_coord = {
264 (float)src_offset.x / (float)src_iview->extent.width,
265 (float)(src_offset.y + src_extent.height) /
266 (float)src_iview->extent.height,
267 (float)src_offset.z / (float)src_iview->extent.depth,
268 },
269 };
270
271 vb_data[2] = (struct blit_vb_data) {
272 .pos = {
273 dest_offset.x + dest_extent.width,
274 dest_offset.y,
275 },
276 .tex_coord = {
277 (float)(src_offset.x + src_extent.width) / (float)src_iview->extent.width,
278 (float)src_offset.y / (float)src_iview->extent.height,
279 (float)src_offset.z / (float)src_iview->extent.depth,
280 },
281 };
282 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
283
284 struct radv_buffer vertex_buffer = {
285 .device = device,
286 .size = vb_size,
287 .bo = cmd_buffer->upload.upload_bo,
288 .offset = offset,
289 };
290
291 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
292 (VkBuffer[]) {
293 radv_buffer_to_handle(&vertex_buffer)
294 },
295 (VkDeviceSize[]) {
296 0,
297 });
298
299 VkSampler sampler;
300 RADV_CALL(CreateSampler)(radv_device_to_handle(device),
301 &(VkSamplerCreateInfo) {
302 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
303 .magFilter = blit_filter,
304 .minFilter = blit_filter,
305 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
306 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
307 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
308 }, &cmd_buffer->pool->alloc, &sampler);
309
310 VkDescriptorSet set;
311 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
312 device->meta_state.blit.ds_layout,
313 &set);
314
315 radv_UpdateDescriptorSets(radv_device_to_handle(device),
316 1, /* writeCount */
317 (VkWriteDescriptorSet[]) {
318 {
319 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
320 .dstSet = set,
321 .dstBinding = 0,
322 .dstArrayElement = 0,
323 .descriptorCount = 1,
324 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
325 .pImageInfo = (VkDescriptorImageInfo[]) {
326 {
327 .sampler = sampler,
328 .imageView = radv_image_view_to_handle(src_iview),
329 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
330 },
331 }
332 }
333 }, 0, NULL);
334
335 VkFramebuffer fb;
336 radv_CreateFramebuffer(radv_device_to_handle(device),
337 &(VkFramebufferCreateInfo) {
338 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
339 .attachmentCount = 1,
340 .pAttachments = (VkImageView[]) {
341 radv_image_view_to_handle(dest_iview),
342 },
343 .width = dest_iview->extent.width,
344 .height = dest_iview->extent.height,
345 .layers = 1,
346 }, &cmd_buffer->pool->alloc, &fb);
347 VkPipeline pipeline;
348 switch (src_iview->aspect_mask) {
349 case VK_IMAGE_ASPECT_COLOR_BIT: {
350 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
351
352 RADV_CALL(CmdBeginRenderPass)(radv_cmd_buffer_to_handle(cmd_buffer),
353 &(VkRenderPassBeginInfo) {
354 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
355 .renderPass = device->meta_state.blit.render_pass[fs_key],
356 .framebuffer = fb,
357 .renderArea = {
358 .offset = { dest_offset.x, dest_offset.y },
359 .extent = { dest_extent.width, dest_extent.height },
360 },
361 .clearValueCount = 0,
362 .pClearValues = NULL,
363 }, VK_SUBPASS_CONTENTS_INLINE);
364 switch (src_image->type) {
365 case VK_IMAGE_TYPE_1D:
366 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
367 break;
368 case VK_IMAGE_TYPE_2D:
369 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
370 break;
371 case VK_IMAGE_TYPE_3D:
372 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
373 break;
374 default:
375 unreachable(!"bad VkImageType");
376 }
377 break;
378 }
379 case VK_IMAGE_ASPECT_DEPTH_BIT:
380 RADV_CALL(CmdBeginRenderPass)(radv_cmd_buffer_to_handle(cmd_buffer),
381 &(VkRenderPassBeginInfo) {
382 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
383 .renderPass = device->meta_state.blit.depth_only_rp,
384 .framebuffer = fb,
385 .renderArea = {
386 .offset = { dest_offset.x, dest_offset.y },
387 .extent = { dest_extent.width, dest_extent.height },
388 },
389 .clearValueCount = 0,
390 .pClearValues = NULL,
391 }, VK_SUBPASS_CONTENTS_INLINE);
392 switch (src_image->type) {
393 case VK_IMAGE_TYPE_1D:
394 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
395 break;
396 case VK_IMAGE_TYPE_2D:
397 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
398 break;
399 case VK_IMAGE_TYPE_3D:
400 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
401 break;
402 default:
403 unreachable(!"bad VkImageType");
404 }
405 break;
406 case VK_IMAGE_ASPECT_STENCIL_BIT:
407 RADV_CALL(CmdBeginRenderPass)(radv_cmd_buffer_to_handle(cmd_buffer),
408 &(VkRenderPassBeginInfo) {
409 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
410 .renderPass = device->meta_state.blit.stencil_only_rp,
411 .framebuffer = fb,
412 .renderArea = {
413 .offset = { dest_offset.x, dest_offset.y },
414 .extent = { dest_extent.width, dest_extent.height },
415 },
416 .clearValueCount = 0,
417 .pClearValues = NULL,
418 }, VK_SUBPASS_CONTENTS_INLINE);
419 switch (src_image->type) {
420 case VK_IMAGE_TYPE_1D:
421 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
422 break;
423 case VK_IMAGE_TYPE_2D:
424 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
425 break;
426 case VK_IMAGE_TYPE_3D:
427 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
428 break;
429 default:
430 unreachable(!"bad VkImageType");
431 }
432 break;
433 default:
434 unreachable(!"bad VkImageType");
435 }
436
437 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
438 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
439 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
440 }
441
442 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
443 VK_PIPELINE_BIND_POINT_GRAPHICS,
444 device->meta_state.blit.pipeline_layout, 0, 1,
445 &set, 0, NULL);
446
447 RADV_CALL(CmdDraw)(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
448
449 RADV_CALL(CmdEndRenderPass)(radv_cmd_buffer_to_handle(cmd_buffer));
450
451 /* At the point where we emit the draw call, all data from the
452 * descriptor sets, etc. has been used. We are free to delete it.
453 */
454 /* TODO: above comment is not valid for at least descriptor sets/pools,
455 * as we may not free them till after execution finishes. Check others. */
456
457 radv_temp_descriptor_set_destroy(cmd_buffer->device, set);
458 radv_DestroySampler(radv_device_to_handle(device), sampler,
459 &cmd_buffer->pool->alloc);
460 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
461 &cmd_buffer->pool->alloc);
462 }
463
464 void radv_CmdBlitImage(
465 VkCommandBuffer commandBuffer,
466 VkImage srcImage,
467 VkImageLayout srcImageLayout,
468 VkImage destImage,
469 VkImageLayout destImageLayout,
470 uint32_t regionCount,
471 const VkImageBlit* pRegions,
472 VkFilter filter)
473
474 {
475 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
476 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
477 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
478 struct radv_meta_saved_state saved_state;
479
480 /* From the Vulkan 1.0 spec:
481 *
482 * vkCmdBlitImage must not be used for multisampled source or
483 * destination images. Use vkCmdResolveImage for this purpose.
484 */
485 assert(src_image->samples == 1);
486 assert(dest_image->samples == 1);
487
488 radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
489
490 for (unsigned r = 0; r < regionCount; r++) {
491 struct radv_image_view src_iview;
492 radv_image_view_init(&src_iview, cmd_buffer->device,
493 &(VkImageViewCreateInfo) {
494 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
495 .image = srcImage,
496 .viewType = radv_meta_get_view_type(src_image),
497 .format = src_image->vk_format,
498 .subresourceRange = {
499 .aspectMask = pRegions[r].srcSubresource.aspectMask,
500 .baseMipLevel = pRegions[r].srcSubresource.mipLevel,
501 .levelCount = 1,
502 .baseArrayLayer = pRegions[r].srcSubresource.baseArrayLayer,
503 .layerCount = 1
504 },
505 },
506 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
507
508 if (pRegions[r].dstOffsets[1].x < pRegions[r].dstOffsets[0].x ||
509 pRegions[r].dstOffsets[1].y < pRegions[r].dstOffsets[0].y ||
510 pRegions[r].srcOffsets[1].x < pRegions[r].srcOffsets[0].x ||
511 pRegions[r].srcOffsets[1].y < pRegions[r].srcOffsets[0].y)
512 radv_finishme("FINISHME: Allow flipping in blits");
513
514 const VkExtent3D dest_extent = {
515 .width = pRegions[r].dstOffsets[1].x - pRegions[r].dstOffsets[0].x,
516 .height = pRegions[r].dstOffsets[1].y - pRegions[r].dstOffsets[0].y,
517 .depth = 1,
518 };
519
520 const VkExtent3D src_extent = {
521 .width = pRegions[r].srcOffsets[1].x - pRegions[r].srcOffsets[0].x,
522 .height = pRegions[r].srcOffsets[1].y - pRegions[r].srcOffsets[0].y,
523 .depth = pRegions[r].srcOffsets[1].z - pRegions[r].srcOffsets[0].z,
524 };
525
526
527 if (pRegions[r].srcSubresource.layerCount > 1)
528 radv_finishme("FINISHME: copy multiple array layers");
529
530 struct radv_image_view dest_iview;
531 unsigned usage;
532 if (pRegions[r].dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT)
533 usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
534 else
535 usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
536
537 for (unsigned i = pRegions[r].dstOffsets[0].z; i < pRegions[r].dstOffsets[1].z; i++) {
538
539 const VkOffset3D dest_offset = {
540 .x = pRegions[r].dstOffsets[0].x,
541 .y = pRegions[r].dstOffsets[0].y,
542 .z = i,
543 };
544 VkOffset3D src_offset = {
545 .x = pRegions[r].srcOffsets[0].x,
546 .y = pRegions[r].srcOffsets[0].y,
547 .z = i,
548 };
549 const uint32_t dest_array_slice =
550 radv_meta_get_iview_layer(dest_image, &pRegions[r].dstSubresource,
551 &dest_offset);
552
553 radv_image_view_init(&dest_iview, cmd_buffer->device,
554 &(VkImageViewCreateInfo) {
555 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
556 .image = destImage,
557 .viewType = radv_meta_get_view_type(dest_image),
558 .format = dest_image->vk_format,
559 .subresourceRange = {
560 .aspectMask = pRegions[r].dstSubresource.aspectMask,
561 .baseMipLevel = pRegions[r].dstSubresource.mipLevel,
562 .levelCount = 1,
563 .baseArrayLayer = dest_array_slice,
564 .layerCount = 1
565 },
566 },
567 cmd_buffer, usage);
568 meta_emit_blit(cmd_buffer,
569 src_image, &src_iview,
570 src_offset, src_extent,
571 dest_image, &dest_iview,
572 dest_offset, dest_extent,
573 filter);
574 }
575 }
576
577 radv_meta_restore(&saved_state, cmd_buffer);
578 }
579
580 void
581 radv_device_finish_meta_blit_state(struct radv_device *device)
582 {
583 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
584 if (device->meta_state.blit.render_pass[i])
585 radv_DestroyRenderPass(radv_device_to_handle(device),
586 device->meta_state.blit.render_pass[i],
587 &device->meta_state.alloc);
588 if (device->meta_state.blit.pipeline_1d_src[i])
589 radv_DestroyPipeline(radv_device_to_handle(device),
590 device->meta_state.blit.pipeline_1d_src[i],
591 &device->meta_state.alloc);
592 if (device->meta_state.blit.pipeline_2d_src[i])
593 radv_DestroyPipeline(radv_device_to_handle(device),
594 device->meta_state.blit.pipeline_2d_src[i],
595 &device->meta_state.alloc);
596 if (device->meta_state.blit.pipeline_3d_src[i])
597 radv_DestroyPipeline(radv_device_to_handle(device),
598 device->meta_state.blit.pipeline_3d_src[i],
599 &device->meta_state.alloc);
600 }
601
602 if (device->meta_state.blit.depth_only_rp)
603 radv_DestroyRenderPass(radv_device_to_handle(device),
604 device->meta_state.blit.depth_only_rp,
605 &device->meta_state.alloc);
606 if (device->meta_state.blit.depth_only_1d_pipeline)
607 radv_DestroyPipeline(radv_device_to_handle(device),
608 device->meta_state.blit.depth_only_1d_pipeline,
609 &device->meta_state.alloc);
610 if (device->meta_state.blit.depth_only_2d_pipeline)
611 radv_DestroyPipeline(radv_device_to_handle(device),
612 device->meta_state.blit.depth_only_2d_pipeline,
613 &device->meta_state.alloc);
614 if (device->meta_state.blit.depth_only_3d_pipeline)
615 radv_DestroyPipeline(radv_device_to_handle(device),
616 device->meta_state.blit.depth_only_3d_pipeline,
617 &device->meta_state.alloc);
618 if (device->meta_state.blit.stencil_only_rp)
619 radv_DestroyRenderPass(radv_device_to_handle(device),
620 device->meta_state.blit.stencil_only_rp,
621 &device->meta_state.alloc);
622 if (device->meta_state.blit.stencil_only_1d_pipeline)
623 radv_DestroyPipeline(radv_device_to_handle(device),
624 device->meta_state.blit.stencil_only_1d_pipeline,
625 &device->meta_state.alloc);
626 if (device->meta_state.blit.stencil_only_2d_pipeline)
627 radv_DestroyPipeline(radv_device_to_handle(device),
628 device->meta_state.blit.stencil_only_2d_pipeline,
629 &device->meta_state.alloc);
630 if (device->meta_state.blit.stencil_only_3d_pipeline)
631 radv_DestroyPipeline(radv_device_to_handle(device),
632 device->meta_state.blit.stencil_only_3d_pipeline,
633 &device->meta_state.alloc);
634 if (device->meta_state.blit.pipeline_layout)
635 radv_DestroyPipelineLayout(radv_device_to_handle(device),
636 device->meta_state.blit.pipeline_layout,
637 &device->meta_state.alloc);
638 if (device->meta_state.blit.ds_layout)
639 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
640 device->meta_state.blit.ds_layout,
641 &device->meta_state.alloc);
642 }
643
644 static VkFormat pipeline_formats[] = {
645 VK_FORMAT_R8G8B8A8_UNORM,
646 VK_FORMAT_R8G8B8A8_UINT,
647 VK_FORMAT_R8G8B8A8_SINT,
648 VK_FORMAT_R16G16B16A16_UNORM,
649 VK_FORMAT_R16G16B16A16_SNORM,
650 VK_FORMAT_R16G16B16A16_UINT,
651 VK_FORMAT_R16G16B16A16_SINT,
652 VK_FORMAT_R32_SFLOAT,
653 VK_FORMAT_R32G32_SFLOAT,
654 VK_FORMAT_R32G32B32A32_SFLOAT
655 };
656
657 static VkResult
658 radv_device_init_meta_blit_color(struct radv_device *device,
659 struct radv_shader_module *vs)
660 {
661 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
662 VkResult result;
663
664 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
665 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
666 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
667
668 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
669 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
670 result = radv_CreateRenderPass(radv_device_to_handle(device),
671 &(VkRenderPassCreateInfo) {
672 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
673 .attachmentCount = 1,
674 .pAttachments = &(VkAttachmentDescription) {
675 .format = pipeline_formats[i],
676 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
677 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
678 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
679 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
680 },
681 .subpassCount = 1,
682 .pSubpasses = &(VkSubpassDescription) {
683 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
684 .inputAttachmentCount = 0,
685 .colorAttachmentCount = 1,
686 .pColorAttachments = &(VkAttachmentReference) {
687 .attachment = 0,
688 .layout = VK_IMAGE_LAYOUT_GENERAL,
689 },
690 .pResolveAttachments = NULL,
691 .pDepthStencilAttachment = &(VkAttachmentReference) {
692 .attachment = VK_ATTACHMENT_UNUSED,
693 .layout = VK_IMAGE_LAYOUT_GENERAL,
694 },
695 .preserveAttachmentCount = 1,
696 .pPreserveAttachments = (uint32_t[]) { 0 },
697 },
698 .dependencyCount = 0,
699 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
700 if (result != VK_SUCCESS)
701 goto fail;
702
703 VkPipelineVertexInputStateCreateInfo vi_create_info = {
704 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
705 .vertexBindingDescriptionCount = 1,
706 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
707 {
708 .binding = 0,
709 .stride = 5 * sizeof(float),
710 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
711 },
712 },
713 .vertexAttributeDescriptionCount = 2,
714 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
715 {
716 /* Position */
717 .location = 0,
718 .binding = 0,
719 .format = VK_FORMAT_R32G32_SFLOAT,
720 .offset = 0
721 },
722 {
723 /* Texture Coordinate */
724 .location = 1,
725 .binding = 0,
726 .format = VK_FORMAT_R32G32B32_SFLOAT,
727 .offset = 8
728 }
729 }
730 };
731
732 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
733 {
734 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
735 .stage = VK_SHADER_STAGE_VERTEX_BIT,
736 .module = radv_shader_module_to_handle(vs),
737 .pName = "main",
738 .pSpecializationInfo = NULL
739 }, {
740 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
741 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
742 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
743 .pName = "main",
744 .pSpecializationInfo = NULL
745 },
746 };
747
748 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
749 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
750 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
751 .pStages = pipeline_shader_stages,
752 .pVertexInputState = &vi_create_info,
753 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
754 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
755 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
756 .primitiveRestartEnable = false,
757 },
758 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
759 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
760 .viewportCount = 0,
761 .scissorCount = 0,
762 },
763 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
764 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
765 .rasterizerDiscardEnable = false,
766 .polygonMode = VK_POLYGON_MODE_FILL,
767 .cullMode = VK_CULL_MODE_NONE,
768 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
769 },
770 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
771 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
772 .rasterizationSamples = 1,
773 .sampleShadingEnable = false,
774 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
775 },
776 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
777 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
778 .attachmentCount = 1,
779 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
780 { .colorWriteMask =
781 VK_COLOR_COMPONENT_A_BIT |
782 VK_COLOR_COMPONENT_R_BIT |
783 VK_COLOR_COMPONENT_G_BIT |
784 VK_COLOR_COMPONENT_B_BIT },
785 }
786 },
787 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
788 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
789 .dynamicStateCount = 2,
790 .pDynamicStates = (VkDynamicState[]) {
791 VK_DYNAMIC_STATE_LINE_WIDTH,
792 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
793 },
794 },
795 .flags = 0,
796 .layout = device->meta_state.blit.pipeline_layout,
797 .renderPass = device->meta_state.blit.render_pass[key],
798 .subpass = 0,
799 };
800
801 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
802 .use_rectlist = true
803 };
804
805 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
806 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
807 radv_pipeline_cache_to_handle(&device->meta_state.cache),
808 &vk_pipeline_info, &radv_pipeline_info,
809 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
810 if (result != VK_SUCCESS)
811 goto fail;
812
813 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
814 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
815 radv_pipeline_cache_to_handle(&device->meta_state.cache),
816 &vk_pipeline_info, &radv_pipeline_info,
817 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
818 if (result != VK_SUCCESS)
819 goto fail;
820
821 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
822 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
823 radv_pipeline_cache_to_handle(&device->meta_state.cache),
824 &vk_pipeline_info, &radv_pipeline_info,
825 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
826 if (result != VK_SUCCESS)
827 goto fail;
828
829 }
830
831 result = VK_SUCCESS;
832 fail:
833 ralloc_free(fs_1d.nir);
834 ralloc_free(fs_2d.nir);
835 ralloc_free(fs_3d.nir);
836 return result;
837 }
838
839 static VkResult
840 radv_device_init_meta_blit_depth(struct radv_device *device,
841 struct radv_shader_module *vs)
842 {
843 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
844 VkResult result;
845
846 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
847 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
848 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
849
850 result = radv_CreateRenderPass(radv_device_to_handle(device),
851 &(VkRenderPassCreateInfo) {
852 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
853 .attachmentCount = 1,
854 .pAttachments = &(VkAttachmentDescription) {
855 .format = 0,
856 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
857 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
858 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
859 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
860 },
861 .subpassCount = 1,
862 .pSubpasses = &(VkSubpassDescription) {
863 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
864 .inputAttachmentCount = 0,
865 .colorAttachmentCount = 0,
866 .pColorAttachments = NULL,
867 .pResolveAttachments = NULL,
868 .pDepthStencilAttachment = &(VkAttachmentReference) {
869 .attachment = 0,
870 .layout = VK_IMAGE_LAYOUT_GENERAL,
871 },
872 .preserveAttachmentCount = 1,
873 .pPreserveAttachments = (uint32_t[]) { 0 },
874 },
875 .dependencyCount = 0,
876 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
877 if (result != VK_SUCCESS)
878 goto fail;
879
880 VkPipelineVertexInputStateCreateInfo vi_create_info = {
881 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
882 .vertexBindingDescriptionCount = 1,
883 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
884 {
885 .binding = 0,
886 .stride = 5 * sizeof(float),
887 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
888 },
889 },
890 .vertexAttributeDescriptionCount = 2,
891 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
892 {
893 /* Position */
894 .location = 0,
895 .binding = 0,
896 .format = VK_FORMAT_R32G32_SFLOAT,
897 .offset = 0
898 },
899 {
900 /* Texture Coordinate */
901 .location = 1,
902 .binding = 0,
903 .format = VK_FORMAT_R32G32B32_SFLOAT,
904 .offset = 8
905 }
906 }
907 };
908
909 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
910 {
911 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
912 .stage = VK_SHADER_STAGE_VERTEX_BIT,
913 .module = radv_shader_module_to_handle(vs),
914 .pName = "main",
915 .pSpecializationInfo = NULL
916 }, {
917 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
918 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
919 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
920 .pName = "main",
921 .pSpecializationInfo = NULL
922 },
923 };
924
925 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
926 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
927 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
928 .pStages = pipeline_shader_stages,
929 .pVertexInputState = &vi_create_info,
930 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
931 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
932 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
933 .primitiveRestartEnable = false,
934 },
935 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
936 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
937 .viewportCount = 0,
938 .scissorCount = 0,
939 },
940 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
941 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
942 .rasterizerDiscardEnable = false,
943 .polygonMode = VK_POLYGON_MODE_FILL,
944 .cullMode = VK_CULL_MODE_NONE,
945 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
946 },
947 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
948 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
949 .rasterizationSamples = 1,
950 .sampleShadingEnable = false,
951 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
952 },
953 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
954 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
955 .attachmentCount = 0,
956 .pAttachments = NULL,
957 },
958 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
959 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
960 .depthTestEnable = true,
961 .depthWriteEnable = true,
962 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
963 },
964 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
965 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
966 .dynamicStateCount = 7,
967 .pDynamicStates = (VkDynamicState[]) {
968 VK_DYNAMIC_STATE_LINE_WIDTH,
969 VK_DYNAMIC_STATE_DEPTH_BIAS,
970 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
971 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
972 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
973 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
974 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
975 },
976 },
977 .flags = 0,
978 .layout = device->meta_state.blit.pipeline_layout,
979 .renderPass = device->meta_state.blit.depth_only_rp,
980 .subpass = 0,
981 };
982
983 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
984 .use_rectlist = true
985 };
986
987 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
988 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
989 radv_pipeline_cache_to_handle(&device->meta_state.cache),
990 &vk_pipeline_info, &radv_pipeline_info,
991 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
992 if (result != VK_SUCCESS)
993 goto fail;
994
995 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
996 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
997 radv_pipeline_cache_to_handle(&device->meta_state.cache),
998 &vk_pipeline_info, &radv_pipeline_info,
999 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1000 if (result != VK_SUCCESS)
1001 goto fail;
1002
1003 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1004 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1005 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1006 &vk_pipeline_info, &radv_pipeline_info,
1007 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1008 if (result != VK_SUCCESS)
1009 goto fail;
1010
1011 fail:
1012 ralloc_free(fs_1d.nir);
1013 ralloc_free(fs_2d.nir);
1014 ralloc_free(fs_3d.nir);
1015 return result;
1016 }
1017
1018 static VkResult
1019 radv_device_init_meta_blit_stencil(struct radv_device *device,
1020 struct radv_shader_module *vs)
1021 {
1022 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1023 VkResult result;
1024
1025 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1026 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1027 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1028
1029 result = radv_CreateRenderPass(radv_device_to_handle(device),
1030 &(VkRenderPassCreateInfo) {
1031 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1032 .attachmentCount = 1,
1033 .pAttachments = &(VkAttachmentDescription) {
1034 .format = 0,
1035 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1036 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1037 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1038 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1039 },
1040 .subpassCount = 1,
1041 .pSubpasses = &(VkSubpassDescription) {
1042 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1043 .inputAttachmentCount = 0,
1044 .colorAttachmentCount = 0,
1045 .pColorAttachments = NULL,
1046 .pResolveAttachments = NULL,
1047 .pDepthStencilAttachment = &(VkAttachmentReference) {
1048 .attachment = 0,
1049 .layout = VK_IMAGE_LAYOUT_GENERAL,
1050 },
1051 .preserveAttachmentCount = 1,
1052 .pPreserveAttachments = (uint32_t[]) { 0 },
1053 },
1054 .dependencyCount = 0,
1055 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1056 if (result != VK_SUCCESS)
1057 goto fail;
1058
1059 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1060 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1061 .vertexBindingDescriptionCount = 1,
1062 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
1063 {
1064 .binding = 0,
1065 .stride = 5 * sizeof(float),
1066 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
1067 },
1068 },
1069 .vertexAttributeDescriptionCount = 2,
1070 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
1071 {
1072 /* Position */
1073 .location = 0,
1074 .binding = 0,
1075 .format = VK_FORMAT_R32G32_SFLOAT,
1076 .offset = 0
1077 },
1078 {
1079 /* Texture Coordinate */
1080 .location = 1,
1081 .binding = 0,
1082 .format = VK_FORMAT_R32G32B32_SFLOAT,
1083 .offset = 8
1084 }
1085 }
1086 };
1087
1088 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1089 {
1090 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1091 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1092 .module = radv_shader_module_to_handle(vs),
1093 .pName = "main",
1094 .pSpecializationInfo = NULL
1095 }, {
1096 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1097 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1098 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1099 .pName = "main",
1100 .pSpecializationInfo = NULL
1101 },
1102 };
1103
1104 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1105 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1106 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1107 .pStages = pipeline_shader_stages,
1108 .pVertexInputState = &vi_create_info,
1109 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1110 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1111 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1112 .primitiveRestartEnable = false,
1113 },
1114 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1115 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1116 .viewportCount = 0,
1117 .scissorCount = 0,
1118 },
1119 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1120 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1121 .rasterizerDiscardEnable = false,
1122 .polygonMode = VK_POLYGON_MODE_FILL,
1123 .cullMode = VK_CULL_MODE_NONE,
1124 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1125 },
1126 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1127 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1128 .rasterizationSamples = 1,
1129 .sampleShadingEnable = false,
1130 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1131 },
1132 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1133 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1134 .attachmentCount = 0,
1135 .pAttachments = NULL,
1136 },
1137 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1138 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1139 .depthTestEnable = false,
1140 .depthWriteEnable = false,
1141 .stencilTestEnable = true,
1142 .front = {
1143 .failOp = VK_STENCIL_OP_REPLACE,
1144 .passOp = VK_STENCIL_OP_REPLACE,
1145 .depthFailOp = VK_STENCIL_OP_REPLACE,
1146 .compareOp = VK_COMPARE_OP_ALWAYS,
1147 .compareMask = 0xff,
1148 .writeMask = 0xff,
1149 .reference = 0
1150 },
1151 .back = {
1152 .failOp = VK_STENCIL_OP_REPLACE,
1153 .passOp = VK_STENCIL_OP_REPLACE,
1154 .depthFailOp = VK_STENCIL_OP_REPLACE,
1155 .compareOp = VK_COMPARE_OP_ALWAYS,
1156 .compareMask = 0xff,
1157 .writeMask = 0xff,
1158 .reference = 0
1159 },
1160 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1161 },
1162
1163 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1164 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1165 .dynamicStateCount = 4,
1166 .pDynamicStates = (VkDynamicState[]) {
1167 VK_DYNAMIC_STATE_LINE_WIDTH,
1168 VK_DYNAMIC_STATE_DEPTH_BIAS,
1169 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1170 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1171 },
1172 },
1173 .flags = 0,
1174 .layout = device->meta_state.blit.pipeline_layout,
1175 .renderPass = device->meta_state.blit.stencil_only_rp,
1176 .subpass = 0,
1177 };
1178
1179 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1180 .use_rectlist = true
1181 };
1182
1183 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1184 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1185 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1186 &vk_pipeline_info, &radv_pipeline_info,
1187 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1188 if (result != VK_SUCCESS)
1189 goto fail;
1190
1191 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1192 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1193 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1194 &vk_pipeline_info, &radv_pipeline_info,
1195 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1196 if (result != VK_SUCCESS)
1197 goto fail;
1198
1199 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1200 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1201 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1202 &vk_pipeline_info, &radv_pipeline_info,
1203 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1204 if (result != VK_SUCCESS)
1205 goto fail;
1206
1207 fail:
1208 ralloc_free(fs_1d.nir);
1209 ralloc_free(fs_2d.nir);
1210 ralloc_free(fs_3d.nir);
1211 return result;
1212 }
1213
1214 VkResult
1215 radv_device_init_meta_blit_state(struct radv_device *device)
1216 {
1217 VkResult result;
1218 struct radv_shader_module vs = {0};
1219 zero(device->meta_state.blit);
1220
1221 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1222 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1223 .bindingCount = 1,
1224 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1225 {
1226 .binding = 0,
1227 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1228 .descriptorCount = 1,
1229 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1230 .pImmutableSamplers = NULL
1231 },
1232 }
1233 };
1234 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1235 &ds_layout_info,
1236 &device->meta_state.alloc,
1237 &device->meta_state.blit.ds_layout);
1238 if (result != VK_SUCCESS)
1239 goto fail;
1240
1241 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1242 &(VkPipelineLayoutCreateInfo) {
1243 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1244 .setLayoutCount = 1,
1245 .pSetLayouts = &device->meta_state.blit.ds_layout,
1246 },
1247 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1248 if (result != VK_SUCCESS)
1249 goto fail;
1250
1251 vs.nir = build_nir_vertex_shader();
1252
1253 result = radv_device_init_meta_blit_color(device, &vs);
1254 if (result != VK_SUCCESS)
1255 goto fail;
1256
1257 result = radv_device_init_meta_blit_depth(device, &vs);
1258 if (result != VK_SUCCESS)
1259 goto fail;
1260
1261 result = radv_device_init_meta_blit_stencil(device, &vs);
1262 if (result != VK_SUCCESS)
1263 goto fail;
1264 return VK_SUCCESS;
1265
1266 fail:
1267 ralloc_free(vs.nir);
1268 radv_device_finish_meta_blit_state(device);
1269 return result;
1270 }