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cac0a4dd55f32dfc04c6d3c8f8dddfdb6d8ca9c3
[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_src_type {
32 BLIT2D_SRC_TYPE_IMAGE,
33 BLIT2D_SRC_TYPE_IMAGE_3D,
34 BLIT2D_SRC_TYPE_BUFFER,
35 BLIT2D_NUM_SRC_TYPES,
36 };
37
38 static void
39 create_iview(struct radv_cmd_buffer *cmd_buffer,
40 struct radv_meta_blit2d_surf *surf,
41 struct radv_image_view *iview, VkFormat depth_format,
42 VkImageAspectFlagBits aspects)
43 {
44 VkFormat format;
45 VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D :
46 radv_meta_get_view_type(surf->image);
47
48 if (depth_format)
49 format = depth_format;
50 else
51 format = surf->format;
52
53 radv_image_view_init(iview, cmd_buffer->device,
54 &(VkImageViewCreateInfo) {
55 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
56 .image = radv_image_to_handle(surf->image),
57 .viewType = view_type,
58 .format = format,
59 .subresourceRange = {
60 .aspectMask = aspects,
61 .baseMipLevel = surf->level,
62 .levelCount = 1,
63 .baseArrayLayer = surf->layer,
64 .layerCount = 1
65 },
66 });
67 }
68
69 static void
70 create_bview(struct radv_cmd_buffer *cmd_buffer,
71 struct radv_meta_blit2d_buffer *src,
72 struct radv_buffer_view *bview, VkFormat depth_format)
73 {
74 VkFormat format;
75
76 if (depth_format)
77 format = depth_format;
78 else
79 format = src->format;
80 radv_buffer_view_init(bview, cmd_buffer->device,
81 &(VkBufferViewCreateInfo) {
82 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
83 .flags = 0,
84 .buffer = radv_buffer_to_handle(src->buffer),
85 .format = format,
86 .offset = src->offset,
87 .range = VK_WHOLE_SIZE,
88 });
89
90 }
91
92 struct blit2d_src_temps {
93 struct radv_image_view iview;
94 struct radv_buffer_view bview;
95 };
96
97 static void
98 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
99 struct radv_meta_blit2d_surf *src_img,
100 struct radv_meta_blit2d_buffer *src_buf,
101 struct blit2d_src_temps *tmp,
102 enum blit2d_src_type src_type, VkFormat depth_format,
103 VkImageAspectFlagBits aspects,
104 uint32_t log2_samples)
105 {
106 struct radv_device *device = cmd_buffer->device;
107
108 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
109 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
110
111 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
112 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
113 0, /* set */
114 1, /* descriptorWriteCount */
115 (VkWriteDescriptorSet[]) {
116 {
117 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
118 .dstBinding = 0,
119 .dstArrayElement = 0,
120 .descriptorCount = 1,
121 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
122 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
123 }
124 });
125
126 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
127 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
128 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
129 &src_buf->pitch);
130 } else {
131 create_iview(cmd_buffer, src_img, &tmp->iview, depth_format, aspects);
132
133 if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)
134 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
135 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
136 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
137 &src_img->layer);
138
139 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
140 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
141 0, /* set */
142 1, /* descriptorWriteCount */
143 (VkWriteDescriptorSet[]) {
144 {
145 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
146 .dstBinding = 0,
147 .dstArrayElement = 0,
148 .descriptorCount = 1,
149 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
150 .pImageInfo = (VkDescriptorImageInfo[]) {
151 {
152 .sampler = VK_NULL_HANDLE,
153 .imageView = radv_image_view_to_handle(&tmp->iview),
154 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
155 },
156 }
157 }
158 });
159 }
160 }
161
162 struct blit2d_dst_temps {
163 VkImage image;
164 struct radv_image_view iview;
165 VkFramebuffer fb;
166 };
167
168 static void
169 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
170 struct radv_meta_blit2d_surf *dst,
171 uint32_t width,
172 uint32_t height,
173 VkFormat depth_format,
174 struct blit2d_dst_temps *tmp,
175 VkImageAspectFlagBits aspects)
176 {
177 create_iview(cmd_buffer, dst, &tmp->iview, depth_format, aspects);
178
179 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
180 &(VkFramebufferCreateInfo) {
181 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
182 .attachmentCount = 1,
183 .pAttachments = (VkImageView[]) {
184 radv_image_view_to_handle(&tmp->iview),
185 },
186 .width = width,
187 .height = height,
188 .layers = 1
189 }, &cmd_buffer->pool->alloc, &tmp->fb);
190 }
191
192 static void
193 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
194 enum blit2d_src_type src_type, unsigned fs_key,
195 uint32_t log2_samples)
196 {
197 VkPipeline pipeline =
198 cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
199
200 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
201 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
202 }
203
204 static void
205 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
206 enum blit2d_src_type src_type,
207 uint32_t log2_samples)
208 {
209 VkPipeline pipeline =
210 cmd_buffer->device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type];
211
212 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
213 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
214 }
215
216 static void
217 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
218 enum blit2d_src_type src_type,
219 uint32_t log2_samples)
220 {
221 VkPipeline pipeline =
222 cmd_buffer->device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type];
223
224 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
225 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
226 }
227
228 static void
229 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
230 struct radv_meta_blit2d_surf *src_img,
231 struct radv_meta_blit2d_buffer *src_buf,
232 struct radv_meta_blit2d_surf *dst,
233 unsigned num_rects,
234 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type,
235 uint32_t log2_samples)
236 {
237 struct radv_device *device = cmd_buffer->device;
238
239 for (unsigned r = 0; r < num_rects; ++r) {
240 unsigned i;
241 for_each_bit(i, dst->aspect_mask) {
242 unsigned aspect_mask = 1u << i;
243 VkFormat depth_format = 0;
244 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
245 depth_format = vk_format_stencil_only(dst->image->vk_format);
246 else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
247 depth_format = vk_format_depth_only(dst->image->vk_format);
248 struct blit2d_src_temps src_temps;
249 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, aspect_mask, log2_samples);
250
251 struct blit2d_dst_temps dst_temps;
252 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
253 rects[r].dst_y + rects[r].height, depth_format, &dst_temps, aspect_mask);
254
255 float vertex_push_constants[4] = {
256 rects[r].src_x,
257 rects[r].src_y,
258 rects[r].src_x + rects[r].width,
259 rects[r].src_y + rects[r].height,
260 };
261
262 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
263 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
264 VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
265 vertex_push_constants);
266
267 if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
268 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
269 unsigned dst_layout = radv_meta_dst_layout_from_layout(dst->current_layout);
270
271 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
272 &(VkRenderPassBeginInfo) {
273 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
274 .renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout],
275 .framebuffer = dst_temps.fb,
276 .renderArea = {
277 .offset = { rects[r].dst_x, rects[r].dst_y, },
278 .extent = { rects[r].width, rects[r].height },
279 },
280 .clearValueCount = 0,
281 .pClearValues = NULL,
282 }, VK_SUBPASS_CONTENTS_INLINE);
283
284
285 bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples);
286 } else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
287 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
288 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
289 &(VkRenderPassBeginInfo) {
290 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
291 .renderPass = device->meta_state.blit2d_depth_only_rp[ds_layout],
292 .framebuffer = dst_temps.fb,
293 .renderArea = {
294 .offset = { rects[r].dst_x, rects[r].dst_y, },
295 .extent = { rects[r].width, rects[r].height },
296 },
297 .clearValueCount = 0,
298 .pClearValues = NULL,
299 }, VK_SUBPASS_CONTENTS_INLINE);
300
301
302 bind_depth_pipeline(cmd_buffer, src_type, log2_samples);
303
304 } else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
305 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
306 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
307 &(VkRenderPassBeginInfo) {
308 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
309 .renderPass = device->meta_state.blit2d_stencil_only_rp[ds_layout],
310 .framebuffer = dst_temps.fb,
311 .renderArea = {
312 .offset = { rects[r].dst_x, rects[r].dst_y, },
313 .extent = { rects[r].width, rects[r].height },
314 },
315 .clearValueCount = 0,
316 .pClearValues = NULL,
317 }, VK_SUBPASS_CONTENTS_INLINE);
318
319
320 bind_stencil_pipeline(cmd_buffer, src_type, log2_samples);
321 } else
322 unreachable("Processing blit2d with multiple aspects.");
323
324 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
325 .x = rects[r].dst_x,
326 .y = rects[r].dst_y,
327 .width = rects[r].width,
328 .height = rects[r].height,
329 .minDepth = 0.0f,
330 .maxDepth = 1.0f
331 });
332
333 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
334 .offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
335 .extent = (VkExtent2D) { rects[r].width, rects[r].height },
336 });
337
338
339
340 if (log2_samples > 0) {
341 for (uint32_t sample = 0; sample < src_img->image->info.samples; sample++) {
342 uint32_t sample_mask = 1 << sample;
343 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
344 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
345 VK_SHADER_STAGE_FRAGMENT_BIT, 20, 4,
346 &sample);
347
348 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
349 device->meta_state.blit2d[log2_samples].p_layouts[src_type],
350 VK_SHADER_STAGE_FRAGMENT_BIT, 24, 4,
351 &sample_mask);
352
353 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
354 }
355 }
356 else
357 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
358 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
359
360 /* At the point where we emit the draw call, all data from the
361 * descriptor sets, etc. has been used. We are free to delete it.
362 */
363 radv_DestroyFramebuffer(radv_device_to_handle(device),
364 dst_temps.fb,
365 &cmd_buffer->pool->alloc);
366 }
367 }
368 }
369
370 void
371 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
372 struct radv_meta_blit2d_surf *src_img,
373 struct radv_meta_blit2d_buffer *src_buf,
374 struct radv_meta_blit2d_surf *dst,
375 unsigned num_rects,
376 struct radv_meta_blit2d_rect *rects)
377 {
378 bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
379 (src_img && src_img->image->type == VK_IMAGE_TYPE_3D);
380 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
381 use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D : BLIT2D_SRC_TYPE_IMAGE;
382 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
383 num_rects, rects, src_type,
384 src_img ? util_logbase2(src_img->image->info.samples) : 0);
385 }
386
387 static nir_shader *
388 build_nir_vertex_shader(void)
389 {
390 const struct glsl_type *vec4 = glsl_vec4_type();
391 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
392 nir_builder b;
393
394 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
395 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_vs");
396
397 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
398 vec4, "gl_Position");
399 pos_out->data.location = VARYING_SLOT_POS;
400
401 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
402 vec2, "v_tex_pos");
403 tex_pos_out->data.location = VARYING_SLOT_VAR0;
404 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
405
406 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
407 nir_store_var(&b, pos_out, outvec, 0xf);
408
409 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
410 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
411 nir_intrinsic_set_base(src_box, 0);
412 nir_intrinsic_set_range(src_box, 16);
413 src_box->num_components = 4;
414 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
415 nir_builder_instr_insert(&b, &src_box->instr);
416
417 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
418 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
419 nir_builder_instr_insert(&b, &vertex_id->instr);
420
421 /* vertex 0 - src_x, src_y */
422 /* vertex 1 - src_x, src_y+h */
423 /* vertex 2 - src_x+w, src_y */
424 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
425 channel 1 is vertex id != 1 ? src_y : src_y + w */
426
427 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
428 nir_imm_int(&b, 2));
429 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
430 nir_imm_int(&b, 1));
431
432 nir_ssa_def *comp[2];
433 comp[0] = nir_bcsel(&b, c0cmp,
434 nir_channel(&b, &src_box->dest.ssa, 0),
435 nir_channel(&b, &src_box->dest.ssa, 2));
436
437 comp[1] = nir_bcsel(&b, c1cmp,
438 nir_channel(&b, &src_box->dest.ssa, 1),
439 nir_channel(&b, &src_box->dest.ssa, 3));
440 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
441 nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
442 return b.shader;
443 }
444
445 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
446 struct radv_device *,
447 nir_ssa_def *, bool, bool);
448
449 static nir_ssa_def *
450 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
451 nir_ssa_def *tex_pos, bool is_3d, bool is_multisampled)
452 {
453 enum glsl_sampler_dim dim =
454 is_3d ? GLSL_SAMPLER_DIM_3D : is_multisampled ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
455 const struct glsl_type *sampler_type =
456 glsl_sampler_type(dim, false, false, GLSL_TYPE_UINT);
457 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
458 sampler_type, "s_tex");
459 sampler->data.descriptor_set = 0;
460 sampler->data.binding = 0;
461
462 nir_ssa_def *tex_pos_3d = NULL;
463 nir_intrinsic_instr *sample_idx = NULL;
464 if (is_3d) {
465 nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
466 nir_intrinsic_set_base(layer, 16);
467 nir_intrinsic_set_range(layer, 4);
468 layer->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
469 layer->num_components = 1;
470 nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
471 nir_builder_instr_insert(b, &layer->instr);
472
473 nir_ssa_def *chans[3];
474 chans[0] = nir_channel(b, tex_pos, 0);
475 chans[1] = nir_channel(b, tex_pos, 1);
476 chans[2] = &layer->dest.ssa;
477 tex_pos_3d = nir_vec(b, chans, 3);
478 }
479 if (is_multisampled) {
480 sample_idx = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
481 nir_intrinsic_set_base(sample_idx, 20);
482 nir_intrinsic_set_range(sample_idx, 4);
483 sample_idx->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
484 sample_idx->num_components = 1;
485 nir_ssa_dest_init(&sample_idx->instr, &sample_idx->dest, 1, 32, "sample_idx");
486 nir_builder_instr_insert(b, &sample_idx->instr);
487 }
488
489 nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
490
491 nir_tex_instr *tex = nir_tex_instr_create(b->shader, is_multisampled ? 4 : 3);
492 tex->sampler_dim = dim;
493 tex->op = is_multisampled ? nir_texop_txf_ms : nir_texop_txf;
494 tex->src[0].src_type = nir_tex_src_coord;
495 tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
496 tex->src[1].src_type = is_multisampled ? nir_tex_src_ms_index : nir_tex_src_lod;
497 tex->src[1].src = nir_src_for_ssa(is_multisampled ? &sample_idx->dest.ssa : nir_imm_int(b, 0));
498 tex->src[2].src_type = nir_tex_src_texture_deref;
499 tex->src[2].src = nir_src_for_ssa(tex_deref);
500 if (is_multisampled) {
501 tex->src[3].src_type = nir_tex_src_lod;
502 tex->src[3].src = nir_src_for_ssa(nir_imm_int(b, 0));
503 }
504 tex->dest_type = nir_type_uint;
505 tex->is_array = false;
506 tex->coord_components = is_3d ? 3 : 2;
507
508 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
509 nir_builder_instr_insert(b, &tex->instr);
510
511 return &tex->dest.ssa;
512 }
513
514
515 static nir_ssa_def *
516 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
517 nir_ssa_def *tex_pos, bool is_3d, bool is_multisampled)
518 {
519 const struct glsl_type *sampler_type =
520 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
521 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
522 sampler_type, "s_tex");
523 sampler->data.descriptor_set = 0;
524 sampler->data.binding = 0;
525
526 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
527 nir_intrinsic_set_base(width, 16);
528 nir_intrinsic_set_range(width, 4);
529 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
530 width->num_components = 1;
531 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
532 nir_builder_instr_insert(b, &width->instr);
533
534 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
535 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
536 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
537 pos_x = nir_iadd(b, pos_x, pos_y);
538 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
539
540 nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
541
542 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
543 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
544 tex->op = nir_texop_txf;
545 tex->src[0].src_type = nir_tex_src_coord;
546 tex->src[0].src = nir_src_for_ssa(pos_x);
547 tex->src[1].src_type = nir_tex_src_texture_deref;
548 tex->src[1].src = nir_src_for_ssa(tex_deref);
549 tex->dest_type = nir_type_uint;
550 tex->is_array = false;
551 tex->coord_components = 1;
552
553 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
554 nir_builder_instr_insert(b, &tex->instr);
555
556 return &tex->dest.ssa;
557 }
558
559 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
560 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
561 .vertexBindingDescriptionCount = 0,
562 .vertexAttributeDescriptionCount = 0,
563 };
564
565 static void
566 build_nir_store_sample_mask(struct nir_builder *b)
567 {
568 nir_intrinsic_instr *sample_mask = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
569 nir_intrinsic_set_base(sample_mask, 24);
570 nir_intrinsic_set_range(sample_mask, 4);
571 sample_mask->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
572 sample_mask->num_components = 1;
573 nir_ssa_dest_init(&sample_mask->instr, &sample_mask->dest, 1, 32, "sample_mask");
574 nir_builder_instr_insert(b, &sample_mask->instr);
575
576 const struct glsl_type *sample_mask_out_type = glsl_uint_type();
577
578 nir_variable *sample_mask_out =
579 nir_variable_create(b->shader, nir_var_shader_out,
580 sample_mask_out_type, "sample_mask_out");
581 sample_mask_out->data.location = FRAG_RESULT_SAMPLE_MASK;
582
583 nir_store_var(b, sample_mask_out, &sample_mask->dest.ssa, 0x1);
584 }
585
586 static nir_shader *
587 build_nir_copy_fragment_shader(struct radv_device *device,
588 texel_fetch_build_func txf_func, const char* name, bool is_3d,
589 bool is_multisampled)
590 {
591 const struct glsl_type *vec4 = glsl_vec4_type();
592 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
593 nir_builder b;
594
595 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
596 b.shader->info.name = ralloc_strdup(b.shader, name);
597
598 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
599 vec2, "v_tex_pos");
600 tex_pos_in->data.location = VARYING_SLOT_VAR0;
601
602 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
603 vec4, "f_color");
604 color_out->data.location = FRAG_RESULT_DATA0;
605
606 if (is_multisampled) {
607 build_nir_store_sample_mask(&b);
608 }
609
610 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
611 nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
612
613 nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
614 nir_store_var(&b, color_out, color, 0xf);
615
616 return b.shader;
617 }
618
619 static nir_shader *
620 build_nir_copy_fragment_shader_depth(struct radv_device *device,
621 texel_fetch_build_func txf_func, const char* name, bool is_3d,
622 bool is_multisampled)
623 {
624 const struct glsl_type *vec4 = glsl_vec4_type();
625 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
626 nir_builder b;
627
628 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
629 b.shader->info.name = ralloc_strdup(b.shader, name);
630
631 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
632 vec2, "v_tex_pos");
633 tex_pos_in->data.location = VARYING_SLOT_VAR0;
634
635 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
636 vec4, "f_color");
637 color_out->data.location = FRAG_RESULT_DEPTH;
638
639 if (is_multisampled) {
640 build_nir_store_sample_mask(&b);
641 }
642
643 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
644 nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
645
646 nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
647 nir_store_var(&b, color_out, color, 0x1);
648
649 return b.shader;
650 }
651
652 static nir_shader *
653 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
654 texel_fetch_build_func txf_func, const char* name, bool is_3d,
655 bool is_multisampled)
656 {
657 const struct glsl_type *vec4 = glsl_vec4_type();
658 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
659 nir_builder b;
660
661 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
662 b.shader->info.name = ralloc_strdup(b.shader, name);
663
664 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
665 vec2, "v_tex_pos");
666 tex_pos_in->data.location = VARYING_SLOT_VAR0;
667
668 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
669 vec4, "f_color");
670 color_out->data.location = FRAG_RESULT_STENCIL;
671
672 if (is_multisampled) {
673 build_nir_store_sample_mask(&b);
674 }
675
676 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
677 nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
678
679 nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
680 nir_store_var(&b, color_out, color, 0x1);
681
682 return b.shader;
683 }
684
685 void
686 radv_device_finish_meta_blit2d_state(struct radv_device *device)
687 {
688 struct radv_meta_state *state = &device->meta_state;
689
690 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
691 for (unsigned k = 0; k < RADV_META_DST_LAYOUT_COUNT; ++k) {
692 radv_DestroyRenderPass(radv_device_to_handle(device),
693 state->blit2d_render_passes[j][k],
694 &state->alloc);
695 }
696 }
697
698 for (enum radv_blit_ds_layout j = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; j < RADV_BLIT_DS_LAYOUT_COUNT; j++) {
699 radv_DestroyRenderPass(radv_device_to_handle(device),
700 state->blit2d_depth_only_rp[j], &state->alloc);
701 radv_DestroyRenderPass(radv_device_to_handle(device),
702 state->blit2d_stencil_only_rp[j], &state->alloc);
703 }
704
705 for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; ++log2_samples) {
706 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
707 radv_DestroyPipelineLayout(radv_device_to_handle(device),
708 state->blit2d[log2_samples].p_layouts[src],
709 &state->alloc);
710 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
711 state->blit2d[log2_samples].ds_layouts[src],
712 &state->alloc);
713
714 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
715 radv_DestroyPipeline(radv_device_to_handle(device),
716 state->blit2d[log2_samples].pipelines[src][j],
717 &state->alloc);
718 }
719
720 radv_DestroyPipeline(radv_device_to_handle(device),
721 state->blit2d[log2_samples].depth_only_pipeline[src],
722 &state->alloc);
723 radv_DestroyPipeline(radv_device_to_handle(device),
724 state->blit2d[log2_samples].stencil_only_pipeline[src],
725 &state->alloc);
726 }
727 }
728 }
729
730 static VkResult
731 blit2d_init_color_pipeline(struct radv_device *device,
732 enum blit2d_src_type src_type,
733 VkFormat format,
734 uint32_t log2_samples)
735 {
736 VkResult result;
737 unsigned fs_key = radv_format_meta_fs_key(format);
738 const char *name;
739
740 texel_fetch_build_func src_func;
741 switch(src_type) {
742 case BLIT2D_SRC_TYPE_IMAGE:
743 src_func = build_nir_texel_fetch;
744 name = "meta_blit2d_image_fs";
745 break;
746 case BLIT2D_SRC_TYPE_IMAGE_3D:
747 src_func = build_nir_texel_fetch;
748 name = "meta_blit3d_image_fs";
749 break;
750 case BLIT2D_SRC_TYPE_BUFFER:
751 src_func = build_nir_buffer_fetch;
752 name = "meta_blit2d_buffer_fs";
753 break;
754 default:
755 unreachable("unknown blit src type\n");
756 break;
757 }
758
759 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
760 struct radv_shader_module fs = { .nir = NULL };
761
762
763 fs.nir = build_nir_copy_fragment_shader(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
764 vi_create_info = &normal_vi_create_info;
765
766 struct radv_shader_module vs = {
767 .nir = build_nir_vertex_shader(),
768 };
769
770 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
771 {
772 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
773 .stage = VK_SHADER_STAGE_VERTEX_BIT,
774 .module = radv_shader_module_to_handle(&vs),
775 .pName = "main",
776 .pSpecializationInfo = NULL
777 }, {
778 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
779 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
780 .module = radv_shader_module_to_handle(&fs),
781 .pName = "main",
782 .pSpecializationInfo = NULL
783 },
784 };
785
786 for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) {
787 if (!device->meta_state.blit2d_render_passes[fs_key][dst_layout]) {
788 VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
789
790 result = radv_CreateRenderPass(radv_device_to_handle(device),
791 &(VkRenderPassCreateInfo) {
792 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
793 .attachmentCount = 1,
794 .pAttachments = &(VkAttachmentDescription) {
795 .format = format,
796 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
797 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
798 .initialLayout = layout,
799 .finalLayout = layout,
800 },
801 .subpassCount = 1,
802 .pSubpasses = &(VkSubpassDescription) {
803 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
804 .inputAttachmentCount = 0,
805 .colorAttachmentCount = 1,
806 .pColorAttachments = &(VkAttachmentReference) {
807 .attachment = 0,
808 .layout = layout,
809 },
810 .pResolveAttachments = NULL,
811 .pDepthStencilAttachment = &(VkAttachmentReference) {
812 .attachment = VK_ATTACHMENT_UNUSED,
813 .layout = layout,
814 },
815 .preserveAttachmentCount = 1,
816 .pPreserveAttachments = (uint32_t[]) { 0 },
817 },
818 .dependencyCount = 0,
819 }, &device->meta_state.alloc, &device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
820 }
821 }
822
823 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
824 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
825 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
826 .pStages = pipeline_shader_stages,
827 .pVertexInputState = vi_create_info,
828 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
829 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
830 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
831 .primitiveRestartEnable = false,
832 },
833 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
834 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
835 .viewportCount = 1,
836 .scissorCount = 1,
837 },
838 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
839 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
840 .rasterizerDiscardEnable = false,
841 .polygonMode = VK_POLYGON_MODE_FILL,
842 .cullMode = VK_CULL_MODE_NONE,
843 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
844 },
845 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
846 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
847 .rasterizationSamples = 1 << log2_samples,
848 .sampleShadingEnable = false,
849 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
850 },
851 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
852 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
853 .attachmentCount = 1,
854 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
855 { .colorWriteMask =
856 VK_COLOR_COMPONENT_A_BIT |
857 VK_COLOR_COMPONENT_R_BIT |
858 VK_COLOR_COMPONENT_G_BIT |
859 VK_COLOR_COMPONENT_B_BIT },
860 }
861 },
862 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
863 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
864 .dynamicStateCount = 9,
865 .pDynamicStates = (VkDynamicState[]) {
866 VK_DYNAMIC_STATE_VIEWPORT,
867 VK_DYNAMIC_STATE_SCISSOR,
868 VK_DYNAMIC_STATE_LINE_WIDTH,
869 VK_DYNAMIC_STATE_DEPTH_BIAS,
870 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
871 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
872 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
873 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
874 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
875 },
876 },
877 .flags = 0,
878 .layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
879 .renderPass = device->meta_state.blit2d_render_passes[fs_key][0],
880 .subpass = 0,
881 };
882
883 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
884 .use_rectlist = true
885 };
886
887 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
888 radv_pipeline_cache_to_handle(&device->meta_state.cache),
889 &vk_pipeline_info, &radv_pipeline_info,
890 &device->meta_state.alloc,
891 &device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key]);
892
893
894 ralloc_free(vs.nir);
895 ralloc_free(fs.nir);
896
897 return result;
898 }
899
900 static VkResult
901 blit2d_init_depth_only_pipeline(struct radv_device *device,
902 enum blit2d_src_type src_type,
903 uint32_t log2_samples)
904 {
905 VkResult result;
906 const char *name;
907
908 texel_fetch_build_func src_func;
909 switch(src_type) {
910 case BLIT2D_SRC_TYPE_IMAGE:
911 src_func = build_nir_texel_fetch;
912 name = "meta_blit2d_depth_image_fs";
913 break;
914 case BLIT2D_SRC_TYPE_IMAGE_3D:
915 src_func = build_nir_texel_fetch;
916 name = "meta_blit3d_depth_image_fs";
917 break;
918 case BLIT2D_SRC_TYPE_BUFFER:
919 src_func = build_nir_buffer_fetch;
920 name = "meta_blit2d_depth_buffer_fs";
921 break;
922 default:
923 unreachable("unknown blit src type\n");
924 break;
925 }
926
927 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
928 struct radv_shader_module fs = { .nir = NULL };
929
930 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
931 vi_create_info = &normal_vi_create_info;
932
933 struct radv_shader_module vs = {
934 .nir = build_nir_vertex_shader(),
935 };
936
937 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
938 {
939 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
940 .stage = VK_SHADER_STAGE_VERTEX_BIT,
941 .module = radv_shader_module_to_handle(&vs),
942 .pName = "main",
943 .pSpecializationInfo = NULL
944 }, {
945 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
946 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
947 .module = radv_shader_module_to_handle(&fs),
948 .pName = "main",
949 .pSpecializationInfo = NULL
950 },
951 };
952
953 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
954 if (!device->meta_state.blit2d_depth_only_rp[ds_layout]) {
955 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
956 result = radv_CreateRenderPass(radv_device_to_handle(device),
957 &(VkRenderPassCreateInfo) {
958 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
959 .attachmentCount = 1,
960 .pAttachments = &(VkAttachmentDescription) {
961 .format = VK_FORMAT_D32_SFLOAT,
962 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
963 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
964 .initialLayout = layout,
965 .finalLayout = layout,
966 },
967 .subpassCount = 1,
968 .pSubpasses = &(VkSubpassDescription) {
969 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
970 .inputAttachmentCount = 0,
971 .colorAttachmentCount = 0,
972 .pColorAttachments = NULL,
973 .pResolveAttachments = NULL,
974 .pDepthStencilAttachment = &(VkAttachmentReference) {
975 .attachment = 0,
976 .layout = layout,
977 },
978 .preserveAttachmentCount = 1,
979 .pPreserveAttachments = (uint32_t[]) { 0 },
980 },
981 .dependencyCount = 0,
982 }, &device->meta_state.alloc, &device->meta_state.blit2d_depth_only_rp[ds_layout]);
983 }
984 }
985
986 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
987 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
988 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
989 .pStages = pipeline_shader_stages,
990 .pVertexInputState = vi_create_info,
991 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
992 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
993 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
994 .primitiveRestartEnable = false,
995 },
996 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
997 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
998 .viewportCount = 1,
999 .scissorCount = 1,
1000 },
1001 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1002 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1003 .rasterizerDiscardEnable = false,
1004 .polygonMode = VK_POLYGON_MODE_FILL,
1005 .cullMode = VK_CULL_MODE_NONE,
1006 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1007 },
1008 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1009 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1010 .rasterizationSamples = 1 << log2_samples,
1011 .sampleShadingEnable = false,
1012 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1013 },
1014 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1015 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1016 .attachmentCount = 0,
1017 .pAttachments = NULL,
1018 },
1019 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1020 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1021 .depthTestEnable = true,
1022 .depthWriteEnable = true,
1023 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1024 },
1025 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1026 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1027 .dynamicStateCount = 9,
1028 .pDynamicStates = (VkDynamicState[]) {
1029 VK_DYNAMIC_STATE_VIEWPORT,
1030 VK_DYNAMIC_STATE_SCISSOR,
1031 VK_DYNAMIC_STATE_LINE_WIDTH,
1032 VK_DYNAMIC_STATE_DEPTH_BIAS,
1033 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1034 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1035 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
1036 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
1037 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
1038 },
1039 },
1040 .flags = 0,
1041 .layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
1042 .renderPass = device->meta_state.blit2d_depth_only_rp[0],
1043 .subpass = 0,
1044 };
1045
1046 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1047 .use_rectlist = true
1048 };
1049
1050 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1051 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1052 &vk_pipeline_info, &radv_pipeline_info,
1053 &device->meta_state.alloc,
1054 &device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type]);
1055
1056
1057 ralloc_free(vs.nir);
1058 ralloc_free(fs.nir);
1059
1060 return result;
1061 }
1062
1063 static VkResult
1064 blit2d_init_stencil_only_pipeline(struct radv_device *device,
1065 enum blit2d_src_type src_type,
1066 uint32_t log2_samples)
1067 {
1068 VkResult result;
1069 const char *name;
1070
1071 texel_fetch_build_func src_func;
1072 switch(src_type) {
1073 case BLIT2D_SRC_TYPE_IMAGE:
1074 src_func = build_nir_texel_fetch;
1075 name = "meta_blit2d_stencil_image_fs";
1076 break;
1077 case BLIT2D_SRC_TYPE_IMAGE_3D:
1078 src_func = build_nir_texel_fetch;
1079 name = "meta_blit3d_stencil_image_fs";
1080 break;
1081 case BLIT2D_SRC_TYPE_BUFFER:
1082 src_func = build_nir_buffer_fetch;
1083 name = "meta_blit2d_stencil_buffer_fs";
1084 break;
1085 default:
1086 unreachable("unknown blit src type\n");
1087 break;
1088 }
1089
1090 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1091 struct radv_shader_module fs = { .nir = NULL };
1092
1093 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
1094 vi_create_info = &normal_vi_create_info;
1095
1096 struct radv_shader_module vs = {
1097 .nir = build_nir_vertex_shader(),
1098 };
1099
1100 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1101 {
1102 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1103 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1104 .module = radv_shader_module_to_handle(&vs),
1105 .pName = "main",
1106 .pSpecializationInfo = NULL
1107 }, {
1108 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1109 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1110 .module = radv_shader_module_to_handle(&fs),
1111 .pName = "main",
1112 .pSpecializationInfo = NULL
1113 },
1114 };
1115
1116 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1117 if (!device->meta_state.blit2d_stencil_only_rp[ds_layout]) {
1118 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1119 result = radv_CreateRenderPass(radv_device_to_handle(device),
1120 &(VkRenderPassCreateInfo) {
1121 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1122 .attachmentCount = 1,
1123 .pAttachments = &(VkAttachmentDescription) {
1124 .format = VK_FORMAT_S8_UINT,
1125 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1126 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1127 .initialLayout = layout,
1128 .finalLayout = layout,
1129 },
1130 .subpassCount = 1,
1131 .pSubpasses = &(VkSubpassDescription) {
1132 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1133 .inputAttachmentCount = 0,
1134 .colorAttachmentCount = 0,
1135 .pColorAttachments = NULL,
1136 .pResolveAttachments = NULL,
1137 .pDepthStencilAttachment = &(VkAttachmentReference) {
1138 .attachment = 0,
1139 .layout = layout,
1140 },
1141 .preserveAttachmentCount = 1,
1142 .pPreserveAttachments = (uint32_t[]) { 0 },
1143 },
1144 .dependencyCount = 0,
1145 }, &device->meta_state.alloc, &device->meta_state.blit2d_stencil_only_rp[ds_layout]);
1146 }
1147 }
1148
1149 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1150 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1151 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1152 .pStages = pipeline_shader_stages,
1153 .pVertexInputState = vi_create_info,
1154 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1155 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1156 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1157 .primitiveRestartEnable = false,
1158 },
1159 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1160 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1161 .viewportCount = 1,
1162 .scissorCount = 1,
1163 },
1164 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1165 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1166 .rasterizerDiscardEnable = false,
1167 .polygonMode = VK_POLYGON_MODE_FILL,
1168 .cullMode = VK_CULL_MODE_NONE,
1169 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1170 },
1171 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1172 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1173 .rasterizationSamples = 1 << log2_samples,
1174 .sampleShadingEnable = false,
1175 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1176 },
1177 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1178 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1179 .attachmentCount = 0,
1180 .pAttachments = NULL,
1181 },
1182 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1183 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1184 .depthTestEnable = false,
1185 .depthWriteEnable = false,
1186 .stencilTestEnable = true,
1187 .front = {
1188 .failOp = VK_STENCIL_OP_REPLACE,
1189 .passOp = VK_STENCIL_OP_REPLACE,
1190 .depthFailOp = VK_STENCIL_OP_REPLACE,
1191 .compareOp = VK_COMPARE_OP_ALWAYS,
1192 .compareMask = 0xff,
1193 .writeMask = 0xff,
1194 .reference = 0
1195 },
1196 .back = {
1197 .failOp = VK_STENCIL_OP_REPLACE,
1198 .passOp = VK_STENCIL_OP_REPLACE,
1199 .depthFailOp = VK_STENCIL_OP_REPLACE,
1200 .compareOp = VK_COMPARE_OP_ALWAYS,
1201 .compareMask = 0xff,
1202 .writeMask = 0xff,
1203 .reference = 0
1204 },
1205 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1206 },
1207 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1208 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1209 .dynamicStateCount = 6,
1210 .pDynamicStates = (VkDynamicState[]) {
1211 VK_DYNAMIC_STATE_VIEWPORT,
1212 VK_DYNAMIC_STATE_SCISSOR,
1213 VK_DYNAMIC_STATE_LINE_WIDTH,
1214 VK_DYNAMIC_STATE_DEPTH_BIAS,
1215 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1216 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1217 },
1218 },
1219 .flags = 0,
1220 .layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
1221 .renderPass = device->meta_state.blit2d_stencil_only_rp[0],
1222 .subpass = 0,
1223 };
1224
1225 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1226 .use_rectlist = true
1227 };
1228
1229 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1230 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1231 &vk_pipeline_info, &radv_pipeline_info,
1232 &device->meta_state.alloc,
1233 &device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]);
1234
1235
1236 ralloc_free(vs.nir);
1237 ralloc_free(fs.nir);
1238
1239 return result;
1240 }
1241
1242 static VkFormat pipeline_formats[] = {
1243 VK_FORMAT_R8G8B8A8_UNORM,
1244 VK_FORMAT_R8G8B8A8_UINT,
1245 VK_FORMAT_R8G8B8A8_SINT,
1246 VK_FORMAT_A2R10G10B10_UINT_PACK32,
1247 VK_FORMAT_A2R10G10B10_SINT_PACK32,
1248 VK_FORMAT_R16G16B16A16_UNORM,
1249 VK_FORMAT_R16G16B16A16_SNORM,
1250 VK_FORMAT_R16G16B16A16_UINT,
1251 VK_FORMAT_R16G16B16A16_SINT,
1252 VK_FORMAT_R32_SFLOAT,
1253 VK_FORMAT_R32G32_SFLOAT,
1254 VK_FORMAT_R32G32B32A32_SFLOAT
1255 };
1256
1257 static VkResult
1258 meta_blit2d_create_pipe_layout(struct radv_device *device,
1259 int idx,
1260 uint32_t log2_samples)
1261 {
1262 VkResult result;
1263 VkDescriptorType desc_type = (idx == BLIT2D_SRC_TYPE_BUFFER) ? VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER : VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE;
1264 const VkPushConstantRange push_constant_ranges[] = {
1265 {VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
1266 {VK_SHADER_STAGE_FRAGMENT_BIT, 16, 12},
1267 };
1268 int num_push_constant_range = (idx != BLIT2D_SRC_TYPE_IMAGE || log2_samples > 0) ? 2 : 1;
1269
1270 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1271 &(VkDescriptorSetLayoutCreateInfo) {
1272 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1273 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1274 .bindingCount = 1,
1275 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1276 {
1277 .binding = 0,
1278 .descriptorType = desc_type,
1279 .descriptorCount = 1,
1280 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1281 .pImmutableSamplers = NULL
1282 },
1283 }
1284 }, &device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].ds_layouts[idx]);
1285 if (result != VK_SUCCESS)
1286 goto fail;
1287
1288 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1289 &(VkPipelineLayoutCreateInfo) {
1290 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1291 .setLayoutCount = 1,
1292 .pSetLayouts = &device->meta_state.blit2d[log2_samples].ds_layouts[idx],
1293 .pushConstantRangeCount = num_push_constant_range,
1294 .pPushConstantRanges = push_constant_ranges,
1295 },
1296 &device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].p_layouts[idx]);
1297 if (result != VK_SUCCESS)
1298 goto fail;
1299 return VK_SUCCESS;
1300 fail:
1301 return result;
1302 }
1303
1304 VkResult
1305 radv_device_init_meta_blit2d_state(struct radv_device *device)
1306 {
1307 VkResult result;
1308 bool create_3d = device->physical_device->rad_info.chip_class >= GFX9;
1309
1310 for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; log2_samples++) {
1311 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1312 if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
1313 continue;
1314
1315 /* Don't need to handle copies between buffers and multisample images. */
1316 if (src == BLIT2D_SRC_TYPE_BUFFER && log2_samples > 0)
1317 continue;
1318
1319 result = meta_blit2d_create_pipe_layout(device, src, log2_samples);
1320 if (result != VK_SUCCESS)
1321 goto fail;
1322
1323 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1324 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j], log2_samples);
1325 if (result != VK_SUCCESS)
1326 goto fail;
1327 }
1328
1329 result = blit2d_init_depth_only_pipeline(device, src, log2_samples);
1330 if (result != VK_SUCCESS)
1331 goto fail;
1332
1333 result = blit2d_init_stencil_only_pipeline(device, src, log2_samples);
1334 if (result != VK_SUCCESS)
1335 goto fail;
1336 }
1337 }
1338
1339 return VK_SUCCESS;
1340
1341 fail:
1342 radv_device_finish_meta_blit2d_state(device);
1343 return result;
1344 }