2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
31 enum blit2d_src_type
{
32 BLIT2D_SRC_TYPE_IMAGE
,
33 BLIT2D_SRC_TYPE_BUFFER
,
38 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
39 struct radv_meta_blit2d_surf
*surf
,
40 struct radv_image_view
*iview
, VkFormat depth_format
)
45 format
= depth_format
;
47 format
= surf
->format
;
49 radv_image_view_init(iview
, cmd_buffer
->device
,
50 &(VkImageViewCreateInfo
) {
51 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
52 .image
= radv_image_to_handle(surf
->image
),
53 .viewType
= VK_IMAGE_VIEW_TYPE_2D
,
56 .aspectMask
= surf
->aspect_mask
,
57 .baseMipLevel
= surf
->level
,
59 .baseArrayLayer
= surf
->layer
,
66 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
67 struct radv_meta_blit2d_buffer
*src
,
68 struct radv_buffer_view
*bview
, VkFormat depth_format
)
73 format
= depth_format
;
76 radv_buffer_view_init(bview
, cmd_buffer
->device
,
77 &(VkBufferViewCreateInfo
) {
78 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
80 .buffer
= radv_buffer_to_handle(src
->buffer
),
82 .offset
= src
->offset
,
83 .range
= VK_WHOLE_SIZE
,
88 struct blit2d_src_temps
{
89 struct radv_image_view iview
;
90 struct radv_buffer_view bview
;
94 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
95 struct radv_meta_blit2d_surf
*src_img
,
96 struct radv_meta_blit2d_buffer
*src_buf
,
97 struct blit2d_src_temps
*tmp
,
98 enum blit2d_src_type src_type
, VkFormat depth_format
)
100 struct radv_device
*device
= cmd_buffer
->device
;
102 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
103 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
105 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
106 device
->meta_state
.blit2d
.p_layouts
[src_type
],
108 1, /* descriptorWriteCount */
109 (VkWriteDescriptorSet
[]) {
111 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
113 .dstArrayElement
= 0,
114 .descriptorCount
= 1,
115 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
116 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
120 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
121 device
->meta_state
.blit2d
.p_layouts
[src_type
],
122 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
125 create_iview(cmd_buffer
, src_img
, &tmp
->iview
, depth_format
);
127 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
128 device
->meta_state
.blit2d
.p_layouts
[src_type
],
130 1, /* descriptorWriteCount */
131 (VkWriteDescriptorSet
[]) {
133 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
135 .dstArrayElement
= 0,
136 .descriptorCount
= 1,
137 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
138 .pImageInfo
= (VkDescriptorImageInfo
[]) {
140 .sampler
= VK_NULL_HANDLE
,
141 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
142 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
150 struct blit2d_dst_temps
{
152 struct radv_image_view iview
;
157 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
158 struct radv_meta_blit2d_surf
*dst
,
161 VkFormat depth_format
,
162 struct blit2d_dst_temps
*tmp
)
164 create_iview(cmd_buffer
, dst
, &tmp
->iview
, depth_format
);
166 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
167 &(VkFramebufferCreateInfo
) {
168 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
169 .attachmentCount
= 1,
170 .pAttachments
= (VkImageView
[]) {
171 radv_image_view_to_handle(&tmp
->iview
),
176 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
180 blit2d_unbind_dst(struct radv_cmd_buffer
*cmd_buffer
,
181 struct blit2d_dst_temps
*tmp
)
183 VkDevice vk_device
= radv_device_to_handle(cmd_buffer
->device
);
184 radv_DestroyFramebuffer(vk_device
, tmp
->fb
, &cmd_buffer
->pool
->alloc
);
188 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
189 enum blit2d_src_type src_type
, unsigned fs_key
)
191 VkPipeline pipeline
=
192 cmd_buffer
->device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
];
194 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
195 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
196 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
201 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
202 enum blit2d_src_type src_type
)
204 VkPipeline pipeline
=
205 cmd_buffer
->device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
];
207 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
208 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
209 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
214 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
215 enum blit2d_src_type src_type
)
217 VkPipeline pipeline
=
218 cmd_buffer
->device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
];
220 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
221 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
222 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
227 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
228 struct radv_meta_blit2d_surf
*src_img
,
229 struct radv_meta_blit2d_buffer
*src_buf
,
230 struct radv_meta_blit2d_surf
*dst
,
232 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
)
234 struct radv_device
*device
= cmd_buffer
->device
;
236 for (unsigned r
= 0; r
< num_rects
; ++r
) {
237 VkFormat depth_format
= 0;
238 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
239 depth_format
= vk_format_stencil_only(dst
->image
->vk_format
);
240 else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
)
241 depth_format
= vk_format_depth_only(dst
->image
->vk_format
);
242 struct blit2d_src_temps src_temps
;
243 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
);
245 struct blit2d_dst_temps dst_temps
;
246 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
247 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
);
249 float vertex_push_constants
[4] = {
252 rects
[r
].src_x
+ rects
[r
].width
,
253 rects
[r
].src_y
+ rects
[r
].height
,
256 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
257 device
->meta_state
.blit2d
.p_layouts
[src_type
],
258 VK_SHADER_STAGE_VERTEX_BIT
, 0, 16,
259 vertex_push_constants
);
261 if (dst
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
262 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
264 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
265 &(VkRenderPassBeginInfo
) {
266 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
267 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
268 .framebuffer
= dst_temps
.fb
,
270 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
271 .extent
= { rects
[r
].width
, rects
[r
].height
},
273 .clearValueCount
= 0,
274 .pClearValues
= NULL
,
275 }, VK_SUBPASS_CONTENTS_INLINE
);
278 bind_pipeline(cmd_buffer
, src_type
, fs_key
);
279 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
280 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
281 &(VkRenderPassBeginInfo
) {
282 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
283 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
284 .framebuffer
= dst_temps
.fb
,
286 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
287 .extent
= { rects
[r
].width
, rects
[r
].height
},
289 .clearValueCount
= 0,
290 .pClearValues
= NULL
,
291 }, VK_SUBPASS_CONTENTS_INLINE
);
294 bind_depth_pipeline(cmd_buffer
, src_type
);
296 } else if (dst
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
297 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
298 &(VkRenderPassBeginInfo
) {
299 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
300 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
301 .framebuffer
= dst_temps
.fb
,
303 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
304 .extent
= { rects
[r
].width
, rects
[r
].height
},
306 .clearValueCount
= 0,
307 .pClearValues
= NULL
,
308 }, VK_SUBPASS_CONTENTS_INLINE
);
311 bind_stencil_pipeline(cmd_buffer
, src_type
);
314 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
317 .width
= rects
[r
].width
,
318 .height
= rects
[r
].height
,
323 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
324 .offset
= (VkOffset2D
) { rects
[r
].dst_x
, rects
[r
].dst_y
},
325 .extent
= (VkExtent2D
) { rects
[r
].width
, rects
[r
].height
},
330 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
331 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
333 /* At the point where we emit the draw call, all data from the
334 * descriptor sets, etc. has been used. We are free to delete it.
336 blit2d_unbind_dst(cmd_buffer
, &dst_temps
);
341 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
342 struct radv_meta_blit2d_surf
*src_img
,
343 struct radv_meta_blit2d_buffer
*src_buf
,
344 struct radv_meta_blit2d_surf
*dst
,
346 struct radv_meta_blit2d_rect
*rects
)
348 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
349 BLIT2D_SRC_TYPE_IMAGE
;
350 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
351 num_rects
, rects
, src_type
);
355 build_nir_vertex_shader(void)
357 const struct glsl_type
*vec4
= glsl_vec4_type();
358 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
361 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
362 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit2d_vs");
364 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
365 vec4
, "gl_Position");
366 pos_out
->data
.location
= VARYING_SLOT_POS
;
368 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
370 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
371 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
373 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
374 nir_store_var(&b
, pos_out
, outvec
, 0xf);
376 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
377 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
378 nir_intrinsic_set_base(src_box
, 0);
379 nir_intrinsic_set_range(src_box
, 16);
380 src_box
->num_components
= 4;
381 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
382 nir_builder_instr_insert(&b
, &src_box
->instr
);
384 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
385 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
386 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
388 /* vertex 0 - src_x, src_y */
389 /* vertex 1 - src_x, src_y+h */
390 /* vertex 2 - src_x+w, src_y */
391 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
392 channel 1 is vertex id != 1 ? src_y : src_y + w */
394 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
396 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
399 nir_ssa_def
*comp
[2];
400 comp
[0] = nir_bcsel(&b
, c0cmp
,
401 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
402 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
404 comp
[1] = nir_bcsel(&b
, c1cmp
,
405 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
406 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
407 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 2);
408 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0x3);
412 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
413 struct radv_device
*,
417 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
418 nir_ssa_def
*tex_pos
)
420 const struct glsl_type
*sampler_type
=
421 glsl_sampler_type(GLSL_SAMPLER_DIM_2D
, false, false, GLSL_TYPE_UINT
);
422 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
423 sampler_type
, "s_tex");
424 sampler
->data
.descriptor_set
= 0;
425 sampler
->data
.binding
= 0;
427 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
428 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
429 tex
->op
= nir_texop_txf
;
430 tex
->src
[0].src_type
= nir_tex_src_coord
;
431 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
432 tex
->src
[1].src_type
= nir_tex_src_lod
;
433 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
434 tex
->dest_type
= nir_type_uint
;
435 tex
->is_array
= false;
436 tex
->coord_components
= 2;
437 tex
->texture
= nir_deref_var_create(tex
, sampler
);
440 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
441 nir_builder_instr_insert(b
, &tex
->instr
);
443 return &tex
->dest
.ssa
;
448 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
449 nir_ssa_def
*tex_pos
)
451 const struct glsl_type
*sampler_type
=
452 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
453 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
454 sampler_type
, "s_tex");
455 sampler
->data
.descriptor_set
= 0;
456 sampler
->data
.binding
= 0;
458 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
459 nir_intrinsic_set_base(width
, 16);
460 nir_intrinsic_set_range(width
, 4);
461 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
462 width
->num_components
= 1;
463 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
464 nir_builder_instr_insert(b
, &width
->instr
);
466 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
467 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
468 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
469 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
470 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
472 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
473 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
474 tex
->op
= nir_texop_txf
;
475 tex
->src
[0].src_type
= nir_tex_src_coord
;
476 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
477 tex
->dest_type
= nir_type_uint
;
478 tex
->is_array
= false;
479 tex
->coord_components
= 1;
480 tex
->texture
= nir_deref_var_create(tex
, sampler
);
483 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
484 nir_builder_instr_insert(b
, &tex
->instr
);
486 return &tex
->dest
.ssa
;
489 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
490 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
491 .vertexBindingDescriptionCount
= 0,
492 .vertexAttributeDescriptionCount
= 0,
496 build_nir_copy_fragment_shader(struct radv_device
*device
,
497 texel_fetch_build_func txf_func
, const char* name
)
499 const struct glsl_type
*vec4
= glsl_vec4_type();
500 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
503 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
504 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
506 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
508 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
510 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
512 color_out
->data
.location
= FRAG_RESULT_DATA0
;
514 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
515 unsigned swiz
[4] = { 0, 1 };
516 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
518 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
519 nir_store_var(&b
, color_out
, color
, 0xf);
525 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
526 texel_fetch_build_func txf_func
, const char* name
)
528 const struct glsl_type
*vec4
= glsl_vec4_type();
529 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
532 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
533 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
535 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
537 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
539 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
541 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
543 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
544 unsigned swiz
[4] = { 0, 1 };
545 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
547 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
548 nir_store_var(&b
, color_out
, color
, 0x1);
554 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
555 texel_fetch_build_func txf_func
, const char* name
)
557 const struct glsl_type
*vec4
= glsl_vec4_type();
558 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
561 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
562 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
564 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
566 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
568 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
570 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
572 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
573 unsigned swiz
[4] = { 0, 1 };
574 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
576 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
);
577 nir_store_var(&b
, color_out
, color
, 0x1);
583 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
585 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
586 if (device
->meta_state
.blit2d
.render_passes
[j
]) {
587 radv_DestroyRenderPass(radv_device_to_handle(device
),
588 device
->meta_state
.blit2d
.render_passes
[j
],
589 &device
->meta_state
.alloc
);
593 radv_DestroyRenderPass(radv_device_to_handle(device
),
594 device
->meta_state
.blit2d
.depth_only_rp
,
595 &device
->meta_state
.alloc
);
596 radv_DestroyRenderPass(radv_device_to_handle(device
),
597 device
->meta_state
.blit2d
.stencil_only_rp
,
598 &device
->meta_state
.alloc
);
600 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
601 if (device
->meta_state
.blit2d
.p_layouts
[src
]) {
602 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
603 device
->meta_state
.blit2d
.p_layouts
[src
],
604 &device
->meta_state
.alloc
);
607 if (device
->meta_state
.blit2d
.ds_layouts
[src
]) {
608 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
609 device
->meta_state
.blit2d
.ds_layouts
[src
],
610 &device
->meta_state
.alloc
);
613 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
614 if (device
->meta_state
.blit2d
.pipelines
[src
][j
]) {
615 radv_DestroyPipeline(radv_device_to_handle(device
),
616 device
->meta_state
.blit2d
.pipelines
[src
][j
],
617 &device
->meta_state
.alloc
);
621 radv_DestroyPipeline(radv_device_to_handle(device
),
622 device
->meta_state
.blit2d
.depth_only_pipeline
[src
],
623 &device
->meta_state
.alloc
);
624 radv_DestroyPipeline(radv_device_to_handle(device
),
625 device
->meta_state
.blit2d
.stencil_only_pipeline
[src
],
626 &device
->meta_state
.alloc
);
631 blit2d_init_color_pipeline(struct radv_device
*device
,
632 enum blit2d_src_type src_type
,
636 unsigned fs_key
= radv_format_meta_fs_key(format
);
639 texel_fetch_build_func src_func
;
641 case BLIT2D_SRC_TYPE_IMAGE
:
642 src_func
= build_nir_texel_fetch
;
643 name
= "meta_blit2d_image_fs";
645 case BLIT2D_SRC_TYPE_BUFFER
:
646 src_func
= build_nir_buffer_fetch
;
647 name
= "meta_blit2d_buffer_fs";
650 unreachable("unknown blit src type\n");
654 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
655 struct radv_shader_module fs
= { .nir
= NULL
};
658 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
);
659 vi_create_info
= &normal_vi_create_info
;
661 struct radv_shader_module vs
= {
662 .nir
= build_nir_vertex_shader(),
665 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
667 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
668 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
669 .module
= radv_shader_module_to_handle(&vs
),
671 .pSpecializationInfo
= NULL
673 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
674 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
675 .module
= radv_shader_module_to_handle(&fs
),
677 .pSpecializationInfo
= NULL
681 if (!device
->meta_state
.blit2d
.render_passes
[fs_key
]) {
682 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
683 &(VkRenderPassCreateInfo
) {
684 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
685 .attachmentCount
= 1,
686 .pAttachments
= &(VkAttachmentDescription
) {
688 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
689 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
690 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
691 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
694 .pSubpasses
= &(VkSubpassDescription
) {
695 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
696 .inputAttachmentCount
= 0,
697 .colorAttachmentCount
= 1,
698 .pColorAttachments
= &(VkAttachmentReference
) {
700 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
702 .pResolveAttachments
= NULL
,
703 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
704 .attachment
= VK_ATTACHMENT_UNUSED
,
705 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
707 .preserveAttachmentCount
= 1,
708 .pPreserveAttachments
= (uint32_t[]) { 0 },
710 .dependencyCount
= 0,
711 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.render_passes
[fs_key
]);
714 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
715 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
716 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
717 .pStages
= pipeline_shader_stages
,
718 .pVertexInputState
= vi_create_info
,
719 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
720 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
721 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
722 .primitiveRestartEnable
= false,
724 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
725 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
729 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
730 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
731 .rasterizerDiscardEnable
= false,
732 .polygonMode
= VK_POLYGON_MODE_FILL
,
733 .cullMode
= VK_CULL_MODE_NONE
,
734 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
736 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
737 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
738 .rasterizationSamples
= 1,
739 .sampleShadingEnable
= false,
740 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
742 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
743 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
744 .attachmentCount
= 1,
745 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
747 VK_COLOR_COMPONENT_A_BIT
|
748 VK_COLOR_COMPONENT_R_BIT
|
749 VK_COLOR_COMPONENT_G_BIT
|
750 VK_COLOR_COMPONENT_B_BIT
},
753 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
754 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
755 .dynamicStateCount
= 9,
756 .pDynamicStates
= (VkDynamicState
[]) {
757 VK_DYNAMIC_STATE_VIEWPORT
,
758 VK_DYNAMIC_STATE_SCISSOR
,
759 VK_DYNAMIC_STATE_LINE_WIDTH
,
760 VK_DYNAMIC_STATE_DEPTH_BIAS
,
761 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
762 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
763 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
764 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
765 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
769 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
770 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
774 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
778 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
779 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
780 &vk_pipeline_info
, &radv_pipeline_info
,
781 &device
->meta_state
.alloc
,
782 &device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
]);
792 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
793 enum blit2d_src_type src_type
)
798 texel_fetch_build_func src_func
;
800 case BLIT2D_SRC_TYPE_IMAGE
:
801 src_func
= build_nir_texel_fetch
;
802 name
= "meta_blit2d_depth_image_fs";
804 case BLIT2D_SRC_TYPE_BUFFER
:
805 src_func
= build_nir_buffer_fetch
;
806 name
= "meta_blit2d_depth_buffer_fs";
809 unreachable("unknown blit src type\n");
813 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
814 struct radv_shader_module fs
= { .nir
= NULL
};
816 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
);
817 vi_create_info
= &normal_vi_create_info
;
819 struct radv_shader_module vs
= {
820 .nir
= build_nir_vertex_shader(),
823 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
825 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
826 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
827 .module
= radv_shader_module_to_handle(&vs
),
829 .pSpecializationInfo
= NULL
831 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
832 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
833 .module
= radv_shader_module_to_handle(&fs
),
835 .pSpecializationInfo
= NULL
839 if (!device
->meta_state
.blit2d
.depth_only_rp
) {
840 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
841 &(VkRenderPassCreateInfo
) {
842 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
843 .attachmentCount
= 1,
844 .pAttachments
= &(VkAttachmentDescription
) {
845 .format
= VK_FORMAT_D32_SFLOAT
,
846 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
847 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
848 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
849 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
852 .pSubpasses
= &(VkSubpassDescription
) {
853 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
854 .inputAttachmentCount
= 0,
855 .colorAttachmentCount
= 0,
856 .pColorAttachments
= NULL
,
857 .pResolveAttachments
= NULL
,
858 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
860 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
862 .preserveAttachmentCount
= 1,
863 .pPreserveAttachments
= (uint32_t[]) { 0 },
865 .dependencyCount
= 0,
866 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.depth_only_rp
);
869 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
870 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
871 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
872 .pStages
= pipeline_shader_stages
,
873 .pVertexInputState
= vi_create_info
,
874 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
875 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
876 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
877 .primitiveRestartEnable
= false,
879 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
880 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
884 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
885 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
886 .rasterizerDiscardEnable
= false,
887 .polygonMode
= VK_POLYGON_MODE_FILL
,
888 .cullMode
= VK_CULL_MODE_NONE
,
889 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
891 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
892 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
893 .rasterizationSamples
= 1,
894 .sampleShadingEnable
= false,
895 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
897 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
898 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
899 .attachmentCount
= 0,
900 .pAttachments
= NULL
,
902 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
903 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
904 .depthTestEnable
= true,
905 .depthWriteEnable
= true,
906 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
908 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
909 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
910 .dynamicStateCount
= 9,
911 .pDynamicStates
= (VkDynamicState
[]) {
912 VK_DYNAMIC_STATE_VIEWPORT
,
913 VK_DYNAMIC_STATE_SCISSOR
,
914 VK_DYNAMIC_STATE_LINE_WIDTH
,
915 VK_DYNAMIC_STATE_DEPTH_BIAS
,
916 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
917 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
918 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
919 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
920 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
924 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
925 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
,
929 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
933 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
934 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
935 &vk_pipeline_info
, &radv_pipeline_info
,
936 &device
->meta_state
.alloc
,
937 &device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
]);
947 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
948 enum blit2d_src_type src_type
)
953 texel_fetch_build_func src_func
;
955 case BLIT2D_SRC_TYPE_IMAGE
:
956 src_func
= build_nir_texel_fetch
;
957 name
= "meta_blit2d_stencil_image_fs";
959 case BLIT2D_SRC_TYPE_BUFFER
:
960 src_func
= build_nir_buffer_fetch
;
961 name
= "meta_blit2d_stencil_buffer_fs";
964 unreachable("unknown blit src type\n");
968 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
969 struct radv_shader_module fs
= { .nir
= NULL
};
971 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
);
972 vi_create_info
= &normal_vi_create_info
;
974 struct radv_shader_module vs
= {
975 .nir
= build_nir_vertex_shader(),
978 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
980 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
981 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
982 .module
= radv_shader_module_to_handle(&vs
),
984 .pSpecializationInfo
= NULL
986 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
987 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
988 .module
= radv_shader_module_to_handle(&fs
),
990 .pSpecializationInfo
= NULL
994 if (!device
->meta_state
.blit2d
.stencil_only_rp
) {
995 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
996 &(VkRenderPassCreateInfo
) {
997 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
998 .attachmentCount
= 1,
999 .pAttachments
= &(VkAttachmentDescription
) {
1000 .format
= VK_FORMAT_S8_UINT
,
1001 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1002 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1003 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1004 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1007 .pSubpasses
= &(VkSubpassDescription
) {
1008 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1009 .inputAttachmentCount
= 0,
1010 .colorAttachmentCount
= 0,
1011 .pColorAttachments
= NULL
,
1012 .pResolveAttachments
= NULL
,
1013 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1015 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
1017 .preserveAttachmentCount
= 1,
1018 .pPreserveAttachments
= (uint32_t[]) { 0 },
1020 .dependencyCount
= 0,
1021 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.stencil_only_rp
);
1024 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1025 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1026 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1027 .pStages
= pipeline_shader_stages
,
1028 .pVertexInputState
= vi_create_info
,
1029 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1030 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1031 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1032 .primitiveRestartEnable
= false,
1034 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1035 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1039 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1040 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1041 .rasterizerDiscardEnable
= false,
1042 .polygonMode
= VK_POLYGON_MODE_FILL
,
1043 .cullMode
= VK_CULL_MODE_NONE
,
1044 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1046 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1047 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1048 .rasterizationSamples
= 1,
1049 .sampleShadingEnable
= false,
1050 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1052 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1053 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1054 .attachmentCount
= 0,
1055 .pAttachments
= NULL
,
1057 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1058 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1059 .depthTestEnable
= false,
1060 .depthWriteEnable
= false,
1061 .stencilTestEnable
= true,
1063 .failOp
= VK_STENCIL_OP_REPLACE
,
1064 .passOp
= VK_STENCIL_OP_REPLACE
,
1065 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1066 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1067 .compareMask
= 0xff,
1072 .failOp
= VK_STENCIL_OP_REPLACE
,
1073 .passOp
= VK_STENCIL_OP_REPLACE
,
1074 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1075 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1076 .compareMask
= 0xff,
1080 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1082 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1083 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1084 .dynamicStateCount
= 6,
1085 .pDynamicStates
= (VkDynamicState
[]) {
1086 VK_DYNAMIC_STATE_VIEWPORT
,
1087 VK_DYNAMIC_STATE_SCISSOR
,
1088 VK_DYNAMIC_STATE_LINE_WIDTH
,
1089 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1090 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1091 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1095 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
1096 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
,
1100 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1101 .use_rectlist
= true
1104 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1105 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1106 &vk_pipeline_info
, &radv_pipeline_info
,
1107 &device
->meta_state
.alloc
,
1108 &device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
]);
1111 ralloc_free(vs
.nir
);
1112 ralloc_free(fs
.nir
);
1117 static VkFormat pipeline_formats
[] = {
1118 VK_FORMAT_R8G8B8A8_UNORM
,
1119 VK_FORMAT_R8G8B8A8_UINT
,
1120 VK_FORMAT_R8G8B8A8_SINT
,
1121 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
1122 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
1123 VK_FORMAT_R16G16B16A16_UNORM
,
1124 VK_FORMAT_R16G16B16A16_SNORM
,
1125 VK_FORMAT_R16G16B16A16_UINT
,
1126 VK_FORMAT_R16G16B16A16_SINT
,
1127 VK_FORMAT_R32_SFLOAT
,
1128 VK_FORMAT_R32G32_SFLOAT
,
1129 VK_FORMAT_R32G32B32A32_SFLOAT
1133 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1137 zero(device
->meta_state
.blit2d
);
1139 const VkPushConstantRange push_constant_ranges
[] = {
1140 {VK_SHADER_STAGE_VERTEX_BIT
, 0, 16},
1141 {VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4},
1143 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1144 &(VkDescriptorSetLayoutCreateInfo
) {
1145 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1146 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1148 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1151 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
1152 .descriptorCount
= 1,
1153 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1154 .pImmutableSamplers
= NULL
1157 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1158 if (result
!= VK_SUCCESS
)
1161 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1162 &(VkPipelineLayoutCreateInfo
) {
1163 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1164 .setLayoutCount
= 1,
1165 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_IMAGE
],
1166 .pushConstantRangeCount
= 1,
1167 .pPushConstantRanges
= push_constant_ranges
,
1169 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_IMAGE
]);
1170 if (result
!= VK_SUCCESS
)
1173 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1174 &(VkDescriptorSetLayoutCreateInfo
) {
1175 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1176 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1178 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1181 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
1182 .descriptorCount
= 1,
1183 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1184 .pImmutableSamplers
= NULL
1187 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1188 if (result
!= VK_SUCCESS
)
1192 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1193 &(VkPipelineLayoutCreateInfo
) {
1194 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1195 .setLayoutCount
= 1,
1196 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[BLIT2D_SRC_TYPE_BUFFER
],
1197 .pushConstantRangeCount
= 2,
1198 .pPushConstantRanges
= push_constant_ranges
,
1200 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[BLIT2D_SRC_TYPE_BUFFER
]);
1201 if (result
!= VK_SUCCESS
)
1204 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1205 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1206 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
]);
1207 if (result
!= VK_SUCCESS
)
1211 result
= blit2d_init_depth_only_pipeline(device
, src
);
1212 if (result
!= VK_SUCCESS
)
1215 result
= blit2d_init_stencil_only_pipeline(device
, src
);
1216 if (result
!= VK_SUCCESS
)
1223 radv_device_finish_meta_blit2d_state(device
);