radv: drop emit2d_dst_type.
[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_src_type {
32 BLIT2D_SRC_TYPE_IMAGE,
33 BLIT2D_SRC_TYPE_BUFFER,
34 BLIT2D_NUM_SRC_TYPES,
35 };
36
37 static void
38 create_iview(struct radv_cmd_buffer *cmd_buffer,
39 struct radv_meta_blit2d_surf *surf,
40 struct radv_image_view *iview, VkFormat depth_format)
41 {
42 VkFormat format;
43
44 if (depth_format)
45 format = depth_format;
46 else
47 format = surf->format;
48
49 radv_image_view_init(iview, cmd_buffer->device,
50 &(VkImageViewCreateInfo) {
51 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
52 .image = radv_image_to_handle(surf->image),
53 .viewType = VK_IMAGE_VIEW_TYPE_2D,
54 .format = format,
55 .subresourceRange = {
56 .aspectMask = surf->aspect_mask,
57 .baseMipLevel = surf->level,
58 .levelCount = 1,
59 .baseArrayLayer = surf->layer,
60 .layerCount = 1
61 },
62 });
63 }
64
65 static void
66 create_bview(struct radv_cmd_buffer *cmd_buffer,
67 struct radv_meta_blit2d_buffer *src,
68 struct radv_buffer_view *bview, VkFormat depth_format)
69 {
70 VkFormat format;
71
72 if (depth_format)
73 format = depth_format;
74 else
75 format = src->format;
76 radv_buffer_view_init(bview, cmd_buffer->device,
77 &(VkBufferViewCreateInfo) {
78 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
79 .flags = 0,
80 .buffer = radv_buffer_to_handle(src->buffer),
81 .format = format,
82 .offset = src->offset,
83 .range = VK_WHOLE_SIZE,
84 }, cmd_buffer);
85
86 }
87
88 struct blit2d_src_temps {
89 struct radv_image_view iview;
90 struct radv_buffer_view bview;
91 };
92
93 static void
94 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
95 struct radv_meta_blit2d_surf *src_img,
96 struct radv_meta_blit2d_buffer *src_buf,
97 struct blit2d_src_temps *tmp,
98 enum blit2d_src_type src_type, VkFormat depth_format)
99 {
100 struct radv_device *device = cmd_buffer->device;
101
102 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
103 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
104
105 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
106 device->meta_state.blit2d.p_layouts[src_type],
107 0, /* set */
108 1, /* descriptorWriteCount */
109 (VkWriteDescriptorSet[]) {
110 {
111 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
112 .dstBinding = 0,
113 .dstArrayElement = 0,
114 .descriptorCount = 1,
115 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
116 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
117 }
118 });
119
120 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
121 device->meta_state.blit2d.p_layouts[src_type],
122 VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
123 &src_buf->pitch);
124 } else {
125 create_iview(cmd_buffer, src_img, &tmp->iview, depth_format);
126
127 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
128 device->meta_state.blit2d.p_layouts[src_type],
129 0, /* set */
130 1, /* descriptorWriteCount */
131 (VkWriteDescriptorSet[]) {
132 {
133 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
134 .dstBinding = 0,
135 .dstArrayElement = 0,
136 .descriptorCount = 1,
137 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
138 .pImageInfo = (VkDescriptorImageInfo[]) {
139 {
140 .sampler = VK_NULL_HANDLE,
141 .imageView = radv_image_view_to_handle(&tmp->iview),
142 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
143 },
144 }
145 }
146 });
147 }
148 }
149
150 struct blit2d_dst_temps {
151 VkImage image;
152 struct radv_image_view iview;
153 VkFramebuffer fb;
154 };
155
156 static void
157 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
158 struct radv_meta_blit2d_surf *dst,
159 uint32_t width,
160 uint32_t height,
161 VkFormat depth_format,
162 struct blit2d_dst_temps *tmp)
163 {
164 create_iview(cmd_buffer, dst, &tmp->iview, depth_format);
165
166 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
167 &(VkFramebufferCreateInfo) {
168 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
169 .attachmentCount = 1,
170 .pAttachments = (VkImageView[]) {
171 radv_image_view_to_handle(&tmp->iview),
172 },
173 .width = width,
174 .height = height,
175 .layers = 1
176 }, &cmd_buffer->pool->alloc, &tmp->fb);
177 }
178
179 static void
180 blit2d_unbind_dst(struct radv_cmd_buffer *cmd_buffer,
181 struct blit2d_dst_temps *tmp)
182 {
183 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
184 radv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
185 }
186
187 static void
188 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
189 enum blit2d_src_type src_type, unsigned fs_key)
190 {
191 VkPipeline pipeline =
192 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
193
194 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
195 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
196 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
197 }
198 }
199
200 static void
201 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
202 enum blit2d_src_type src_type)
203 {
204 VkPipeline pipeline =
205 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
206
207 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
208 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
209 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
210 }
211 }
212
213 static void
214 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
215 enum blit2d_src_type src_type)
216 {
217 VkPipeline pipeline =
218 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
219
220 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
221 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
222 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
223 }
224 }
225
226 static void
227 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
228 struct radv_meta_blit2d_surf *src_img,
229 struct radv_meta_blit2d_buffer *src_buf,
230 struct radv_meta_blit2d_surf *dst,
231 unsigned num_rects,
232 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
233 {
234 struct radv_device *device = cmd_buffer->device;
235
236 for (unsigned r = 0; r < num_rects; ++r) {
237 VkFormat depth_format = 0;
238 if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
239 depth_format = vk_format_stencil_only(dst->image->vk_format);
240 else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
241 depth_format = vk_format_depth_only(dst->image->vk_format);
242 struct blit2d_src_temps src_temps;
243 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format);
244
245 struct blit2d_dst_temps dst_temps;
246 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
247 rects[r].dst_y + rects[r].height, depth_format, &dst_temps);
248
249 float vertex_push_constants[4] = {
250 rects[r].src_x,
251 rects[r].src_y,
252 rects[r].src_x + rects[r].width,
253 rects[r].src_y + rects[r].height,
254 };
255
256 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
257 device->meta_state.blit2d.p_layouts[src_type],
258 VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
259 vertex_push_constants);
260
261 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
262 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
263
264 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
265 &(VkRenderPassBeginInfo) {
266 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
267 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
268 .framebuffer = dst_temps.fb,
269 .renderArea = {
270 .offset = { rects[r].dst_x, rects[r].dst_y, },
271 .extent = { rects[r].width, rects[r].height },
272 },
273 .clearValueCount = 0,
274 .pClearValues = NULL,
275 }, VK_SUBPASS_CONTENTS_INLINE);
276
277
278 bind_pipeline(cmd_buffer, src_type, fs_key);
279 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
280 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
281 &(VkRenderPassBeginInfo) {
282 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
283 .renderPass = device->meta_state.blit2d.depth_only_rp,
284 .framebuffer = dst_temps.fb,
285 .renderArea = {
286 .offset = { rects[r].dst_x, rects[r].dst_y, },
287 .extent = { rects[r].width, rects[r].height },
288 },
289 .clearValueCount = 0,
290 .pClearValues = NULL,
291 }, VK_SUBPASS_CONTENTS_INLINE);
292
293
294 bind_depth_pipeline(cmd_buffer, src_type);
295
296 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
297 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
298 &(VkRenderPassBeginInfo) {
299 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
300 .renderPass = device->meta_state.blit2d.stencil_only_rp,
301 .framebuffer = dst_temps.fb,
302 .renderArea = {
303 .offset = { rects[r].dst_x, rects[r].dst_y, },
304 .extent = { rects[r].width, rects[r].height },
305 },
306 .clearValueCount = 0,
307 .pClearValues = NULL,
308 }, VK_SUBPASS_CONTENTS_INLINE);
309
310
311 bind_stencil_pipeline(cmd_buffer, src_type);
312 }
313
314 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
315 .x = rects[r].dst_x,
316 .y = rects[r].dst_y,
317 .width = rects[r].width,
318 .height = rects[r].height,
319 .minDepth = 0.0f,
320 .maxDepth = 1.0f
321 });
322
323 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
324 .offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
325 .extent = (VkExtent2D) { rects[r].width, rects[r].height },
326 });
327
328
329
330 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
331 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
332
333 /* At the point where we emit the draw call, all data from the
334 * descriptor sets, etc. has been used. We are free to delete it.
335 */
336 blit2d_unbind_dst(cmd_buffer, &dst_temps);
337 }
338 }
339
340 void
341 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
342 struct radv_meta_blit2d_surf *src_img,
343 struct radv_meta_blit2d_buffer *src_buf,
344 struct radv_meta_blit2d_surf *dst,
345 unsigned num_rects,
346 struct radv_meta_blit2d_rect *rects)
347 {
348 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
349 BLIT2D_SRC_TYPE_IMAGE;
350 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
351 num_rects, rects, src_type);
352 }
353
354 static nir_shader *
355 build_nir_vertex_shader(void)
356 {
357 const struct glsl_type *vec4 = glsl_vec4_type();
358 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
359 nir_builder b;
360
361 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
362 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_vs");
363
364 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
365 vec4, "gl_Position");
366 pos_out->data.location = VARYING_SLOT_POS;
367
368 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
369 vec2, "v_tex_pos");
370 tex_pos_out->data.location = VARYING_SLOT_VAR0;
371 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
372
373 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
374 nir_store_var(&b, pos_out, outvec, 0xf);
375
376 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
377 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
378 nir_intrinsic_set_base(src_box, 0);
379 nir_intrinsic_set_range(src_box, 16);
380 src_box->num_components = 4;
381 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
382 nir_builder_instr_insert(&b, &src_box->instr);
383
384 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
385 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
386 nir_builder_instr_insert(&b, &vertex_id->instr);
387
388 /* vertex 0 - src_x, src_y */
389 /* vertex 1 - src_x, src_y+h */
390 /* vertex 2 - src_x+w, src_y */
391 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
392 channel 1 is vertex id != 1 ? src_y : src_y + w */
393
394 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
395 nir_imm_int(&b, 2));
396 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
397 nir_imm_int(&b, 1));
398
399 nir_ssa_def *comp[2];
400 comp[0] = nir_bcsel(&b, c0cmp,
401 nir_channel(&b, &src_box->dest.ssa, 0),
402 nir_channel(&b, &src_box->dest.ssa, 2));
403
404 comp[1] = nir_bcsel(&b, c1cmp,
405 nir_channel(&b, &src_box->dest.ssa, 1),
406 nir_channel(&b, &src_box->dest.ssa, 3));
407 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
408 nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
409 return b.shader;
410 }
411
412 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
413 struct radv_device *,
414 nir_ssa_def *);
415
416 static nir_ssa_def *
417 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
418 nir_ssa_def *tex_pos)
419 {
420 const struct glsl_type *sampler_type =
421 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
422 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
423 sampler_type, "s_tex");
424 sampler->data.descriptor_set = 0;
425 sampler->data.binding = 0;
426
427 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
428 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
429 tex->op = nir_texop_txf;
430 tex->src[0].src_type = nir_tex_src_coord;
431 tex->src[0].src = nir_src_for_ssa(tex_pos);
432 tex->src[1].src_type = nir_tex_src_lod;
433 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
434 tex->dest_type = nir_type_uint;
435 tex->is_array = false;
436 tex->coord_components = 2;
437 tex->texture = nir_deref_var_create(tex, sampler);
438 tex->sampler = NULL;
439
440 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
441 nir_builder_instr_insert(b, &tex->instr);
442
443 return &tex->dest.ssa;
444 }
445
446
447 static nir_ssa_def *
448 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
449 nir_ssa_def *tex_pos)
450 {
451 const struct glsl_type *sampler_type =
452 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
453 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
454 sampler_type, "s_tex");
455 sampler->data.descriptor_set = 0;
456 sampler->data.binding = 0;
457
458 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
459 nir_intrinsic_set_base(width, 16);
460 nir_intrinsic_set_range(width, 4);
461 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
462 width->num_components = 1;
463 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
464 nir_builder_instr_insert(b, &width->instr);
465
466 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
467 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
468 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
469 pos_x = nir_iadd(b, pos_x, pos_y);
470 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
471
472 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
473 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
474 tex->op = nir_texop_txf;
475 tex->src[0].src_type = nir_tex_src_coord;
476 tex->src[0].src = nir_src_for_ssa(pos_x);
477 tex->dest_type = nir_type_uint;
478 tex->is_array = false;
479 tex->coord_components = 1;
480 tex->texture = nir_deref_var_create(tex, sampler);
481 tex->sampler = NULL;
482
483 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
484 nir_builder_instr_insert(b, &tex->instr);
485
486 return &tex->dest.ssa;
487 }
488
489 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
490 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
491 .vertexBindingDescriptionCount = 0,
492 .vertexAttributeDescriptionCount = 0,
493 };
494
495 static nir_shader *
496 build_nir_copy_fragment_shader(struct radv_device *device,
497 texel_fetch_build_func txf_func, const char* name)
498 {
499 const struct glsl_type *vec4 = glsl_vec4_type();
500 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
501 nir_builder b;
502
503 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
504 b.shader->info.name = ralloc_strdup(b.shader, name);
505
506 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
507 vec2, "v_tex_pos");
508 tex_pos_in->data.location = VARYING_SLOT_VAR0;
509
510 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
511 vec4, "f_color");
512 color_out->data.location = FRAG_RESULT_DATA0;
513
514 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
515 unsigned swiz[4] = { 0, 1 };
516 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
517
518 nir_ssa_def *color = txf_func(&b, device, tex_pos);
519 nir_store_var(&b, color_out, color, 0xf);
520
521 return b.shader;
522 }
523
524 static nir_shader *
525 build_nir_copy_fragment_shader_depth(struct radv_device *device,
526 texel_fetch_build_func txf_func, const char* name)
527 {
528 const struct glsl_type *vec4 = glsl_vec4_type();
529 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
530 nir_builder b;
531
532 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
533 b.shader->info.name = ralloc_strdup(b.shader, name);
534
535 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
536 vec2, "v_tex_pos");
537 tex_pos_in->data.location = VARYING_SLOT_VAR0;
538
539 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
540 vec4, "f_color");
541 color_out->data.location = FRAG_RESULT_DEPTH;
542
543 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
544 unsigned swiz[4] = { 0, 1 };
545 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
546
547 nir_ssa_def *color = txf_func(&b, device, tex_pos);
548 nir_store_var(&b, color_out, color, 0x1);
549
550 return b.shader;
551 }
552
553 static nir_shader *
554 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
555 texel_fetch_build_func txf_func, const char* name)
556 {
557 const struct glsl_type *vec4 = glsl_vec4_type();
558 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
559 nir_builder b;
560
561 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
562 b.shader->info.name = ralloc_strdup(b.shader, name);
563
564 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
565 vec2, "v_tex_pos");
566 tex_pos_in->data.location = VARYING_SLOT_VAR0;
567
568 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
569 vec4, "f_color");
570 color_out->data.location = FRAG_RESULT_STENCIL;
571
572 nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
573 unsigned swiz[4] = { 0, 1 };
574 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
575
576 nir_ssa_def *color = txf_func(&b, device, tex_pos);
577 nir_store_var(&b, color_out, color, 0x1);
578
579 return b.shader;
580 }
581
582 void
583 radv_device_finish_meta_blit2d_state(struct radv_device *device)
584 {
585 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
586 if (device->meta_state.blit2d.render_passes[j]) {
587 radv_DestroyRenderPass(radv_device_to_handle(device),
588 device->meta_state.blit2d.render_passes[j],
589 &device->meta_state.alloc);
590 }
591 }
592
593 radv_DestroyRenderPass(radv_device_to_handle(device),
594 device->meta_state.blit2d.depth_only_rp,
595 &device->meta_state.alloc);
596 radv_DestroyRenderPass(radv_device_to_handle(device),
597 device->meta_state.blit2d.stencil_only_rp,
598 &device->meta_state.alloc);
599
600 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
601 if (device->meta_state.blit2d.p_layouts[src]) {
602 radv_DestroyPipelineLayout(radv_device_to_handle(device),
603 device->meta_state.blit2d.p_layouts[src],
604 &device->meta_state.alloc);
605 }
606
607 if (device->meta_state.blit2d.ds_layouts[src]) {
608 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
609 device->meta_state.blit2d.ds_layouts[src],
610 &device->meta_state.alloc);
611 }
612
613 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
614 if (device->meta_state.blit2d.pipelines[src][j]) {
615 radv_DestroyPipeline(radv_device_to_handle(device),
616 device->meta_state.blit2d.pipelines[src][j],
617 &device->meta_state.alloc);
618 }
619 }
620
621 radv_DestroyPipeline(radv_device_to_handle(device),
622 device->meta_state.blit2d.depth_only_pipeline[src],
623 &device->meta_state.alloc);
624 radv_DestroyPipeline(radv_device_to_handle(device),
625 device->meta_state.blit2d.stencil_only_pipeline[src],
626 &device->meta_state.alloc);
627 }
628 }
629
630 static VkResult
631 blit2d_init_color_pipeline(struct radv_device *device,
632 enum blit2d_src_type src_type,
633 VkFormat format)
634 {
635 VkResult result;
636 unsigned fs_key = radv_format_meta_fs_key(format);
637 const char *name;
638
639 texel_fetch_build_func src_func;
640 switch(src_type) {
641 case BLIT2D_SRC_TYPE_IMAGE:
642 src_func = build_nir_texel_fetch;
643 name = "meta_blit2d_image_fs";
644 break;
645 case BLIT2D_SRC_TYPE_BUFFER:
646 src_func = build_nir_buffer_fetch;
647 name = "meta_blit2d_buffer_fs";
648 break;
649 default:
650 unreachable("unknown blit src type\n");
651 break;
652 }
653
654 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
655 struct radv_shader_module fs = { .nir = NULL };
656
657
658 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
659 vi_create_info = &normal_vi_create_info;
660
661 struct radv_shader_module vs = {
662 .nir = build_nir_vertex_shader(),
663 };
664
665 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
666 {
667 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
668 .stage = VK_SHADER_STAGE_VERTEX_BIT,
669 .module = radv_shader_module_to_handle(&vs),
670 .pName = "main",
671 .pSpecializationInfo = NULL
672 }, {
673 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
674 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
675 .module = radv_shader_module_to_handle(&fs),
676 .pName = "main",
677 .pSpecializationInfo = NULL
678 },
679 };
680
681 if (!device->meta_state.blit2d.render_passes[fs_key]) {
682 result = radv_CreateRenderPass(radv_device_to_handle(device),
683 &(VkRenderPassCreateInfo) {
684 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
685 .attachmentCount = 1,
686 .pAttachments = &(VkAttachmentDescription) {
687 .format = format,
688 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
689 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
690 .initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
691 .finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
692 },
693 .subpassCount = 1,
694 .pSubpasses = &(VkSubpassDescription) {
695 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
696 .inputAttachmentCount = 0,
697 .colorAttachmentCount = 1,
698 .pColorAttachments = &(VkAttachmentReference) {
699 .attachment = 0,
700 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
701 },
702 .pResolveAttachments = NULL,
703 .pDepthStencilAttachment = &(VkAttachmentReference) {
704 .attachment = VK_ATTACHMENT_UNUSED,
705 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
706 },
707 .preserveAttachmentCount = 1,
708 .pPreserveAttachments = (uint32_t[]) { 0 },
709 },
710 .dependencyCount = 0,
711 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
712 }
713
714 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
715 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
716 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
717 .pStages = pipeline_shader_stages,
718 .pVertexInputState = vi_create_info,
719 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
720 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
721 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
722 .primitiveRestartEnable = false,
723 },
724 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
725 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
726 .viewportCount = 1,
727 .scissorCount = 1,
728 },
729 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
730 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
731 .rasterizerDiscardEnable = false,
732 .polygonMode = VK_POLYGON_MODE_FILL,
733 .cullMode = VK_CULL_MODE_NONE,
734 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
735 },
736 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
737 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
738 .rasterizationSamples = 1,
739 .sampleShadingEnable = false,
740 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
741 },
742 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
743 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
744 .attachmentCount = 1,
745 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
746 { .colorWriteMask =
747 VK_COLOR_COMPONENT_A_BIT |
748 VK_COLOR_COMPONENT_R_BIT |
749 VK_COLOR_COMPONENT_G_BIT |
750 VK_COLOR_COMPONENT_B_BIT },
751 }
752 },
753 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
754 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
755 .dynamicStateCount = 9,
756 .pDynamicStates = (VkDynamicState[]) {
757 VK_DYNAMIC_STATE_VIEWPORT,
758 VK_DYNAMIC_STATE_SCISSOR,
759 VK_DYNAMIC_STATE_LINE_WIDTH,
760 VK_DYNAMIC_STATE_DEPTH_BIAS,
761 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
762 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
763 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
764 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
765 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
766 },
767 },
768 .flags = 0,
769 .layout = device->meta_state.blit2d.p_layouts[src_type],
770 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
771 .subpass = 0,
772 };
773
774 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
775 .use_rectlist = true
776 };
777
778 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
779 radv_pipeline_cache_to_handle(&device->meta_state.cache),
780 &vk_pipeline_info, &radv_pipeline_info,
781 &device->meta_state.alloc,
782 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
783
784
785 ralloc_free(vs.nir);
786 ralloc_free(fs.nir);
787
788 return result;
789 }
790
791 static VkResult
792 blit2d_init_depth_only_pipeline(struct radv_device *device,
793 enum blit2d_src_type src_type)
794 {
795 VkResult result;
796 const char *name;
797
798 texel_fetch_build_func src_func;
799 switch(src_type) {
800 case BLIT2D_SRC_TYPE_IMAGE:
801 src_func = build_nir_texel_fetch;
802 name = "meta_blit2d_depth_image_fs";
803 break;
804 case BLIT2D_SRC_TYPE_BUFFER:
805 src_func = build_nir_buffer_fetch;
806 name = "meta_blit2d_depth_buffer_fs";
807 break;
808 default:
809 unreachable("unknown blit src type\n");
810 break;
811 }
812
813 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
814 struct radv_shader_module fs = { .nir = NULL };
815
816 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
817 vi_create_info = &normal_vi_create_info;
818
819 struct radv_shader_module vs = {
820 .nir = build_nir_vertex_shader(),
821 };
822
823 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
824 {
825 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
826 .stage = VK_SHADER_STAGE_VERTEX_BIT,
827 .module = radv_shader_module_to_handle(&vs),
828 .pName = "main",
829 .pSpecializationInfo = NULL
830 }, {
831 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
832 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
833 .module = radv_shader_module_to_handle(&fs),
834 .pName = "main",
835 .pSpecializationInfo = NULL
836 },
837 };
838
839 if (!device->meta_state.blit2d.depth_only_rp) {
840 result = radv_CreateRenderPass(radv_device_to_handle(device),
841 &(VkRenderPassCreateInfo) {
842 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
843 .attachmentCount = 1,
844 .pAttachments = &(VkAttachmentDescription) {
845 .format = VK_FORMAT_D32_SFLOAT,
846 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
847 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
848 .initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
849 .finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
850 },
851 .subpassCount = 1,
852 .pSubpasses = &(VkSubpassDescription) {
853 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
854 .inputAttachmentCount = 0,
855 .colorAttachmentCount = 0,
856 .pColorAttachments = NULL,
857 .pResolveAttachments = NULL,
858 .pDepthStencilAttachment = &(VkAttachmentReference) {
859 .attachment = 0,
860 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
861 },
862 .preserveAttachmentCount = 1,
863 .pPreserveAttachments = (uint32_t[]) { 0 },
864 },
865 .dependencyCount = 0,
866 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
867 }
868
869 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
870 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
871 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
872 .pStages = pipeline_shader_stages,
873 .pVertexInputState = vi_create_info,
874 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
875 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
876 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
877 .primitiveRestartEnable = false,
878 },
879 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
880 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
881 .viewportCount = 1,
882 .scissorCount = 1,
883 },
884 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
885 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
886 .rasterizerDiscardEnable = false,
887 .polygonMode = VK_POLYGON_MODE_FILL,
888 .cullMode = VK_CULL_MODE_NONE,
889 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
890 },
891 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
892 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
893 .rasterizationSamples = 1,
894 .sampleShadingEnable = false,
895 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
896 },
897 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
898 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
899 .attachmentCount = 0,
900 .pAttachments = NULL,
901 },
902 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
903 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
904 .depthTestEnable = true,
905 .depthWriteEnable = true,
906 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
907 },
908 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
909 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
910 .dynamicStateCount = 9,
911 .pDynamicStates = (VkDynamicState[]) {
912 VK_DYNAMIC_STATE_VIEWPORT,
913 VK_DYNAMIC_STATE_SCISSOR,
914 VK_DYNAMIC_STATE_LINE_WIDTH,
915 VK_DYNAMIC_STATE_DEPTH_BIAS,
916 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
917 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
918 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
919 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
920 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
921 },
922 },
923 .flags = 0,
924 .layout = device->meta_state.blit2d.p_layouts[src_type],
925 .renderPass = device->meta_state.blit2d.depth_only_rp,
926 .subpass = 0,
927 };
928
929 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
930 .use_rectlist = true
931 };
932
933 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
934 radv_pipeline_cache_to_handle(&device->meta_state.cache),
935 &vk_pipeline_info, &radv_pipeline_info,
936 &device->meta_state.alloc,
937 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
938
939
940 ralloc_free(vs.nir);
941 ralloc_free(fs.nir);
942
943 return result;
944 }
945
946 static VkResult
947 blit2d_init_stencil_only_pipeline(struct radv_device *device,
948 enum blit2d_src_type src_type)
949 {
950 VkResult result;
951 const char *name;
952
953 texel_fetch_build_func src_func;
954 switch(src_type) {
955 case BLIT2D_SRC_TYPE_IMAGE:
956 src_func = build_nir_texel_fetch;
957 name = "meta_blit2d_stencil_image_fs";
958 break;
959 case BLIT2D_SRC_TYPE_BUFFER:
960 src_func = build_nir_buffer_fetch;
961 name = "meta_blit2d_stencil_buffer_fs";
962 break;
963 default:
964 unreachable("unknown blit src type\n");
965 break;
966 }
967
968 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
969 struct radv_shader_module fs = { .nir = NULL };
970
971 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
972 vi_create_info = &normal_vi_create_info;
973
974 struct radv_shader_module vs = {
975 .nir = build_nir_vertex_shader(),
976 };
977
978 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
979 {
980 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
981 .stage = VK_SHADER_STAGE_VERTEX_BIT,
982 .module = radv_shader_module_to_handle(&vs),
983 .pName = "main",
984 .pSpecializationInfo = NULL
985 }, {
986 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
987 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
988 .module = radv_shader_module_to_handle(&fs),
989 .pName = "main",
990 .pSpecializationInfo = NULL
991 },
992 };
993
994 if (!device->meta_state.blit2d.stencil_only_rp) {
995 result = radv_CreateRenderPass(radv_device_to_handle(device),
996 &(VkRenderPassCreateInfo) {
997 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
998 .attachmentCount = 1,
999 .pAttachments = &(VkAttachmentDescription) {
1000 .format = VK_FORMAT_S8_UINT,
1001 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1002 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1003 .initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
1004 .finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
1005 },
1006 .subpassCount = 1,
1007 .pSubpasses = &(VkSubpassDescription) {
1008 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1009 .inputAttachmentCount = 0,
1010 .colorAttachmentCount = 0,
1011 .pColorAttachments = NULL,
1012 .pResolveAttachments = NULL,
1013 .pDepthStencilAttachment = &(VkAttachmentReference) {
1014 .attachment = 0,
1015 .layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
1016 },
1017 .preserveAttachmentCount = 1,
1018 .pPreserveAttachments = (uint32_t[]) { 0 },
1019 },
1020 .dependencyCount = 0,
1021 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1022 }
1023
1024 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1025 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1026 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1027 .pStages = pipeline_shader_stages,
1028 .pVertexInputState = vi_create_info,
1029 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1030 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1031 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1032 .primitiveRestartEnable = false,
1033 },
1034 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1035 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1036 .viewportCount = 1,
1037 .scissorCount = 1,
1038 },
1039 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1040 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1041 .rasterizerDiscardEnable = false,
1042 .polygonMode = VK_POLYGON_MODE_FILL,
1043 .cullMode = VK_CULL_MODE_NONE,
1044 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1045 },
1046 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1047 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1048 .rasterizationSamples = 1,
1049 .sampleShadingEnable = false,
1050 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1051 },
1052 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1053 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1054 .attachmentCount = 0,
1055 .pAttachments = NULL,
1056 },
1057 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1058 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1059 .depthTestEnable = false,
1060 .depthWriteEnable = false,
1061 .stencilTestEnable = true,
1062 .front = {
1063 .failOp = VK_STENCIL_OP_REPLACE,
1064 .passOp = VK_STENCIL_OP_REPLACE,
1065 .depthFailOp = VK_STENCIL_OP_REPLACE,
1066 .compareOp = VK_COMPARE_OP_ALWAYS,
1067 .compareMask = 0xff,
1068 .writeMask = 0xff,
1069 .reference = 0
1070 },
1071 .back = {
1072 .failOp = VK_STENCIL_OP_REPLACE,
1073 .passOp = VK_STENCIL_OP_REPLACE,
1074 .depthFailOp = VK_STENCIL_OP_REPLACE,
1075 .compareOp = VK_COMPARE_OP_ALWAYS,
1076 .compareMask = 0xff,
1077 .writeMask = 0xff,
1078 .reference = 0
1079 },
1080 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1081 },
1082 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1083 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1084 .dynamicStateCount = 6,
1085 .pDynamicStates = (VkDynamicState[]) {
1086 VK_DYNAMIC_STATE_VIEWPORT,
1087 VK_DYNAMIC_STATE_SCISSOR,
1088 VK_DYNAMIC_STATE_LINE_WIDTH,
1089 VK_DYNAMIC_STATE_DEPTH_BIAS,
1090 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1091 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1092 },
1093 },
1094 .flags = 0,
1095 .layout = device->meta_state.blit2d.p_layouts[src_type],
1096 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1097 .subpass = 0,
1098 };
1099
1100 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1101 .use_rectlist = true
1102 };
1103
1104 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1105 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1106 &vk_pipeline_info, &radv_pipeline_info,
1107 &device->meta_state.alloc,
1108 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1109
1110
1111 ralloc_free(vs.nir);
1112 ralloc_free(fs.nir);
1113
1114 return result;
1115 }
1116
1117 static VkFormat pipeline_formats[] = {
1118 VK_FORMAT_R8G8B8A8_UNORM,
1119 VK_FORMAT_R8G8B8A8_UINT,
1120 VK_FORMAT_R8G8B8A8_SINT,
1121 VK_FORMAT_A2R10G10B10_UINT_PACK32,
1122 VK_FORMAT_A2R10G10B10_SINT_PACK32,
1123 VK_FORMAT_R16G16B16A16_UNORM,
1124 VK_FORMAT_R16G16B16A16_SNORM,
1125 VK_FORMAT_R16G16B16A16_UINT,
1126 VK_FORMAT_R16G16B16A16_SINT,
1127 VK_FORMAT_R32_SFLOAT,
1128 VK_FORMAT_R32G32_SFLOAT,
1129 VK_FORMAT_R32G32B32A32_SFLOAT
1130 };
1131
1132 VkResult
1133 radv_device_init_meta_blit2d_state(struct radv_device *device)
1134 {
1135 VkResult result;
1136
1137 zero(device->meta_state.blit2d);
1138
1139 const VkPushConstantRange push_constant_ranges[] = {
1140 {VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
1141 {VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4},
1142 };
1143 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1144 &(VkDescriptorSetLayoutCreateInfo) {
1145 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1146 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1147 .bindingCount = 1,
1148 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1149 {
1150 .binding = 0,
1151 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1152 .descriptorCount = 1,
1153 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1154 .pImmutableSamplers = NULL
1155 },
1156 }
1157 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1158 if (result != VK_SUCCESS)
1159 goto fail;
1160
1161 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1162 &(VkPipelineLayoutCreateInfo) {
1163 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1164 .setLayoutCount = 1,
1165 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1166 .pushConstantRangeCount = 1,
1167 .pPushConstantRanges = push_constant_ranges,
1168 },
1169 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1170 if (result != VK_SUCCESS)
1171 goto fail;
1172
1173 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1174 &(VkDescriptorSetLayoutCreateInfo) {
1175 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1176 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1177 .bindingCount = 1,
1178 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1179 {
1180 .binding = 0,
1181 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1182 .descriptorCount = 1,
1183 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1184 .pImmutableSamplers = NULL
1185 },
1186 }
1187 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1188 if (result != VK_SUCCESS)
1189 goto fail;
1190
1191
1192 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1193 &(VkPipelineLayoutCreateInfo) {
1194 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1195 .setLayoutCount = 1,
1196 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1197 .pushConstantRangeCount = 2,
1198 .pPushConstantRanges = push_constant_ranges,
1199 },
1200 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1201 if (result != VK_SUCCESS)
1202 goto fail;
1203
1204 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1205 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1206 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1207 if (result != VK_SUCCESS)
1208 goto fail;
1209 }
1210
1211 result = blit2d_init_depth_only_pipeline(device, src);
1212 if (result != VK_SUCCESS)
1213 goto fail;
1214
1215 result = blit2d_init_stencil_only_pipeline(device, src);
1216 if (result != VK_SUCCESS)
1217 goto fail;
1218 }
1219
1220 return VK_SUCCESS;
1221
1222 fail:
1223 radv_device_finish_meta_blit2d_state(device);
1224 return result;
1225 }