2 * Copyright © 2016 Red Hat
5 * Copyright © 2016 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
31 enum blit2d_src_type
{
32 BLIT2D_SRC_TYPE_IMAGE
,
33 BLIT2D_SRC_TYPE_IMAGE_3D
,
34 BLIT2D_SRC_TYPE_BUFFER
,
39 create_iview(struct radv_cmd_buffer
*cmd_buffer
,
40 struct radv_meta_blit2d_surf
*surf
,
41 struct radv_image_view
*iview
, VkFormat depth_format
,
42 VkImageAspectFlagBits aspects
)
45 VkImageViewType view_type
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX9
? VK_IMAGE_VIEW_TYPE_2D
:
46 radv_meta_get_view_type(surf
->image
);
49 format
= depth_format
;
51 format
= surf
->format
;
53 radv_image_view_init(iview
, cmd_buffer
->device
,
54 &(VkImageViewCreateInfo
) {
55 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
56 .image
= radv_image_to_handle(surf
->image
),
57 .viewType
= view_type
,
60 .aspectMask
= aspects
,
61 .baseMipLevel
= surf
->level
,
63 .baseArrayLayer
= surf
->layer
,
70 create_bview(struct radv_cmd_buffer
*cmd_buffer
,
71 struct radv_meta_blit2d_buffer
*src
,
72 struct radv_buffer_view
*bview
, VkFormat depth_format
)
77 format
= depth_format
;
80 radv_buffer_view_init(bview
, cmd_buffer
->device
,
81 &(VkBufferViewCreateInfo
) {
82 .sType
= VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO
,
84 .buffer
= radv_buffer_to_handle(src
->buffer
),
86 .offset
= src
->offset
,
87 .range
= VK_WHOLE_SIZE
,
92 struct blit2d_src_temps
{
93 struct radv_image_view iview
;
94 struct radv_buffer_view bview
;
98 blit2d_bind_src(struct radv_cmd_buffer
*cmd_buffer
,
99 struct radv_meta_blit2d_surf
*src_img
,
100 struct radv_meta_blit2d_buffer
*src_buf
,
101 struct blit2d_src_temps
*tmp
,
102 enum blit2d_src_type src_type
, VkFormat depth_format
,
103 VkImageAspectFlagBits aspects
)
105 struct radv_device
*device
= cmd_buffer
->device
;
107 if (src_type
== BLIT2D_SRC_TYPE_BUFFER
) {
108 create_bview(cmd_buffer
, src_buf
, &tmp
->bview
, depth_format
);
110 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
111 device
->meta_state
.blit2d
.p_layouts
[src_type
],
113 1, /* descriptorWriteCount */
114 (VkWriteDescriptorSet
[]) {
116 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
118 .dstArrayElement
= 0,
119 .descriptorCount
= 1,
120 .descriptorType
= VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
,
121 .pTexelBufferView
= (VkBufferView
[]) { radv_buffer_view_to_handle(&tmp
->bview
) }
125 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
126 device
->meta_state
.blit2d
.p_layouts
[src_type
],
127 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
130 create_iview(cmd_buffer
, src_img
, &tmp
->iview
, depth_format
, aspects
);
132 if (src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
)
133 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
134 device
->meta_state
.blit2d
.p_layouts
[src_type
],
135 VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4,
138 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
139 device
->meta_state
.blit2d
.p_layouts
[src_type
],
141 1, /* descriptorWriteCount */
142 (VkWriteDescriptorSet
[]) {
144 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
146 .dstArrayElement
= 0,
147 .descriptorCount
= 1,
148 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
149 .pImageInfo
= (VkDescriptorImageInfo
[]) {
151 .sampler
= VK_NULL_HANDLE
,
152 .imageView
= radv_image_view_to_handle(&tmp
->iview
),
153 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
161 struct blit2d_dst_temps
{
163 struct radv_image_view iview
;
168 blit2d_bind_dst(struct radv_cmd_buffer
*cmd_buffer
,
169 struct radv_meta_blit2d_surf
*dst
,
172 VkFormat depth_format
,
173 struct blit2d_dst_temps
*tmp
,
174 VkImageAspectFlagBits aspects
)
176 create_iview(cmd_buffer
, dst
, &tmp
->iview
, depth_format
, aspects
);
178 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer
->device
),
179 &(VkFramebufferCreateInfo
) {
180 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
181 .attachmentCount
= 1,
182 .pAttachments
= (VkImageView
[]) {
183 radv_image_view_to_handle(&tmp
->iview
),
188 }, &cmd_buffer
->pool
->alloc
, &tmp
->fb
);
192 bind_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
193 enum blit2d_src_type src_type
, unsigned fs_key
)
195 VkPipeline pipeline
=
196 cmd_buffer
->device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
];
198 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
199 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
203 bind_depth_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
204 enum blit2d_src_type src_type
)
206 VkPipeline pipeline
=
207 cmd_buffer
->device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
];
209 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
210 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
214 bind_stencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
215 enum blit2d_src_type src_type
)
217 VkPipeline pipeline
=
218 cmd_buffer
->device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
];
220 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
221 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
225 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer
*cmd_buffer
,
226 struct radv_meta_blit2d_surf
*src_img
,
227 struct radv_meta_blit2d_buffer
*src_buf
,
228 struct radv_meta_blit2d_surf
*dst
,
230 struct radv_meta_blit2d_rect
*rects
, enum blit2d_src_type src_type
)
232 struct radv_device
*device
= cmd_buffer
->device
;
234 for (unsigned r
= 0; r
< num_rects
; ++r
) {
236 for_each_bit(i
, dst
->aspect_mask
) {
237 unsigned aspect_mask
= 1u << i
;
238 VkFormat depth_format
= 0;
239 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
240 depth_format
= vk_format_stencil_only(dst
->image
->vk_format
);
241 else if (aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
)
242 depth_format
= vk_format_depth_only(dst
->image
->vk_format
);
243 struct blit2d_src_temps src_temps
;
244 blit2d_bind_src(cmd_buffer
, src_img
, src_buf
, &src_temps
, src_type
, depth_format
, aspect_mask
);
246 struct blit2d_dst_temps dst_temps
;
247 blit2d_bind_dst(cmd_buffer
, dst
, rects
[r
].dst_x
+ rects
[r
].width
,
248 rects
[r
].dst_y
+ rects
[r
].height
, depth_format
, &dst_temps
, aspect_mask
);
250 float vertex_push_constants
[4] = {
253 rects
[r
].src_x
+ rects
[r
].width
,
254 rects
[r
].src_y
+ rects
[r
].height
,
257 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
258 device
->meta_state
.blit2d
.p_layouts
[src_type
],
259 VK_SHADER_STAGE_VERTEX_BIT
, 0, 16,
260 vertex_push_constants
);
262 if (aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
263 unsigned fs_key
= radv_format_meta_fs_key(dst_temps
.iview
.vk_format
);
265 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
266 &(VkRenderPassBeginInfo
) {
267 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
268 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
269 .framebuffer
= dst_temps
.fb
,
271 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
272 .extent
= { rects
[r
].width
, rects
[r
].height
},
274 .clearValueCount
= 0,
275 .pClearValues
= NULL
,
276 }, VK_SUBPASS_CONTENTS_INLINE
);
279 bind_pipeline(cmd_buffer
, src_type
, fs_key
);
280 } else if (aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
281 enum radv_blit_ds_layout ds_layout
= radv_meta_blit_ds_to_type(dst
->current_layout
);
282 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
283 &(VkRenderPassBeginInfo
) {
284 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
285 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
[ds_layout
],
286 .framebuffer
= dst_temps
.fb
,
288 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
289 .extent
= { rects
[r
].width
, rects
[r
].height
},
291 .clearValueCount
= 0,
292 .pClearValues
= NULL
,
293 }, VK_SUBPASS_CONTENTS_INLINE
);
296 bind_depth_pipeline(cmd_buffer
, src_type
);
298 } else if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
299 enum radv_blit_ds_layout ds_layout
= radv_meta_blit_ds_to_type(dst
->current_layout
);
300 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
301 &(VkRenderPassBeginInfo
) {
302 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
303 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
[ds_layout
],
304 .framebuffer
= dst_temps
.fb
,
306 .offset
= { rects
[r
].dst_x
, rects
[r
].dst_y
, },
307 .extent
= { rects
[r
].width
, rects
[r
].height
},
309 .clearValueCount
= 0,
310 .pClearValues
= NULL
,
311 }, VK_SUBPASS_CONTENTS_INLINE
);
314 bind_stencil_pipeline(cmd_buffer
, src_type
);
316 unreachable("Processing blit2d with multiple aspects.");
318 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
321 .width
= rects
[r
].width
,
322 .height
= rects
[r
].height
,
327 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
328 .offset
= (VkOffset2D
) { rects
[r
].dst_x
, rects
[r
].dst_y
},
329 .extent
= (VkExtent2D
) { rects
[r
].width
, rects
[r
].height
},
334 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
335 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
337 /* At the point where we emit the draw call, all data from the
338 * descriptor sets, etc. has been used. We are free to delete it.
340 radv_DestroyFramebuffer(radv_device_to_handle(device
),
342 &cmd_buffer
->pool
->alloc
);
348 radv_meta_blit2d(struct radv_cmd_buffer
*cmd_buffer
,
349 struct radv_meta_blit2d_surf
*src_img
,
350 struct radv_meta_blit2d_buffer
*src_buf
,
351 struct radv_meta_blit2d_surf
*dst
,
353 struct radv_meta_blit2d_rect
*rects
)
355 bool use_3d
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
356 (src_img
&& src_img
->image
->type
== VK_IMAGE_TYPE_3D
);
357 enum blit2d_src_type src_type
= src_buf
? BLIT2D_SRC_TYPE_BUFFER
:
358 use_3d
? BLIT2D_SRC_TYPE_IMAGE_3D
: BLIT2D_SRC_TYPE_IMAGE
;
359 radv_meta_blit2d_normal_dst(cmd_buffer
, src_img
, src_buf
, dst
,
360 num_rects
, rects
, src_type
);
364 build_nir_vertex_shader(void)
366 const struct glsl_type
*vec4
= glsl_vec4_type();
367 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
370 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
371 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit2d_vs");
373 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
374 vec4
, "gl_Position");
375 pos_out
->data
.location
= VARYING_SLOT_POS
;
377 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
379 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
380 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
382 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
383 nir_store_var(&b
, pos_out
, outvec
, 0xf);
385 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
386 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
387 nir_intrinsic_set_base(src_box
, 0);
388 nir_intrinsic_set_range(src_box
, 16);
389 src_box
->num_components
= 4;
390 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
391 nir_builder_instr_insert(&b
, &src_box
->instr
);
393 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
394 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
395 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
397 /* vertex 0 - src_x, src_y */
398 /* vertex 1 - src_x, src_y+h */
399 /* vertex 2 - src_x+w, src_y */
400 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
401 channel 1 is vertex id != 1 ? src_y : src_y + w */
403 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
405 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
408 nir_ssa_def
*comp
[2];
409 comp
[0] = nir_bcsel(&b
, c0cmp
,
410 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
411 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
413 comp
[1] = nir_bcsel(&b
, c1cmp
,
414 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
415 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
416 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 2);
417 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0x3);
421 typedef nir_ssa_def
* (*texel_fetch_build_func
)(struct nir_builder
*,
422 struct radv_device
*,
423 nir_ssa_def
*, bool);
426 build_nir_texel_fetch(struct nir_builder
*b
, struct radv_device
*device
,
427 nir_ssa_def
*tex_pos
, bool is_3d
)
429 enum glsl_sampler_dim dim
= is_3d
? GLSL_SAMPLER_DIM_3D
: GLSL_SAMPLER_DIM_2D
;
430 const struct glsl_type
*sampler_type
=
431 glsl_sampler_type(dim
, false, false, GLSL_TYPE_UINT
);
432 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
433 sampler_type
, "s_tex");
434 sampler
->data
.descriptor_set
= 0;
435 sampler
->data
.binding
= 0;
437 nir_ssa_def
*tex_pos_3d
= NULL
;
439 nir_intrinsic_instr
*layer
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
440 nir_intrinsic_set_base(layer
, 16);
441 nir_intrinsic_set_range(layer
, 4);
442 layer
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
443 layer
->num_components
= 1;
444 nir_ssa_dest_init(&layer
->instr
, &layer
->dest
, 1, 32, "layer");
445 nir_builder_instr_insert(b
, &layer
->instr
);
447 nir_ssa_def
*chans
[3];
448 chans
[0] = nir_channel(b
, tex_pos
, 0);
449 chans
[1] = nir_channel(b
, tex_pos
, 1);
450 chans
[2] = &layer
->dest
.ssa
;
451 tex_pos_3d
= nir_vec(b
, chans
, 3);
453 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
454 tex
->sampler_dim
= dim
;
455 tex
->op
= nir_texop_txf
;
456 tex
->src
[0].src_type
= nir_tex_src_coord
;
457 tex
->src
[0].src
= nir_src_for_ssa(is_3d
? tex_pos_3d
: tex_pos
);
458 tex
->src
[1].src_type
= nir_tex_src_lod
;
459 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
460 tex
->dest_type
= nir_type_uint
;
461 tex
->is_array
= false;
462 tex
->coord_components
= is_3d
? 3 : 2;
463 tex
->texture
= nir_deref_var_create(tex
, sampler
);
466 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
467 nir_builder_instr_insert(b
, &tex
->instr
);
469 return &tex
->dest
.ssa
;
474 build_nir_buffer_fetch(struct nir_builder
*b
, struct radv_device
*device
,
475 nir_ssa_def
*tex_pos
, bool is_3d
)
477 const struct glsl_type
*sampler_type
=
478 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF
, false, false, GLSL_TYPE_UINT
);
479 nir_variable
*sampler
= nir_variable_create(b
->shader
, nir_var_uniform
,
480 sampler_type
, "s_tex");
481 sampler
->data
.descriptor_set
= 0;
482 sampler
->data
.binding
= 0;
484 nir_intrinsic_instr
*width
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
485 nir_intrinsic_set_base(width
, 16);
486 nir_intrinsic_set_range(width
, 4);
487 width
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
488 width
->num_components
= 1;
489 nir_ssa_dest_init(&width
->instr
, &width
->dest
, 1, 32, "width");
490 nir_builder_instr_insert(b
, &width
->instr
);
492 nir_ssa_def
*pos_x
= nir_channel(b
, tex_pos
, 0);
493 nir_ssa_def
*pos_y
= nir_channel(b
, tex_pos
, 1);
494 pos_y
= nir_imul(b
, pos_y
, &width
->dest
.ssa
);
495 pos_x
= nir_iadd(b
, pos_x
, pos_y
);
496 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
498 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 1);
499 tex
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
500 tex
->op
= nir_texop_txf
;
501 tex
->src
[0].src_type
= nir_tex_src_coord
;
502 tex
->src
[0].src
= nir_src_for_ssa(pos_x
);
503 tex
->dest_type
= nir_type_uint
;
504 tex
->is_array
= false;
505 tex
->coord_components
= 1;
506 tex
->texture
= nir_deref_var_create(tex
, sampler
);
509 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
510 nir_builder_instr_insert(b
, &tex
->instr
);
512 return &tex
->dest
.ssa
;
515 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info
= {
516 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
517 .vertexBindingDescriptionCount
= 0,
518 .vertexAttributeDescriptionCount
= 0,
522 build_nir_copy_fragment_shader(struct radv_device
*device
,
523 texel_fetch_build_func txf_func
, const char* name
, bool is_3d
)
525 const struct glsl_type
*vec4
= glsl_vec4_type();
526 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
529 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
530 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
532 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
534 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
536 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
538 color_out
->data
.location
= FRAG_RESULT_DATA0
;
540 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
541 unsigned swiz
[4] = { 0, 1 };
542 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
544 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
, is_3d
);
545 nir_store_var(&b
, color_out
, color
, 0xf);
551 build_nir_copy_fragment_shader_depth(struct radv_device
*device
,
552 texel_fetch_build_func txf_func
, const char* name
, bool is_3d
)
554 const struct glsl_type
*vec4
= glsl_vec4_type();
555 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
558 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
559 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
561 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
563 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
565 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
567 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
569 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
570 unsigned swiz
[4] = { 0, 1 };
571 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
573 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
, is_3d
);
574 nir_store_var(&b
, color_out
, color
, 0x1);
580 build_nir_copy_fragment_shader_stencil(struct radv_device
*device
,
581 texel_fetch_build_func txf_func
, const char* name
, bool is_3d
)
583 const struct glsl_type
*vec4
= glsl_vec4_type();
584 const struct glsl_type
*vec2
= glsl_vector_type(GLSL_TYPE_FLOAT
, 2);
587 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
588 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
590 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
592 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
594 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
596 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
598 nir_ssa_def
*pos_int
= nir_f2i32(&b
, nir_load_var(&b
, tex_pos_in
));
599 unsigned swiz
[4] = { 0, 1 };
600 nir_ssa_def
*tex_pos
= nir_swizzle(&b
, pos_int
, swiz
, 2, false);
602 nir_ssa_def
*color
= txf_func(&b
, device
, tex_pos
, is_3d
);
603 nir_store_var(&b
, color_out
, color
, 0x1);
609 radv_device_finish_meta_blit2d_state(struct radv_device
*device
)
611 struct radv_meta_state
*state
= &device
->meta_state
;
613 for(unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
614 radv_DestroyRenderPass(radv_device_to_handle(device
),
615 state
->blit2d
.render_passes
[j
],
619 for (enum radv_blit_ds_layout j
= RADV_BLIT_DS_LAYOUT_TILE_ENABLE
; j
< RADV_BLIT_DS_LAYOUT_COUNT
; j
++) {
620 radv_DestroyRenderPass(radv_device_to_handle(device
),
621 state
->blit2d
.depth_only_rp
[j
], &state
->alloc
);
622 radv_DestroyRenderPass(radv_device_to_handle(device
),
623 state
->blit2d
.stencil_only_rp
[j
], &state
->alloc
);
626 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
627 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
628 state
->blit2d
.p_layouts
[src
],
630 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
631 state
->blit2d
.ds_layouts
[src
],
634 for (unsigned j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
635 radv_DestroyPipeline(radv_device_to_handle(device
),
636 state
->blit2d
.pipelines
[src
][j
],
640 radv_DestroyPipeline(radv_device_to_handle(device
),
641 state
->blit2d
.depth_only_pipeline
[src
],
643 radv_DestroyPipeline(radv_device_to_handle(device
),
644 state
->blit2d
.stencil_only_pipeline
[src
],
650 blit2d_init_color_pipeline(struct radv_device
*device
,
651 enum blit2d_src_type src_type
,
655 unsigned fs_key
= radv_format_meta_fs_key(format
);
658 texel_fetch_build_func src_func
;
660 case BLIT2D_SRC_TYPE_IMAGE
:
661 src_func
= build_nir_texel_fetch
;
662 name
= "meta_blit2d_image_fs";
664 case BLIT2D_SRC_TYPE_IMAGE_3D
:
665 src_func
= build_nir_texel_fetch
;
666 name
= "meta_blit3d_image_fs";
668 case BLIT2D_SRC_TYPE_BUFFER
:
669 src_func
= build_nir_buffer_fetch
;
670 name
= "meta_blit2d_buffer_fs";
673 unreachable("unknown blit src type\n");
677 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
678 struct radv_shader_module fs
= { .nir
= NULL
};
681 fs
.nir
= build_nir_copy_fragment_shader(device
, src_func
, name
, src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
);
682 vi_create_info
= &normal_vi_create_info
;
684 struct radv_shader_module vs
= {
685 .nir
= build_nir_vertex_shader(),
688 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
690 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
691 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
692 .module
= radv_shader_module_to_handle(&vs
),
694 .pSpecializationInfo
= NULL
696 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
697 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
698 .module
= radv_shader_module_to_handle(&fs
),
700 .pSpecializationInfo
= NULL
704 if (!device
->meta_state
.blit2d
.render_passes
[fs_key
]) {
705 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
706 &(VkRenderPassCreateInfo
) {
707 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
708 .attachmentCount
= 1,
709 .pAttachments
= &(VkAttachmentDescription
) {
711 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
712 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
713 .initialLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
714 .finalLayout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
717 .pSubpasses
= &(VkSubpassDescription
) {
718 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
719 .inputAttachmentCount
= 0,
720 .colorAttachmentCount
= 1,
721 .pColorAttachments
= &(VkAttachmentReference
) {
723 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
725 .pResolveAttachments
= NULL
,
726 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
727 .attachment
= VK_ATTACHMENT_UNUSED
,
728 .layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
,
730 .preserveAttachmentCount
= 1,
731 .pPreserveAttachments
= (uint32_t[]) { 0 },
733 .dependencyCount
= 0,
734 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.render_passes
[fs_key
]);
737 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
738 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
739 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
740 .pStages
= pipeline_shader_stages
,
741 .pVertexInputState
= vi_create_info
,
742 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
743 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
744 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
745 .primitiveRestartEnable
= false,
747 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
748 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
752 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
753 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
754 .rasterizerDiscardEnable
= false,
755 .polygonMode
= VK_POLYGON_MODE_FILL
,
756 .cullMode
= VK_CULL_MODE_NONE
,
757 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
759 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
760 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
761 .rasterizationSamples
= 1,
762 .sampleShadingEnable
= false,
763 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
765 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
766 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
767 .attachmentCount
= 1,
768 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
770 VK_COLOR_COMPONENT_A_BIT
|
771 VK_COLOR_COMPONENT_R_BIT
|
772 VK_COLOR_COMPONENT_G_BIT
|
773 VK_COLOR_COMPONENT_B_BIT
},
776 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
777 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
778 .dynamicStateCount
= 9,
779 .pDynamicStates
= (VkDynamicState
[]) {
780 VK_DYNAMIC_STATE_VIEWPORT
,
781 VK_DYNAMIC_STATE_SCISSOR
,
782 VK_DYNAMIC_STATE_LINE_WIDTH
,
783 VK_DYNAMIC_STATE_DEPTH_BIAS
,
784 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
785 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
786 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
787 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
788 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
792 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
793 .renderPass
= device
->meta_state
.blit2d
.render_passes
[fs_key
],
797 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
801 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
802 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
803 &vk_pipeline_info
, &radv_pipeline_info
,
804 &device
->meta_state
.alloc
,
805 &device
->meta_state
.blit2d
.pipelines
[src_type
][fs_key
]);
815 blit2d_init_depth_only_pipeline(struct radv_device
*device
,
816 enum blit2d_src_type src_type
)
821 texel_fetch_build_func src_func
;
823 case BLIT2D_SRC_TYPE_IMAGE
:
824 src_func
= build_nir_texel_fetch
;
825 name
= "meta_blit2d_depth_image_fs";
827 case BLIT2D_SRC_TYPE_IMAGE_3D
:
828 src_func
= build_nir_texel_fetch
;
829 name
= "meta_blit3d_depth_image_fs";
831 case BLIT2D_SRC_TYPE_BUFFER
:
832 src_func
= build_nir_buffer_fetch
;
833 name
= "meta_blit2d_depth_buffer_fs";
836 unreachable("unknown blit src type\n");
840 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
841 struct radv_shader_module fs
= { .nir
= NULL
};
843 fs
.nir
= build_nir_copy_fragment_shader_depth(device
, src_func
, name
, src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
);
844 vi_create_info
= &normal_vi_create_info
;
846 struct radv_shader_module vs
= {
847 .nir
= build_nir_vertex_shader(),
850 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
852 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
853 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
854 .module
= radv_shader_module_to_handle(&vs
),
856 .pSpecializationInfo
= NULL
858 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
859 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
860 .module
= radv_shader_module_to_handle(&fs
),
862 .pSpecializationInfo
= NULL
866 for (enum radv_blit_ds_layout ds_layout
= RADV_BLIT_DS_LAYOUT_TILE_ENABLE
; ds_layout
< RADV_BLIT_DS_LAYOUT_COUNT
; ds_layout
++) {
867 if (!device
->meta_state
.blit2d
.depth_only_rp
[ds_layout
]) {
868 VkImageLayout layout
= radv_meta_blit_ds_to_layout(ds_layout
);
869 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
870 &(VkRenderPassCreateInfo
) {
871 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
872 .attachmentCount
= 1,
873 .pAttachments
= &(VkAttachmentDescription
) {
874 .format
= VK_FORMAT_D32_SFLOAT
,
875 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
876 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
877 .initialLayout
= layout
,
878 .finalLayout
= layout
,
881 .pSubpasses
= &(VkSubpassDescription
) {
882 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
883 .inputAttachmentCount
= 0,
884 .colorAttachmentCount
= 0,
885 .pColorAttachments
= NULL
,
886 .pResolveAttachments
= NULL
,
887 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
891 .preserveAttachmentCount
= 1,
892 .pPreserveAttachments
= (uint32_t[]) { 0 },
894 .dependencyCount
= 0,
895 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.depth_only_rp
[ds_layout
]);
899 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
900 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
901 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
902 .pStages
= pipeline_shader_stages
,
903 .pVertexInputState
= vi_create_info
,
904 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
905 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
906 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
907 .primitiveRestartEnable
= false,
909 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
910 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
914 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
915 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
916 .rasterizerDiscardEnable
= false,
917 .polygonMode
= VK_POLYGON_MODE_FILL
,
918 .cullMode
= VK_CULL_MODE_NONE
,
919 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
921 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
922 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
923 .rasterizationSamples
= 1,
924 .sampleShadingEnable
= false,
925 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
927 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
928 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
929 .attachmentCount
= 0,
930 .pAttachments
= NULL
,
932 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
933 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
934 .depthTestEnable
= true,
935 .depthWriteEnable
= true,
936 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
938 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
939 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
940 .dynamicStateCount
= 9,
941 .pDynamicStates
= (VkDynamicState
[]) {
942 VK_DYNAMIC_STATE_VIEWPORT
,
943 VK_DYNAMIC_STATE_SCISSOR
,
944 VK_DYNAMIC_STATE_LINE_WIDTH
,
945 VK_DYNAMIC_STATE_DEPTH_BIAS
,
946 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
947 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
948 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
949 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
950 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
954 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
955 .renderPass
= device
->meta_state
.blit2d
.depth_only_rp
[0],
959 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
963 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
964 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
965 &vk_pipeline_info
, &radv_pipeline_info
,
966 &device
->meta_state
.alloc
,
967 &device
->meta_state
.blit2d
.depth_only_pipeline
[src_type
]);
977 blit2d_init_stencil_only_pipeline(struct radv_device
*device
,
978 enum blit2d_src_type src_type
)
983 texel_fetch_build_func src_func
;
985 case BLIT2D_SRC_TYPE_IMAGE
:
986 src_func
= build_nir_texel_fetch
;
987 name
= "meta_blit2d_stencil_image_fs";
989 case BLIT2D_SRC_TYPE_IMAGE_3D
:
990 src_func
= build_nir_texel_fetch
;
991 name
= "meta_blit3d_stencil_image_fs";
993 case BLIT2D_SRC_TYPE_BUFFER
:
994 src_func
= build_nir_buffer_fetch
;
995 name
= "meta_blit2d_stencil_buffer_fs";
998 unreachable("unknown blit src type\n");
1002 const VkPipelineVertexInputStateCreateInfo
*vi_create_info
;
1003 struct radv_shader_module fs
= { .nir
= NULL
};
1005 fs
.nir
= build_nir_copy_fragment_shader_stencil(device
, src_func
, name
, src_type
== BLIT2D_SRC_TYPE_IMAGE_3D
);
1006 vi_create_info
= &normal_vi_create_info
;
1008 struct radv_shader_module vs
= {
1009 .nir
= build_nir_vertex_shader(),
1012 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1014 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1015 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1016 .module
= radv_shader_module_to_handle(&vs
),
1018 .pSpecializationInfo
= NULL
1020 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1021 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1022 .module
= radv_shader_module_to_handle(&fs
),
1024 .pSpecializationInfo
= NULL
1028 for (enum radv_blit_ds_layout ds_layout
= RADV_BLIT_DS_LAYOUT_TILE_ENABLE
; ds_layout
< RADV_BLIT_DS_LAYOUT_COUNT
; ds_layout
++) {
1029 if (!device
->meta_state
.blit2d
.stencil_only_rp
[ds_layout
]) {
1030 VkImageLayout layout
= radv_meta_blit_ds_to_layout(ds_layout
);
1031 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1032 &(VkRenderPassCreateInfo
) {
1033 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1034 .attachmentCount
= 1,
1035 .pAttachments
= &(VkAttachmentDescription
) {
1036 .format
= VK_FORMAT_S8_UINT
,
1037 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1038 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1039 .initialLayout
= layout
,
1040 .finalLayout
= layout
,
1043 .pSubpasses
= &(VkSubpassDescription
) {
1044 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1045 .inputAttachmentCount
= 0,
1046 .colorAttachmentCount
= 0,
1047 .pColorAttachments
= NULL
,
1048 .pResolveAttachments
= NULL
,
1049 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1053 .preserveAttachmentCount
= 1,
1054 .pPreserveAttachments
= (uint32_t[]) { 0 },
1056 .dependencyCount
= 0,
1057 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.stencil_only_rp
[ds_layout
]);
1061 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1062 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1063 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1064 .pStages
= pipeline_shader_stages
,
1065 .pVertexInputState
= vi_create_info
,
1066 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1067 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1068 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1069 .primitiveRestartEnable
= false,
1071 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1072 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1076 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1077 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1078 .rasterizerDiscardEnable
= false,
1079 .polygonMode
= VK_POLYGON_MODE_FILL
,
1080 .cullMode
= VK_CULL_MODE_NONE
,
1081 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1083 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1084 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1085 .rasterizationSamples
= 1,
1086 .sampleShadingEnable
= false,
1087 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1089 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1090 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1091 .attachmentCount
= 0,
1092 .pAttachments
= NULL
,
1094 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1095 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1096 .depthTestEnable
= false,
1097 .depthWriteEnable
= false,
1098 .stencilTestEnable
= true,
1100 .failOp
= VK_STENCIL_OP_REPLACE
,
1101 .passOp
= VK_STENCIL_OP_REPLACE
,
1102 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1103 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1104 .compareMask
= 0xff,
1109 .failOp
= VK_STENCIL_OP_REPLACE
,
1110 .passOp
= VK_STENCIL_OP_REPLACE
,
1111 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1112 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1113 .compareMask
= 0xff,
1117 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1119 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1120 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1121 .dynamicStateCount
= 6,
1122 .pDynamicStates
= (VkDynamicState
[]) {
1123 VK_DYNAMIC_STATE_VIEWPORT
,
1124 VK_DYNAMIC_STATE_SCISSOR
,
1125 VK_DYNAMIC_STATE_LINE_WIDTH
,
1126 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1127 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1128 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1132 .layout
= device
->meta_state
.blit2d
.p_layouts
[src_type
],
1133 .renderPass
= device
->meta_state
.blit2d
.stencil_only_rp
[0],
1137 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1138 .use_rectlist
= true
1141 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1142 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1143 &vk_pipeline_info
, &radv_pipeline_info
,
1144 &device
->meta_state
.alloc
,
1145 &device
->meta_state
.blit2d
.stencil_only_pipeline
[src_type
]);
1148 ralloc_free(vs
.nir
);
1149 ralloc_free(fs
.nir
);
1154 static VkFormat pipeline_formats
[] = {
1155 VK_FORMAT_R8G8B8A8_UNORM
,
1156 VK_FORMAT_R8G8B8A8_UINT
,
1157 VK_FORMAT_R8G8B8A8_SINT
,
1158 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
1159 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
1160 VK_FORMAT_R16G16B16A16_UNORM
,
1161 VK_FORMAT_R16G16B16A16_SNORM
,
1162 VK_FORMAT_R16G16B16A16_UINT
,
1163 VK_FORMAT_R16G16B16A16_SINT
,
1164 VK_FORMAT_R32_SFLOAT
,
1165 VK_FORMAT_R32G32_SFLOAT
,
1166 VK_FORMAT_R32G32B32A32_SFLOAT
1170 meta_blit2d_create_pipe_layout(struct radv_device
*device
,
1174 VkDescriptorType desc_type
= (idx
== BLIT2D_SRC_TYPE_BUFFER
) ? VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
;
1175 const VkPushConstantRange push_constant_ranges
[] = {
1176 {VK_SHADER_STAGE_VERTEX_BIT
, 0, 16},
1177 {VK_SHADER_STAGE_FRAGMENT_BIT
, 16, 4},
1179 int num_push_constant_range
= (idx
!= BLIT2D_SRC_TYPE_IMAGE
) ? 2 : 1;
1181 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1182 &(VkDescriptorSetLayoutCreateInfo
) {
1183 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1184 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1186 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1189 .descriptorType
= desc_type
,
1190 .descriptorCount
= 1,
1191 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1192 .pImmutableSamplers
= NULL
1195 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.ds_layouts
[idx
]);
1196 if (result
!= VK_SUCCESS
)
1199 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1200 &(VkPipelineLayoutCreateInfo
) {
1201 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1202 .setLayoutCount
= 1,
1203 .pSetLayouts
= &device
->meta_state
.blit2d
.ds_layouts
[idx
],
1204 .pushConstantRangeCount
= num_push_constant_range
,
1205 .pPushConstantRanges
= push_constant_ranges
,
1207 &device
->meta_state
.alloc
, &device
->meta_state
.blit2d
.p_layouts
[idx
]);
1208 if (result
!= VK_SUCCESS
)
1216 radv_device_init_meta_blit2d_state(struct radv_device
*device
)
1219 bool create_3d
= device
->physical_device
->rad_info
.chip_class
>= GFX9
;
1221 for (unsigned src
= 0; src
< BLIT2D_NUM_SRC_TYPES
; src
++) {
1222 if (src
== BLIT2D_SRC_TYPE_IMAGE_3D
&& !create_3d
)
1225 result
= meta_blit2d_create_pipe_layout(device
, src
);
1226 if (result
!= VK_SUCCESS
)
1229 for (unsigned j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
1230 result
= blit2d_init_color_pipeline(device
, src
, pipeline_formats
[j
]);
1231 if (result
!= VK_SUCCESS
)
1235 result
= blit2d_init_depth_only_pipeline(device
, src
);
1236 if (result
!= VK_SUCCESS
)
1239 result
= blit2d_init_stencil_only_pipeline(device
, src
);
1240 if (result
!= VK_SUCCESS
)
1247 radv_device_finish_meta_blit2d_state(device
);