nir/i965/anv/radv/gallium: make shader info a pointer
[mesa.git] / src / amd / vulkan / radv_meta_blit2d.c
1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29
30 enum blit2d_dst_type {
31 /* We can bind this destination as a "normal" render target and render
32 * to it just like you would anywhere else.
33 */
34 BLIT2D_DST_TYPE_NORMAL,
35
36 /* The destination has a 3-channel RGB format. Since we can't render to
37 * non-power-of-two textures, we have to bind it as a red texture and
38 * select the correct component for the given red pixel in the shader.
39 */
40 BLIT2D_DST_TYPE_RGB,
41
42 BLIT2D_NUM_DST_TYPES,
43 };
44
45
46 enum blit2d_src_type {
47 BLIT2D_SRC_TYPE_IMAGE,
48 BLIT2D_SRC_TYPE_BUFFER,
49 BLIT2D_NUM_SRC_TYPES,
50 };
51
52 static void
53 create_iview(struct radv_cmd_buffer *cmd_buffer,
54 struct radv_meta_blit2d_surf *surf,
55 VkImageUsageFlags usage,
56 struct radv_image_view *iview, VkFormat depth_format)
57 {
58 VkFormat format;
59
60 if (depth_format)
61 format = depth_format;
62 else
63 format = surf->format;
64
65 radv_image_view_init(iview, cmd_buffer->device,
66 &(VkImageViewCreateInfo) {
67 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
68 .image = radv_image_to_handle(surf->image),
69 .viewType = VK_IMAGE_VIEW_TYPE_2D,
70 .format = format,
71 .subresourceRange = {
72 .aspectMask = surf->aspect_mask,
73 .baseMipLevel = surf->level,
74 .levelCount = 1,
75 .baseArrayLayer = surf->layer,
76 .layerCount = 1
77 },
78 }, cmd_buffer, usage);
79 }
80
81 static void
82 create_bview(struct radv_cmd_buffer *cmd_buffer,
83 struct radv_meta_blit2d_buffer *src,
84 struct radv_buffer_view *bview, VkFormat depth_format)
85 {
86 VkFormat format;
87
88 if (depth_format)
89 format = depth_format;
90 else
91 format = src->format;
92 radv_buffer_view_init(bview, cmd_buffer->device,
93 &(VkBufferViewCreateInfo) {
94 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
95 .flags = 0,
96 .buffer = radv_buffer_to_handle(src->buffer),
97 .format = format,
98 .offset = src->offset,
99 .range = VK_WHOLE_SIZE,
100 }, cmd_buffer);
101
102 }
103
104 struct blit2d_src_temps {
105 struct radv_image_view iview;
106
107 VkDescriptorSet set;
108 struct radv_buffer_view bview;
109 };
110
111 static void
112 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
113 struct radv_meta_blit2d_surf *src_img,
114 struct radv_meta_blit2d_buffer *src_buf,
115 struct radv_meta_blit2d_rect *rect,
116 struct blit2d_src_temps *tmp,
117 enum blit2d_src_type src_type, VkFormat depth_format)
118 {
119 struct radv_device *device = cmd_buffer->device;
120 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
121
122 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
123 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
124
125 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
126 device->meta_state.blit2d.ds_layouts[src_type],
127 &tmp->set);
128
129 radv_UpdateDescriptorSets(vk_device,
130 1, /* writeCount */
131 (VkWriteDescriptorSet[]) {
132 {
133 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
134 .dstSet = tmp->set,
135 .dstBinding = 0,
136 .dstArrayElement = 0,
137 .descriptorCount = 1,
138 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
139 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
140 }
141 }, 0, NULL);
142
143 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
144 device->meta_state.blit2d.p_layouts[src_type],
145 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4,
146 &src_buf->pitch);
147 } else {
148 create_iview(cmd_buffer, src_img, VK_IMAGE_USAGE_SAMPLED_BIT, &tmp->iview,
149 depth_format);
150
151 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
152 device->meta_state.blit2d.ds_layouts[src_type],
153 &tmp->set);
154
155 radv_UpdateDescriptorSets(vk_device,
156 1, /* writeCount */
157 (VkWriteDescriptorSet[]) {
158 {
159 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
160 .dstSet = tmp->set,
161 .dstBinding = 0,
162 .dstArrayElement = 0,
163 .descriptorCount = 1,
164 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
165 .pImageInfo = (VkDescriptorImageInfo[]) {
166 {
167 .sampler = NULL,
168 .imageView = radv_image_view_to_handle(&tmp->iview),
169 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
170 },
171 }
172 }
173 }, 0, NULL);
174
175 }
176
177 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
178 VK_PIPELINE_BIND_POINT_GRAPHICS,
179 device->meta_state.blit2d.p_layouts[src_type], 0, 1,
180 &tmp->set, 0, NULL);
181 }
182
183 static void
184 blit2d_unbind_src(struct radv_cmd_buffer *cmd_buffer,
185 struct blit2d_src_temps *tmp,
186 enum blit2d_src_type src_type)
187 {
188 radv_temp_descriptor_set_destroy(cmd_buffer->device, tmp->set);
189 }
190
191 struct blit2d_dst_temps {
192 VkImage image;
193 struct radv_image_view iview;
194 VkFramebuffer fb;
195 };
196
197 static void
198 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
199 struct radv_meta_blit2d_surf *dst,
200 uint32_t width,
201 uint32_t height,
202 VkFormat depth_format,
203 struct blit2d_dst_temps *tmp)
204 {
205 VkImageUsageFlagBits bits;
206
207 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT)
208 bits = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
209 else
210 bits = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
211
212 create_iview(cmd_buffer, dst, bits,
213 &tmp->iview, depth_format);
214
215 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
216 &(VkFramebufferCreateInfo) {
217 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
218 .attachmentCount = 1,
219 .pAttachments = (VkImageView[]) {
220 radv_image_view_to_handle(&tmp->iview),
221 },
222 .width = width,
223 .height = height,
224 .layers = 1
225 }, &cmd_buffer->pool->alloc, &tmp->fb);
226 }
227
228 static void
229 blit2d_unbind_dst(struct radv_cmd_buffer *cmd_buffer,
230 struct blit2d_dst_temps *tmp)
231 {
232 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
233 radv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
234 }
235
236 static void
237 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
238 enum blit2d_src_type src_type, unsigned fs_key)
239 {
240 VkPipeline pipeline =
241 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
242
243 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
244 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
245 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
246 }
247 }
248
249 static void
250 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
251 enum blit2d_src_type src_type)
252 {
253 VkPipeline pipeline =
254 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
255
256 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
257 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
258 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
259 }
260 }
261
262 static void
263 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
264 enum blit2d_src_type src_type)
265 {
266 VkPipeline pipeline =
267 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
268
269 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
270 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
271 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
272 }
273 }
274
275 static void
276 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
277 struct radv_meta_blit2d_surf *src_img,
278 struct radv_meta_blit2d_buffer *src_buf,
279 struct radv_meta_blit2d_surf *dst,
280 unsigned num_rects,
281 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
282 {
283 struct radv_device *device = cmd_buffer->device;
284
285 for (unsigned r = 0; r < num_rects; ++r) {
286 VkFormat depth_format = 0;
287 if (dst->aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT)
288 depth_format = dst->image->vk_format;
289 struct blit2d_src_temps src_temps;
290 blit2d_bind_src(cmd_buffer, src_img, src_buf, &rects[r], &src_temps, src_type, depth_format);
291
292 uint32_t offset = 0;
293 struct blit2d_dst_temps dst_temps;
294 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
295 rects[r].dst_y + rects[r].height, depth_format, &dst_temps);
296
297 struct blit_vb_data {
298 float pos[2];
299 float tex_coord[2];
300 } vb_data[3];
301
302 unsigned vb_size = 3 * sizeof(*vb_data);
303
304 vb_data[0] = (struct blit_vb_data) {
305 .pos = {
306 rects[r].dst_x,
307 rects[r].dst_y,
308 },
309 .tex_coord = {
310 rects[r].src_x,
311 rects[r].src_y,
312 },
313 };
314
315 vb_data[1] = (struct blit_vb_data) {
316 .pos = {
317 rects[r].dst_x,
318 rects[r].dst_y + rects[r].height,
319 },
320 .tex_coord = {
321 rects[r].src_x,
322 rects[r].src_y + rects[r].height,
323 },
324 };
325
326 vb_data[2] = (struct blit_vb_data) {
327 .pos = {
328 rects[r].dst_x + rects[r].width,
329 rects[r].dst_y,
330 },
331 .tex_coord = {
332 rects[r].src_x + rects[r].width,
333 rects[r].src_y,
334 },
335 };
336
337
338 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
339
340 struct radv_buffer vertex_buffer = {
341 .device = device,
342 .size = vb_size,
343 .bo = cmd_buffer->upload.upload_bo,
344 .offset = offset,
345 };
346
347 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
348 (VkBuffer[]) {
349 radv_buffer_to_handle(&vertex_buffer),
350 },
351 (VkDeviceSize[]) {
352 0,
353 });
354
355
356 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
357 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
358
359 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
360 &(VkRenderPassBeginInfo) {
361 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
362 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
363 .framebuffer = dst_temps.fb,
364 .renderArea = {
365 .offset = { rects[r].dst_x, rects[r].dst_y, },
366 .extent = { rects[r].width, rects[r].height },
367 },
368 .clearValueCount = 0,
369 .pClearValues = NULL,
370 }, VK_SUBPASS_CONTENTS_INLINE);
371
372
373 bind_pipeline(cmd_buffer, src_type, fs_key);
374 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
375 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
376 &(VkRenderPassBeginInfo) {
377 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
378 .renderPass = device->meta_state.blit2d.depth_only_rp,
379 .framebuffer = dst_temps.fb,
380 .renderArea = {
381 .offset = { rects[r].dst_x, rects[r].dst_y, },
382 .extent = { rects[r].width, rects[r].height },
383 },
384 .clearValueCount = 0,
385 .pClearValues = NULL,
386 }, VK_SUBPASS_CONTENTS_INLINE);
387
388
389 bind_depth_pipeline(cmd_buffer, src_type);
390
391 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
392 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
393 &(VkRenderPassBeginInfo) {
394 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
395 .renderPass = device->meta_state.blit2d.stencil_only_rp,
396 .framebuffer = dst_temps.fb,
397 .renderArea = {
398 .offset = { rects[r].dst_x, rects[r].dst_y, },
399 .extent = { rects[r].width, rects[r].height },
400 },
401 .clearValueCount = 0,
402 .pClearValues = NULL,
403 }, VK_SUBPASS_CONTENTS_INLINE);
404
405
406 bind_stencil_pipeline(cmd_buffer, src_type);
407 }
408
409 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
410 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
411
412 /* At the point where we emit the draw call, all data from the
413 * descriptor sets, etc. has been used. We are free to delete it.
414 */
415 blit2d_unbind_src(cmd_buffer, &src_temps, src_type);
416 blit2d_unbind_dst(cmd_buffer, &dst_temps);
417 }
418 }
419
420 void
421 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
422 struct radv_meta_blit2d_surf *src_img,
423 struct radv_meta_blit2d_buffer *src_buf,
424 struct radv_meta_blit2d_surf *dst,
425 unsigned num_rects,
426 struct radv_meta_blit2d_rect *rects)
427 {
428 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
429 BLIT2D_SRC_TYPE_IMAGE;
430 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
431 num_rects, rects, src_type);
432 }
433
434 static nir_shader *
435 build_nir_vertex_shader(void)
436 {
437 const struct glsl_type *vec4 = glsl_vec4_type();
438 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
439 nir_builder b;
440
441 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
442 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
443
444 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
445 vec4, "a_pos");
446 pos_in->data.location = VERT_ATTRIB_GENERIC0;
447 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
448 vec4, "gl_Position");
449 pos_out->data.location = VARYING_SLOT_POS;
450 nir_copy_var(&b, pos_out, pos_in);
451
452 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
453 vec2, "a_tex_pos");
454 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
455 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
456 vec2, "v_tex_pos");
457 tex_pos_out->data.location = VARYING_SLOT_VAR0;
458 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
459 nir_copy_var(&b, tex_pos_out, tex_pos_in);
460
461 return b.shader;
462 }
463
464 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
465 struct radv_device *,
466 nir_ssa_def *);
467
468 static nir_ssa_def *
469 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
470 nir_ssa_def *tex_pos)
471 {
472 const struct glsl_type *sampler_type =
473 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
474 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
475 sampler_type, "s_tex");
476 sampler->data.descriptor_set = 0;
477 sampler->data.binding = 0;
478
479 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
480 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
481 tex->op = nir_texop_txf;
482 tex->src[0].src_type = nir_tex_src_coord;
483 tex->src[0].src = nir_src_for_ssa(tex_pos);
484 tex->src[1].src_type = nir_tex_src_lod;
485 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
486 tex->dest_type = nir_type_uint;
487 tex->is_array = false;
488 tex->coord_components = 2;
489 tex->texture = nir_deref_var_create(tex, sampler);
490 tex->sampler = NULL;
491
492 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
493 nir_builder_instr_insert(b, &tex->instr);
494
495 return &tex->dest.ssa;
496 }
497
498
499 static nir_ssa_def *
500 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
501 nir_ssa_def *tex_pos)
502 {
503 const struct glsl_type *sampler_type =
504 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
505 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
506 sampler_type, "s_tex");
507 sampler->data.descriptor_set = 0;
508 sampler->data.binding = 0;
509
510 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
511 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
512 width->num_components = 1;
513 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
514 nir_builder_instr_insert(b, &width->instr);
515
516 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
517 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
518 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
519 pos_x = nir_iadd(b, pos_x, pos_y);
520 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
521
522 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
523 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
524 tex->op = nir_texop_txf;
525 tex->src[0].src_type = nir_tex_src_coord;
526 tex->src[0].src = nir_src_for_ssa(pos_x);
527 tex->dest_type = nir_type_uint;
528 tex->is_array = false;
529 tex->coord_components = 1;
530 tex->texture = nir_deref_var_create(tex, sampler);
531 tex->sampler = NULL;
532
533 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
534 nir_builder_instr_insert(b, &tex->instr);
535
536 return &tex->dest.ssa;
537 }
538
539 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
540 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
541 .vertexBindingDescriptionCount = 1,
542 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
543 {
544 .binding = 0,
545 .stride = 4 * sizeof(float),
546 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
547 },
548 },
549 .vertexAttributeDescriptionCount = 2,
550 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
551 {
552 /* Position */
553 .location = 0,
554 .binding = 0,
555 .format = VK_FORMAT_R32G32_SFLOAT,
556 .offset = 0
557 },
558 {
559 /* Texture Coordinate */
560 .location = 1,
561 .binding = 0,
562 .format = VK_FORMAT_R32G32_SFLOAT,
563 .offset = 8
564 },
565 },
566 };
567
568 static nir_shader *
569 build_nir_copy_fragment_shader(struct radv_device *device,
570 texel_fetch_build_func txf_func, const char* name)
571 {
572 const struct glsl_type *vec4 = glsl_vec4_type();
573 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
574 nir_builder b;
575
576 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
577 b.shader->info->name = ralloc_strdup(b.shader, name);
578
579 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
580 vec2, "v_tex_pos");
581 tex_pos_in->data.location = VARYING_SLOT_VAR0;
582
583 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
584 vec4, "f_color");
585 color_out->data.location = FRAG_RESULT_DATA0;
586
587 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
588 unsigned swiz[4] = { 0, 1 };
589 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
590
591 nir_ssa_def *color = txf_func(&b, device, tex_pos);
592 nir_store_var(&b, color_out, color, 0xf);
593
594 return b.shader;
595 }
596
597 static nir_shader *
598 build_nir_copy_fragment_shader_depth(struct radv_device *device,
599 texel_fetch_build_func txf_func, const char* name)
600 {
601 const struct glsl_type *vec4 = glsl_vec4_type();
602 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
603 nir_builder b;
604
605 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
606 b.shader->info->name = ralloc_strdup(b.shader, name);
607
608 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
609 vec2, "v_tex_pos");
610 tex_pos_in->data.location = VARYING_SLOT_VAR0;
611
612 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
613 vec4, "f_color");
614 color_out->data.location = FRAG_RESULT_DEPTH;
615
616 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
617 unsigned swiz[4] = { 0, 1 };
618 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
619
620 nir_ssa_def *color = txf_func(&b, device, tex_pos);
621 nir_store_var(&b, color_out, color, 0x1);
622
623 return b.shader;
624 }
625
626 static nir_shader *
627 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
628 texel_fetch_build_func txf_func, const char* name)
629 {
630 const struct glsl_type *vec4 = glsl_vec4_type();
631 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
632 nir_builder b;
633
634 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
635 b.shader->info->name = ralloc_strdup(b.shader, name);
636
637 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
638 vec2, "v_tex_pos");
639 tex_pos_in->data.location = VARYING_SLOT_VAR0;
640
641 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
642 vec4, "f_color");
643 color_out->data.location = FRAG_RESULT_STENCIL;
644
645 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
646 unsigned swiz[4] = { 0, 1 };
647 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
648
649 nir_ssa_def *color = txf_func(&b, device, tex_pos);
650 nir_store_var(&b, color_out, color, 0x1);
651
652 return b.shader;
653 }
654
655 void
656 radv_device_finish_meta_blit2d_state(struct radv_device *device)
657 {
658 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
659 if (device->meta_state.blit2d.render_passes[j]) {
660 radv_DestroyRenderPass(radv_device_to_handle(device),
661 device->meta_state.blit2d.render_passes[j],
662 &device->meta_state.alloc);
663 }
664 }
665
666 radv_DestroyRenderPass(radv_device_to_handle(device),
667 device->meta_state.blit2d.depth_only_rp,
668 &device->meta_state.alloc);
669 radv_DestroyRenderPass(radv_device_to_handle(device),
670 device->meta_state.blit2d.stencil_only_rp,
671 &device->meta_state.alloc);
672
673 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
674 if (device->meta_state.blit2d.p_layouts[src]) {
675 radv_DestroyPipelineLayout(radv_device_to_handle(device),
676 device->meta_state.blit2d.p_layouts[src],
677 &device->meta_state.alloc);
678 }
679
680 if (device->meta_state.blit2d.ds_layouts[src]) {
681 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
682 device->meta_state.blit2d.ds_layouts[src],
683 &device->meta_state.alloc);
684 }
685
686 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
687 if (device->meta_state.blit2d.pipelines[src][j]) {
688 radv_DestroyPipeline(radv_device_to_handle(device),
689 device->meta_state.blit2d.pipelines[src][j],
690 &device->meta_state.alloc);
691 }
692 }
693
694 radv_DestroyPipeline(radv_device_to_handle(device),
695 device->meta_state.blit2d.depth_only_pipeline[src],
696 &device->meta_state.alloc);
697 radv_DestroyPipeline(radv_device_to_handle(device),
698 device->meta_state.blit2d.stencil_only_pipeline[src],
699 &device->meta_state.alloc);
700 }
701 }
702
703 static VkResult
704 blit2d_init_color_pipeline(struct radv_device *device,
705 enum blit2d_src_type src_type,
706 VkFormat format)
707 {
708 VkResult result;
709 unsigned fs_key = radv_format_meta_fs_key(format);
710 const char *name;
711
712 texel_fetch_build_func src_func;
713 switch(src_type) {
714 case BLIT2D_SRC_TYPE_IMAGE:
715 src_func = build_nir_texel_fetch;
716 name = "meta_blit2d_image_fs";
717 break;
718 case BLIT2D_SRC_TYPE_BUFFER:
719 src_func = build_nir_buffer_fetch;
720 name = "meta_blit2d_buffer_fs";
721 break;
722 default:
723 unreachable("unknown blit src type\n");
724 break;
725 }
726
727 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
728 struct radv_shader_module fs = { .nir = NULL };
729
730
731 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
732 vi_create_info = &normal_vi_create_info;
733
734 struct radv_shader_module vs = {
735 .nir = build_nir_vertex_shader(),
736 };
737
738 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
739 {
740 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
741 .stage = VK_SHADER_STAGE_VERTEX_BIT,
742 .module = radv_shader_module_to_handle(&vs),
743 .pName = "main",
744 .pSpecializationInfo = NULL
745 }, {
746 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
747 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
748 .module = radv_shader_module_to_handle(&fs),
749 .pName = "main",
750 .pSpecializationInfo = NULL
751 },
752 };
753
754 if (!device->meta_state.blit2d.render_passes[fs_key]) {
755 result = radv_CreateRenderPass(radv_device_to_handle(device),
756 &(VkRenderPassCreateInfo) {
757 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
758 .attachmentCount = 1,
759 .pAttachments = &(VkAttachmentDescription) {
760 .format = format,
761 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
762 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
763 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
764 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
765 },
766 .subpassCount = 1,
767 .pSubpasses = &(VkSubpassDescription) {
768 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
769 .inputAttachmentCount = 0,
770 .colorAttachmentCount = 1,
771 .pColorAttachments = &(VkAttachmentReference) {
772 .attachment = 0,
773 .layout = VK_IMAGE_LAYOUT_GENERAL,
774 },
775 .pResolveAttachments = NULL,
776 .pDepthStencilAttachment = &(VkAttachmentReference) {
777 .attachment = VK_ATTACHMENT_UNUSED,
778 .layout = VK_IMAGE_LAYOUT_GENERAL,
779 },
780 .preserveAttachmentCount = 1,
781 .pPreserveAttachments = (uint32_t[]) { 0 },
782 },
783 .dependencyCount = 0,
784 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
785 }
786
787 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
788 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
789 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
790 .pStages = pipeline_shader_stages,
791 .pVertexInputState = vi_create_info,
792 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
793 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
794 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
795 .primitiveRestartEnable = false,
796 },
797 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
798 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
799 .viewportCount = 0,
800 .scissorCount = 0,
801 },
802 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
803 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
804 .rasterizerDiscardEnable = false,
805 .polygonMode = VK_POLYGON_MODE_FILL,
806 .cullMode = VK_CULL_MODE_NONE,
807 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
808 },
809 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
810 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
811 .rasterizationSamples = 1,
812 .sampleShadingEnable = false,
813 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
814 },
815 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
816 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
817 .attachmentCount = 1,
818 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
819 { .colorWriteMask =
820 VK_COLOR_COMPONENT_A_BIT |
821 VK_COLOR_COMPONENT_R_BIT |
822 VK_COLOR_COMPONENT_G_BIT |
823 VK_COLOR_COMPONENT_B_BIT },
824 }
825 },
826 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
827 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
828 .dynamicStateCount = 7,
829 .pDynamicStates = (VkDynamicState[]) {
830 VK_DYNAMIC_STATE_LINE_WIDTH,
831 VK_DYNAMIC_STATE_DEPTH_BIAS,
832 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
833 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
834 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
835 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
836 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
837 },
838 },
839 .flags = 0,
840 .layout = device->meta_state.blit2d.p_layouts[src_type],
841 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
842 .subpass = 0,
843 };
844
845 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
846 .use_rectlist = true
847 };
848
849 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
850 radv_pipeline_cache_to_handle(&device->meta_state.cache),
851 &vk_pipeline_info, &radv_pipeline_info,
852 &device->meta_state.alloc,
853 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
854
855
856 ralloc_free(vs.nir);
857 ralloc_free(fs.nir);
858
859 return result;
860 }
861
862 static VkResult
863 blit2d_init_depth_only_pipeline(struct radv_device *device,
864 enum blit2d_src_type src_type)
865 {
866 VkResult result;
867 const char *name;
868
869 texel_fetch_build_func src_func;
870 switch(src_type) {
871 case BLIT2D_SRC_TYPE_IMAGE:
872 src_func = build_nir_texel_fetch;
873 name = "meta_blit2d_depth_image_fs";
874 break;
875 case BLIT2D_SRC_TYPE_BUFFER:
876 src_func = build_nir_buffer_fetch;
877 name = "meta_blit2d_depth_buffer_fs";
878 break;
879 default:
880 unreachable("unknown blit src type\n");
881 break;
882 }
883
884 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
885 struct radv_shader_module fs = { .nir = NULL };
886
887 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
888 vi_create_info = &normal_vi_create_info;
889
890 struct radv_shader_module vs = {
891 .nir = build_nir_vertex_shader(),
892 };
893
894 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
895 {
896 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
897 .stage = VK_SHADER_STAGE_VERTEX_BIT,
898 .module = radv_shader_module_to_handle(&vs),
899 .pName = "main",
900 .pSpecializationInfo = NULL
901 }, {
902 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
903 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
904 .module = radv_shader_module_to_handle(&fs),
905 .pName = "main",
906 .pSpecializationInfo = NULL
907 },
908 };
909
910 if (!device->meta_state.blit2d.depth_only_rp) {
911 result = radv_CreateRenderPass(radv_device_to_handle(device),
912 &(VkRenderPassCreateInfo) {
913 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
914 .attachmentCount = 1,
915 .pAttachments = &(VkAttachmentDescription) {
916 .format = 0,
917 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
918 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
919 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
920 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
921 },
922 .subpassCount = 1,
923 .pSubpasses = &(VkSubpassDescription) {
924 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
925 .inputAttachmentCount = 0,
926 .colorAttachmentCount = 0,
927 .pColorAttachments = NULL,
928 .pResolveAttachments = NULL,
929 .pDepthStencilAttachment = &(VkAttachmentReference) {
930 .attachment = 0,
931 .layout = VK_IMAGE_LAYOUT_GENERAL,
932 },
933 .preserveAttachmentCount = 1,
934 .pPreserveAttachments = (uint32_t[]) { 0 },
935 },
936 .dependencyCount = 0,
937 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
938 }
939
940 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
941 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
942 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
943 .pStages = pipeline_shader_stages,
944 .pVertexInputState = vi_create_info,
945 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
946 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
947 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
948 .primitiveRestartEnable = false,
949 },
950 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
951 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
952 .viewportCount = 0,
953 .scissorCount = 0,
954 },
955 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
956 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
957 .rasterizerDiscardEnable = false,
958 .polygonMode = VK_POLYGON_MODE_FILL,
959 .cullMode = VK_CULL_MODE_NONE,
960 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
961 },
962 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
963 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
964 .rasterizationSamples = 1,
965 .sampleShadingEnable = false,
966 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
967 },
968 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
969 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
970 .attachmentCount = 0,
971 .pAttachments = NULL,
972 },
973 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
974 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
975 .depthTestEnable = true,
976 .depthWriteEnable = true,
977 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
978 },
979 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
980 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
981 .dynamicStateCount = 7,
982 .pDynamicStates = (VkDynamicState[]) {
983 VK_DYNAMIC_STATE_LINE_WIDTH,
984 VK_DYNAMIC_STATE_DEPTH_BIAS,
985 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
986 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
987 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
988 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
989 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
990 },
991 },
992 .flags = 0,
993 .layout = device->meta_state.blit2d.p_layouts[src_type],
994 .renderPass = device->meta_state.blit2d.depth_only_rp,
995 .subpass = 0,
996 };
997
998 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
999 .use_rectlist = true
1000 };
1001
1002 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1003 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1004 &vk_pipeline_info, &radv_pipeline_info,
1005 &device->meta_state.alloc,
1006 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
1007
1008
1009 ralloc_free(vs.nir);
1010 ralloc_free(fs.nir);
1011
1012 return result;
1013 }
1014
1015 static VkResult
1016 blit2d_init_stencil_only_pipeline(struct radv_device *device,
1017 enum blit2d_src_type src_type)
1018 {
1019 VkResult result;
1020 const char *name;
1021
1022 texel_fetch_build_func src_func;
1023 switch(src_type) {
1024 case BLIT2D_SRC_TYPE_IMAGE:
1025 src_func = build_nir_texel_fetch;
1026 name = "meta_blit2d_stencil_image_fs";
1027 break;
1028 case BLIT2D_SRC_TYPE_BUFFER:
1029 src_func = build_nir_buffer_fetch;
1030 name = "meta_blit2d_stencil_buffer_fs";
1031 break;
1032 default:
1033 unreachable("unknown blit src type\n");
1034 break;
1035 }
1036
1037 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1038 struct radv_shader_module fs = { .nir = NULL };
1039
1040 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
1041 vi_create_info = &normal_vi_create_info;
1042
1043 struct radv_shader_module vs = {
1044 .nir = build_nir_vertex_shader(),
1045 };
1046
1047 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1048 {
1049 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1050 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1051 .module = radv_shader_module_to_handle(&vs),
1052 .pName = "main",
1053 .pSpecializationInfo = NULL
1054 }, {
1055 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1056 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1057 .module = radv_shader_module_to_handle(&fs),
1058 .pName = "main",
1059 .pSpecializationInfo = NULL
1060 },
1061 };
1062
1063 if (!device->meta_state.blit2d.stencil_only_rp) {
1064 result = radv_CreateRenderPass(radv_device_to_handle(device),
1065 &(VkRenderPassCreateInfo) {
1066 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1067 .attachmentCount = 1,
1068 .pAttachments = &(VkAttachmentDescription) {
1069 .format = 0,
1070 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1071 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1072 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1073 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1074 },
1075 .subpassCount = 1,
1076 .pSubpasses = &(VkSubpassDescription) {
1077 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1078 .inputAttachmentCount = 0,
1079 .colorAttachmentCount = 0,
1080 .pColorAttachments = NULL,
1081 .pResolveAttachments = NULL,
1082 .pDepthStencilAttachment = &(VkAttachmentReference) {
1083 .attachment = 0,
1084 .layout = VK_IMAGE_LAYOUT_GENERAL,
1085 },
1086 .preserveAttachmentCount = 1,
1087 .pPreserveAttachments = (uint32_t[]) { 0 },
1088 },
1089 .dependencyCount = 0,
1090 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1091 }
1092
1093 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1094 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1095 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1096 .pStages = pipeline_shader_stages,
1097 .pVertexInputState = vi_create_info,
1098 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1099 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1100 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1101 .primitiveRestartEnable = false,
1102 },
1103 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1104 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1105 .viewportCount = 0,
1106 .scissorCount = 0,
1107 },
1108 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1109 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1110 .rasterizerDiscardEnable = false,
1111 .polygonMode = VK_POLYGON_MODE_FILL,
1112 .cullMode = VK_CULL_MODE_NONE,
1113 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1114 },
1115 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1116 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1117 .rasterizationSamples = 1,
1118 .sampleShadingEnable = false,
1119 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1120 },
1121 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1122 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1123 .attachmentCount = 0,
1124 .pAttachments = NULL,
1125 },
1126 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1127 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1128 .depthTestEnable = false,
1129 .depthWriteEnable = false,
1130 .stencilTestEnable = true,
1131 .front = {
1132 .failOp = VK_STENCIL_OP_REPLACE,
1133 .passOp = VK_STENCIL_OP_REPLACE,
1134 .depthFailOp = VK_STENCIL_OP_REPLACE,
1135 .compareOp = VK_COMPARE_OP_ALWAYS,
1136 .compareMask = 0xff,
1137 .writeMask = 0xff,
1138 .reference = 0
1139 },
1140 .back = {
1141 .failOp = VK_STENCIL_OP_REPLACE,
1142 .passOp = VK_STENCIL_OP_REPLACE,
1143 .depthFailOp = VK_STENCIL_OP_REPLACE,
1144 .compareOp = VK_COMPARE_OP_ALWAYS,
1145 .compareMask = 0xff,
1146 .writeMask = 0xff,
1147 .reference = 0
1148 },
1149 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1150 },
1151 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1152 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1153 .dynamicStateCount = 4,
1154 .pDynamicStates = (VkDynamicState[]) {
1155 VK_DYNAMIC_STATE_LINE_WIDTH,
1156 VK_DYNAMIC_STATE_DEPTH_BIAS,
1157 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1158 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1159 },
1160 },
1161 .flags = 0,
1162 .layout = device->meta_state.blit2d.p_layouts[src_type],
1163 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1164 .subpass = 0,
1165 };
1166
1167 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1168 .use_rectlist = true
1169 };
1170
1171 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1172 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1173 &vk_pipeline_info, &radv_pipeline_info,
1174 &device->meta_state.alloc,
1175 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1176
1177
1178 ralloc_free(vs.nir);
1179 ralloc_free(fs.nir);
1180
1181 return result;
1182 }
1183
1184 static VkFormat pipeline_formats[] = {
1185 VK_FORMAT_R8G8B8A8_UNORM,
1186 VK_FORMAT_R8G8B8A8_UINT,
1187 VK_FORMAT_R8G8B8A8_SINT,
1188 VK_FORMAT_R16G16B16A16_UNORM,
1189 VK_FORMAT_R16G16B16A16_SNORM,
1190 VK_FORMAT_R16G16B16A16_UINT,
1191 VK_FORMAT_R16G16B16A16_SINT,
1192 VK_FORMAT_R32_SFLOAT,
1193 VK_FORMAT_R32G32_SFLOAT,
1194 VK_FORMAT_R32G32B32A32_SFLOAT
1195 };
1196
1197 VkResult
1198 radv_device_init_meta_blit2d_state(struct radv_device *device)
1199 {
1200 VkResult result;
1201
1202 zero(device->meta_state.blit2d);
1203
1204 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1205 &(VkDescriptorSetLayoutCreateInfo) {
1206 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1207 .bindingCount = 1,
1208 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1209 {
1210 .binding = 0,
1211 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1212 .descriptorCount = 1,
1213 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1214 .pImmutableSamplers = NULL
1215 },
1216 }
1217 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1218 if (result != VK_SUCCESS)
1219 goto fail;
1220
1221 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1222 &(VkPipelineLayoutCreateInfo) {
1223 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1224 .setLayoutCount = 1,
1225 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1226 },
1227 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1228 if (result != VK_SUCCESS)
1229 goto fail;
1230
1231 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1232 &(VkDescriptorSetLayoutCreateInfo) {
1233 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1234 .bindingCount = 1,
1235 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1236 {
1237 .binding = 0,
1238 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1239 .descriptorCount = 1,
1240 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1241 .pImmutableSamplers = NULL
1242 },
1243 }
1244 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1245 if (result != VK_SUCCESS)
1246 goto fail;
1247
1248 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4};
1249 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1250 &(VkPipelineLayoutCreateInfo) {
1251 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1252 .setLayoutCount = 1,
1253 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1254 .pushConstantRangeCount = 1,
1255 .pPushConstantRanges = &push_constant_range,
1256 },
1257 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1258 if (result != VK_SUCCESS)
1259 goto fail;
1260
1261 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1262 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1263 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1264 if (result != VK_SUCCESS)
1265 goto fail;
1266 }
1267
1268 result = blit2d_init_depth_only_pipeline(device, src);
1269 if (result != VK_SUCCESS)
1270 goto fail;
1271
1272 result = blit2d_init_stencil_only_pipeline(device, src);
1273 if (result != VK_SUCCESS)
1274 goto fail;
1275 }
1276
1277 return VK_SUCCESS;
1278
1279 fail:
1280 radv_device_finish_meta_blit2d_state(device);
1281 return result;
1282 }