2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
34 DEPTH_CLEAR_FAST_EXPCLEAR
,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
39 build_color_shaders(struct nir_shader
**out_vs
,
40 struct nir_shader
**out_fs
,
46 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
47 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
49 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
50 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
52 const struct glsl_type
*position_type
= glsl_vec4_type();
53 const struct glsl_type
*color_type
= glsl_vec4_type();
55 nir_variable
*vs_out_pos
=
56 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
58 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
60 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
61 nir_intrinsic_set_base(in_color_load
, 0);
62 nir_intrinsic_set_range(in_color_load
, 16);
63 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
64 in_color_load
->num_components
= 4;
65 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
68 nir_variable
*fs_out_color
=
69 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
71 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
73 nir_store_var(&fs_b
, fs_out_color
, &in_color_load
->dest
.ssa
, 0xf);
75 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&vs_b
);
76 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
78 const struct glsl_type
*layer_type
= glsl_int_type();
79 nir_variable
*vs_out_layer
=
80 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
82 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
83 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
84 nir_ssa_def
*inst_id
= nir_load_system_value(&vs_b
, nir_intrinsic_load_instance_id
, 0);
85 nir_ssa_def
*base_instance
= nir_load_system_value(&vs_b
, nir_intrinsic_load_base_instance
, 0);
87 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
88 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
90 *out_vs
= vs_b
.shader
;
91 *out_fs
= fs_b
.shader
;
95 create_pipeline(struct radv_device
*device
,
96 struct radv_render_pass
*render_pass
,
98 struct nir_shader
*vs_nir
,
99 struct nir_shader
*fs_nir
,
100 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
101 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
102 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
103 const VkPipelineLayout layout
,
104 const struct radv_graphics_pipeline_create_info
*extra
,
105 const VkAllocationCallbacks
*alloc
,
106 VkPipeline
*pipeline
)
108 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
112 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
114 result
= radv_graphics_pipeline_create(device_h
,
115 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
116 &(VkGraphicsPipelineCreateInfo
) {
117 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
118 .stageCount
= fs_nir
? 2 : 1,
119 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
121 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
122 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
123 .module
= radv_shader_module_to_handle(&vs_m
),
127 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
128 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
129 .module
= radv_shader_module_to_handle(&fs_m
),
133 .pVertexInputState
= vi_state
,
134 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
135 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
136 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
137 .primitiveRestartEnable
= false,
139 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
140 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
144 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
145 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
146 .rasterizerDiscardEnable
= false,
147 .polygonMode
= VK_POLYGON_MODE_FILL
,
148 .cullMode
= VK_CULL_MODE_NONE
,
149 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
150 .depthBiasEnable
= false,
152 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
153 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
154 .rasterizationSamples
= samples
,
155 .sampleShadingEnable
= false,
157 .alphaToCoverageEnable
= false,
158 .alphaToOneEnable
= false,
160 .pDepthStencilState
= ds_state
,
161 .pColorBlendState
= cb_state
,
162 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
168 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
169 .dynamicStateCount
= 8,
170 .pDynamicStates
= (VkDynamicState
[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT
,
173 VK_DYNAMIC_STATE_SCISSOR
,
174 VK_DYNAMIC_STATE_LINE_WIDTH
,
175 VK_DYNAMIC_STATE_DEPTH_BIAS
,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
184 .renderPass
= radv_render_pass_to_handle(render_pass
),
198 create_color_renderpass(struct radv_device
*device
,
203 return radv_CreateRenderPass(radv_device_to_handle(device
),
204 &(VkRenderPassCreateInfo
) {
205 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
206 .attachmentCount
= 1,
207 .pAttachments
= &(VkAttachmentDescription
) {
210 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
211 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
212 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
213 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
216 .pSubpasses
= &(VkSubpassDescription
) {
217 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
218 .inputAttachmentCount
= 0,
219 .colorAttachmentCount
= 1,
220 .pColorAttachments
= &(VkAttachmentReference
) {
222 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
224 .pResolveAttachments
= NULL
,
225 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
226 .attachment
= VK_ATTACHMENT_UNUSED
,
227 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
229 .preserveAttachmentCount
= 1,
230 .pPreserveAttachments
= (uint32_t[]) { 0 },
232 .dependencyCount
= 0,
233 }, &device
->meta_state
.alloc
, pass
);
237 create_color_pipeline(struct radv_device
*device
,
239 uint32_t frag_output
,
240 VkPipeline
*pipeline
,
243 struct nir_shader
*vs_nir
;
244 struct nir_shader
*fs_nir
;
246 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
248 const VkPipelineVertexInputStateCreateInfo vi_state
= {
249 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
250 .vertexBindingDescriptionCount
= 0,
251 .vertexAttributeDescriptionCount
= 0,
254 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
255 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
256 .depthTestEnable
= false,
257 .depthWriteEnable
= false,
258 .depthBoundsTestEnable
= false,
259 .stencilTestEnable
= false,
262 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
263 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
264 .blendEnable
= false,
265 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
266 VK_COLOR_COMPONENT_R_BIT
|
267 VK_COLOR_COMPONENT_G_BIT
|
268 VK_COLOR_COMPONENT_B_BIT
,
271 const VkPipelineColorBlendStateCreateInfo cb_state
= {
272 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
273 .logicOpEnable
= false,
274 .attachmentCount
= MAX_RTS
,
275 .pAttachments
= blend_attachment_state
279 struct radv_graphics_pipeline_create_info extra
= {
280 .use_rectlist
= true,
282 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
283 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
284 device
->meta_state
.clear_color_p_layout
,
285 &extra
, &device
->meta_state
.alloc
, pipeline
);
291 radv_device_finish_meta_clear_state(struct radv_device
*device
)
293 struct radv_meta_state
*state
= &device
->meta_state
;
295 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
296 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
297 radv_DestroyPipeline(radv_device_to_handle(device
),
298 state
->clear
[i
].color_pipelines
[j
],
300 radv_DestroyRenderPass(radv_device_to_handle(device
),
301 state
->clear
[i
].render_pass
[j
],
305 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
306 radv_DestroyPipeline(radv_device_to_handle(device
),
307 state
->clear
[i
].depth_only_pipeline
[j
],
309 radv_DestroyPipeline(radv_device_to_handle(device
),
310 state
->clear
[i
].stencil_only_pipeline
[j
],
312 radv_DestroyPipeline(radv_device_to_handle(device
),
313 state
->clear
[i
].depthstencil_pipeline
[j
],
316 radv_DestroyRenderPass(radv_device_to_handle(device
),
317 state
->clear
[i
].depthstencil_rp
,
320 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
321 state
->clear_color_p_layout
,
323 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
324 state
->clear_depth_p_layout
,
329 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
330 const VkClearAttachment
*clear_att
,
331 const VkClearRect
*clear_rect
,
334 struct radv_device
*device
= cmd_buffer
->device
;
335 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
336 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
337 const uint32_t subpass_att
= clear_att
->colorAttachment
;
338 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
339 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
340 const uint32_t samples
= iview
->image
->info
.samples
;
341 const uint32_t samples_log2
= ffs(samples
) - 1;
342 unsigned fs_key
= radv_format_meta_fs_key(iview
->vk_format
);
343 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
344 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
348 radv_finishme("color clears incomplete");
352 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
354 radv_finishme("color clears incomplete");
357 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
359 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
360 assert(clear_att
->colorAttachment
< subpass
->color_count
);
362 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
363 device
->meta_state
.clear_color_p_layout
,
364 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16,
367 struct radv_subpass clear_subpass
= {
369 .color_attachments
= (VkAttachmentReference
[]) {
370 subpass
->color_attachments
[clear_att
->colorAttachment
]
372 .depth_stencil_attachment
= (VkAttachmentReference
) { VK_ATTACHMENT_UNUSED
, VK_IMAGE_LAYOUT_UNDEFINED
}
375 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
, false);
377 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
380 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
381 .x
= clear_rect
->rect
.offset
.x
,
382 .y
= clear_rect
->rect
.offset
.y
,
383 .width
= clear_rect
->rect
.extent
.width
,
384 .height
= clear_rect
->rect
.extent
.height
,
389 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
393 for_each_bit(i
, view_mask
)
394 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
396 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
399 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
404 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
406 nir_builder vs_b
, fs_b
;
408 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
409 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
411 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
412 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
413 const struct glsl_type
*position_out_type
= glsl_vec4_type();
415 nir_variable
*vs_out_pos
=
416 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_out_type
,
418 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
420 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(vs_b
.shader
, nir_intrinsic_load_push_constant
);
421 nir_intrinsic_set_base(in_color_load
, 0);
422 nir_intrinsic_set_range(in_color_load
, 4);
423 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&vs_b
, 0));
424 in_color_load
->num_components
= 1;
425 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
426 nir_builder_instr_insert(&vs_b
, &in_color_load
->instr
);
428 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices_comp2(&vs_b
, &in_color_load
->dest
.ssa
);
429 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
431 const struct glsl_type
*layer_type
= glsl_int_type();
432 nir_variable
*vs_out_layer
=
433 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
435 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
436 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
437 nir_ssa_def
*inst_id
= nir_load_system_value(&vs_b
, nir_intrinsic_load_instance_id
, 0);
438 nir_ssa_def
*base_instance
= nir_load_system_value(&vs_b
, nir_intrinsic_load_base_instance
, 0);
440 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
441 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
443 *out_vs
= vs_b
.shader
;
444 *out_fs
= fs_b
.shader
;
448 create_depthstencil_renderpass(struct radv_device
*device
,
450 VkRenderPass
*render_pass
)
452 return radv_CreateRenderPass(radv_device_to_handle(device
),
453 &(VkRenderPassCreateInfo
) {
454 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
455 .attachmentCount
= 1,
456 .pAttachments
= &(VkAttachmentDescription
) {
457 .format
= VK_FORMAT_D32_SFLOAT_S8_UINT
,
459 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
460 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
461 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
462 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
465 .pSubpasses
= &(VkSubpassDescription
) {
466 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
467 .inputAttachmentCount
= 0,
468 .colorAttachmentCount
= 0,
469 .pColorAttachments
= NULL
,
470 .pResolveAttachments
= NULL
,
471 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
473 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
475 .preserveAttachmentCount
= 1,
476 .pPreserveAttachments
= (uint32_t[]) { 0 },
478 .dependencyCount
= 0,
479 }, &device
->meta_state
.alloc
, render_pass
);
483 create_depthstencil_pipeline(struct radv_device
*device
,
484 VkImageAspectFlags aspects
,
487 VkPipeline
*pipeline
,
488 VkRenderPass render_pass
)
490 struct nir_shader
*vs_nir
, *fs_nir
;
492 build_depthstencil_shader(&vs_nir
, &fs_nir
);
494 const VkPipelineVertexInputStateCreateInfo vi_state
= {
495 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
496 .vertexBindingDescriptionCount
= 0,
497 .vertexAttributeDescriptionCount
= 0,
500 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
501 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
502 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
503 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
504 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
505 .depthBoundsTestEnable
= false,
506 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
508 .passOp
= VK_STENCIL_OP_REPLACE
,
509 .compareOp
= VK_COMPARE_OP_ALWAYS
,
510 .writeMask
= UINT32_MAX
,
511 .reference
= 0, /* dynamic */
513 .back
= { 0 /* dont care */ },
516 const VkPipelineColorBlendStateCreateInfo cb_state
= {
517 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
518 .logicOpEnable
= false,
519 .attachmentCount
= 0,
520 .pAttachments
= NULL
,
523 struct radv_graphics_pipeline_create_info extra
= {
524 .use_rectlist
= true,
527 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
528 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
529 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
531 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
532 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
533 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
535 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
536 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
537 device
->meta_state
.clear_depth_p_layout
,
538 &extra
, &device
->meta_state
.alloc
, pipeline
);
542 static bool depth_view_can_fast_clear(struct radv_cmd_buffer
*cmd_buffer
,
543 const struct radv_image_view
*iview
,
544 VkImageAspectFlags aspects
,
545 VkImageLayout layout
,
546 const VkClearRect
*clear_rect
,
547 VkClearDepthStencilValue clear_value
)
549 uint32_t queue_mask
= radv_image_queue_family_mask(iview
->image
,
550 cmd_buffer
->queue_family_index
,
551 cmd_buffer
->queue_family_index
);
552 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
553 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
554 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
556 if (radv_image_is_tc_compat_htile(iview
->image
) &&
557 (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) && clear_value
.depth
!= 0.0 &&
558 clear_value
.depth
!= 1.0) ||
559 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) && clear_value
.stencil
!= 0)))
561 if (radv_image_has_htile(iview
->image
) &&
562 iview
->base_mip
== 0 &&
563 iview
->base_layer
== 0 &&
564 radv_layout_is_htile_compressed(iview
->image
, layout
, queue_mask
) &&
565 !radv_image_extent_compare(iview
->image
, &iview
->extent
))
571 pick_depthstencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
572 struct radv_meta_state
*meta_state
,
573 const struct radv_image_view
*iview
,
575 VkImageAspectFlags aspects
,
576 VkImageLayout layout
,
577 const VkClearRect
*clear_rect
,
578 VkClearDepthStencilValue clear_value
)
580 bool fast
= depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
, layout
, clear_rect
, clear_value
);
581 int index
= DEPTH_CLEAR_SLOW
;
584 /* we don't know the previous clear values, so we always have
585 * the NO_EXPCLEAR path */
586 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
590 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
591 return meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
592 case VK_IMAGE_ASPECT_DEPTH_BIT
:
593 return meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
594 case VK_IMAGE_ASPECT_STENCIL_BIT
:
595 return meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
597 unreachable("expected depth or stencil aspect");
601 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
602 const VkClearAttachment
*clear_att
,
603 const VkClearRect
*clear_rect
)
605 struct radv_device
*device
= cmd_buffer
->device
;
606 struct radv_meta_state
*meta_state
= &device
->meta_state
;
607 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
608 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
609 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
610 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
611 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
612 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
613 const uint32_t samples
= iview
->image
->info
.samples
;
614 const uint32_t samples_log2
= ffs(samples
) - 1;
615 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
617 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
619 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
620 clear_value
.depth
= 1.0f
;
622 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
623 device
->meta_state
.clear_depth_p_layout
,
624 VK_SHADER_STAGE_VERTEX_BIT
, 0, 4,
627 uint32_t prev_reference
= cmd_buffer
->state
.dynamic
.stencil_reference
.front
;
628 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
629 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
630 clear_value
.stencil
);
633 VkPipeline pipeline
= pick_depthstencil_pipeline(cmd_buffer
,
638 subpass
->depth_stencil_attachment
.layout
,
642 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
645 if (depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
,
646 subpass
->depth_stencil_attachment
.layout
,
647 clear_rect
, clear_value
))
648 radv_set_depth_clear_regs(cmd_buffer
, iview
->image
, clear_value
, aspects
);
650 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
651 .x
= clear_rect
->rect
.offset
.x
,
652 .y
= clear_rect
->rect
.offset
.y
,
653 .width
= clear_rect
->rect
.extent
.width
,
654 .height
= clear_rect
->rect
.extent
.height
,
659 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
661 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
663 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
664 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
670 emit_fast_htile_clear(struct radv_cmd_buffer
*cmd_buffer
,
671 const VkClearAttachment
*clear_att
,
672 const VkClearRect
*clear_rect
,
673 enum radv_cmd_flush_bits
*pre_flush
,
674 enum radv_cmd_flush_bits
*post_flush
)
676 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
677 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
678 VkImageLayout image_layout
= subpass
->depth_stencil_attachment
.layout
;
679 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
680 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
681 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
682 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
683 uint32_t clear_word
, flush_bits
;
685 if (!radv_image_has_htile(iview
->image
))
688 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
691 if (!radv_layout_is_htile_compressed(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
694 /* don't fast clear 3D */
695 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
698 /* all layers are bound */
699 if (iview
->base_layer
> 0)
701 if (iview
->image
->info
.array_size
!= iview
->layer_count
)
704 if (!radv_image_extent_compare(iview
->image
, &iview
->extent
))
707 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
708 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
709 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
712 if (clear_rect
->baseArrayLayer
!= 0)
714 if (clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
717 if ((clear_value
.depth
!= 0.0 && clear_value
.depth
!= 1.0) || !(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
720 if (vk_format_aspects(iview
->image
->vk_format
) & VK_IMAGE_ASPECT_STENCIL_BIT
) {
721 if (clear_value
.stencil
!= 0 || !(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
))
723 clear_word
= clear_value
.depth
? 0xfffc0000 : 0;
725 clear_word
= clear_value
.depth
? 0xfffffff0 : 0;
728 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
729 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) & ~ *pre_flush
;
730 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
732 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
733 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
735 flush_bits
= radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
736 iview
->image
->offset
+ iview
->image
->htile_offset
,
737 iview
->image
->surface
.htile_size
, clear_word
);
739 radv_set_depth_clear_regs(cmd_buffer
, iview
->image
, clear_value
, aspects
);
741 *post_flush
|= flush_bits
;
743 cmd_buffer
->state
.flush_bits
|= flush_bits
;
751 static VkFormat pipeline_formats
[] = {
752 VK_FORMAT_R8G8B8A8_UNORM
,
753 VK_FORMAT_R8G8B8A8_UINT
,
754 VK_FORMAT_R8G8B8A8_SINT
,
755 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
756 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
757 VK_FORMAT_R16G16B16A16_UNORM
,
758 VK_FORMAT_R16G16B16A16_SNORM
,
759 VK_FORMAT_R16G16B16A16_UINT
,
760 VK_FORMAT_R16G16B16A16_SINT
,
761 VK_FORMAT_R32_SFLOAT
,
762 VK_FORMAT_R32G32_SFLOAT
,
763 VK_FORMAT_R32G32B32A32_SFLOAT
767 radv_device_init_meta_clear_state(struct radv_device
*device
)
770 struct radv_meta_state
*state
= &device
->meta_state
;
772 VkPipelineLayoutCreateInfo pl_color_create_info
= {
773 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
775 .pushConstantRangeCount
= 1,
776 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16},
779 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
780 &pl_color_create_info
,
781 &device
->meta_state
.alloc
,
782 &device
->meta_state
.clear_color_p_layout
);
783 if (res
!= VK_SUCCESS
)
786 VkPipelineLayoutCreateInfo pl_depth_create_info
= {
787 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
789 .pushConstantRangeCount
= 1,
790 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_VERTEX_BIT
, 0, 4},
793 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
794 &pl_depth_create_info
,
795 &device
->meta_state
.alloc
,
796 &device
->meta_state
.clear_depth_p_layout
);
797 if (res
!= VK_SUCCESS
)
800 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
801 uint32_t samples
= 1 << i
;
802 for (uint32_t j
= 0; j
< ARRAY_SIZE(pipeline_formats
); ++j
) {
803 VkFormat format
= pipeline_formats
[j
];
804 unsigned fs_key
= radv_format_meta_fs_key(format
);
805 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
807 res
= create_color_renderpass(device
, format
, samples
,
808 &state
->clear
[i
].render_pass
[fs_key
]);
809 if (res
!= VK_SUCCESS
)
812 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
813 state
->clear
[i
].render_pass
[fs_key
]);
814 if (res
!= VK_SUCCESS
)
819 res
= create_depthstencil_renderpass(device
,
821 &state
->clear
[i
].depthstencil_rp
);
822 if (res
!= VK_SUCCESS
)
825 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
826 res
= create_depthstencil_pipeline(device
,
827 VK_IMAGE_ASPECT_DEPTH_BIT
,
830 &state
->clear
[i
].depth_only_pipeline
[j
],
831 state
->clear
[i
].depthstencil_rp
);
832 if (res
!= VK_SUCCESS
)
835 res
= create_depthstencil_pipeline(device
,
836 VK_IMAGE_ASPECT_STENCIL_BIT
,
839 &state
->clear
[i
].stencil_only_pipeline
[j
],
840 state
->clear
[i
].depthstencil_rp
);
841 if (res
!= VK_SUCCESS
)
844 res
= create_depthstencil_pipeline(device
,
845 VK_IMAGE_ASPECT_DEPTH_BIT
|
846 VK_IMAGE_ASPECT_STENCIL_BIT
,
849 &state
->clear
[i
].depthstencil_pipeline
[j
],
850 state
->clear
[i
].depthstencil_rp
);
851 if (res
!= VK_SUCCESS
)
858 radv_device_finish_meta_clear_state(device
);
863 radv_get_cmask_fast_clear_value(const struct radv_image
*image
)
865 uint32_t value
= 0; /* Default value when no DCC. */
867 /* The fast-clear value is different for images that have both DCC and
870 if (radv_image_has_dcc(image
)) {
871 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
872 return image
->info
.samples
> 1 ? 0xcccccccc : 0xffffffff;
879 radv_clear_cmask(struct radv_cmd_buffer
*cmd_buffer
,
880 struct radv_image
*image
, uint32_t value
)
882 return radv_fill_buffer(cmd_buffer
, image
->bo
,
883 image
->offset
+ image
->cmask
.offset
,
884 image
->cmask
.size
, value
);
888 radv_clear_dcc(struct radv_cmd_buffer
*cmd_buffer
,
889 struct radv_image
*image
, uint32_t value
)
891 return radv_fill_buffer(cmd_buffer
, image
->bo
,
892 image
->offset
+ image
->dcc_offset
,
893 image
->surface
.dcc_size
, value
);
896 static void vi_get_fast_clear_parameters(VkFormat format
,
897 const VkClearColorValue
*clear_value
,
898 uint32_t* reset_value
,
899 bool *can_avoid_fast_clear_elim
)
903 bool main_value
= false;
904 bool extra_value
= false;
906 *can_avoid_fast_clear_elim
= false;
908 *reset_value
= 0x20202020U
;
910 const struct vk_format_description
*desc
= vk_format_description(format
);
911 if (format
== VK_FORMAT_B10G11R11_UFLOAT_PACK32
||
912 format
== VK_FORMAT_R5G6B5_UNORM_PACK16
||
913 format
== VK_FORMAT_B5G6R5_UNORM_PACK16
)
915 else if (desc
->layout
== VK_FORMAT_LAYOUT_PLAIN
) {
916 if (radv_translate_colorswap(format
, false) <= 1)
917 extra_channel
= desc
->nr_channels
- 1;
923 for (i
= 0; i
< 4; i
++) {
924 int index
= desc
->swizzle
[i
] - VK_SWIZZLE_X
;
925 if (desc
->swizzle
[i
] < VK_SWIZZLE_X
||
926 desc
->swizzle
[i
] > VK_SWIZZLE_W
)
929 if (desc
->channel
[i
].pure_integer
&&
930 desc
->channel
[i
].type
== VK_FORMAT_TYPE_SIGNED
) {
931 /* Use the maximum value for clamping the clear color. */
932 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
934 values
[i
] = clear_value
->int32
[i
] != 0;
935 if (clear_value
->int32
[i
] != 0 && MIN2(clear_value
->int32
[i
], max
) != max
)
937 } else if (desc
->channel
[i
].pure_integer
&&
938 desc
->channel
[i
].type
== VK_FORMAT_TYPE_UNSIGNED
) {
939 /* Use the maximum value for clamping the clear color. */
940 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
942 values
[i
] = clear_value
->uint32
[i
] != 0U;
943 if (clear_value
->uint32
[i
] != 0U && MIN2(clear_value
->uint32
[i
], max
) != max
)
946 values
[i
] = clear_value
->float32
[i
] != 0.0F
;
947 if (clear_value
->float32
[i
] != 0.0F
&& clear_value
->float32
[i
] != 1.0F
)
951 if (index
== extra_channel
)
952 extra_value
= values
[i
];
954 main_value
= values
[i
];
957 for (int i
= 0; i
< 4; ++i
)
958 if (values
[i
] != main_value
&&
959 desc
->swizzle
[i
] - VK_SWIZZLE_X
!= extra_channel
&&
960 desc
->swizzle
[i
] >= VK_SWIZZLE_X
&&
961 desc
->swizzle
[i
] <= VK_SWIZZLE_W
)
964 *can_avoid_fast_clear_elim
= true;
966 *reset_value
|= 0x80808080U
;
969 *reset_value
|= 0x40404040U
;
974 emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
975 const VkClearAttachment
*clear_att
,
976 const VkClearRect
*clear_rect
,
977 enum radv_cmd_flush_bits
*pre_flush
,
978 enum radv_cmd_flush_bits
*post_flush
,
981 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
982 const uint32_t subpass_att
= clear_att
->colorAttachment
;
983 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
984 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
985 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
986 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
987 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
988 uint32_t clear_color
[2], flush_bits
;
989 uint32_t cmask_clear_value
;
992 if (!radv_image_has_cmask(iview
->image
) && !radv_image_has_dcc(iview
->image
))
995 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
998 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
1001 /* don't fast clear 3D */
1002 if (iview
->image
->type
== VK_IMAGE_TYPE_3D
)
1005 /* all layers are bound */
1006 if (iview
->base_layer
> 0)
1008 if (iview
->image
->info
.array_size
!= iview
->layer_count
)
1011 if (iview
->image
->info
.levels
> 1)
1014 if (iview
->image
->surface
.is_linear
)
1016 if (!radv_image_extent_compare(iview
->image
, &iview
->extent
))
1019 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
1020 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
1021 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1024 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1025 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1027 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1029 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1032 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1033 if (!radv_image_has_dcc(iview
->image
) &&
1034 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_STONEY
)
1038 ret
= radv_format_pack_clear_color(iview
->image
->vk_format
,
1039 clear_color
, &clear_value
);
1044 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1045 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
1046 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1048 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1049 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
1051 cmask_clear_value
= radv_get_cmask_fast_clear_value(iview
->image
);
1053 /* clear cmask buffer */
1054 if (radv_image_has_dcc(iview
->image
)) {
1055 uint32_t reset_value
;
1056 bool can_avoid_fast_clear_elim
;
1057 bool need_decompress_pass
= false;
1059 vi_get_fast_clear_parameters(iview
->image
->vk_format
,
1060 &clear_value
, &reset_value
,
1061 &can_avoid_fast_clear_elim
);
1063 if (iview
->image
->info
.samples
> 1) {
1064 /* DCC fast clear with MSAA should clear CMASK. */
1065 assert(radv_image_has_cmask(iview
->image
));
1067 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1070 need_decompress_pass
= true;
1073 if (!can_avoid_fast_clear_elim
)
1074 need_decompress_pass
= true;
1076 flush_bits
= radv_clear_dcc(cmd_buffer
, iview
->image
, reset_value
);
1078 radv_set_dcc_need_cmask_elim_pred(cmd_buffer
, iview
->image
,
1079 need_decompress_pass
);
1081 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1086 *post_flush
|= flush_bits
;
1088 cmd_buffer
->state
.flush_bits
|= flush_bits
;
1091 radv_set_color_clear_regs(cmd_buffer
, iview
->image
, subpass_att
, clear_color
);
1099 * The parameters mean that same as those in vkCmdClearAttachments.
1102 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
1103 const VkClearAttachment
*clear_att
,
1104 const VkClearRect
*clear_rect
,
1105 enum radv_cmd_flush_bits
*pre_flush
,
1106 enum radv_cmd_flush_bits
*post_flush
,
1109 if (clear_att
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1110 if (!emit_fast_color_clear(cmd_buffer
, clear_att
, clear_rect
,
1111 pre_flush
, post_flush
, view_mask
))
1112 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
, view_mask
);
1114 assert(clear_att
->aspectMask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1115 VK_IMAGE_ASPECT_STENCIL_BIT
));
1116 if (!emit_fast_htile_clear(cmd_buffer
, clear_att
, clear_rect
,
1117 pre_flush
, post_flush
))
1118 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
);
1123 radv_attachment_needs_clear(struct radv_cmd_state
*cmd_state
, uint32_t a
)
1125 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1126 return (a
!= VK_ATTACHMENT_UNUSED
&&
1127 cmd_state
->attachments
[a
].pending_clear_aspects
&&
1128 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[a
].cleared_views
)));
1132 radv_subpass_needs_clear(struct radv_cmd_buffer
*cmd_buffer
)
1134 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1137 if (!cmd_state
->subpass
)
1140 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1141 a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1142 if (radv_attachment_needs_clear(cmd_state
, a
))
1146 a
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1147 return radv_attachment_needs_clear(cmd_state
, a
);
1151 radv_subpass_clear_attachment(struct radv_cmd_buffer
*cmd_buffer
,
1152 struct radv_attachment_state
*attachment
,
1153 const VkClearAttachment
*clear_att
,
1154 enum radv_cmd_flush_bits
*pre_flush
,
1155 enum radv_cmd_flush_bits
*post_flush
)
1157 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1158 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1160 VkClearRect clear_rect
= {
1161 .rect
= cmd_state
->render_area
,
1162 .baseArrayLayer
= 0,
1163 .layerCount
= cmd_state
->framebuffer
->layers
,
1166 emit_clear(cmd_buffer
, clear_att
, &clear_rect
, pre_flush
, post_flush
,
1167 view_mask
& ~attachment
->cleared_views
);
1169 attachment
->cleared_views
|= view_mask
;
1171 attachment
->pending_clear_aspects
= 0;
1175 * Emit any pending attachment clears for the current subpass.
1177 * @see radv_attachment_state::pending_clear_aspects
1180 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
1182 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1183 struct radv_meta_saved_state saved_state
;
1184 enum radv_cmd_flush_bits pre_flush
= 0;
1185 enum radv_cmd_flush_bits post_flush
= 0;
1187 if (!radv_subpass_needs_clear(cmd_buffer
))
1190 radv_meta_save(&saved_state
, cmd_buffer
,
1191 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1192 RADV_META_SAVE_CONSTANTS
);
1194 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1195 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1197 if (!radv_attachment_needs_clear(cmd_state
, a
))
1200 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1201 VK_IMAGE_ASPECT_COLOR_BIT
);
1203 VkClearAttachment clear_att
= {
1204 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1205 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1206 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1209 radv_subpass_clear_attachment(cmd_buffer
,
1210 &cmd_state
->attachments
[a
],
1211 &clear_att
, &pre_flush
,
1215 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1216 if (radv_attachment_needs_clear(cmd_state
, ds
)) {
1217 VkClearAttachment clear_att
= {
1218 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1219 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1222 radv_subpass_clear_attachment(cmd_buffer
,
1223 &cmd_state
->attachments
[ds
],
1224 &clear_att
, &pre_flush
,
1228 radv_meta_restore(&saved_state
, cmd_buffer
);
1229 cmd_buffer
->state
.flush_bits
|= post_flush
;
1233 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
1234 struct radv_image
*image
,
1235 VkImageLayout image_layout
,
1236 const VkImageSubresourceRange
*range
,
1237 VkFormat format
, int level
, int layer
,
1238 const VkClearValue
*clear_val
)
1240 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
1241 struct radv_image_view iview
;
1242 uint32_t width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
1243 uint32_t height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
1245 radv_image_view_init(&iview
, cmd_buffer
->device
,
1246 &(VkImageViewCreateInfo
) {
1247 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1248 .image
= radv_image_to_handle(image
),
1249 .viewType
= radv_meta_get_view_type(image
),
1251 .subresourceRange
= {
1252 .aspectMask
= range
->aspectMask
,
1253 .baseMipLevel
= range
->baseMipLevel
+ level
,
1255 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
1261 radv_CreateFramebuffer(device_h
,
1262 &(VkFramebufferCreateInfo
) {
1263 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1264 .attachmentCount
= 1,
1265 .pAttachments
= (VkImageView
[]) {
1266 radv_image_view_to_handle(&iview
),
1272 &cmd_buffer
->pool
->alloc
,
1275 VkAttachmentDescription att_desc
= {
1276 .format
= iview
.vk_format
,
1277 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1278 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1279 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1280 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1281 .initialLayout
= image_layout
,
1282 .finalLayout
= image_layout
,
1285 VkSubpassDescription subpass_desc
= {
1286 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1287 .inputAttachmentCount
= 0,
1288 .colorAttachmentCount
= 0,
1289 .pColorAttachments
= NULL
,
1290 .pResolveAttachments
= NULL
,
1291 .pDepthStencilAttachment
= NULL
,
1292 .preserveAttachmentCount
= 0,
1293 .pPreserveAttachments
= NULL
,
1296 const VkAttachmentReference att_ref
= {
1298 .layout
= image_layout
,
1301 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1302 subpass_desc
.colorAttachmentCount
= 1;
1303 subpass_desc
.pColorAttachments
= &att_ref
;
1305 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1309 radv_CreateRenderPass(device_h
,
1310 &(VkRenderPassCreateInfo
) {
1311 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1312 .attachmentCount
= 1,
1313 .pAttachments
= &att_desc
,
1315 .pSubpasses
= &subpass_desc
,
1317 &cmd_buffer
->pool
->alloc
,
1320 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1321 &(VkRenderPassBeginInfo
) {
1322 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1324 .offset
= { 0, 0, },
1332 .clearValueCount
= 0,
1333 .pClearValues
= NULL
,
1335 VK_SUBPASS_CONTENTS_INLINE
);
1337 VkClearAttachment clear_att
= {
1338 .aspectMask
= range
->aspectMask
,
1339 .colorAttachment
= 0,
1340 .clearValue
= *clear_val
,
1343 VkClearRect clear_rect
= {
1346 .extent
= { width
, height
},
1348 .baseArrayLayer
= range
->baseArrayLayer
,
1349 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1352 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
, 0);
1354 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1355 radv_DestroyRenderPass(device_h
, pass
,
1356 &cmd_buffer
->pool
->alloc
);
1357 radv_DestroyFramebuffer(device_h
, fb
,
1358 &cmd_buffer
->pool
->alloc
);
1361 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
1362 struct radv_image
*image
,
1363 VkImageLayout image_layout
,
1364 const VkClearValue
*clear_value
,
1365 uint32_t range_count
,
1366 const VkImageSubresourceRange
*ranges
,
1369 VkFormat format
= image
->vk_format
;
1370 VkClearValue internal_clear_value
= *clear_value
;
1372 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
1374 format
= VK_FORMAT_R32_UINT
;
1375 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
1376 internal_clear_value
.color
.uint32
[0] = value
;
1379 if (format
== VK_FORMAT_R4G4_UNORM_PACK8
) {
1381 format
= VK_FORMAT_R8_UINT
;
1382 r
= float_to_ubyte(clear_value
->color
.float32
[0]) >> 4;
1383 g
= float_to_ubyte(clear_value
->color
.float32
[1]) >> 4;
1384 internal_clear_value
.color
.uint32
[0] = (r
<< 4) | (g
& 0xf);
1387 for (uint32_t r
= 0; r
< range_count
; r
++) {
1388 const VkImageSubresourceRange
*range
= &ranges
[r
];
1389 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1390 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1391 radv_minify(image
->info
.depth
, range
->baseMipLevel
+ l
) :
1392 radv_get_layerCount(image
, range
);
1393 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1396 struct radv_meta_blit2d_surf surf
;
1397 surf
.format
= format
;
1399 surf
.level
= range
->baseMipLevel
+ l
;
1400 surf
.layer
= range
->baseArrayLayer
+ s
;
1401 surf
.aspect_mask
= range
->aspectMask
;
1402 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
1403 &internal_clear_value
.color
);
1405 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
1406 range
, format
, l
, s
, &internal_clear_value
);
1413 void radv_CmdClearColorImage(
1414 VkCommandBuffer commandBuffer
,
1416 VkImageLayout imageLayout
,
1417 const VkClearColorValue
* pColor
,
1418 uint32_t rangeCount
,
1419 const VkImageSubresourceRange
* pRanges
)
1421 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1422 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1423 struct radv_meta_saved_state saved_state
;
1424 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1427 radv_meta_save(&saved_state
, cmd_buffer
,
1428 RADV_META_SAVE_COMPUTE_PIPELINE
|
1429 RADV_META_SAVE_CONSTANTS
|
1430 RADV_META_SAVE_DESCRIPTORS
);
1432 radv_meta_save(&saved_state
, cmd_buffer
,
1433 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1434 RADV_META_SAVE_CONSTANTS
);
1437 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1438 (const VkClearValue
*) pColor
,
1439 rangeCount
, pRanges
, cs
);
1441 radv_meta_restore(&saved_state
, cmd_buffer
);
1444 void radv_CmdClearDepthStencilImage(
1445 VkCommandBuffer commandBuffer
,
1447 VkImageLayout imageLayout
,
1448 const VkClearDepthStencilValue
* pDepthStencil
,
1449 uint32_t rangeCount
,
1450 const VkImageSubresourceRange
* pRanges
)
1452 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1453 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1454 struct radv_meta_saved_state saved_state
;
1456 radv_meta_save(&saved_state
, cmd_buffer
,
1457 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1458 RADV_META_SAVE_CONSTANTS
);
1460 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1461 (const VkClearValue
*) pDepthStencil
,
1462 rangeCount
, pRanges
, false);
1464 radv_meta_restore(&saved_state
, cmd_buffer
);
1467 void radv_CmdClearAttachments(
1468 VkCommandBuffer commandBuffer
,
1469 uint32_t attachmentCount
,
1470 const VkClearAttachment
* pAttachments
,
1472 const VkClearRect
* pRects
)
1474 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1475 struct radv_meta_saved_state saved_state
;
1476 enum radv_cmd_flush_bits pre_flush
= 0;
1477 enum radv_cmd_flush_bits post_flush
= 0;
1479 if (!cmd_buffer
->state
.subpass
)
1482 radv_meta_save(&saved_state
, cmd_buffer
,
1483 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1484 RADV_META_SAVE_CONSTANTS
);
1486 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1489 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1490 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1491 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
,
1492 cmd_buffer
->state
.subpass
->view_mask
);
1496 radv_meta_restore(&saved_state
, cmd_buffer
);
1497 cmd_buffer
->state
.flush_bits
|= post_flush
;