2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
34 DEPTH_CLEAR_FAST_EXPCLEAR
,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
39 build_color_shaders(struct nir_shader
**out_vs
,
40 struct nir_shader
**out_fs
,
46 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
47 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
49 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
50 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
52 const struct glsl_type
*position_type
= glsl_vec4_type();
53 const struct glsl_type
*color_type
= glsl_vec4_type();
55 nir_variable
*vs_out_pos
=
56 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
58 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
60 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
61 nir_intrinsic_set_base(in_color_load
, 0);
62 nir_intrinsic_set_range(in_color_load
, 16);
63 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
64 in_color_load
->num_components
= 4;
65 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
68 nir_variable
*fs_out_color
=
69 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
71 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
73 nir_store_var(&fs_b
, fs_out_color
, &in_color_load
->dest
.ssa
, 0xf);
75 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&vs_b
);
76 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
78 const struct glsl_type
*layer_type
= glsl_int_type();
79 nir_variable
*vs_out_layer
=
80 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
82 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
83 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
84 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
85 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
87 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
88 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
90 *out_vs
= vs_b
.shader
;
91 *out_fs
= fs_b
.shader
;
95 create_pipeline(struct radv_device
*device
,
96 struct radv_render_pass
*render_pass
,
98 struct nir_shader
*vs_nir
,
99 struct nir_shader
*fs_nir
,
100 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
101 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
102 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
103 const VkPipelineLayout layout
,
104 const struct radv_graphics_pipeline_create_info
*extra
,
105 const VkAllocationCallbacks
*alloc
,
106 VkPipeline
*pipeline
)
108 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
112 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
114 result
= radv_graphics_pipeline_create(device_h
,
115 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
116 &(VkGraphicsPipelineCreateInfo
) {
117 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
118 .stageCount
= fs_nir
? 2 : 1,
119 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
121 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
122 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
123 .module
= radv_shader_module_to_handle(&vs_m
),
127 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
128 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
129 .module
= radv_shader_module_to_handle(&fs_m
),
133 .pVertexInputState
= vi_state
,
134 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
135 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
136 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
137 .primitiveRestartEnable
= false,
139 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
140 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
144 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
145 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
146 .rasterizerDiscardEnable
= false,
147 .polygonMode
= VK_POLYGON_MODE_FILL
,
148 .cullMode
= VK_CULL_MODE_NONE
,
149 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
150 .depthBiasEnable
= false,
152 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
153 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
154 .rasterizationSamples
= samples
,
155 .sampleShadingEnable
= false,
157 .alphaToCoverageEnable
= false,
158 .alphaToOneEnable
= false,
160 .pDepthStencilState
= ds_state
,
161 .pColorBlendState
= cb_state
,
162 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
168 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
169 .dynamicStateCount
= 8,
170 .pDynamicStates
= (VkDynamicState
[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT
,
173 VK_DYNAMIC_STATE_SCISSOR
,
174 VK_DYNAMIC_STATE_LINE_WIDTH
,
175 VK_DYNAMIC_STATE_DEPTH_BIAS
,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
184 .renderPass
= radv_render_pass_to_handle(render_pass
),
198 create_color_renderpass(struct radv_device
*device
,
203 mtx_lock(&device
->meta_state
.mtx
);
205 mtx_unlock (&device
->meta_state
.mtx
);
209 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
210 &(VkRenderPassCreateInfo
) {
211 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
212 .attachmentCount
= 1,
213 .pAttachments
= &(VkAttachmentDescription
) {
216 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
217 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
218 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
219 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
222 .pSubpasses
= &(VkSubpassDescription
) {
223 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
224 .inputAttachmentCount
= 0,
225 .colorAttachmentCount
= 1,
226 .pColorAttachments
= &(VkAttachmentReference
) {
228 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
230 .pResolveAttachments
= NULL
,
231 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
232 .attachment
= VK_ATTACHMENT_UNUSED
,
233 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
235 .preserveAttachmentCount
= 1,
236 .pPreserveAttachments
= (uint32_t[]) { 0 },
238 .dependencyCount
= 0,
239 }, &device
->meta_state
.alloc
, pass
);
240 mtx_unlock(&device
->meta_state
.mtx
);
245 create_color_pipeline(struct radv_device
*device
,
247 uint32_t frag_output
,
248 VkPipeline
*pipeline
,
251 struct nir_shader
*vs_nir
;
252 struct nir_shader
*fs_nir
;
255 mtx_lock(&device
->meta_state
.mtx
);
257 mtx_unlock(&device
->meta_state
.mtx
);
261 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
263 const VkPipelineVertexInputStateCreateInfo vi_state
= {
264 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
265 .vertexBindingDescriptionCount
= 0,
266 .vertexAttributeDescriptionCount
= 0,
269 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
270 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
271 .depthTestEnable
= false,
272 .depthWriteEnable
= false,
273 .depthBoundsTestEnable
= false,
274 .stencilTestEnable
= false,
277 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
278 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
279 .blendEnable
= false,
280 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
281 VK_COLOR_COMPONENT_R_BIT
|
282 VK_COLOR_COMPONENT_G_BIT
|
283 VK_COLOR_COMPONENT_B_BIT
,
286 const VkPipelineColorBlendStateCreateInfo cb_state
= {
287 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
288 .logicOpEnable
= false,
289 .attachmentCount
= MAX_RTS
,
290 .pAttachments
= blend_attachment_state
294 struct radv_graphics_pipeline_create_info extra
= {
295 .use_rectlist
= true,
297 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
298 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
299 device
->meta_state
.clear_color_p_layout
,
300 &extra
, &device
->meta_state
.alloc
, pipeline
);
302 mtx_unlock(&device
->meta_state
.mtx
);
307 finish_meta_clear_htile_mask_state(struct radv_device
*device
)
309 struct radv_meta_state
*state
= &device
->meta_state
;
311 radv_DestroyPipeline(radv_device_to_handle(device
),
312 state
->clear_htile_mask_pipeline
,
314 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
315 state
->clear_htile_mask_p_layout
,
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
318 state
->clear_htile_mask_ds_layout
,
323 radv_device_finish_meta_clear_state(struct radv_device
*device
)
325 struct radv_meta_state
*state
= &device
->meta_state
;
327 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
328 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
329 radv_DestroyPipeline(radv_device_to_handle(device
),
330 state
->clear
[i
].color_pipelines
[j
],
332 radv_DestroyRenderPass(radv_device_to_handle(device
),
333 state
->clear
[i
].render_pass
[j
],
337 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
338 radv_DestroyPipeline(radv_device_to_handle(device
),
339 state
->clear
[i
].depth_only_pipeline
[j
],
341 radv_DestroyPipeline(radv_device_to_handle(device
),
342 state
->clear
[i
].stencil_only_pipeline
[j
],
344 radv_DestroyPipeline(radv_device_to_handle(device
),
345 state
->clear
[i
].depthstencil_pipeline
[j
],
348 radv_DestroyRenderPass(radv_device_to_handle(device
),
349 state
->clear
[i
].depthstencil_rp
,
352 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
353 state
->clear_color_p_layout
,
355 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
356 state
->clear_depth_p_layout
,
359 finish_meta_clear_htile_mask_state(device
);
363 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
364 const VkClearAttachment
*clear_att
,
365 const VkClearRect
*clear_rect
,
368 struct radv_device
*device
= cmd_buffer
->device
;
369 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
370 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
371 const uint32_t subpass_att
= clear_att
->colorAttachment
;
372 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
373 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
374 const uint32_t samples
= iview
->image
->info
.samples
;
375 const uint32_t samples_log2
= ffs(samples
) - 1;
376 unsigned fs_key
= radv_format_meta_fs_key(iview
->vk_format
);
377 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
378 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
382 radv_finishme("color clears incomplete");
386 if (device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
] == VK_NULL_HANDLE
) {
387 VkResult ret
= create_color_renderpass(device
, radv_fs_key_format_exemplars
[fs_key
],
389 &device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
390 if (ret
!= VK_SUCCESS
) {
391 cmd_buffer
->record_result
= ret
;
396 if (device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
] == VK_NULL_HANDLE
) {
397 VkResult ret
= create_color_pipeline(device
, samples
, 0,
398 &device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
],
399 device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
400 if (ret
!= VK_SUCCESS
) {
401 cmd_buffer
->record_result
= ret
;
406 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
408 radv_finishme("color clears incomplete");
411 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
413 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
414 assert(clear_att
->colorAttachment
< subpass
->color_count
);
416 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
417 device
->meta_state
.clear_color_p_layout
,
418 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16,
421 struct radv_subpass clear_subpass
= {
423 .color_attachments
= (struct radv_subpass_attachment
[]) {
424 subpass
->color_attachments
[clear_att
->colorAttachment
]
426 .depth_stencil_attachment
= (struct radv_subpass_attachment
) { VK_ATTACHMENT_UNUSED
, VK_IMAGE_LAYOUT_UNDEFINED
}
429 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
, false);
431 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
434 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
435 .x
= clear_rect
->rect
.offset
.x
,
436 .y
= clear_rect
->rect
.offset
.y
,
437 .width
= clear_rect
->rect
.extent
.width
,
438 .height
= clear_rect
->rect
.extent
.height
,
443 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
447 for_each_bit(i
, view_mask
)
448 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
450 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
453 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
, false);
458 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
460 nir_builder vs_b
, fs_b
;
462 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
463 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
465 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
466 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
467 const struct glsl_type
*position_out_type
= glsl_vec4_type();
469 nir_variable
*vs_out_pos
=
470 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_out_type
,
472 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
474 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(vs_b
.shader
, nir_intrinsic_load_push_constant
);
475 nir_intrinsic_set_base(in_color_load
, 0);
476 nir_intrinsic_set_range(in_color_load
, 4);
477 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&vs_b
, 0));
478 in_color_load
->num_components
= 1;
479 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
480 nir_builder_instr_insert(&vs_b
, &in_color_load
->instr
);
482 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices_comp2(&vs_b
, &in_color_load
->dest
.ssa
);
483 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
485 const struct glsl_type
*layer_type
= glsl_int_type();
486 nir_variable
*vs_out_layer
=
487 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
489 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
490 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
491 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
492 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
494 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
495 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
497 *out_vs
= vs_b
.shader
;
498 *out_fs
= fs_b
.shader
;
502 create_depthstencil_renderpass(struct radv_device
*device
,
504 VkRenderPass
*render_pass
)
506 mtx_lock(&device
->meta_state
.mtx
);
508 mtx_unlock(&device
->meta_state
.mtx
);
512 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
513 &(VkRenderPassCreateInfo
) {
514 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
515 .attachmentCount
= 1,
516 .pAttachments
= &(VkAttachmentDescription
) {
517 .format
= VK_FORMAT_D32_SFLOAT_S8_UINT
,
519 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
520 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
521 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
522 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
525 .pSubpasses
= &(VkSubpassDescription
) {
526 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
527 .inputAttachmentCount
= 0,
528 .colorAttachmentCount
= 0,
529 .pColorAttachments
= NULL
,
530 .pResolveAttachments
= NULL
,
531 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
533 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
535 .preserveAttachmentCount
= 1,
536 .pPreserveAttachments
= (uint32_t[]) { 0 },
538 .dependencyCount
= 0,
539 }, &device
->meta_state
.alloc
, render_pass
);
540 mtx_unlock(&device
->meta_state
.mtx
);
545 create_depthstencil_pipeline(struct radv_device
*device
,
546 VkImageAspectFlags aspects
,
549 VkPipeline
*pipeline
,
550 VkRenderPass render_pass
)
552 struct nir_shader
*vs_nir
, *fs_nir
;
555 mtx_lock(&device
->meta_state
.mtx
);
557 mtx_unlock(&device
->meta_state
.mtx
);
561 build_depthstencil_shader(&vs_nir
, &fs_nir
);
563 const VkPipelineVertexInputStateCreateInfo vi_state
= {
564 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
565 .vertexBindingDescriptionCount
= 0,
566 .vertexAttributeDescriptionCount
= 0,
569 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
570 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
571 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
572 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
573 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
574 .depthBoundsTestEnable
= false,
575 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
577 .passOp
= VK_STENCIL_OP_REPLACE
,
578 .compareOp
= VK_COMPARE_OP_ALWAYS
,
579 .writeMask
= UINT32_MAX
,
580 .reference
= 0, /* dynamic */
582 .back
= { 0 /* dont care */ },
585 const VkPipelineColorBlendStateCreateInfo cb_state
= {
586 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
587 .logicOpEnable
= false,
588 .attachmentCount
= 0,
589 .pAttachments
= NULL
,
592 struct radv_graphics_pipeline_create_info extra
= {
593 .use_rectlist
= true,
596 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
597 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
598 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
600 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
601 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
602 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
604 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
605 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
606 device
->meta_state
.clear_depth_p_layout
,
607 &extra
, &device
->meta_state
.alloc
, pipeline
);
609 mtx_unlock(&device
->meta_state
.mtx
);
613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer
*cmd_buffer
,
614 const struct radv_image_view
*iview
,
615 VkImageAspectFlags aspects
,
616 VkImageLayout layout
,
617 const VkClearRect
*clear_rect
,
618 VkClearDepthStencilValue clear_value
)
620 uint32_t queue_mask
= radv_image_queue_family_mask(iview
->image
,
621 cmd_buffer
->queue_family_index
,
622 cmd_buffer
->queue_family_index
);
623 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
624 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
625 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
627 if (radv_image_is_tc_compat_htile(iview
->image
) &&
628 (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) && clear_value
.depth
!= 0.0 &&
629 clear_value
.depth
!= 1.0) ||
630 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) && clear_value
.stencil
!= 0)))
632 if (radv_image_has_htile(iview
->image
) &&
633 iview
->base_mip
== 0 &&
634 iview
->base_layer
== 0 &&
635 radv_layout_is_htile_compressed(iview
->image
, layout
, queue_mask
) &&
636 !radv_image_extent_compare(iview
->image
, &iview
->extent
))
642 pick_depthstencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
643 struct radv_meta_state
*meta_state
,
644 const struct radv_image_view
*iview
,
646 VkImageAspectFlags aspects
,
647 VkImageLayout layout
,
648 const VkClearRect
*clear_rect
,
649 VkClearDepthStencilValue clear_value
)
651 bool fast
= depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
, layout
, clear_rect
, clear_value
);
652 int index
= DEPTH_CLEAR_SLOW
;
653 VkPipeline
*pipeline
;
656 /* we don't know the previous clear values, so we always have
657 * the NO_EXPCLEAR path */
658 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
662 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
663 pipeline
= &meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
665 case VK_IMAGE_ASPECT_DEPTH_BIT
:
666 pipeline
= &meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
668 case VK_IMAGE_ASPECT_STENCIL_BIT
:
669 pipeline
= &meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
672 unreachable("expected depth or stencil aspect");
675 if (cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
== VK_NULL_HANDLE
) {
676 VkResult ret
= create_depthstencil_renderpass(cmd_buffer
->device
, 1u << samples_log2
,
677 &cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
678 if (ret
!= VK_SUCCESS
) {
679 cmd_buffer
->record_result
= ret
;
680 return VK_NULL_HANDLE
;
684 if (*pipeline
== VK_NULL_HANDLE
) {
685 VkResult ret
= create_depthstencil_pipeline(cmd_buffer
->device
, aspects
, 1u << samples_log2
, index
,
686 pipeline
, cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
687 if (ret
!= VK_SUCCESS
) {
688 cmd_buffer
->record_result
= ret
;
689 return VK_NULL_HANDLE
;
696 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
697 const VkClearAttachment
*clear_att
,
698 const VkClearRect
*clear_rect
)
700 struct radv_device
*device
= cmd_buffer
->device
;
701 struct radv_meta_state
*meta_state
= &device
->meta_state
;
702 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
703 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
704 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
705 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
706 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
707 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
708 const uint32_t samples
= iview
->image
->info
.samples
;
709 const uint32_t samples_log2
= ffs(samples
) - 1;
710 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
712 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
714 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
715 clear_value
.depth
= 1.0f
;
717 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
718 device
->meta_state
.clear_depth_p_layout
,
719 VK_SHADER_STAGE_VERTEX_BIT
, 0, 4,
722 uint32_t prev_reference
= cmd_buffer
->state
.dynamic
.stencil_reference
.front
;
723 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
724 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
725 clear_value
.stencil
);
728 VkPipeline pipeline
= pick_depthstencil_pipeline(cmd_buffer
,
733 subpass
->depth_stencil_attachment
.layout
,
739 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
742 if (depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
,
743 subpass
->depth_stencil_attachment
.layout
,
744 clear_rect
, clear_value
))
745 radv_update_ds_clear_metadata(cmd_buffer
, iview
->image
,
746 clear_value
, aspects
);
748 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
749 .x
= clear_rect
->rect
.offset
.x
,
750 .y
= clear_rect
->rect
.offset
.y
,
751 .width
= clear_rect
->rect
.extent
.width
,
752 .height
= clear_rect
->rect
.extent
.height
,
757 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
759 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
761 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
762 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
768 clear_htile_mask(struct radv_cmd_buffer
*cmd_buffer
,
769 struct radeon_winsys_bo
*bo
, uint64_t offset
, uint64_t size
,
770 uint32_t htile_value
, uint32_t htile_mask
)
772 struct radv_device
*device
= cmd_buffer
->device
;
773 struct radv_meta_state
*state
= &device
->meta_state
;
774 uint64_t block_count
= round_up_u64(size
, 1024);
775 struct radv_meta_saved_state saved_state
;
777 radv_meta_save(&saved_state
, cmd_buffer
,
778 RADV_META_SAVE_COMPUTE_PIPELINE
|
779 RADV_META_SAVE_CONSTANTS
|
780 RADV_META_SAVE_DESCRIPTORS
);
782 struct radv_buffer dst_buffer
= {
788 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
789 VK_PIPELINE_BIND_POINT_COMPUTE
,
790 state
->clear_htile_mask_pipeline
);
792 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_COMPUTE
,
793 state
->clear_htile_mask_p_layout
,
795 1, /* descriptorWriteCount */
796 (VkWriteDescriptorSet
[]) {
798 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
800 .dstArrayElement
= 0,
801 .descriptorCount
= 1,
802 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
803 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
804 .buffer
= radv_buffer_to_handle(&dst_buffer
),
811 const unsigned constants
[2] = {
812 htile_value
& htile_mask
,
816 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
817 state
->clear_htile_mask_p_layout
,
818 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8,
821 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer
), block_count
, 1, 1);
823 radv_meta_restore(&saved_state
, cmd_buffer
);
825 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
826 RADV_CMD_FLAG_INV_VMEM_L1
|
827 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
831 radv_get_htile_fast_clear_value(const struct radv_image
*image
,
832 VkClearDepthStencilValue value
)
834 uint32_t clear_value
;
836 if (!image
->surface
.has_stencil
) {
837 clear_value
= value
.depth
? 0xfffffff0 : 0;
839 clear_value
= value
.depth
? 0xfffc0000 : 0;
846 radv_get_htile_mask(const struct radv_image
*image
, VkImageAspectFlags aspects
)
850 if (!image
->surface
.has_stencil
) {
851 /* All the HTILE buffer is used when there is no stencil. */
854 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
856 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
864 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value
)
866 return value
.depth
== 1.0f
|| value
.depth
== 0.0f
;
870 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value
)
872 return value
.stencil
== 0;
876 * Determine if the given image can be fast cleared.
879 radv_image_can_fast_clear(struct radv_device
*device
, struct radv_image
*image
)
881 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
884 if (vk_format_is_color(image
->vk_format
)) {
885 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
888 /* RB+ doesn't work with CMASK fast clear on Stoney. */
889 if (!radv_image_has_dcc(image
) &&
890 device
->physical_device
->rad_info
.family
== CHIP_STONEY
)
893 if (!radv_image_has_htile(image
))
896 /* GFX8 only supports 32-bit depth surfaces but we can enable
897 * TC-compat HTILE for 16-bit surfaces if no Z planes are
898 * compressed. Though, fast HTILE clears don't seem to work.
900 if (device
->physical_device
->rad_info
.chip_class
== VI
&&
901 image
->vk_format
== VK_FORMAT_D16_UNORM
)
905 /* Do not fast clears 3D images. */
906 if (image
->type
== VK_IMAGE_TYPE_3D
)
913 * Determine if the given image view can be fast cleared.
916 radv_image_view_can_fast_clear(struct radv_device
*device
,
917 const struct radv_image_view
*iview
)
919 struct radv_image
*image
= iview
->image
;
921 /* Only fast clear if the image itself can be fast cleared. */
922 if (!radv_image_can_fast_clear(device
, image
))
925 /* Only fast clear if all layers are bound. */
926 if (iview
->base_layer
> 0 ||
927 iview
->layer_count
!= image
->info
.array_size
)
930 /* Only fast clear if the view covers the whole image. */
931 if (!radv_image_extent_compare(image
, &iview
->extent
))
938 radv_can_fast_clear_depth(struct radv_cmd_buffer
*cmd_buffer
,
939 const struct radv_image_view
*iview
,
940 VkImageLayout image_layout
,
941 VkImageAspectFlags aspects
,
942 const VkClearRect
*clear_rect
,
943 const VkClearDepthStencilValue clear_value
)
945 if (!radv_image_view_can_fast_clear(cmd_buffer
->device
, iview
))
948 if (!radv_layout_is_htile_compressed(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
951 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
952 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
953 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
956 if (clear_rect
->baseArrayLayer
!= 0)
958 if (clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
961 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX9
&&
962 (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) ||
963 ((vk_format_aspects(iview
->image
->vk_format
) & VK_IMAGE_ASPECT_STENCIL_BIT
) &&
964 !(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
))))
967 if (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
968 !radv_is_fast_clear_depth_allowed(clear_value
)) ||
969 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
970 !radv_is_fast_clear_stencil_allowed(clear_value
)))
977 radv_fast_clear_depth(struct radv_cmd_buffer
*cmd_buffer
,
978 const struct radv_image_view
*iview
,
979 const VkClearAttachment
*clear_att
,
980 enum radv_cmd_flush_bits
*pre_flush
,
981 enum radv_cmd_flush_bits
*post_flush
)
983 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
984 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
985 uint32_t clear_word
, flush_bits
;
988 clear_word
= radv_get_htile_fast_clear_value(iview
->image
, clear_value
);
989 htile_mask
= radv_get_htile_mask(iview
->image
, aspects
);
992 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
993 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) & ~ *pre_flush
;
994 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
997 if (htile_mask
== UINT_MAX
) {
998 /* Clear the whole HTILE buffer. */
999 flush_bits
= radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
1000 iview
->image
->offset
+ iview
->image
->htile_offset
,
1001 iview
->image
->surface
.htile_size
, clear_word
);
1003 /* Only clear depth or stencil bytes in the HTILE buffer. */
1004 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
);
1005 flush_bits
= clear_htile_mask(cmd_buffer
, iview
->image
->bo
,
1006 iview
->image
->offset
+ iview
->image
->htile_offset
,
1007 iview
->image
->surface
.htile_size
, clear_word
,
1011 radv_update_ds_clear_metadata(cmd_buffer
, iview
->image
, clear_value
, aspects
);
1013 *post_flush
|= flush_bits
;
1018 build_clear_htile_mask_shader()
1022 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
1023 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_clear_htile_mask");
1024 b
.shader
->info
.cs
.local_size
[0] = 64;
1025 b
.shader
->info
.cs
.local_size
[1] = 1;
1026 b
.shader
->info
.cs
.local_size
[2] = 1;
1028 nir_ssa_def
*invoc_id
= nir_load_system_value(&b
, nir_intrinsic_load_local_invocation_id
, 0);
1029 nir_ssa_def
*wg_id
= nir_load_system_value(&b
, nir_intrinsic_load_work_group_id
, 0);
1030 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
1031 b
.shader
->info
.cs
.local_size
[0],
1032 b
.shader
->info
.cs
.local_size
[1],
1033 b
.shader
->info
.cs
.local_size
[2], 0);
1035 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
1037 nir_ssa_def
*offset
= nir_imul(&b
, global_id
, nir_imm_int(&b
, 16));
1038 offset
= nir_channel(&b
, offset
, 0);
1040 nir_intrinsic_instr
*buf
=
1041 nir_intrinsic_instr_create(b
.shader
,
1042 nir_intrinsic_vulkan_resource_index
);
1044 buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
1045 nir_intrinsic_set_desc_set(buf
, 0);
1046 nir_intrinsic_set_binding(buf
, 0);
1047 nir_ssa_dest_init(&buf
->instr
, &buf
->dest
, 1, 32, NULL
);
1048 nir_builder_instr_insert(&b
, &buf
->instr
);
1050 nir_intrinsic_instr
*constants
=
1051 nir_intrinsic_instr_create(b
.shader
,
1052 nir_intrinsic_load_push_constant
);
1053 nir_intrinsic_set_base(constants
, 0);
1054 nir_intrinsic_set_range(constants
, 8);
1055 constants
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
1056 constants
->num_components
= 2;
1057 nir_ssa_dest_init(&constants
->instr
, &constants
->dest
, 2, 32, "constants");
1058 nir_builder_instr_insert(&b
, &constants
->instr
);
1060 nir_intrinsic_instr
*load
=
1061 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
1062 load
->src
[0] = nir_src_for_ssa(&buf
->dest
.ssa
);
1063 load
->src
[1] = nir_src_for_ssa(offset
);
1064 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1065 load
->num_components
= 4;
1066 nir_builder_instr_insert(&b
, &load
->instr
);
1068 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1070 nir_iand(&b
, &load
->dest
.ssa
,
1071 nir_channel(&b
, &constants
->dest
.ssa
, 1));
1072 data
= nir_ior(&b
, data
, nir_channel(&b
, &constants
->dest
.ssa
, 0));
1074 nir_intrinsic_instr
*store
=
1075 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
1076 store
->src
[0] = nir_src_for_ssa(data
);
1077 store
->src
[1] = nir_src_for_ssa(&buf
->dest
.ssa
);
1078 store
->src
[2] = nir_src_for_ssa(offset
);
1079 nir_intrinsic_set_write_mask(store
, 0xf);
1080 store
->num_components
= 4;
1081 nir_builder_instr_insert(&b
, &store
->instr
);
1087 init_meta_clear_htile_mask_state(struct radv_device
*device
)
1089 struct radv_meta_state
*state
= &device
->meta_state
;
1090 struct radv_shader_module cs
= { .nir
= NULL
};
1093 cs
.nir
= build_clear_htile_mask_shader();
1095 VkDescriptorSetLayoutCreateInfo ds_layout_info
= {
1096 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1097 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1099 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1102 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
1103 .descriptorCount
= 1,
1104 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
1105 .pImmutableSamplers
= NULL
1110 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1111 &ds_layout_info
, &state
->alloc
,
1112 &state
->clear_htile_mask_ds_layout
);
1113 if (result
!= VK_SUCCESS
)
1116 VkPipelineLayoutCreateInfo p_layout_info
= {
1117 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1118 .setLayoutCount
= 1,
1119 .pSetLayouts
= &state
->clear_htile_mask_ds_layout
,
1120 .pushConstantRangeCount
= 1,
1121 .pPushConstantRanges
= &(VkPushConstantRange
){
1122 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8,
1126 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1127 &p_layout_info
, &state
->alloc
,
1128 &state
->clear_htile_mask_p_layout
);
1129 if (result
!= VK_SUCCESS
)
1132 VkPipelineShaderStageCreateInfo shader_stage
= {
1133 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1134 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1135 .module
= radv_shader_module_to_handle(&cs
),
1137 .pSpecializationInfo
= NULL
,
1140 VkComputePipelineCreateInfo pipeline_info
= {
1141 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1142 .stage
= shader_stage
,
1144 .layout
= state
->clear_htile_mask_p_layout
,
1147 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1148 radv_pipeline_cache_to_handle(&state
->cache
),
1149 1, &pipeline_info
, NULL
,
1150 &state
->clear_htile_mask_pipeline
);
1152 ralloc_free(cs
.nir
);
1155 ralloc_free(cs
.nir
);
1160 radv_device_init_meta_clear_state(struct radv_device
*device
, bool on_demand
)
1163 struct radv_meta_state
*state
= &device
->meta_state
;
1165 VkPipelineLayoutCreateInfo pl_color_create_info
= {
1166 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1167 .setLayoutCount
= 0,
1168 .pushConstantRangeCount
= 1,
1169 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16},
1172 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1173 &pl_color_create_info
,
1174 &device
->meta_state
.alloc
,
1175 &device
->meta_state
.clear_color_p_layout
);
1176 if (res
!= VK_SUCCESS
)
1179 VkPipelineLayoutCreateInfo pl_depth_create_info
= {
1180 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1181 .setLayoutCount
= 0,
1182 .pushConstantRangeCount
= 1,
1183 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_VERTEX_BIT
, 0, 4},
1186 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1187 &pl_depth_create_info
,
1188 &device
->meta_state
.alloc
,
1189 &device
->meta_state
.clear_depth_p_layout
);
1190 if (res
!= VK_SUCCESS
)
1193 res
= init_meta_clear_htile_mask_state(device
);
1194 if (res
!= VK_SUCCESS
)
1200 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
1201 uint32_t samples
= 1 << i
;
1202 for (uint32_t j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
1203 VkFormat format
= radv_fs_key_format_exemplars
[j
];
1204 unsigned fs_key
= radv_format_meta_fs_key(format
);
1205 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
1207 res
= create_color_renderpass(device
, format
, samples
,
1208 &state
->clear
[i
].render_pass
[fs_key
]);
1209 if (res
!= VK_SUCCESS
)
1212 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
1213 state
->clear
[i
].render_pass
[fs_key
]);
1214 if (res
!= VK_SUCCESS
)
1219 res
= create_depthstencil_renderpass(device
,
1221 &state
->clear
[i
].depthstencil_rp
);
1222 if (res
!= VK_SUCCESS
)
1225 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
1226 res
= create_depthstencil_pipeline(device
,
1227 VK_IMAGE_ASPECT_DEPTH_BIT
,
1230 &state
->clear
[i
].depth_only_pipeline
[j
],
1231 state
->clear
[i
].depthstencil_rp
);
1232 if (res
!= VK_SUCCESS
)
1235 res
= create_depthstencil_pipeline(device
,
1236 VK_IMAGE_ASPECT_STENCIL_BIT
,
1239 &state
->clear
[i
].stencil_only_pipeline
[j
],
1240 state
->clear
[i
].depthstencil_rp
);
1241 if (res
!= VK_SUCCESS
)
1244 res
= create_depthstencil_pipeline(device
,
1245 VK_IMAGE_ASPECT_DEPTH_BIT
|
1246 VK_IMAGE_ASPECT_STENCIL_BIT
,
1249 &state
->clear
[i
].depthstencil_pipeline
[j
],
1250 state
->clear
[i
].depthstencil_rp
);
1251 if (res
!= VK_SUCCESS
)
1258 radv_device_finish_meta_clear_state(device
);
1263 radv_get_cmask_fast_clear_value(const struct radv_image
*image
)
1265 uint32_t value
= 0; /* Default value when no DCC. */
1267 /* The fast-clear value is different for images that have both DCC and
1270 if (radv_image_has_dcc(image
)) {
1271 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1272 return image
->info
.samples
> 1 ? 0xcccccccc : 0xffffffff;
1279 radv_clear_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1280 struct radv_image
*image
, uint32_t value
)
1282 return radv_fill_buffer(cmd_buffer
, image
->bo
,
1283 image
->offset
+ image
->cmask
.offset
,
1284 image
->cmask
.size
, value
);
1288 radv_clear_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1289 struct radv_image
*image
, uint32_t value
)
1291 /* Mark the image as being compressed. */
1292 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1294 return radv_fill_buffer(cmd_buffer
, image
->bo
,
1295 image
->offset
+ image
->dcc_offset
,
1296 image
->surface
.dcc_size
, value
);
1299 static void vi_get_fast_clear_parameters(VkFormat format
,
1300 const VkClearColorValue
*clear_value
,
1301 uint32_t* reset_value
,
1302 bool *can_avoid_fast_clear_elim
)
1304 bool values
[4] = {};
1306 bool main_value
= false;
1307 bool extra_value
= false;
1309 *can_avoid_fast_clear_elim
= false;
1311 *reset_value
= 0x20202020U
;
1313 const struct vk_format_description
*desc
= vk_format_description(format
);
1314 if (format
== VK_FORMAT_B10G11R11_UFLOAT_PACK32
||
1315 format
== VK_FORMAT_R5G6B5_UNORM_PACK16
||
1316 format
== VK_FORMAT_B5G6R5_UNORM_PACK16
)
1318 else if (desc
->layout
== VK_FORMAT_LAYOUT_PLAIN
) {
1319 if (radv_translate_colorswap(format
, false) <= 1)
1320 extra_channel
= desc
->nr_channels
- 1;
1326 for (i
= 0; i
< 4; i
++) {
1327 int index
= desc
->swizzle
[i
] - VK_SWIZZLE_X
;
1328 if (desc
->swizzle
[i
] < VK_SWIZZLE_X
||
1329 desc
->swizzle
[i
] > VK_SWIZZLE_W
)
1332 if (desc
->channel
[i
].pure_integer
&&
1333 desc
->channel
[i
].type
== VK_FORMAT_TYPE_SIGNED
) {
1334 /* Use the maximum value for clamping the clear color. */
1335 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
1337 values
[i
] = clear_value
->int32
[i
] != 0;
1338 if (clear_value
->int32
[i
] != 0 && MIN2(clear_value
->int32
[i
], max
) != max
)
1340 } else if (desc
->channel
[i
].pure_integer
&&
1341 desc
->channel
[i
].type
== VK_FORMAT_TYPE_UNSIGNED
) {
1342 /* Use the maximum value for clamping the clear color. */
1343 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
1345 values
[i
] = clear_value
->uint32
[i
] != 0U;
1346 if (clear_value
->uint32
[i
] != 0U && MIN2(clear_value
->uint32
[i
], max
) != max
)
1349 values
[i
] = clear_value
->float32
[i
] != 0.0F
;
1350 if (clear_value
->float32
[i
] != 0.0F
&& clear_value
->float32
[i
] != 1.0F
)
1354 if (index
== extra_channel
)
1355 extra_value
= values
[i
];
1357 main_value
= values
[i
];
1360 for (int i
= 0; i
< 4; ++i
)
1361 if (values
[i
] != main_value
&&
1362 desc
->swizzle
[i
] - VK_SWIZZLE_X
!= extra_channel
&&
1363 desc
->swizzle
[i
] >= VK_SWIZZLE_X
&&
1364 desc
->swizzle
[i
] <= VK_SWIZZLE_W
)
1367 *can_avoid_fast_clear_elim
= true;
1369 *reset_value
|= 0x80808080U
;
1372 *reset_value
|= 0x40404040U
;
1377 radv_can_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1378 const struct radv_image_view
*iview
,
1379 VkImageLayout image_layout
,
1380 const VkClearRect
*clear_rect
,
1381 VkClearColorValue clear_value
,
1384 uint32_t clear_color
[2];
1386 if (!radv_image_view_can_fast_clear(cmd_buffer
->device
, iview
))
1389 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
1392 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
1393 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
1394 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1397 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1398 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1400 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1402 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1406 if (!radv_format_pack_clear_color(iview
->vk_format
,
1407 clear_color
, &clear_value
))
1410 if (radv_image_has_dcc(iview
->image
)) {
1411 bool can_avoid_fast_clear_elim
;
1412 uint32_t reset_value
;
1414 vi_get_fast_clear_parameters(iview
->vk_format
,
1415 &clear_value
, &reset_value
,
1416 &can_avoid_fast_clear_elim
);
1418 if (iview
->image
->info
.samples
> 1) {
1419 /* DCC fast clear with MSAA should clear CMASK. */
1420 /* FIXME: This doesn't work for now. There is a
1421 * hardware bug with fast clears and DCC for MSAA
1422 * textures. AMDVLK has a workaround but it doesn't
1423 * seem to work here. Note that we might emit useless
1424 * CB flushes but that shouldn't matter.
1426 if (!can_avoid_fast_clear_elim
)
1436 radv_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1437 const struct radv_image_view
*iview
,
1438 const VkClearAttachment
*clear_att
,
1439 uint32_t subpass_att
,
1440 enum radv_cmd_flush_bits
*pre_flush
,
1441 enum radv_cmd_flush_bits
*post_flush
)
1443 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1444 uint32_t clear_color
[2], flush_bits
= 0;
1445 uint32_t cmask_clear_value
;
1448 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1449 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
1450 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1454 radv_format_pack_clear_color(iview
->vk_format
, clear_color
, &clear_value
);
1456 cmask_clear_value
= radv_get_cmask_fast_clear_value(iview
->image
);
1458 /* clear cmask buffer */
1459 if (radv_image_has_dcc(iview
->image
)) {
1460 uint32_t reset_value
;
1461 bool can_avoid_fast_clear_elim
;
1462 bool need_decompress_pass
= false;
1464 vi_get_fast_clear_parameters(iview
->vk_format
,
1465 &clear_value
, &reset_value
,
1466 &can_avoid_fast_clear_elim
);
1468 if (radv_image_has_cmask(iview
->image
)) {
1469 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1472 need_decompress_pass
= true;
1475 if (!can_avoid_fast_clear_elim
)
1476 need_decompress_pass
= true;
1478 flush_bits
|= radv_clear_dcc(cmd_buffer
, iview
->image
, reset_value
);
1480 radv_update_fce_metadata(cmd_buffer
, iview
->image
,
1481 need_decompress_pass
);
1483 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1488 *post_flush
|= flush_bits
;
1491 radv_update_color_clear_metadata(cmd_buffer
, iview
->image
, subpass_att
,
1496 * The parameters mean that same as those in vkCmdClearAttachments.
1499 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
1500 const VkClearAttachment
*clear_att
,
1501 const VkClearRect
*clear_rect
,
1502 enum radv_cmd_flush_bits
*pre_flush
,
1503 enum radv_cmd_flush_bits
*post_flush
,
1506 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1507 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1508 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
1510 if (aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1511 const uint32_t subpass_att
= clear_att
->colorAttachment
;
1512 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
1513 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
1514 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
1515 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1517 if (radv_can_fast_clear_color(cmd_buffer
, iview
, image_layout
,
1518 clear_rect
, clear_value
, view_mask
)) {
1519 radv_fast_clear_color(cmd_buffer
, iview
, clear_att
,
1520 subpass_att
, pre_flush
,
1523 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
, view_mask
);
1526 const uint32_t pass_att
= subpass
->depth_stencil_attachment
.attachment
;
1527 VkImageLayout image_layout
= subpass
->depth_stencil_attachment
.layout
;
1528 const struct radv_image_view
*iview
= fb
->attachments
[pass_att
].attachment
;
1529 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
1531 assert(aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1532 VK_IMAGE_ASPECT_STENCIL_BIT
));
1534 if (radv_can_fast_clear_depth(cmd_buffer
, iview
, image_layout
,
1535 aspects
, clear_rect
, clear_value
)) {
1536 radv_fast_clear_depth(cmd_buffer
, iview
, clear_att
,
1537 pre_flush
, post_flush
);
1539 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
);
1545 radv_attachment_needs_clear(struct radv_cmd_state
*cmd_state
, uint32_t a
)
1547 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1548 return (a
!= VK_ATTACHMENT_UNUSED
&&
1549 cmd_state
->attachments
[a
].pending_clear_aspects
&&
1550 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[a
].cleared_views
)));
1554 radv_subpass_needs_clear(struct radv_cmd_buffer
*cmd_buffer
)
1556 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1559 if (!cmd_state
->subpass
)
1562 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1563 a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1564 if (radv_attachment_needs_clear(cmd_state
, a
))
1568 a
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1569 return radv_attachment_needs_clear(cmd_state
, a
);
1573 radv_subpass_clear_attachment(struct radv_cmd_buffer
*cmd_buffer
,
1574 struct radv_attachment_state
*attachment
,
1575 const VkClearAttachment
*clear_att
,
1576 enum radv_cmd_flush_bits
*pre_flush
,
1577 enum radv_cmd_flush_bits
*post_flush
)
1579 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1580 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1582 VkClearRect clear_rect
= {
1583 .rect
= cmd_state
->render_area
,
1584 .baseArrayLayer
= 0,
1585 .layerCount
= cmd_state
->framebuffer
->layers
,
1588 emit_clear(cmd_buffer
, clear_att
, &clear_rect
, pre_flush
, post_flush
,
1589 view_mask
& ~attachment
->cleared_views
);
1591 attachment
->cleared_views
|= view_mask
;
1593 attachment
->pending_clear_aspects
= 0;
1597 * Emit any pending attachment clears for the current subpass.
1599 * @see radv_attachment_state::pending_clear_aspects
1602 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
1604 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1605 struct radv_meta_saved_state saved_state
;
1606 enum radv_cmd_flush_bits pre_flush
= 0;
1607 enum radv_cmd_flush_bits post_flush
= 0;
1609 if (!radv_subpass_needs_clear(cmd_buffer
))
1612 radv_meta_save(&saved_state
, cmd_buffer
,
1613 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1614 RADV_META_SAVE_CONSTANTS
);
1616 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1617 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1619 if (!radv_attachment_needs_clear(cmd_state
, a
))
1622 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1623 VK_IMAGE_ASPECT_COLOR_BIT
);
1625 VkClearAttachment clear_att
= {
1626 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1627 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1628 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1631 radv_subpass_clear_attachment(cmd_buffer
,
1632 &cmd_state
->attachments
[a
],
1633 &clear_att
, &pre_flush
,
1637 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1638 if (radv_attachment_needs_clear(cmd_state
, ds
)) {
1639 VkClearAttachment clear_att
= {
1640 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1641 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1644 radv_subpass_clear_attachment(cmd_buffer
,
1645 &cmd_state
->attachments
[ds
],
1646 &clear_att
, &pre_flush
,
1650 radv_meta_restore(&saved_state
, cmd_buffer
);
1651 cmd_buffer
->state
.flush_bits
|= post_flush
;
1655 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
1656 struct radv_image
*image
,
1657 VkImageLayout image_layout
,
1658 const VkImageSubresourceRange
*range
,
1659 VkFormat format
, int level
, int layer
,
1660 const VkClearValue
*clear_val
)
1662 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
1663 struct radv_image_view iview
;
1664 uint32_t width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
1665 uint32_t height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
1667 radv_image_view_init(&iview
, cmd_buffer
->device
,
1668 &(VkImageViewCreateInfo
) {
1669 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1670 .image
= radv_image_to_handle(image
),
1671 .viewType
= radv_meta_get_view_type(image
),
1673 .subresourceRange
= {
1674 .aspectMask
= range
->aspectMask
,
1675 .baseMipLevel
= range
->baseMipLevel
+ level
,
1677 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
1683 radv_CreateFramebuffer(device_h
,
1684 &(VkFramebufferCreateInfo
) {
1685 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1686 .attachmentCount
= 1,
1687 .pAttachments
= (VkImageView
[]) {
1688 radv_image_view_to_handle(&iview
),
1694 &cmd_buffer
->pool
->alloc
,
1697 VkAttachmentDescription att_desc
= {
1698 .format
= iview
.vk_format
,
1699 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1700 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1701 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1702 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1703 .initialLayout
= image_layout
,
1704 .finalLayout
= image_layout
,
1707 VkSubpassDescription subpass_desc
= {
1708 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1709 .inputAttachmentCount
= 0,
1710 .colorAttachmentCount
= 0,
1711 .pColorAttachments
= NULL
,
1712 .pResolveAttachments
= NULL
,
1713 .pDepthStencilAttachment
= NULL
,
1714 .preserveAttachmentCount
= 0,
1715 .pPreserveAttachments
= NULL
,
1718 const VkAttachmentReference att_ref
= {
1720 .layout
= image_layout
,
1723 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1724 subpass_desc
.colorAttachmentCount
= 1;
1725 subpass_desc
.pColorAttachments
= &att_ref
;
1727 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1731 radv_CreateRenderPass(device_h
,
1732 &(VkRenderPassCreateInfo
) {
1733 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1734 .attachmentCount
= 1,
1735 .pAttachments
= &att_desc
,
1737 .pSubpasses
= &subpass_desc
,
1739 &cmd_buffer
->pool
->alloc
,
1742 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1743 &(VkRenderPassBeginInfo
) {
1744 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1746 .offset
= { 0, 0, },
1754 .clearValueCount
= 0,
1755 .pClearValues
= NULL
,
1757 VK_SUBPASS_CONTENTS_INLINE
);
1759 VkClearAttachment clear_att
= {
1760 .aspectMask
= range
->aspectMask
,
1761 .colorAttachment
= 0,
1762 .clearValue
= *clear_val
,
1765 VkClearRect clear_rect
= {
1768 .extent
= { width
, height
},
1770 .baseArrayLayer
= range
->baseArrayLayer
,
1771 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1774 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
, 0);
1776 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1777 radv_DestroyRenderPass(device_h
, pass
,
1778 &cmd_buffer
->pool
->alloc
);
1779 radv_DestroyFramebuffer(device_h
, fb
,
1780 &cmd_buffer
->pool
->alloc
);
1784 * Return TRUE if a fast color or depth clear has been performed.
1787 radv_fast_clear_range(struct radv_cmd_buffer
*cmd_buffer
,
1788 struct radv_image
*image
,
1790 VkImageLayout image_layout
,
1791 const VkImageSubresourceRange
*range
,
1792 const VkClearValue
*clear_val
)
1794 struct radv_image_view iview
;
1796 radv_image_view_init(&iview
, cmd_buffer
->device
,
1797 &(VkImageViewCreateInfo
) {
1798 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1799 .image
= radv_image_to_handle(image
),
1800 .viewType
= radv_meta_get_view_type(image
),
1801 .format
= image
->vk_format
,
1802 .subresourceRange
= {
1803 .aspectMask
= range
->aspectMask
,
1804 .baseMipLevel
= range
->baseMipLevel
,
1805 .levelCount
= range
->levelCount
,
1806 .baseArrayLayer
= range
->baseArrayLayer
,
1807 .layerCount
= range
->layerCount
,
1811 VkClearRect clear_rect
= {
1815 radv_minify(image
->info
.width
, range
->baseMipLevel
),
1816 radv_minify(image
->info
.height
, range
->baseMipLevel
),
1819 .baseArrayLayer
= range
->baseArrayLayer
,
1820 .layerCount
= range
->layerCount
,
1823 VkClearAttachment clear_att
= {
1824 .aspectMask
= range
->aspectMask
,
1825 .colorAttachment
= 0,
1826 .clearValue
= *clear_val
,
1829 if (vk_format_is_color(format
)) {
1830 if (radv_can_fast_clear_color(cmd_buffer
, &iview
,
1831 image_layout
, &clear_rect
,
1832 clear_att
.clearValue
.color
, 0)) {
1833 radv_fast_clear_color(cmd_buffer
, &iview
, &clear_att
,
1834 clear_att
.colorAttachment
,
1839 if (radv_can_fast_clear_depth(cmd_buffer
, &iview
, image_layout
,
1840 range
->aspectMask
, &clear_rect
,
1841 clear_att
.clearValue
.depthStencil
)) {
1842 radv_fast_clear_depth(cmd_buffer
, &iview
, &clear_att
,
1852 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
1853 struct radv_image
*image
,
1854 VkImageLayout image_layout
,
1855 const VkClearValue
*clear_value
,
1856 uint32_t range_count
,
1857 const VkImageSubresourceRange
*ranges
,
1860 VkFormat format
= image
->vk_format
;
1861 VkClearValue internal_clear_value
= *clear_value
;
1863 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
1865 format
= VK_FORMAT_R32_UINT
;
1866 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
1867 internal_clear_value
.color
.uint32
[0] = value
;
1870 if (format
== VK_FORMAT_R4G4_UNORM_PACK8
) {
1872 format
= VK_FORMAT_R8_UINT
;
1873 r
= float_to_ubyte(clear_value
->color
.float32
[0]) >> 4;
1874 g
= float_to_ubyte(clear_value
->color
.float32
[1]) >> 4;
1875 internal_clear_value
.color
.uint32
[0] = (r
<< 4) | (g
& 0xf);
1878 if (format
== VK_FORMAT_R32G32B32_UINT
||
1879 format
== VK_FORMAT_R32G32B32_SINT
||
1880 format
== VK_FORMAT_R32G32B32_SFLOAT
)
1883 for (uint32_t r
= 0; r
< range_count
; r
++) {
1884 const VkImageSubresourceRange
*range
= &ranges
[r
];
1886 /* Try to perform a fast clear first, otherwise fallback to
1890 radv_fast_clear_range(cmd_buffer
, image
, format
,
1891 image_layout
, range
,
1892 &internal_clear_value
)) {
1896 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1897 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1898 radv_minify(image
->info
.depth
, range
->baseMipLevel
+ l
) :
1899 radv_get_layerCount(image
, range
);
1900 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1903 struct radv_meta_blit2d_surf surf
;
1904 surf
.format
= format
;
1906 surf
.level
= range
->baseMipLevel
+ l
;
1907 surf
.layer
= range
->baseArrayLayer
+ s
;
1908 surf
.aspect_mask
= range
->aspectMask
;
1909 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
1910 &internal_clear_value
.color
);
1912 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
1913 range
, format
, l
, s
, &internal_clear_value
);
1920 void radv_CmdClearColorImage(
1921 VkCommandBuffer commandBuffer
,
1923 VkImageLayout imageLayout
,
1924 const VkClearColorValue
* pColor
,
1925 uint32_t rangeCount
,
1926 const VkImageSubresourceRange
* pRanges
)
1928 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1929 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1930 struct radv_meta_saved_state saved_state
;
1931 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
1934 radv_meta_save(&saved_state
, cmd_buffer
,
1935 RADV_META_SAVE_COMPUTE_PIPELINE
|
1936 RADV_META_SAVE_CONSTANTS
|
1937 RADV_META_SAVE_DESCRIPTORS
);
1939 radv_meta_save(&saved_state
, cmd_buffer
,
1940 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1941 RADV_META_SAVE_CONSTANTS
);
1944 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1945 (const VkClearValue
*) pColor
,
1946 rangeCount
, pRanges
, cs
);
1948 radv_meta_restore(&saved_state
, cmd_buffer
);
1951 void radv_CmdClearDepthStencilImage(
1952 VkCommandBuffer commandBuffer
,
1954 VkImageLayout imageLayout
,
1955 const VkClearDepthStencilValue
* pDepthStencil
,
1956 uint32_t rangeCount
,
1957 const VkImageSubresourceRange
* pRanges
)
1959 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1960 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
1961 struct radv_meta_saved_state saved_state
;
1963 radv_meta_save(&saved_state
, cmd_buffer
,
1964 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1965 RADV_META_SAVE_CONSTANTS
);
1967 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
1968 (const VkClearValue
*) pDepthStencil
,
1969 rangeCount
, pRanges
, false);
1971 radv_meta_restore(&saved_state
, cmd_buffer
);
1974 void radv_CmdClearAttachments(
1975 VkCommandBuffer commandBuffer
,
1976 uint32_t attachmentCount
,
1977 const VkClearAttachment
* pAttachments
,
1979 const VkClearRect
* pRects
)
1981 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1982 struct radv_meta_saved_state saved_state
;
1983 enum radv_cmd_flush_bits pre_flush
= 0;
1984 enum radv_cmd_flush_bits post_flush
= 0;
1986 if (!cmd_buffer
->state
.subpass
)
1989 radv_meta_save(&saved_state
, cmd_buffer
,
1990 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1991 RADV_META_SAVE_CONSTANTS
);
1993 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1996 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1997 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1998 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
,
1999 cmd_buffer
->state
.subpass
->view_mask
);
2003 radv_meta_restore(&saved_state
, cmd_buffer
);
2004 cmd_buffer
->state
.flush_bits
|= post_flush
;