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radv: Add multiple planes to images.
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 0,
236 .pPreserveAttachments = NULL,
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
374 uint32_t samples, samples_log2;
375 VkFormat format;
376 unsigned fs_key;
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 /* When a framebuffer is bound to the current command buffer, get the
382 * number of samples from it. Otherwise, get the number of samples from
383 * the render pass because it's likely a secondary command buffer.
384 */
385 if (iview) {
386 samples = iview->image->info.samples;
387 format = iview->vk_format;
388 } else {
389 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
390 format = cmd_buffer->state.pass->attachments[pass_att].format;
391 }
392
393 samples_log2 = ffs(samples) - 1;
394 fs_key = radv_format_meta_fs_key(format);
395
396 if (fs_key == -1) {
397 radv_finishme("color clears incomplete");
398 return;
399 }
400
401 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
402 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
403 samples,
404 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
405 if (ret != VK_SUCCESS) {
406 cmd_buffer->record_result = ret;
407 return;
408 }
409 }
410
411 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
412 VkResult ret = create_color_pipeline(device, samples, 0,
413 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
414 device->meta_state.clear[samples_log2].render_pass[fs_key]);
415 if (ret != VK_SUCCESS) {
416 cmd_buffer->record_result = ret;
417 return;
418 }
419 }
420
421 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
422 if (!pipeline) {
423 radv_finishme("color clears incomplete");
424 return;
425 }
426 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
427 assert(pipeline);
428 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
429 assert(clear_att->colorAttachment < subpass->color_count);
430
431 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
432 device->meta_state.clear_color_p_layout,
433 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
434 &clear_value);
435
436 struct radv_subpass clear_subpass = {
437 .color_count = 1,
438 .color_attachments = (struct radv_subpass_attachment[]) {
439 subpass->color_attachments[clear_att->colorAttachment]
440 },
441 .depth_stencil_attachment = NULL,
442 };
443
444 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
445
446 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
447 pipeline);
448
449 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
450 .x = clear_rect->rect.offset.x,
451 .y = clear_rect->rect.offset.y,
452 .width = clear_rect->rect.extent.width,
453 .height = clear_rect->rect.extent.height,
454 .minDepth = 0.0f,
455 .maxDepth = 1.0f
456 });
457
458 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
459
460 if (view_mask) {
461 unsigned i;
462 for_each_bit(i, view_mask)
463 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
464 } else {
465 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
466 }
467
468 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
469 }
470
471
472 static void
473 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
474 {
475 nir_builder vs_b, fs_b;
476
477 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
478 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
479
480 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
481 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
482 const struct glsl_type *position_out_type = glsl_vec4_type();
483
484 nir_variable *vs_out_pos =
485 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
486 "gl_Position");
487 vs_out_pos->data.location = VARYING_SLOT_POS;
488
489 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
490 nir_intrinsic_set_base(in_color_load, 0);
491 nir_intrinsic_set_range(in_color_load, 4);
492 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
493 in_color_load->num_components = 1;
494 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
495 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
496
497 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
498 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
499
500 const struct glsl_type *layer_type = glsl_int_type();
501 nir_variable *vs_out_layer =
502 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
503 "v_layer");
504 vs_out_layer->data.location = VARYING_SLOT_LAYER;
505 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
506 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
507 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
508
509 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
510 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
511
512 *out_vs = vs_b.shader;
513 *out_fs = fs_b.shader;
514 }
515
516 static VkResult
517 create_depthstencil_renderpass(struct radv_device *device,
518 uint32_t samples,
519 VkRenderPass *render_pass)
520 {
521 mtx_lock(&device->meta_state.mtx);
522 if (*render_pass) {
523 mtx_unlock(&device->meta_state.mtx);
524 return VK_SUCCESS;
525 }
526
527 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
528 &(VkRenderPassCreateInfo) {
529 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
530 .attachmentCount = 1,
531 .pAttachments = &(VkAttachmentDescription) {
532 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
533 .samples = samples,
534 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
535 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
536 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
537 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
538 },
539 .subpassCount = 1,
540 .pSubpasses = &(VkSubpassDescription) {
541 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
542 .inputAttachmentCount = 0,
543 .colorAttachmentCount = 0,
544 .pColorAttachments = NULL,
545 .pResolveAttachments = NULL,
546 .pDepthStencilAttachment = &(VkAttachmentReference) {
547 .attachment = 0,
548 .layout = VK_IMAGE_LAYOUT_GENERAL,
549 },
550 .preserveAttachmentCount = 0,
551 .pPreserveAttachments = NULL,
552 },
553 .dependencyCount = 0,
554 }, &device->meta_state.alloc, render_pass);
555 mtx_unlock(&device->meta_state.mtx);
556 return result;
557 }
558
559 static VkResult
560 create_depthstencil_pipeline(struct radv_device *device,
561 VkImageAspectFlags aspects,
562 uint32_t samples,
563 int index,
564 VkPipeline *pipeline,
565 VkRenderPass render_pass)
566 {
567 struct nir_shader *vs_nir, *fs_nir;
568 VkResult result;
569
570 mtx_lock(&device->meta_state.mtx);
571 if (*pipeline) {
572 mtx_unlock(&device->meta_state.mtx);
573 return VK_SUCCESS;
574 }
575
576 build_depthstencil_shader(&vs_nir, &fs_nir);
577
578 const VkPipelineVertexInputStateCreateInfo vi_state = {
579 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
580 .vertexBindingDescriptionCount = 0,
581 .vertexAttributeDescriptionCount = 0,
582 };
583
584 const VkPipelineDepthStencilStateCreateInfo ds_state = {
585 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
586 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
587 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
588 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
589 .depthBoundsTestEnable = false,
590 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
591 .front = {
592 .passOp = VK_STENCIL_OP_REPLACE,
593 .compareOp = VK_COMPARE_OP_ALWAYS,
594 .writeMask = UINT32_MAX,
595 .reference = 0, /* dynamic */
596 },
597 .back = { 0 /* dont care */ },
598 };
599
600 const VkPipelineColorBlendStateCreateInfo cb_state = {
601 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
602 .logicOpEnable = false,
603 .attachmentCount = 0,
604 .pAttachments = NULL,
605 };
606
607 struct radv_graphics_pipeline_create_info extra = {
608 .use_rectlist = true,
609 };
610
611 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
612 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
613 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
614 }
615 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
616 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
617 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
618 }
619 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
620 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
621 device->meta_state.clear_depth_p_layout,
622 &extra, &device->meta_state.alloc, pipeline);
623
624 mtx_unlock(&device->meta_state.mtx);
625 return result;
626 }
627
628 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
629 const struct radv_image_view *iview,
630 VkImageAspectFlags aspects,
631 VkImageLayout layout,
632 const VkClearRect *clear_rect,
633 VkClearDepthStencilValue clear_value)
634 {
635 if (!iview)
636 return false;
637
638 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
639 cmd_buffer->queue_family_index,
640 cmd_buffer->queue_family_index);
641 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
642 clear_rect->rect.extent.width != iview->extent.width ||
643 clear_rect->rect.extent.height != iview->extent.height)
644 return false;
645 if (radv_image_is_tc_compat_htile(iview->image) &&
646 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
647 clear_value.depth != 1.0) ||
648 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
649 return false;
650 if (radv_image_has_htile(iview->image) &&
651 iview->base_mip == 0 &&
652 iview->base_layer == 0 &&
653 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
654 radv_image_extent_compare(iview->image, &iview->extent))
655 return true;
656 return false;
657 }
658
659 static VkPipeline
660 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
661 struct radv_meta_state *meta_state,
662 const struct radv_image_view *iview,
663 int samples_log2,
664 VkImageAspectFlags aspects,
665 VkImageLayout layout,
666 const VkClearRect *clear_rect,
667 VkClearDepthStencilValue clear_value)
668 {
669 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
670 int index = DEPTH_CLEAR_SLOW;
671 VkPipeline *pipeline;
672
673 if (fast) {
674 /* we don't know the previous clear values, so we always have
675 * the NO_EXPCLEAR path */
676 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
677 }
678
679 switch (aspects) {
680 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
681 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
682 break;
683 case VK_IMAGE_ASPECT_DEPTH_BIT:
684 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
685 break;
686 case VK_IMAGE_ASPECT_STENCIL_BIT:
687 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
688 break;
689 default:
690 unreachable("expected depth or stencil aspect");
691 }
692
693 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
694 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
695 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
696 if (ret != VK_SUCCESS) {
697 cmd_buffer->record_result = ret;
698 return VK_NULL_HANDLE;
699 }
700 }
701
702 if (*pipeline == VK_NULL_HANDLE) {
703 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
704 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
705 if (ret != VK_SUCCESS) {
706 cmd_buffer->record_result = ret;
707 return VK_NULL_HANDLE;
708 }
709 }
710 return *pipeline;
711 }
712
713 static void
714 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
715 const VkClearAttachment *clear_att,
716 const VkClearRect *clear_rect,
717 uint32_t view_mask)
718 {
719 struct radv_device *device = cmd_buffer->device;
720 struct radv_meta_state *meta_state = &device->meta_state;
721 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
722 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
723 const uint32_t pass_att = subpass->depth_stencil_attachment->attachment;
724 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
725 VkImageAspectFlags aspects = clear_att->aspectMask;
726 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
727 uint32_t samples, samples_log2;
728 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
729
730 /* When a framebuffer is bound to the current command buffer, get the
731 * number of samples from it. Otherwise, get the number of samples from
732 * the render pass because it's likely a secondary command buffer.
733 */
734 if (iview) {
735 samples = iview->image->info.samples;
736 } else {
737 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
738 }
739
740 samples_log2 = ffs(samples) - 1;
741
742 assert(pass_att != VK_ATTACHMENT_UNUSED);
743
744 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
745 clear_value.depth = 1.0f;
746
747 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
748 device->meta_state.clear_depth_p_layout,
749 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
750 &clear_value.depth);
751
752 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
753 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
754 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
755 clear_value.stencil);
756 }
757
758 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
759 meta_state,
760 iview,
761 samples_log2,
762 aspects,
763 subpass->depth_stencil_attachment->layout,
764 clear_rect,
765 clear_value);
766 if (!pipeline)
767 return;
768
769 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
770 pipeline);
771
772 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
773 subpass->depth_stencil_attachment->layout,
774 clear_rect, clear_value))
775 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
776 clear_value, aspects);
777
778 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
779 .x = clear_rect->rect.offset.x,
780 .y = clear_rect->rect.offset.y,
781 .width = clear_rect->rect.extent.width,
782 .height = clear_rect->rect.extent.height,
783 .minDepth = 0.0f,
784 .maxDepth = 1.0f
785 });
786
787 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
788
789 if (view_mask) {
790 unsigned i;
791 for_each_bit(i, view_mask)
792 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
793 } else {
794 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
795 }
796
797 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
798 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
799 prev_reference);
800 }
801 }
802
803 static uint32_t
804 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
805 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
806 uint32_t htile_value, uint32_t htile_mask)
807 {
808 struct radv_device *device = cmd_buffer->device;
809 struct radv_meta_state *state = &device->meta_state;
810 uint64_t block_count = round_up_u64(size, 1024);
811 struct radv_meta_saved_state saved_state;
812
813 radv_meta_save(&saved_state, cmd_buffer,
814 RADV_META_SAVE_COMPUTE_PIPELINE |
815 RADV_META_SAVE_CONSTANTS |
816 RADV_META_SAVE_DESCRIPTORS);
817
818 struct radv_buffer dst_buffer = {
819 .bo = bo,
820 .offset = offset,
821 .size = size
822 };
823
824 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
825 VK_PIPELINE_BIND_POINT_COMPUTE,
826 state->clear_htile_mask_pipeline);
827
828 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
829 state->clear_htile_mask_p_layout,
830 0, /* set */
831 1, /* descriptorWriteCount */
832 (VkWriteDescriptorSet[]) {
833 {
834 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
835 .dstBinding = 0,
836 .dstArrayElement = 0,
837 .descriptorCount = 1,
838 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
839 .pBufferInfo = &(VkDescriptorBufferInfo) {
840 .buffer = radv_buffer_to_handle(&dst_buffer),
841 .offset = 0,
842 .range = size
843 }
844 }
845 });
846
847 const unsigned constants[2] = {
848 htile_value & htile_mask,
849 ~htile_mask,
850 };
851
852 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
853 state->clear_htile_mask_p_layout,
854 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
855 constants);
856
857 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
858
859 radv_meta_restore(&saved_state, cmd_buffer);
860
861 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
862 RADV_CMD_FLAG_INV_VMEM_L1 |
863 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
864 }
865
866 static uint32_t
867 radv_get_htile_fast_clear_value(const struct radv_image *image,
868 VkClearDepthStencilValue value)
869 {
870 uint32_t clear_value;
871
872 if (!image->planes[0].surface.has_stencil) {
873 clear_value = value.depth ? 0xfffffff0 : 0;
874 } else {
875 clear_value = value.depth ? 0xfffc0000 : 0;
876 }
877
878 return clear_value;
879 }
880
881 static uint32_t
882 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
883 {
884 uint32_t mask = 0;
885
886 if (!image->planes[0].surface.has_stencil) {
887 /* All the HTILE buffer is used when there is no stencil. */
888 mask = UINT32_MAX;
889 } else {
890 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
891 mask |= 0xfffffc0f;
892 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
893 mask |= 0x000003f0;
894 }
895
896 return mask;
897 }
898
899 static bool
900 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
901 {
902 return value.depth == 1.0f || value.depth == 0.0f;
903 }
904
905 static bool
906 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
907 {
908 return value.stencil == 0;
909 }
910
911 /**
912 * Determine if the given image can be fast cleared.
913 */
914 static bool
915 radv_image_can_fast_clear(struct radv_device *device, struct radv_image *image)
916 {
917 if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
918 return false;
919
920 if (vk_format_is_color(image->vk_format)) {
921 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
922 return false;
923
924 /* RB+ doesn't work with CMASK fast clear on Stoney. */
925 if (!radv_image_has_dcc(image) &&
926 device->physical_device->rad_info.family == CHIP_STONEY)
927 return false;
928 } else {
929 if (!radv_image_has_htile(image))
930 return false;
931 }
932
933 /* Do not fast clears 3D images. */
934 if (image->type == VK_IMAGE_TYPE_3D)
935 return false;
936
937 return true;
938 }
939
940 /**
941 * Determine if the given image view can be fast cleared.
942 */
943 static bool
944 radv_image_view_can_fast_clear(struct radv_device *device,
945 const struct radv_image_view *iview)
946 {
947 struct radv_image *image;
948
949 if (!iview)
950 return false;
951 image = iview->image;
952
953 /* Only fast clear if the image itself can be fast cleared. */
954 if (!radv_image_can_fast_clear(device, image))
955 return false;
956
957 /* Only fast clear if all layers are bound. */
958 if (iview->base_layer > 0 ||
959 iview->layer_count != image->info.array_size)
960 return false;
961
962 /* Only fast clear if the view covers the whole image. */
963 if (!radv_image_extent_compare(image, &iview->extent))
964 return false;
965
966 return true;
967 }
968
969 static bool
970 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
971 const struct radv_image_view *iview,
972 VkImageLayout image_layout,
973 VkImageAspectFlags aspects,
974 const VkClearRect *clear_rect,
975 const VkClearDepthStencilValue clear_value,
976 uint32_t view_mask)
977 {
978 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
979 return false;
980
981 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
982 return false;
983
984 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
985 clear_rect->rect.extent.width != iview->image->info.width ||
986 clear_rect->rect.extent.height != iview->image->info.height)
987 return false;
988
989 if (view_mask && (iview->image->info.array_size >= 32 ||
990 (1u << iview->image->info.array_size) - 1u != view_mask))
991 return false;
992 if (!view_mask && clear_rect->baseArrayLayer != 0)
993 return false;
994 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
995 return false;
996
997 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
998 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
999 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1000 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
1001 return false;
1002
1003 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1004 !radv_is_fast_clear_depth_allowed(clear_value)) ||
1005 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1006 !radv_is_fast_clear_stencil_allowed(clear_value)))
1007 return false;
1008
1009 return true;
1010 }
1011
1012 static void
1013 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
1014 const struct radv_image_view *iview,
1015 const VkClearAttachment *clear_att,
1016 enum radv_cmd_flush_bits *pre_flush,
1017 enum radv_cmd_flush_bits *post_flush)
1018 {
1019 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1020 VkImageAspectFlags aspects = clear_att->aspectMask;
1021 uint32_t clear_word, flush_bits;
1022 uint32_t htile_mask;
1023
1024 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
1025 htile_mask = radv_get_htile_mask(iview->image, aspects);
1026
1027 if (pre_flush) {
1028 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1029 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
1030 *pre_flush |= cmd_buffer->state.flush_bits;
1031 }
1032
1033 if (htile_mask == UINT_MAX) {
1034 /* Clear the whole HTILE buffer. */
1035 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1036 iview->image->offset + iview->image->htile_offset,
1037 iview->image->planes[0].surface.htile_size, clear_word);
1038 } else {
1039 /* Only clear depth or stencil bytes in the HTILE buffer. */
1040 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
1041 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1042 iview->image->offset + iview->image->htile_offset,
1043 iview->image->planes[0].surface.htile_size, clear_word,
1044 htile_mask);
1045 }
1046
1047 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1048 if (post_flush) {
1049 *post_flush |= flush_bits;
1050 }
1051 }
1052
1053 static nir_shader *
1054 build_clear_htile_mask_shader()
1055 {
1056 nir_builder b;
1057
1058 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1059 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1060 b.shader->info.cs.local_size[0] = 64;
1061 b.shader->info.cs.local_size[1] = 1;
1062 b.shader->info.cs.local_size[2] = 1;
1063
1064 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
1065 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
1066 nir_ssa_def *block_size = nir_imm_ivec4(&b,
1067 b.shader->info.cs.local_size[0],
1068 b.shader->info.cs.local_size[1],
1069 b.shader->info.cs.local_size[2], 0);
1070
1071 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1072
1073 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1074 offset = nir_channel(&b, offset, 0);
1075
1076 nir_intrinsic_instr *buf =
1077 nir_intrinsic_instr_create(b.shader,
1078 nir_intrinsic_vulkan_resource_index);
1079
1080 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1081 buf->num_components = 1;
1082 nir_intrinsic_set_desc_set(buf, 0);
1083 nir_intrinsic_set_binding(buf, 0);
1084 nir_ssa_dest_init(&buf->instr, &buf->dest, buf->num_components, 32, NULL);
1085 nir_builder_instr_insert(&b, &buf->instr);
1086
1087 nir_intrinsic_instr *constants =
1088 nir_intrinsic_instr_create(b.shader,
1089 nir_intrinsic_load_push_constant);
1090 nir_intrinsic_set_base(constants, 0);
1091 nir_intrinsic_set_range(constants, 8);
1092 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1093 constants->num_components = 2;
1094 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1095 nir_builder_instr_insert(&b, &constants->instr);
1096
1097 nir_intrinsic_instr *load =
1098 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1099 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1100 load->src[1] = nir_src_for_ssa(offset);
1101 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1102 load->num_components = 4;
1103 nir_builder_instr_insert(&b, &load->instr);
1104
1105 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1106 nir_ssa_def *data =
1107 nir_iand(&b, &load->dest.ssa,
1108 nir_channel(&b, &constants->dest.ssa, 1));
1109 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1110
1111 nir_intrinsic_instr *store =
1112 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1113 store->src[0] = nir_src_for_ssa(data);
1114 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1115 store->src[2] = nir_src_for_ssa(offset);
1116 nir_intrinsic_set_write_mask(store, 0xf);
1117 nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
1118 store->num_components = 4;
1119 nir_builder_instr_insert(&b, &store->instr);
1120
1121 return b.shader;
1122 }
1123
1124 static VkResult
1125 init_meta_clear_htile_mask_state(struct radv_device *device)
1126 {
1127 struct radv_meta_state *state = &device->meta_state;
1128 struct radv_shader_module cs = { .nir = NULL };
1129 VkResult result;
1130
1131 cs.nir = build_clear_htile_mask_shader();
1132
1133 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1134 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1135 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1136 .bindingCount = 1,
1137 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1138 {
1139 .binding = 0,
1140 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1141 .descriptorCount = 1,
1142 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1143 .pImmutableSamplers = NULL
1144 },
1145 }
1146 };
1147
1148 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1149 &ds_layout_info, &state->alloc,
1150 &state->clear_htile_mask_ds_layout);
1151 if (result != VK_SUCCESS)
1152 goto fail;
1153
1154 VkPipelineLayoutCreateInfo p_layout_info = {
1155 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1156 .setLayoutCount = 1,
1157 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1158 .pushConstantRangeCount = 1,
1159 .pPushConstantRanges = &(VkPushConstantRange){
1160 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1161 },
1162 };
1163
1164 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1165 &p_layout_info, &state->alloc,
1166 &state->clear_htile_mask_p_layout);
1167 if (result != VK_SUCCESS)
1168 goto fail;
1169
1170 VkPipelineShaderStageCreateInfo shader_stage = {
1171 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1172 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1173 .module = radv_shader_module_to_handle(&cs),
1174 .pName = "main",
1175 .pSpecializationInfo = NULL,
1176 };
1177
1178 VkComputePipelineCreateInfo pipeline_info = {
1179 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1180 .stage = shader_stage,
1181 .flags = 0,
1182 .layout = state->clear_htile_mask_p_layout,
1183 };
1184
1185 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1186 radv_pipeline_cache_to_handle(&state->cache),
1187 1, &pipeline_info, NULL,
1188 &state->clear_htile_mask_pipeline);
1189
1190 ralloc_free(cs.nir);
1191 return result;
1192 fail:
1193 ralloc_free(cs.nir);
1194 return result;
1195 }
1196
1197 VkResult
1198 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1199 {
1200 VkResult res;
1201 struct radv_meta_state *state = &device->meta_state;
1202
1203 VkPipelineLayoutCreateInfo pl_color_create_info = {
1204 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1205 .setLayoutCount = 0,
1206 .pushConstantRangeCount = 1,
1207 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1208 };
1209
1210 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1211 &pl_color_create_info,
1212 &device->meta_state.alloc,
1213 &device->meta_state.clear_color_p_layout);
1214 if (res != VK_SUCCESS)
1215 goto fail;
1216
1217 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1218 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1219 .setLayoutCount = 0,
1220 .pushConstantRangeCount = 1,
1221 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1222 };
1223
1224 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1225 &pl_depth_create_info,
1226 &device->meta_state.alloc,
1227 &device->meta_state.clear_depth_p_layout);
1228 if (res != VK_SUCCESS)
1229 goto fail;
1230
1231 res = init_meta_clear_htile_mask_state(device);
1232 if (res != VK_SUCCESS)
1233 goto fail;
1234
1235 if (on_demand)
1236 return VK_SUCCESS;
1237
1238 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1239 uint32_t samples = 1 << i;
1240 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1241 VkFormat format = radv_fs_key_format_exemplars[j];
1242 unsigned fs_key = radv_format_meta_fs_key(format);
1243 assert(!state->clear[i].color_pipelines[fs_key]);
1244
1245 res = create_color_renderpass(device, format, samples,
1246 &state->clear[i].render_pass[fs_key]);
1247 if (res != VK_SUCCESS)
1248 goto fail;
1249
1250 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1251 state->clear[i].render_pass[fs_key]);
1252 if (res != VK_SUCCESS)
1253 goto fail;
1254
1255 }
1256
1257 res = create_depthstencil_renderpass(device,
1258 samples,
1259 &state->clear[i].depthstencil_rp);
1260 if (res != VK_SUCCESS)
1261 goto fail;
1262
1263 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1264 res = create_depthstencil_pipeline(device,
1265 VK_IMAGE_ASPECT_DEPTH_BIT,
1266 samples,
1267 j,
1268 &state->clear[i].depth_only_pipeline[j],
1269 state->clear[i].depthstencil_rp);
1270 if (res != VK_SUCCESS)
1271 goto fail;
1272
1273 res = create_depthstencil_pipeline(device,
1274 VK_IMAGE_ASPECT_STENCIL_BIT,
1275 samples,
1276 j,
1277 &state->clear[i].stencil_only_pipeline[j],
1278 state->clear[i].depthstencil_rp);
1279 if (res != VK_SUCCESS)
1280 goto fail;
1281
1282 res = create_depthstencil_pipeline(device,
1283 VK_IMAGE_ASPECT_DEPTH_BIT |
1284 VK_IMAGE_ASPECT_STENCIL_BIT,
1285 samples,
1286 j,
1287 &state->clear[i].depthstencil_pipeline[j],
1288 state->clear[i].depthstencil_rp);
1289 if (res != VK_SUCCESS)
1290 goto fail;
1291 }
1292 }
1293 return VK_SUCCESS;
1294
1295 fail:
1296 radv_device_finish_meta_clear_state(device);
1297 return res;
1298 }
1299
1300 static uint32_t
1301 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1302 {
1303 uint32_t value = 0; /* Default value when no DCC. */
1304
1305 /* The fast-clear value is different for images that have both DCC and
1306 * CMASK metadata.
1307 */
1308 if (radv_image_has_dcc(image)) {
1309 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1310 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1311 }
1312
1313 return value;
1314 }
1315
1316 uint32_t
1317 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1318 struct radv_image *image, uint32_t value)
1319 {
1320 return radv_fill_buffer(cmd_buffer, image->bo,
1321 image->offset + image->cmask.offset,
1322 image->cmask.size, value);
1323 }
1324
1325
1326 uint32_t
1327 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
1328 struct radv_image *image, uint32_t value)
1329 {
1330 return radv_fill_buffer(cmd_buffer, image->bo,
1331 image->offset + image->fmask.offset,
1332 image->fmask.size, value);
1333 }
1334
1335 uint32_t
1336 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1337 struct radv_image *image, uint32_t value)
1338 {
1339 /* Mark the image as being compressed. */
1340 radv_update_dcc_metadata(cmd_buffer, image, true);
1341
1342 return radv_fill_buffer(cmd_buffer, image->bo,
1343 image->offset + image->dcc_offset,
1344 image->planes[0].surface.dcc_size, value);
1345 }
1346
1347 static void vi_get_fast_clear_parameters(VkFormat format,
1348 const VkClearColorValue *clear_value,
1349 uint32_t* reset_value,
1350 bool *can_avoid_fast_clear_elim)
1351 {
1352 bool values[4] = {};
1353 int extra_channel;
1354 bool main_value = false;
1355 bool extra_value = false;
1356 int i;
1357 *can_avoid_fast_clear_elim = false;
1358
1359 *reset_value = 0x20202020U;
1360
1361 const struct vk_format_description *desc = vk_format_description(format);
1362 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1363 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1364 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1365 extra_channel = -1;
1366 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1367 if (radv_translate_colorswap(format, false) <= 1)
1368 extra_channel = desc->nr_channels - 1;
1369 else
1370 extra_channel = 0;
1371 } else
1372 return;
1373
1374 for (i = 0; i < 4; i++) {
1375 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1376 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1377 desc->swizzle[i] > VK_SWIZZLE_W)
1378 continue;
1379
1380 if (desc->channel[i].pure_integer &&
1381 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1382 /* Use the maximum value for clamping the clear color. */
1383 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1384
1385 values[i] = clear_value->int32[i] != 0;
1386 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1387 return;
1388 } else if (desc->channel[i].pure_integer &&
1389 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1390 /* Use the maximum value for clamping the clear color. */
1391 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1392
1393 values[i] = clear_value->uint32[i] != 0U;
1394 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1395 return;
1396 } else {
1397 values[i] = clear_value->float32[i] != 0.0F;
1398 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1399 return;
1400 }
1401
1402 if (index == extra_channel)
1403 extra_value = values[i];
1404 else
1405 main_value = values[i];
1406 }
1407
1408 for (int i = 0; i < 4; ++i)
1409 if (values[i] != main_value &&
1410 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1411 desc->swizzle[i] >= VK_SWIZZLE_X &&
1412 desc->swizzle[i] <= VK_SWIZZLE_W)
1413 return;
1414
1415 *can_avoid_fast_clear_elim = true;
1416 if (main_value)
1417 *reset_value |= 0x80808080U;
1418
1419 if (extra_value)
1420 *reset_value |= 0x40404040U;
1421 return;
1422 }
1423
1424 static bool
1425 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1426 const struct radv_image_view *iview,
1427 VkImageLayout image_layout,
1428 const VkClearRect *clear_rect,
1429 VkClearColorValue clear_value,
1430 uint32_t view_mask)
1431 {
1432 uint32_t clear_color[2];
1433
1434 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1435 return false;
1436
1437 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1438 return false;
1439
1440 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1441 clear_rect->rect.extent.width != iview->image->info.width ||
1442 clear_rect->rect.extent.height != iview->image->info.height)
1443 return false;
1444
1445 if (view_mask && (iview->image->info.array_size >= 32 ||
1446 (1u << iview->image->info.array_size) - 1u != view_mask))
1447 return false;
1448 if (!view_mask && clear_rect->baseArrayLayer != 0)
1449 return false;
1450 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1451 return false;
1452
1453 /* DCC */
1454 if (!radv_format_pack_clear_color(iview->vk_format,
1455 clear_color, &clear_value))
1456 return false;
1457
1458 if (radv_image_has_dcc(iview->image)) {
1459 bool can_avoid_fast_clear_elim;
1460 uint32_t reset_value;
1461
1462 vi_get_fast_clear_parameters(iview->vk_format,
1463 &clear_value, &reset_value,
1464 &can_avoid_fast_clear_elim);
1465
1466 if (iview->image->info.samples > 1) {
1467 /* DCC fast clear with MSAA should clear CMASK. */
1468 /* FIXME: This doesn't work for now. There is a
1469 * hardware bug with fast clears and DCC for MSAA
1470 * textures. AMDVLK has a workaround but it doesn't
1471 * seem to work here. Note that we might emit useless
1472 * CB flushes but that shouldn't matter.
1473 */
1474 if (!can_avoid_fast_clear_elim)
1475 return false;
1476 }
1477 }
1478
1479 return true;
1480 }
1481
1482
1483 static void
1484 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1485 const struct radv_image_view *iview,
1486 const VkClearAttachment *clear_att,
1487 uint32_t subpass_att,
1488 enum radv_cmd_flush_bits *pre_flush,
1489 enum radv_cmd_flush_bits *post_flush)
1490 {
1491 VkClearColorValue clear_value = clear_att->clearValue.color;
1492 uint32_t clear_color[2], flush_bits = 0;
1493 uint32_t cmask_clear_value;
1494
1495 if (pre_flush) {
1496 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1497 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1498 *pre_flush |= cmd_buffer->state.flush_bits;
1499 }
1500
1501 /* DCC */
1502 radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1503
1504 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1505
1506 /* clear cmask buffer */
1507 if (radv_image_has_dcc(iview->image)) {
1508 uint32_t reset_value;
1509 bool can_avoid_fast_clear_elim;
1510 bool need_decompress_pass = false;
1511
1512 vi_get_fast_clear_parameters(iview->vk_format,
1513 &clear_value, &reset_value,
1514 &can_avoid_fast_clear_elim);
1515
1516 if (radv_image_has_cmask(iview->image)) {
1517 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1518 cmask_clear_value);
1519
1520 need_decompress_pass = true;
1521 }
1522
1523 if (!can_avoid_fast_clear_elim)
1524 need_decompress_pass = true;
1525
1526 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1527
1528 radv_update_fce_metadata(cmd_buffer, iview->image,
1529 need_decompress_pass);
1530 } else {
1531 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1532 cmask_clear_value);
1533 }
1534
1535 if (post_flush) {
1536 *post_flush |= flush_bits;
1537 }
1538
1539 radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1540 clear_color);
1541 }
1542
1543 /**
1544 * The parameters mean that same as those in vkCmdClearAttachments.
1545 */
1546 static void
1547 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1548 const VkClearAttachment *clear_att,
1549 const VkClearRect *clear_rect,
1550 enum radv_cmd_flush_bits *pre_flush,
1551 enum radv_cmd_flush_bits *post_flush,
1552 uint32_t view_mask)
1553 {
1554 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1555 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1556 VkImageAspectFlags aspects = clear_att->aspectMask;
1557
1558 if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1559 const uint32_t subpass_att = clear_att->colorAttachment;
1560 assert(subpass_att < subpass->color_count);
1561 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1562 if (pass_att == VK_ATTACHMENT_UNUSED)
1563 return;
1564
1565 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1566 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
1567 VkClearColorValue clear_value = clear_att->clearValue.color;
1568
1569 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1570 clear_rect, clear_value, view_mask)) {
1571 radv_fast_clear_color(cmd_buffer, iview, clear_att,
1572 subpass_att, pre_flush,
1573 post_flush);
1574 } else {
1575 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1576 }
1577 } else {
1578 const uint32_t pass_att = subpass->depth_stencil_attachment->attachment;
1579 if (pass_att == VK_ATTACHMENT_UNUSED)
1580 return;
1581
1582 VkImageLayout image_layout = subpass->depth_stencil_attachment->layout;
1583 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
1584 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1585
1586 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1587 VK_IMAGE_ASPECT_STENCIL_BIT));
1588
1589 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1590 aspects, clear_rect, clear_value,
1591 view_mask)) {
1592 radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1593 pre_flush, post_flush);
1594 } else {
1595 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
1596 view_mask);
1597 }
1598 }
1599 }
1600
1601 static inline bool
1602 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1603 {
1604 uint32_t view_mask = cmd_state->subpass->view_mask;
1605 return (a != VK_ATTACHMENT_UNUSED &&
1606 cmd_state->attachments[a].pending_clear_aspects &&
1607 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1608 }
1609
1610 static bool
1611 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1612 {
1613 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1614 uint32_t a;
1615
1616 if (!cmd_state->subpass)
1617 return false;
1618
1619 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1620 a = cmd_state->subpass->color_attachments[i].attachment;
1621 if (radv_attachment_needs_clear(cmd_state, a))
1622 return true;
1623 }
1624
1625 if (!cmd_state->subpass->depth_stencil_attachment)
1626 return false;
1627
1628 a = cmd_state->subpass->depth_stencil_attachment->attachment;
1629 return radv_attachment_needs_clear(cmd_state, a);
1630 }
1631
1632 static void
1633 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1634 struct radv_attachment_state *attachment,
1635 const VkClearAttachment *clear_att,
1636 enum radv_cmd_flush_bits *pre_flush,
1637 enum radv_cmd_flush_bits *post_flush)
1638 {
1639 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1640 uint32_t view_mask = cmd_state->subpass->view_mask;
1641
1642 VkClearRect clear_rect = {
1643 .rect = cmd_state->render_area,
1644 .baseArrayLayer = 0,
1645 .layerCount = cmd_state->framebuffer->layers,
1646 };
1647
1648 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1649 view_mask & ~attachment->cleared_views);
1650 if (view_mask)
1651 attachment->cleared_views |= view_mask;
1652 else
1653 attachment->pending_clear_aspects = 0;
1654 }
1655
1656 /**
1657 * Emit any pending attachment clears for the current subpass.
1658 *
1659 * @see radv_attachment_state::pending_clear_aspects
1660 */
1661 void
1662 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1663 {
1664 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1665 struct radv_meta_saved_state saved_state;
1666 enum radv_cmd_flush_bits pre_flush = 0;
1667 enum radv_cmd_flush_bits post_flush = 0;
1668
1669 if (!radv_subpass_needs_clear(cmd_buffer))
1670 return;
1671
1672 radv_meta_save(&saved_state, cmd_buffer,
1673 RADV_META_SAVE_GRAPHICS_PIPELINE |
1674 RADV_META_SAVE_CONSTANTS);
1675
1676 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1677 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1678
1679 if (!radv_attachment_needs_clear(cmd_state, a))
1680 continue;
1681
1682 assert(cmd_state->attachments[a].pending_clear_aspects ==
1683 VK_IMAGE_ASPECT_COLOR_BIT);
1684
1685 VkClearAttachment clear_att = {
1686 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1687 .colorAttachment = i, /* Use attachment index relative to subpass */
1688 .clearValue = cmd_state->attachments[a].clear_value,
1689 };
1690
1691 radv_subpass_clear_attachment(cmd_buffer,
1692 &cmd_state->attachments[a],
1693 &clear_att, &pre_flush,
1694 &post_flush);
1695 }
1696
1697 if (cmd_state->subpass->depth_stencil_attachment) {
1698 uint32_t ds = cmd_state->subpass->depth_stencil_attachment->attachment;
1699 if (radv_attachment_needs_clear(cmd_state, ds)) {
1700 VkClearAttachment clear_att = {
1701 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1702 .clearValue = cmd_state->attachments[ds].clear_value,
1703 };
1704
1705 radv_subpass_clear_attachment(cmd_buffer,
1706 &cmd_state->attachments[ds],
1707 &clear_att, &pre_flush,
1708 &post_flush);
1709 }
1710 }
1711
1712 radv_meta_restore(&saved_state, cmd_buffer);
1713 cmd_buffer->state.flush_bits |= post_flush;
1714 }
1715
1716 static void
1717 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1718 struct radv_image *image,
1719 VkImageLayout image_layout,
1720 const VkImageSubresourceRange *range,
1721 VkFormat format, int level, int layer,
1722 const VkClearValue *clear_val)
1723 {
1724 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1725 struct radv_image_view iview;
1726 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1727 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1728
1729 radv_image_view_init(&iview, cmd_buffer->device,
1730 &(VkImageViewCreateInfo) {
1731 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1732 .image = radv_image_to_handle(image),
1733 .viewType = radv_meta_get_view_type(image),
1734 .format = format,
1735 .subresourceRange = {
1736 .aspectMask = range->aspectMask,
1737 .baseMipLevel = range->baseMipLevel + level,
1738 .levelCount = 1,
1739 .baseArrayLayer = range->baseArrayLayer + layer,
1740 .layerCount = 1
1741 },
1742 });
1743
1744 VkFramebuffer fb;
1745 radv_CreateFramebuffer(device_h,
1746 &(VkFramebufferCreateInfo) {
1747 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1748 .attachmentCount = 1,
1749 .pAttachments = (VkImageView[]) {
1750 radv_image_view_to_handle(&iview),
1751 },
1752 .width = width,
1753 .height = height,
1754 .layers = 1
1755 },
1756 &cmd_buffer->pool->alloc,
1757 &fb);
1758
1759 VkAttachmentDescription att_desc = {
1760 .format = iview.vk_format,
1761 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1762 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1763 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1764 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1765 .initialLayout = image_layout,
1766 .finalLayout = image_layout,
1767 };
1768
1769 VkSubpassDescription subpass_desc = {
1770 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1771 .inputAttachmentCount = 0,
1772 .colorAttachmentCount = 0,
1773 .pColorAttachments = NULL,
1774 .pResolveAttachments = NULL,
1775 .pDepthStencilAttachment = NULL,
1776 .preserveAttachmentCount = 0,
1777 .pPreserveAttachments = NULL,
1778 };
1779
1780 const VkAttachmentReference att_ref = {
1781 .attachment = 0,
1782 .layout = image_layout,
1783 };
1784
1785 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1786 subpass_desc.colorAttachmentCount = 1;
1787 subpass_desc.pColorAttachments = &att_ref;
1788 } else {
1789 subpass_desc.pDepthStencilAttachment = &att_ref;
1790 }
1791
1792 VkRenderPass pass;
1793 radv_CreateRenderPass(device_h,
1794 &(VkRenderPassCreateInfo) {
1795 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1796 .attachmentCount = 1,
1797 .pAttachments = &att_desc,
1798 .subpassCount = 1,
1799 .pSubpasses = &subpass_desc,
1800 },
1801 &cmd_buffer->pool->alloc,
1802 &pass);
1803
1804 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1805 &(VkRenderPassBeginInfo) {
1806 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1807 .renderArea = {
1808 .offset = { 0, 0, },
1809 .extent = {
1810 .width = width,
1811 .height = height,
1812 },
1813 },
1814 .renderPass = pass,
1815 .framebuffer = fb,
1816 .clearValueCount = 0,
1817 .pClearValues = NULL,
1818 },
1819 VK_SUBPASS_CONTENTS_INLINE);
1820
1821 VkClearAttachment clear_att = {
1822 .aspectMask = range->aspectMask,
1823 .colorAttachment = 0,
1824 .clearValue = *clear_val,
1825 };
1826
1827 VkClearRect clear_rect = {
1828 .rect = {
1829 .offset = { 0, 0 },
1830 .extent = { width, height },
1831 },
1832 .baseArrayLayer = range->baseArrayLayer,
1833 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1834 };
1835
1836 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1837
1838 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1839 radv_DestroyRenderPass(device_h, pass,
1840 &cmd_buffer->pool->alloc);
1841 radv_DestroyFramebuffer(device_h, fb,
1842 &cmd_buffer->pool->alloc);
1843 }
1844
1845 /**
1846 * Return TRUE if a fast color or depth clear has been performed.
1847 */
1848 static bool
1849 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
1850 struct radv_image *image,
1851 VkFormat format,
1852 VkImageLayout image_layout,
1853 const VkImageSubresourceRange *range,
1854 const VkClearValue *clear_val)
1855 {
1856 struct radv_image_view iview;
1857
1858 radv_image_view_init(&iview, cmd_buffer->device,
1859 &(VkImageViewCreateInfo) {
1860 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1861 .image = radv_image_to_handle(image),
1862 .viewType = radv_meta_get_view_type(image),
1863 .format = image->vk_format,
1864 .subresourceRange = {
1865 .aspectMask = range->aspectMask,
1866 .baseMipLevel = range->baseMipLevel,
1867 .levelCount = range->levelCount,
1868 .baseArrayLayer = range->baseArrayLayer,
1869 .layerCount = range->layerCount,
1870 },
1871 });
1872
1873 VkClearRect clear_rect = {
1874 .rect = {
1875 .offset = { 0, 0 },
1876 .extent = {
1877 radv_minify(image->info.width, range->baseMipLevel),
1878 radv_minify(image->info.height, range->baseMipLevel),
1879 },
1880 },
1881 .baseArrayLayer = range->baseArrayLayer,
1882 .layerCount = range->layerCount,
1883 };
1884
1885 VkClearAttachment clear_att = {
1886 .aspectMask = range->aspectMask,
1887 .colorAttachment = 0,
1888 .clearValue = *clear_val,
1889 };
1890
1891 if (vk_format_is_color(format)) {
1892 if (radv_can_fast_clear_color(cmd_buffer, &iview,
1893 image_layout, &clear_rect,
1894 clear_att.clearValue.color, 0)) {
1895 radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
1896 clear_att.colorAttachment,
1897 NULL, NULL);
1898 return true;
1899 }
1900 } else {
1901 if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
1902 range->aspectMask, &clear_rect,
1903 clear_att.clearValue.depthStencil, 0)) {
1904 radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
1905 NULL, NULL);
1906 return true;
1907 }
1908 }
1909
1910 return false;
1911 }
1912
1913 static void
1914 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1915 struct radv_image *image,
1916 VkImageLayout image_layout,
1917 const VkClearValue *clear_value,
1918 uint32_t range_count,
1919 const VkImageSubresourceRange *ranges,
1920 bool cs)
1921 {
1922 VkFormat format = image->vk_format;
1923 VkClearValue internal_clear_value = *clear_value;
1924
1925 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1926 uint32_t value;
1927 format = VK_FORMAT_R32_UINT;
1928 value = float3_to_rgb9e5(clear_value->color.float32);
1929 internal_clear_value.color.uint32[0] = value;
1930 }
1931
1932 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1933 uint8_t r, g;
1934 format = VK_FORMAT_R8_UINT;
1935 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1936 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1937 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1938 }
1939
1940 if (format == VK_FORMAT_R32G32B32_UINT ||
1941 format == VK_FORMAT_R32G32B32_SINT ||
1942 format == VK_FORMAT_R32G32B32_SFLOAT)
1943 cs = true;
1944
1945 for (uint32_t r = 0; r < range_count; r++) {
1946 const VkImageSubresourceRange *range = &ranges[r];
1947
1948 /* Try to perform a fast clear first, otherwise fallback to
1949 * the legacy path.
1950 */
1951 if (!cs &&
1952 radv_fast_clear_range(cmd_buffer, image, format,
1953 image_layout, range,
1954 &internal_clear_value)) {
1955 continue;
1956 }
1957
1958 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1959 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1960 radv_minify(image->info.depth, range->baseMipLevel + l) :
1961 radv_get_layerCount(image, range);
1962 for (uint32_t s = 0; s < layer_count; ++s) {
1963
1964 if (cs) {
1965 struct radv_meta_blit2d_surf surf;
1966 surf.format = format;
1967 surf.image = image;
1968 surf.level = range->baseMipLevel + l;
1969 surf.layer = range->baseArrayLayer + s;
1970 surf.aspect_mask = range->aspectMask;
1971 radv_meta_clear_image_cs(cmd_buffer, &surf,
1972 &internal_clear_value.color);
1973 } else {
1974 radv_clear_image_layer(cmd_buffer, image, image_layout,
1975 range, format, l, s, &internal_clear_value);
1976 }
1977 }
1978 }
1979 }
1980 }
1981
1982 void radv_CmdClearColorImage(
1983 VkCommandBuffer commandBuffer,
1984 VkImage image_h,
1985 VkImageLayout imageLayout,
1986 const VkClearColorValue* pColor,
1987 uint32_t rangeCount,
1988 const VkImageSubresourceRange* pRanges)
1989 {
1990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1991 RADV_FROM_HANDLE(radv_image, image, image_h);
1992 struct radv_meta_saved_state saved_state;
1993 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1994
1995 if (cs) {
1996 radv_meta_save(&saved_state, cmd_buffer,
1997 RADV_META_SAVE_COMPUTE_PIPELINE |
1998 RADV_META_SAVE_CONSTANTS |
1999 RADV_META_SAVE_DESCRIPTORS);
2000 } else {
2001 radv_meta_save(&saved_state, cmd_buffer,
2002 RADV_META_SAVE_GRAPHICS_PIPELINE |
2003 RADV_META_SAVE_CONSTANTS);
2004 }
2005
2006 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2007 (const VkClearValue *) pColor,
2008 rangeCount, pRanges, cs);
2009
2010 radv_meta_restore(&saved_state, cmd_buffer);
2011 }
2012
2013 void radv_CmdClearDepthStencilImage(
2014 VkCommandBuffer commandBuffer,
2015 VkImage image_h,
2016 VkImageLayout imageLayout,
2017 const VkClearDepthStencilValue* pDepthStencil,
2018 uint32_t rangeCount,
2019 const VkImageSubresourceRange* pRanges)
2020 {
2021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2022 RADV_FROM_HANDLE(radv_image, image, image_h);
2023 struct radv_meta_saved_state saved_state;
2024
2025 radv_meta_save(&saved_state, cmd_buffer,
2026 RADV_META_SAVE_GRAPHICS_PIPELINE |
2027 RADV_META_SAVE_CONSTANTS);
2028
2029 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2030 (const VkClearValue *) pDepthStencil,
2031 rangeCount, pRanges, false);
2032
2033 radv_meta_restore(&saved_state, cmd_buffer);
2034 }
2035
2036 void radv_CmdClearAttachments(
2037 VkCommandBuffer commandBuffer,
2038 uint32_t attachmentCount,
2039 const VkClearAttachment* pAttachments,
2040 uint32_t rectCount,
2041 const VkClearRect* pRects)
2042 {
2043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2044 struct radv_meta_saved_state saved_state;
2045 enum radv_cmd_flush_bits pre_flush = 0;
2046 enum radv_cmd_flush_bits post_flush = 0;
2047
2048 if (!cmd_buffer->state.subpass)
2049 return;
2050
2051 radv_meta_save(&saved_state, cmd_buffer,
2052 RADV_META_SAVE_GRAPHICS_PIPELINE |
2053 RADV_META_SAVE_CONSTANTS);
2054
2055 /* FINISHME: We can do better than this dumb loop. It thrashes too much
2056 * state.
2057 */
2058 for (uint32_t a = 0; a < attachmentCount; ++a) {
2059 for (uint32_t r = 0; r < rectCount; ++r) {
2060 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
2061 cmd_buffer->state.subpass->view_mask);
2062 }
2063 }
2064
2065 radv_meta_restore(&saved_state, cmd_buffer);
2066 cmd_buffer->state.flush_bits |= post_flush;
2067 }