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radv: refactor the fast clear path for better re-use
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 1,
236 .pPreserveAttachments = (uint32_t[]) { 0 },
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
374 const uint32_t samples = iview->image->info.samples;
375 const uint32_t samples_log2 = ffs(samples) - 1;
376 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 if (fs_key == -1) {
382 radv_finishme("color clears incomplete");
383 return;
384 }
385
386 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
387 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
388 samples,
389 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
390 if (ret != VK_SUCCESS) {
391 cmd_buffer->record_result = ret;
392 return;
393 }
394 }
395
396 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
397 VkResult ret = create_color_pipeline(device, samples, 0,
398 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
399 device->meta_state.clear[samples_log2].render_pass[fs_key]);
400 if (ret != VK_SUCCESS) {
401 cmd_buffer->record_result = ret;
402 return;
403 }
404 }
405
406 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
407 if (!pipeline) {
408 radv_finishme("color clears incomplete");
409 return;
410 }
411 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
412 assert(pipeline);
413 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
414 assert(clear_att->colorAttachment < subpass->color_count);
415
416 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
417 device->meta_state.clear_color_p_layout,
418 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
419 &clear_value);
420
421 struct radv_subpass clear_subpass = {
422 .color_count = 1,
423 .color_attachments = (struct radv_subpass_attachment[]) {
424 subpass->color_attachments[clear_att->colorAttachment]
425 },
426 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
427 };
428
429 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
430
431 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
432 pipeline);
433
434 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
435 .x = clear_rect->rect.offset.x,
436 .y = clear_rect->rect.offset.y,
437 .width = clear_rect->rect.extent.width,
438 .height = clear_rect->rect.extent.height,
439 .minDepth = 0.0f,
440 .maxDepth = 1.0f
441 });
442
443 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
444
445 if (view_mask) {
446 unsigned i;
447 for_each_bit(i, view_mask)
448 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
449 } else {
450 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
451 }
452
453 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
454 }
455
456
457 static void
458 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
459 {
460 nir_builder vs_b, fs_b;
461
462 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
463 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
464
465 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
466 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
467 const struct glsl_type *position_out_type = glsl_vec4_type();
468
469 nir_variable *vs_out_pos =
470 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
471 "gl_Position");
472 vs_out_pos->data.location = VARYING_SLOT_POS;
473
474 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
475 nir_intrinsic_set_base(in_color_load, 0);
476 nir_intrinsic_set_range(in_color_load, 4);
477 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
478 in_color_load->num_components = 1;
479 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
480 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
481
482 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
483 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
484
485 const struct glsl_type *layer_type = glsl_int_type();
486 nir_variable *vs_out_layer =
487 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
488 "v_layer");
489 vs_out_layer->data.location = VARYING_SLOT_LAYER;
490 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
491 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
492 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
493
494 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
495 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
496
497 *out_vs = vs_b.shader;
498 *out_fs = fs_b.shader;
499 }
500
501 static VkResult
502 create_depthstencil_renderpass(struct radv_device *device,
503 uint32_t samples,
504 VkRenderPass *render_pass)
505 {
506 mtx_lock(&device->meta_state.mtx);
507 if (*render_pass) {
508 mtx_unlock(&device->meta_state.mtx);
509 return VK_SUCCESS;
510 }
511
512 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
513 &(VkRenderPassCreateInfo) {
514 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
515 .attachmentCount = 1,
516 .pAttachments = &(VkAttachmentDescription) {
517 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
518 .samples = samples,
519 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
520 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
521 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
522 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
523 },
524 .subpassCount = 1,
525 .pSubpasses = &(VkSubpassDescription) {
526 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
527 .inputAttachmentCount = 0,
528 .colorAttachmentCount = 0,
529 .pColorAttachments = NULL,
530 .pResolveAttachments = NULL,
531 .pDepthStencilAttachment = &(VkAttachmentReference) {
532 .attachment = 0,
533 .layout = VK_IMAGE_LAYOUT_GENERAL,
534 },
535 .preserveAttachmentCount = 1,
536 .pPreserveAttachments = (uint32_t[]) { 0 },
537 },
538 .dependencyCount = 0,
539 }, &device->meta_state.alloc, render_pass);
540 mtx_unlock(&device->meta_state.mtx);
541 return result;
542 }
543
544 static VkResult
545 create_depthstencil_pipeline(struct radv_device *device,
546 VkImageAspectFlags aspects,
547 uint32_t samples,
548 int index,
549 VkPipeline *pipeline,
550 VkRenderPass render_pass)
551 {
552 struct nir_shader *vs_nir, *fs_nir;
553 VkResult result;
554
555 mtx_lock(&device->meta_state.mtx);
556 if (*pipeline) {
557 mtx_unlock(&device->meta_state.mtx);
558 return VK_SUCCESS;
559 }
560
561 build_depthstencil_shader(&vs_nir, &fs_nir);
562
563 const VkPipelineVertexInputStateCreateInfo vi_state = {
564 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
565 .vertexBindingDescriptionCount = 0,
566 .vertexAttributeDescriptionCount = 0,
567 };
568
569 const VkPipelineDepthStencilStateCreateInfo ds_state = {
570 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
571 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
572 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
573 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
574 .depthBoundsTestEnable = false,
575 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
576 .front = {
577 .passOp = VK_STENCIL_OP_REPLACE,
578 .compareOp = VK_COMPARE_OP_ALWAYS,
579 .writeMask = UINT32_MAX,
580 .reference = 0, /* dynamic */
581 },
582 .back = { 0 /* dont care */ },
583 };
584
585 const VkPipelineColorBlendStateCreateInfo cb_state = {
586 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
587 .logicOpEnable = false,
588 .attachmentCount = 0,
589 .pAttachments = NULL,
590 };
591
592 struct radv_graphics_pipeline_create_info extra = {
593 .use_rectlist = true,
594 };
595
596 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
597 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
598 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
599 }
600 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
601 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
602 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
603 }
604 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
605 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
606 device->meta_state.clear_depth_p_layout,
607 &extra, &device->meta_state.alloc, pipeline);
608
609 mtx_unlock(&device->meta_state.mtx);
610 return result;
611 }
612
613 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
614 const struct radv_image_view *iview,
615 VkImageAspectFlags aspects,
616 VkImageLayout layout,
617 const VkClearRect *clear_rect,
618 VkClearDepthStencilValue clear_value)
619 {
620 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
621 cmd_buffer->queue_family_index,
622 cmd_buffer->queue_family_index);
623 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
624 clear_rect->rect.extent.width != iview->extent.width ||
625 clear_rect->rect.extent.height != iview->extent.height)
626 return false;
627 if (radv_image_is_tc_compat_htile(iview->image) &&
628 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
629 clear_value.depth != 1.0) ||
630 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
631 return false;
632 if (radv_image_has_htile(iview->image) &&
633 iview->base_mip == 0 &&
634 iview->base_layer == 0 &&
635 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
636 !radv_image_extent_compare(iview->image, &iview->extent))
637 return true;
638 return false;
639 }
640
641 static VkPipeline
642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
643 struct radv_meta_state *meta_state,
644 const struct radv_image_view *iview,
645 int samples_log2,
646 VkImageAspectFlags aspects,
647 VkImageLayout layout,
648 const VkClearRect *clear_rect,
649 VkClearDepthStencilValue clear_value)
650 {
651 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
652 int index = DEPTH_CLEAR_SLOW;
653 VkPipeline *pipeline;
654
655 if (fast) {
656 /* we don't know the previous clear values, so we always have
657 * the NO_EXPCLEAR path */
658 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
659 }
660
661 switch (aspects) {
662 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
663 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
664 break;
665 case VK_IMAGE_ASPECT_DEPTH_BIT:
666 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
667 break;
668 case VK_IMAGE_ASPECT_STENCIL_BIT:
669 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
670 break;
671 default:
672 unreachable("expected depth or stencil aspect");
673 }
674
675 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
676 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
677 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
678 if (ret != VK_SUCCESS) {
679 cmd_buffer->record_result = ret;
680 return VK_NULL_HANDLE;
681 }
682 }
683
684 if (*pipeline == VK_NULL_HANDLE) {
685 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
686 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
687 if (ret != VK_SUCCESS) {
688 cmd_buffer->record_result = ret;
689 return VK_NULL_HANDLE;
690 }
691 }
692 return *pipeline;
693 }
694
695 static void
696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
697 const VkClearAttachment *clear_att,
698 const VkClearRect *clear_rect)
699 {
700 struct radv_device *device = cmd_buffer->device;
701 struct radv_meta_state *meta_state = &device->meta_state;
702 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
703 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
704 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
705 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
706 VkImageAspectFlags aspects = clear_att->aspectMask;
707 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
708 const uint32_t samples = iview->image->info.samples;
709 const uint32_t samples_log2 = ffs(samples) - 1;
710 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
711
712 assert(pass_att != VK_ATTACHMENT_UNUSED);
713
714 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
715 clear_value.depth = 1.0f;
716
717 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
718 device->meta_state.clear_depth_p_layout,
719 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
720 &clear_value.depth);
721
722 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
723 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
724 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
725 clear_value.stencil);
726 }
727
728 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
729 meta_state,
730 iview,
731 samples_log2,
732 aspects,
733 subpass->depth_stencil_attachment.layout,
734 clear_rect,
735 clear_value);
736 if (!pipeline)
737 return;
738
739 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
740 pipeline);
741
742 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
743 subpass->depth_stencil_attachment.layout,
744 clear_rect, clear_value))
745 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
746 clear_value, aspects);
747
748 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
749 .x = clear_rect->rect.offset.x,
750 .y = clear_rect->rect.offset.y,
751 .width = clear_rect->rect.extent.width,
752 .height = clear_rect->rect.extent.height,
753 .minDepth = 0.0f,
754 .maxDepth = 1.0f
755 });
756
757 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
758
759 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
760
761 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
762 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
763 prev_reference);
764 }
765 }
766
767 static uint32_t
768 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
769 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
770 uint32_t htile_value, uint32_t htile_mask)
771 {
772 struct radv_device *device = cmd_buffer->device;
773 struct radv_meta_state *state = &device->meta_state;
774 uint64_t block_count = round_up_u64(size, 1024);
775 struct radv_meta_saved_state saved_state;
776
777 radv_meta_save(&saved_state, cmd_buffer,
778 RADV_META_SAVE_COMPUTE_PIPELINE |
779 RADV_META_SAVE_CONSTANTS |
780 RADV_META_SAVE_DESCRIPTORS);
781
782 struct radv_buffer dst_buffer = {
783 .bo = bo,
784 .offset = offset,
785 .size = size
786 };
787
788 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
789 VK_PIPELINE_BIND_POINT_COMPUTE,
790 state->clear_htile_mask_pipeline);
791
792 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
793 state->clear_htile_mask_p_layout,
794 0, /* set */
795 1, /* descriptorWriteCount */
796 (VkWriteDescriptorSet[]) {
797 {
798 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
799 .dstBinding = 0,
800 .dstArrayElement = 0,
801 .descriptorCount = 1,
802 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
803 .pBufferInfo = &(VkDescriptorBufferInfo) {
804 .buffer = radv_buffer_to_handle(&dst_buffer),
805 .offset = 0,
806 .range = size
807 }
808 }
809 });
810
811 const unsigned constants[2] = {
812 htile_value & htile_mask,
813 ~htile_mask,
814 };
815
816 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
817 state->clear_htile_mask_p_layout,
818 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
819 constants);
820
821 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
822
823 radv_meta_restore(&saved_state, cmd_buffer);
824
825 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
826 RADV_CMD_FLAG_INV_VMEM_L1 |
827 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
828 }
829
830 static uint32_t
831 radv_get_htile_fast_clear_value(const struct radv_image *image,
832 VkClearDepthStencilValue value)
833 {
834 uint32_t clear_value;
835
836 if (!image->surface.has_stencil) {
837 clear_value = value.depth ? 0xfffffff0 : 0;
838 } else {
839 clear_value = value.depth ? 0xfffc0000 : 0;
840 }
841
842 return clear_value;
843 }
844
845 static uint32_t
846 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
847 {
848 uint32_t mask = 0;
849
850 if (!image->surface.has_stencil) {
851 /* All the HTILE buffer is used when there is no stencil. */
852 mask = UINT32_MAX;
853 } else {
854 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
855 mask |= 0xfffffc0f;
856 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
857 mask |= 0x000003f0;
858 }
859
860 return mask;
861 }
862
863 static bool
864 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
865 {
866 return value.depth == 1.0f || value.depth == 0.0f;
867 }
868
869 static bool
870 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
871 {
872 return value.stencil == 0;
873 }
874
875 /**
876 * Determine if the given image can be fast cleared.
877 */
878 static bool
879 radv_image_can_fast_clear(struct radv_device *device, struct radv_image *image)
880 {
881 if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
882 return false;
883
884 if (vk_format_is_color(image->vk_format)) {
885 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
886 return false;
887
888 /* RB+ doesn't work with CMASK fast clear on Stoney. */
889 if (!radv_image_has_dcc(image) &&
890 device->physical_device->rad_info.family == CHIP_STONEY)
891 return false;
892 } else {
893 if (!radv_image_has_htile(image))
894 return false;
895
896 /* GFX8 only supports 32-bit depth surfaces but we can enable
897 * TC-compat HTILE for 16-bit surfaces if no Z planes are
898 * compressed. Though, fast HTILE clears don't seem to work.
899 */
900 if (device->physical_device->rad_info.chip_class == VI &&
901 image->vk_format == VK_FORMAT_D16_UNORM)
902 return false;
903 }
904
905 /* Do not fast clears 3D images. */
906 if (image->type == VK_IMAGE_TYPE_3D)
907 return false;
908
909 return true;
910 }
911
912 /**
913 * Determine if the given image view can be fast cleared.
914 */
915 static bool
916 radv_image_view_can_fast_clear(struct radv_device *device,
917 const struct radv_image_view *iview)
918 {
919 struct radv_image *image = iview->image;
920
921 /* Only fast clear if the image itself can be fast cleared. */
922 if (!radv_image_can_fast_clear(device, image))
923 return false;
924
925 /* Only fast clear if all layers are bound. */
926 if (iview->base_layer > 0 ||
927 iview->layer_count != image->info.array_size)
928 return false;
929
930 /* Only fast clear if the view covers the whole image. */
931 if (!radv_image_extent_compare(image, &iview->extent))
932 return false;
933
934 return true;
935 }
936
937 static bool
938 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
939 const struct radv_image_view *iview,
940 VkImageLayout image_layout,
941 VkImageAspectFlags aspects,
942 const VkClearRect *clear_rect,
943 const VkClearDepthStencilValue clear_value)
944 {
945 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
946 return false;
947
948 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
949 return false;
950
951 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
952 clear_rect->rect.extent.width != iview->image->info.width ||
953 clear_rect->rect.extent.height != iview->image->info.height)
954 return false;
955
956 if (clear_rect->baseArrayLayer != 0)
957 return false;
958 if (clear_rect->layerCount != iview->image->info.array_size)
959 return false;
960
961 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
962 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
963 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
964 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
965 return false;
966
967 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
968 !radv_is_fast_clear_depth_allowed(clear_value)) ||
969 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
970 !radv_is_fast_clear_stencil_allowed(clear_value)))
971 return false;
972
973 return true;
974 }
975
976 static void
977 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
978 const struct radv_image_view *iview,
979 const VkClearAttachment *clear_att,
980 enum radv_cmd_flush_bits *pre_flush,
981 enum radv_cmd_flush_bits *post_flush)
982 {
983 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
984 VkImageAspectFlags aspects = clear_att->aspectMask;
985 uint32_t clear_word, flush_bits;
986 uint32_t htile_mask;
987
988 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
989 htile_mask = radv_get_htile_mask(iview->image, aspects);
990
991 if (pre_flush) {
992 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
993 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
994 *pre_flush |= cmd_buffer->state.flush_bits;
995 }
996
997 if (htile_mask == UINT_MAX) {
998 /* Clear the whole HTILE buffer. */
999 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1000 iview->image->offset + iview->image->htile_offset,
1001 iview->image->surface.htile_size, clear_word);
1002 } else {
1003 /* Only clear depth or stencil bytes in the HTILE buffer. */
1004 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
1005 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1006 iview->image->offset + iview->image->htile_offset,
1007 iview->image->surface.htile_size, clear_word,
1008 htile_mask);
1009 }
1010
1011 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1012 if (post_flush) {
1013 *post_flush |= flush_bits;
1014 }
1015 }
1016
1017 static nir_shader *
1018 build_clear_htile_mask_shader()
1019 {
1020 nir_builder b;
1021
1022 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1023 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1024 b.shader->info.cs.local_size[0] = 64;
1025 b.shader->info.cs.local_size[1] = 1;
1026 b.shader->info.cs.local_size[2] = 1;
1027
1028 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
1029 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
1030 nir_ssa_def *block_size = nir_imm_ivec4(&b,
1031 b.shader->info.cs.local_size[0],
1032 b.shader->info.cs.local_size[1],
1033 b.shader->info.cs.local_size[2], 0);
1034
1035 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1036
1037 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1038 offset = nir_channel(&b, offset, 0);
1039
1040 nir_intrinsic_instr *buf =
1041 nir_intrinsic_instr_create(b.shader,
1042 nir_intrinsic_vulkan_resource_index);
1043
1044 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1045 nir_intrinsic_set_desc_set(buf, 0);
1046 nir_intrinsic_set_binding(buf, 0);
1047 nir_ssa_dest_init(&buf->instr, &buf->dest, 1, 32, NULL);
1048 nir_builder_instr_insert(&b, &buf->instr);
1049
1050 nir_intrinsic_instr *constants =
1051 nir_intrinsic_instr_create(b.shader,
1052 nir_intrinsic_load_push_constant);
1053 nir_intrinsic_set_base(constants, 0);
1054 nir_intrinsic_set_range(constants, 8);
1055 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1056 constants->num_components = 2;
1057 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1058 nir_builder_instr_insert(&b, &constants->instr);
1059
1060 nir_intrinsic_instr *load =
1061 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1062 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1063 load->src[1] = nir_src_for_ssa(offset);
1064 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1065 load->num_components = 4;
1066 nir_builder_instr_insert(&b, &load->instr);
1067
1068 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1069 nir_ssa_def *data =
1070 nir_iand(&b, &load->dest.ssa,
1071 nir_channel(&b, &constants->dest.ssa, 1));
1072 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1073
1074 nir_intrinsic_instr *store =
1075 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1076 store->src[0] = nir_src_for_ssa(data);
1077 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1078 store->src[2] = nir_src_for_ssa(offset);
1079 nir_intrinsic_set_write_mask(store, 0xf);
1080 store->num_components = 4;
1081 nir_builder_instr_insert(&b, &store->instr);
1082
1083 return b.shader;
1084 }
1085
1086 static VkResult
1087 init_meta_clear_htile_mask_state(struct radv_device *device)
1088 {
1089 struct radv_meta_state *state = &device->meta_state;
1090 struct radv_shader_module cs = { .nir = NULL };
1091 VkResult result;
1092
1093 cs.nir = build_clear_htile_mask_shader();
1094
1095 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1096 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1097 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1098 .bindingCount = 1,
1099 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1100 {
1101 .binding = 0,
1102 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1103 .descriptorCount = 1,
1104 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1105 .pImmutableSamplers = NULL
1106 },
1107 }
1108 };
1109
1110 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1111 &ds_layout_info, &state->alloc,
1112 &state->clear_htile_mask_ds_layout);
1113 if (result != VK_SUCCESS)
1114 goto fail;
1115
1116 VkPipelineLayoutCreateInfo p_layout_info = {
1117 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1118 .setLayoutCount = 1,
1119 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1120 .pushConstantRangeCount = 1,
1121 .pPushConstantRanges = &(VkPushConstantRange){
1122 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1123 },
1124 };
1125
1126 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1127 &p_layout_info, &state->alloc,
1128 &state->clear_htile_mask_p_layout);
1129 if (result != VK_SUCCESS)
1130 goto fail;
1131
1132 VkPipelineShaderStageCreateInfo shader_stage = {
1133 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1134 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1135 .module = radv_shader_module_to_handle(&cs),
1136 .pName = "main",
1137 .pSpecializationInfo = NULL,
1138 };
1139
1140 VkComputePipelineCreateInfo pipeline_info = {
1141 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1142 .stage = shader_stage,
1143 .flags = 0,
1144 .layout = state->clear_htile_mask_p_layout,
1145 };
1146
1147 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1148 radv_pipeline_cache_to_handle(&state->cache),
1149 1, &pipeline_info, NULL,
1150 &state->clear_htile_mask_pipeline);
1151
1152 ralloc_free(cs.nir);
1153 return result;
1154 fail:
1155 ralloc_free(cs.nir);
1156 return result;
1157 }
1158
1159 VkResult
1160 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1161 {
1162 VkResult res;
1163 struct radv_meta_state *state = &device->meta_state;
1164
1165 VkPipelineLayoutCreateInfo pl_color_create_info = {
1166 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1167 .setLayoutCount = 0,
1168 .pushConstantRangeCount = 1,
1169 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1170 };
1171
1172 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1173 &pl_color_create_info,
1174 &device->meta_state.alloc,
1175 &device->meta_state.clear_color_p_layout);
1176 if (res != VK_SUCCESS)
1177 goto fail;
1178
1179 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1180 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1181 .setLayoutCount = 0,
1182 .pushConstantRangeCount = 1,
1183 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1184 };
1185
1186 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1187 &pl_depth_create_info,
1188 &device->meta_state.alloc,
1189 &device->meta_state.clear_depth_p_layout);
1190 if (res != VK_SUCCESS)
1191 goto fail;
1192
1193 res = init_meta_clear_htile_mask_state(device);
1194 if (res != VK_SUCCESS)
1195 goto fail;
1196
1197 if (on_demand)
1198 return VK_SUCCESS;
1199
1200 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1201 uint32_t samples = 1 << i;
1202 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1203 VkFormat format = radv_fs_key_format_exemplars[j];
1204 unsigned fs_key = radv_format_meta_fs_key(format);
1205 assert(!state->clear[i].color_pipelines[fs_key]);
1206
1207 res = create_color_renderpass(device, format, samples,
1208 &state->clear[i].render_pass[fs_key]);
1209 if (res != VK_SUCCESS)
1210 goto fail;
1211
1212 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1213 state->clear[i].render_pass[fs_key]);
1214 if (res != VK_SUCCESS)
1215 goto fail;
1216
1217 }
1218
1219 res = create_depthstencil_renderpass(device,
1220 samples,
1221 &state->clear[i].depthstencil_rp);
1222 if (res != VK_SUCCESS)
1223 goto fail;
1224
1225 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1226 res = create_depthstencil_pipeline(device,
1227 VK_IMAGE_ASPECT_DEPTH_BIT,
1228 samples,
1229 j,
1230 &state->clear[i].depth_only_pipeline[j],
1231 state->clear[i].depthstencil_rp);
1232 if (res != VK_SUCCESS)
1233 goto fail;
1234
1235 res = create_depthstencil_pipeline(device,
1236 VK_IMAGE_ASPECT_STENCIL_BIT,
1237 samples,
1238 j,
1239 &state->clear[i].stencil_only_pipeline[j],
1240 state->clear[i].depthstencil_rp);
1241 if (res != VK_SUCCESS)
1242 goto fail;
1243
1244 res = create_depthstencil_pipeline(device,
1245 VK_IMAGE_ASPECT_DEPTH_BIT |
1246 VK_IMAGE_ASPECT_STENCIL_BIT,
1247 samples,
1248 j,
1249 &state->clear[i].depthstencil_pipeline[j],
1250 state->clear[i].depthstencil_rp);
1251 if (res != VK_SUCCESS)
1252 goto fail;
1253 }
1254 }
1255 return VK_SUCCESS;
1256
1257 fail:
1258 radv_device_finish_meta_clear_state(device);
1259 return res;
1260 }
1261
1262 static uint32_t
1263 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1264 {
1265 uint32_t value = 0; /* Default value when no DCC. */
1266
1267 /* The fast-clear value is different for images that have both DCC and
1268 * CMASK metadata.
1269 */
1270 if (radv_image_has_dcc(image)) {
1271 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1272 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1273 }
1274
1275 return value;
1276 }
1277
1278 uint32_t
1279 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1280 struct radv_image *image, uint32_t value)
1281 {
1282 return radv_fill_buffer(cmd_buffer, image->bo,
1283 image->offset + image->cmask.offset,
1284 image->cmask.size, value);
1285 }
1286
1287 uint32_t
1288 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1289 struct radv_image *image, uint32_t value)
1290 {
1291 return radv_fill_buffer(cmd_buffer, image->bo,
1292 image->offset + image->dcc_offset,
1293 image->surface.dcc_size, value);
1294 }
1295
1296 static void vi_get_fast_clear_parameters(VkFormat format,
1297 const VkClearColorValue *clear_value,
1298 uint32_t* reset_value,
1299 bool *can_avoid_fast_clear_elim)
1300 {
1301 bool values[4] = {};
1302 int extra_channel;
1303 bool main_value = false;
1304 bool extra_value = false;
1305 int i;
1306 *can_avoid_fast_clear_elim = false;
1307
1308 *reset_value = 0x20202020U;
1309
1310 const struct vk_format_description *desc = vk_format_description(format);
1311 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1312 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1313 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1314 extra_channel = -1;
1315 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1316 if (radv_translate_colorswap(format, false) <= 1)
1317 extra_channel = desc->nr_channels - 1;
1318 else
1319 extra_channel = 0;
1320 } else
1321 return;
1322
1323 for (i = 0; i < 4; i++) {
1324 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1325 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1326 desc->swizzle[i] > VK_SWIZZLE_W)
1327 continue;
1328
1329 if (desc->channel[i].pure_integer &&
1330 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1331 /* Use the maximum value for clamping the clear color. */
1332 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1333
1334 values[i] = clear_value->int32[i] != 0;
1335 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1336 return;
1337 } else if (desc->channel[i].pure_integer &&
1338 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1339 /* Use the maximum value for clamping the clear color. */
1340 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1341
1342 values[i] = clear_value->uint32[i] != 0U;
1343 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1344 return;
1345 } else {
1346 values[i] = clear_value->float32[i] != 0.0F;
1347 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1348 return;
1349 }
1350
1351 if (index == extra_channel)
1352 extra_value = values[i];
1353 else
1354 main_value = values[i];
1355 }
1356
1357 for (int i = 0; i < 4; ++i)
1358 if (values[i] != main_value &&
1359 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1360 desc->swizzle[i] >= VK_SWIZZLE_X &&
1361 desc->swizzle[i] <= VK_SWIZZLE_W)
1362 return;
1363
1364 *can_avoid_fast_clear_elim = true;
1365 if (main_value)
1366 *reset_value |= 0x80808080U;
1367
1368 if (extra_value)
1369 *reset_value |= 0x40404040U;
1370 return;
1371 }
1372
1373 static bool
1374 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1375 const struct radv_image_view *iview,
1376 VkImageLayout image_layout,
1377 const VkClearRect *clear_rect,
1378 VkClearColorValue clear_value,
1379 uint32_t view_mask)
1380 {
1381 uint32_t clear_color[2];
1382
1383 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1384 return false;
1385
1386 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1387 return false;
1388
1389 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1390 clear_rect->rect.extent.width != iview->image->info.width ||
1391 clear_rect->rect.extent.height != iview->image->info.height)
1392 return false;
1393
1394 if (view_mask && (iview->image->info.array_size >= 32 ||
1395 (1u << iview->image->info.array_size) - 1u != view_mask))
1396 return false;
1397 if (!view_mask && clear_rect->baseArrayLayer != 0)
1398 return false;
1399 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1400 return false;
1401
1402 /* DCC */
1403 if (!radv_format_pack_clear_color(iview->vk_format,
1404 clear_color, &clear_value))
1405 return false;
1406
1407 if (radv_image_has_dcc(iview->image)) {
1408 bool can_avoid_fast_clear_elim;
1409 uint32_t reset_value;
1410
1411 vi_get_fast_clear_parameters(iview->vk_format,
1412 &clear_value, &reset_value,
1413 &can_avoid_fast_clear_elim);
1414
1415 if (iview->image->info.samples > 1) {
1416 /* DCC fast clear with MSAA should clear CMASK. */
1417 /* FIXME: This doesn't work for now. There is a
1418 * hardware bug with fast clears and DCC for MSAA
1419 * textures. AMDVLK has a workaround but it doesn't
1420 * seem to work here. Note that we might emit useless
1421 * CB flushes but that shouldn't matter.
1422 */
1423 if (!can_avoid_fast_clear_elim)
1424 return false;
1425 }
1426 }
1427
1428 return true;
1429 }
1430
1431
1432 static void
1433 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1434 const struct radv_image_view *iview,
1435 const VkClearAttachment *clear_att,
1436 uint32_t subpass_att,
1437 enum radv_cmd_flush_bits *pre_flush,
1438 enum radv_cmd_flush_bits *post_flush)
1439 {
1440 VkClearColorValue clear_value = clear_att->clearValue.color;
1441 uint32_t clear_color[2], flush_bits = 0;
1442 uint32_t cmask_clear_value;
1443
1444 if (pre_flush) {
1445 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1446 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1447 *pre_flush |= cmd_buffer->state.flush_bits;
1448 }
1449
1450 /* DCC */
1451 radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1452
1453 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1454
1455 /* clear cmask buffer */
1456 if (radv_image_has_dcc(iview->image)) {
1457 uint32_t reset_value;
1458 bool can_avoid_fast_clear_elim;
1459 bool need_decompress_pass = false;
1460
1461 vi_get_fast_clear_parameters(iview->vk_format,
1462 &clear_value, &reset_value,
1463 &can_avoid_fast_clear_elim);
1464
1465 if (radv_image_has_cmask(iview->image)) {
1466 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1467 cmask_clear_value);
1468
1469 need_decompress_pass = true;
1470 }
1471
1472 if (!can_avoid_fast_clear_elim)
1473 need_decompress_pass = true;
1474
1475 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1476
1477 radv_update_fce_metadata(cmd_buffer, iview->image,
1478 need_decompress_pass);
1479 } else {
1480 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1481 cmask_clear_value);
1482 }
1483
1484 if (post_flush) {
1485 *post_flush |= flush_bits;
1486 }
1487
1488 radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1489 clear_color);
1490 }
1491
1492 /**
1493 * The parameters mean that same as those in vkCmdClearAttachments.
1494 */
1495 static void
1496 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1497 const VkClearAttachment *clear_att,
1498 const VkClearRect *clear_rect,
1499 enum radv_cmd_flush_bits *pre_flush,
1500 enum radv_cmd_flush_bits *post_flush,
1501 uint32_t view_mask)
1502 {
1503 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1504 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1505 VkImageAspectFlags aspects = clear_att->aspectMask;
1506
1507 if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1508 const uint32_t subpass_att = clear_att->colorAttachment;
1509 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1510 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1511 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1512 VkClearColorValue clear_value = clear_att->clearValue.color;
1513
1514 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1515 clear_rect, clear_value, view_mask)) {
1516 radv_fast_clear_color(cmd_buffer, iview, clear_att,
1517 subpass_att, pre_flush,
1518 post_flush);
1519 } else {
1520 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1521 }
1522 } else {
1523 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
1524 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
1525 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1526 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1527
1528 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1529 VK_IMAGE_ASPECT_STENCIL_BIT));
1530
1531 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1532 aspects, clear_rect, clear_value)) {
1533 radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1534 pre_flush, post_flush);
1535 } else {
1536 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1537 }
1538 }
1539 }
1540
1541 static inline bool
1542 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1543 {
1544 uint32_t view_mask = cmd_state->subpass->view_mask;
1545 return (a != VK_ATTACHMENT_UNUSED &&
1546 cmd_state->attachments[a].pending_clear_aspects &&
1547 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1548 }
1549
1550 static bool
1551 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1552 {
1553 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1554 uint32_t a;
1555
1556 if (!cmd_state->subpass)
1557 return false;
1558
1559 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1560 a = cmd_state->subpass->color_attachments[i].attachment;
1561 if (radv_attachment_needs_clear(cmd_state, a))
1562 return true;
1563 }
1564
1565 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1566 return radv_attachment_needs_clear(cmd_state, a);
1567 }
1568
1569 static void
1570 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1571 struct radv_attachment_state *attachment,
1572 const VkClearAttachment *clear_att,
1573 enum radv_cmd_flush_bits *pre_flush,
1574 enum radv_cmd_flush_bits *post_flush)
1575 {
1576 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1577 uint32_t view_mask = cmd_state->subpass->view_mask;
1578
1579 VkClearRect clear_rect = {
1580 .rect = cmd_state->render_area,
1581 .baseArrayLayer = 0,
1582 .layerCount = cmd_state->framebuffer->layers,
1583 };
1584
1585 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1586 view_mask & ~attachment->cleared_views);
1587 if (view_mask)
1588 attachment->cleared_views |= view_mask;
1589 else
1590 attachment->pending_clear_aspects = 0;
1591 }
1592
1593 /**
1594 * Emit any pending attachment clears for the current subpass.
1595 *
1596 * @see radv_attachment_state::pending_clear_aspects
1597 */
1598 void
1599 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1600 {
1601 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1602 struct radv_meta_saved_state saved_state;
1603 enum radv_cmd_flush_bits pre_flush = 0;
1604 enum radv_cmd_flush_bits post_flush = 0;
1605
1606 if (!radv_subpass_needs_clear(cmd_buffer))
1607 return;
1608
1609 radv_meta_save(&saved_state, cmd_buffer,
1610 RADV_META_SAVE_GRAPHICS_PIPELINE |
1611 RADV_META_SAVE_CONSTANTS);
1612
1613 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1614 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1615
1616 if (!radv_attachment_needs_clear(cmd_state, a))
1617 continue;
1618
1619 assert(cmd_state->attachments[a].pending_clear_aspects ==
1620 VK_IMAGE_ASPECT_COLOR_BIT);
1621
1622 VkClearAttachment clear_att = {
1623 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1624 .colorAttachment = i, /* Use attachment index relative to subpass */
1625 .clearValue = cmd_state->attachments[a].clear_value,
1626 };
1627
1628 radv_subpass_clear_attachment(cmd_buffer,
1629 &cmd_state->attachments[a],
1630 &clear_att, &pre_flush,
1631 &post_flush);
1632 }
1633
1634 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1635 if (radv_attachment_needs_clear(cmd_state, ds)) {
1636 VkClearAttachment clear_att = {
1637 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1638 .clearValue = cmd_state->attachments[ds].clear_value,
1639 };
1640
1641 radv_subpass_clear_attachment(cmd_buffer,
1642 &cmd_state->attachments[ds],
1643 &clear_att, &pre_flush,
1644 &post_flush);
1645 }
1646
1647 radv_meta_restore(&saved_state, cmd_buffer);
1648 cmd_buffer->state.flush_bits |= post_flush;
1649 }
1650
1651 static void
1652 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1653 struct radv_image *image,
1654 VkImageLayout image_layout,
1655 const VkImageSubresourceRange *range,
1656 VkFormat format, int level, int layer,
1657 const VkClearValue *clear_val)
1658 {
1659 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1660 struct radv_image_view iview;
1661 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1662 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1663
1664 radv_image_view_init(&iview, cmd_buffer->device,
1665 &(VkImageViewCreateInfo) {
1666 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1667 .image = radv_image_to_handle(image),
1668 .viewType = radv_meta_get_view_type(image),
1669 .format = format,
1670 .subresourceRange = {
1671 .aspectMask = range->aspectMask,
1672 .baseMipLevel = range->baseMipLevel + level,
1673 .levelCount = 1,
1674 .baseArrayLayer = range->baseArrayLayer + layer,
1675 .layerCount = 1
1676 },
1677 });
1678
1679 VkFramebuffer fb;
1680 radv_CreateFramebuffer(device_h,
1681 &(VkFramebufferCreateInfo) {
1682 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1683 .attachmentCount = 1,
1684 .pAttachments = (VkImageView[]) {
1685 radv_image_view_to_handle(&iview),
1686 },
1687 .width = width,
1688 .height = height,
1689 .layers = 1
1690 },
1691 &cmd_buffer->pool->alloc,
1692 &fb);
1693
1694 VkAttachmentDescription att_desc = {
1695 .format = iview.vk_format,
1696 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1697 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1698 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1699 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1700 .initialLayout = image_layout,
1701 .finalLayout = image_layout,
1702 };
1703
1704 VkSubpassDescription subpass_desc = {
1705 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1706 .inputAttachmentCount = 0,
1707 .colorAttachmentCount = 0,
1708 .pColorAttachments = NULL,
1709 .pResolveAttachments = NULL,
1710 .pDepthStencilAttachment = NULL,
1711 .preserveAttachmentCount = 0,
1712 .pPreserveAttachments = NULL,
1713 };
1714
1715 const VkAttachmentReference att_ref = {
1716 .attachment = 0,
1717 .layout = image_layout,
1718 };
1719
1720 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1721 subpass_desc.colorAttachmentCount = 1;
1722 subpass_desc.pColorAttachments = &att_ref;
1723 } else {
1724 subpass_desc.pDepthStencilAttachment = &att_ref;
1725 }
1726
1727 VkRenderPass pass;
1728 radv_CreateRenderPass(device_h,
1729 &(VkRenderPassCreateInfo) {
1730 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1731 .attachmentCount = 1,
1732 .pAttachments = &att_desc,
1733 .subpassCount = 1,
1734 .pSubpasses = &subpass_desc,
1735 },
1736 &cmd_buffer->pool->alloc,
1737 &pass);
1738
1739 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1740 &(VkRenderPassBeginInfo) {
1741 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1742 .renderArea = {
1743 .offset = { 0, 0, },
1744 .extent = {
1745 .width = width,
1746 .height = height,
1747 },
1748 },
1749 .renderPass = pass,
1750 .framebuffer = fb,
1751 .clearValueCount = 0,
1752 .pClearValues = NULL,
1753 },
1754 VK_SUBPASS_CONTENTS_INLINE);
1755
1756 VkClearAttachment clear_att = {
1757 .aspectMask = range->aspectMask,
1758 .colorAttachment = 0,
1759 .clearValue = *clear_val,
1760 };
1761
1762 VkClearRect clear_rect = {
1763 .rect = {
1764 .offset = { 0, 0 },
1765 .extent = { width, height },
1766 },
1767 .baseArrayLayer = range->baseArrayLayer,
1768 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1769 };
1770
1771 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1772
1773 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1774 radv_DestroyRenderPass(device_h, pass,
1775 &cmd_buffer->pool->alloc);
1776 radv_DestroyFramebuffer(device_h, fb,
1777 &cmd_buffer->pool->alloc);
1778 }
1779 static void
1780 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1781 struct radv_image *image,
1782 VkImageLayout image_layout,
1783 const VkClearValue *clear_value,
1784 uint32_t range_count,
1785 const VkImageSubresourceRange *ranges,
1786 bool cs)
1787 {
1788 VkFormat format = image->vk_format;
1789 VkClearValue internal_clear_value = *clear_value;
1790
1791 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1792 uint32_t value;
1793 format = VK_FORMAT_R32_UINT;
1794 value = float3_to_rgb9e5(clear_value->color.float32);
1795 internal_clear_value.color.uint32[0] = value;
1796 }
1797
1798 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1799 uint8_t r, g;
1800 format = VK_FORMAT_R8_UINT;
1801 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1802 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1803 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1804 }
1805
1806 for (uint32_t r = 0; r < range_count; r++) {
1807 const VkImageSubresourceRange *range = &ranges[r];
1808 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1809 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1810 radv_minify(image->info.depth, range->baseMipLevel + l) :
1811 radv_get_layerCount(image, range);
1812 for (uint32_t s = 0; s < layer_count; ++s) {
1813
1814 if (cs ||
1815 (format == VK_FORMAT_R32G32B32_UINT ||
1816 format == VK_FORMAT_R32G32B32_SINT ||
1817 format == VK_FORMAT_R32G32B32_SFLOAT)) {
1818 struct radv_meta_blit2d_surf surf;
1819 surf.format = format;
1820 surf.image = image;
1821 surf.level = range->baseMipLevel + l;
1822 surf.layer = range->baseArrayLayer + s;
1823 surf.aspect_mask = range->aspectMask;
1824 radv_meta_clear_image_cs(cmd_buffer, &surf,
1825 &internal_clear_value.color);
1826 } else {
1827 radv_clear_image_layer(cmd_buffer, image, image_layout,
1828 range, format, l, s, &internal_clear_value);
1829 }
1830 }
1831 }
1832 }
1833 }
1834
1835 void radv_CmdClearColorImage(
1836 VkCommandBuffer commandBuffer,
1837 VkImage image_h,
1838 VkImageLayout imageLayout,
1839 const VkClearColorValue* pColor,
1840 uint32_t rangeCount,
1841 const VkImageSubresourceRange* pRanges)
1842 {
1843 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1844 RADV_FROM_HANDLE(radv_image, image, image_h);
1845 struct radv_meta_saved_state saved_state;
1846 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1847
1848 if (cs) {
1849 radv_meta_save(&saved_state, cmd_buffer,
1850 RADV_META_SAVE_COMPUTE_PIPELINE |
1851 RADV_META_SAVE_CONSTANTS |
1852 RADV_META_SAVE_DESCRIPTORS);
1853 } else {
1854 radv_meta_save(&saved_state, cmd_buffer,
1855 RADV_META_SAVE_GRAPHICS_PIPELINE |
1856 RADV_META_SAVE_CONSTANTS);
1857 }
1858
1859 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1860 (const VkClearValue *) pColor,
1861 rangeCount, pRanges, cs);
1862
1863 radv_meta_restore(&saved_state, cmd_buffer);
1864 }
1865
1866 void radv_CmdClearDepthStencilImage(
1867 VkCommandBuffer commandBuffer,
1868 VkImage image_h,
1869 VkImageLayout imageLayout,
1870 const VkClearDepthStencilValue* pDepthStencil,
1871 uint32_t rangeCount,
1872 const VkImageSubresourceRange* pRanges)
1873 {
1874 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1875 RADV_FROM_HANDLE(radv_image, image, image_h);
1876 struct radv_meta_saved_state saved_state;
1877
1878 radv_meta_save(&saved_state, cmd_buffer,
1879 RADV_META_SAVE_GRAPHICS_PIPELINE |
1880 RADV_META_SAVE_CONSTANTS);
1881
1882 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1883 (const VkClearValue *) pDepthStencil,
1884 rangeCount, pRanges, false);
1885
1886 radv_meta_restore(&saved_state, cmd_buffer);
1887 }
1888
1889 void radv_CmdClearAttachments(
1890 VkCommandBuffer commandBuffer,
1891 uint32_t attachmentCount,
1892 const VkClearAttachment* pAttachments,
1893 uint32_t rectCount,
1894 const VkClearRect* pRects)
1895 {
1896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1897 struct radv_meta_saved_state saved_state;
1898 enum radv_cmd_flush_bits pre_flush = 0;
1899 enum radv_cmd_flush_bits post_flush = 0;
1900
1901 if (!cmd_buffer->state.subpass)
1902 return;
1903
1904 radv_meta_save(&saved_state, cmd_buffer,
1905 RADV_META_SAVE_GRAPHICS_PIPELINE |
1906 RADV_META_SAVE_CONSTANTS);
1907
1908 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1909 * state.
1910 */
1911 for (uint32_t a = 0; a < attachmentCount; ++a) {
1912 for (uint32_t r = 0; r < rectCount; ++r) {
1913 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1914 cmd_buffer->state.subpass->view_mask);
1915 }
1916 }
1917
1918 radv_meta_restore(&saved_state, cmd_buffer);
1919 cmd_buffer->state.flush_bits |= post_flush;
1920 }