src/amd/vulkan/radv_meta_clear.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "radv_debug.h"
  25 #include "radv_meta.h"
  26 #include "radv_private.h"
  27 #include "nir/nir_builder.h"
  28
  29 #include "util/format_rgb9e5.h"
  30 #include "vk_format.h"
  31
  32 enum {
  33         DEPTH_CLEAR_SLOW,
  34         DEPTH_CLEAR_FAST_EXPCLEAR,
  35         DEPTH_CLEAR_FAST_NO_EXPCLEAR
  36 };
  37
  38 static void
  39 build_color_shaders(struct nir_shader **out_vs,
  40                     struct nir_shader **out_fs,
  41                     uint32_t frag_output)
  42 {
  43         nir_builder vs_b;
  44         nir_builder fs_b;
  45
  46         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
  47         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
  48
  49         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
  50         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
  51
  52         const struct glsl_type *position_type = glsl_vec4_type();
  53         const struct glsl_type *color_type = glsl_vec4_type();
  54
  55         nir_variable *vs_out_pos =
  56                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
  57                                     "gl_Position");
  58         vs_out_pos->data.location = VARYING_SLOT_POS;
  59
  60         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
  61         nir_intrinsic_set_base(in_color_load, 0);
  62         nir_intrinsic_set_range(in_color_load, 16);
  63         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
  64         in_color_load->num_components = 4;
  65         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
  66         nir_builder_instr_insert(&fs_b, &in_color_load->instr);
  67
  68         nir_variable *fs_out_color =
  69                 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
  70                                     "f_color");
  71         fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
  72
  73         nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
  74
  75         nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
  76         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
  77
  78         const struct glsl_type *layer_type = glsl_int_type();
  79         nir_variable *vs_out_layer =
  80                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
  81                                     "v_layer");
  82         vs_out_layer->data.location = VARYING_SLOT_LAYER;
  83         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
  84         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
  85         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
  86
  87         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
  88         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
  89
  90         *out_vs = vs_b.shader;
  91         *out_fs = fs_b.shader;
  92 }
  93
  94 static VkResult
  95 create_pipeline(struct radv_device *device,
  96                 struct radv_render_pass *render_pass,
  97                 uint32_t samples,
  98                 struct nir_shader *vs_nir,
  99                 struct nir_shader *fs_nir,
 100                 const VkPipelineVertexInputStateCreateInfo *vi_state,
 101                 const VkPipelineDepthStencilStateCreateInfo *ds_state,
 102                 const VkPipelineColorBlendStateCreateInfo *cb_state,
 103                 const VkPipelineLayout layout,
 104                 const struct radv_graphics_pipeline_create_info *extra,
 105                 const VkAllocationCallbacks *alloc,
 106                 VkPipeline *pipeline)
 107 {
 108         VkDevice device_h = radv_device_to_handle(device);
 109         VkResult result;
 110
 111         struct radv_shader_module vs_m = { .nir = vs_nir };
 112         struct radv_shader_module fs_m = { .nir = fs_nir };
 113
 114         result = radv_graphics_pipeline_create(device_h,
 115                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 116                                                &(VkGraphicsPipelineCreateInfo) {
 117                                                        .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 118                                                                .stageCount = fs_nir ? 2 : 1,
 119                                                                .pStages = (VkPipelineShaderStageCreateInfo[]) {
 120                                                                {
 121                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 122                                                                        .stage = VK_SHADER_STAGE_VERTEX_BIT,
 123                                                                        .module = radv_shader_module_to_handle(&vs_m),
 124                                                                        .pName = "main",
 125                                                                },
 126                                                                {
 127                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 128                                                                        .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 129                                                                        .module = radv_shader_module_to_handle(&fs_m),
 130                                                                        .pName = "main",
 131                                                                },
 132                                                        },
 133                                                                .pVertexInputState = vi_state,
 134                                                                         .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 135                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 136                                                                .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 137                                                                .primitiveRestartEnable = false,
 138                                                        },
 139                                                                         .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 140                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 141                                                                .viewportCount = 1,
 142                                                                .scissorCount = 1,
 143                                                        },
 144                                                                                  .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 145                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 146                                                                .rasterizerDiscardEnable = false,
 147                                                                .polygonMode = VK_POLYGON_MODE_FILL,
 148                                                                .cullMode = VK_CULL_MODE_NONE,
 149                                                                .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
 150                                                                .depthBiasEnable = false,
 151                                                        },
 152                                                                                           .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
 153                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
 154                                                                .rasterizationSamples = samples,
 155                                                                .sampleShadingEnable = false,
 156                                                                .pSampleMask = NULL,
 157                                                                .alphaToCoverageEnable = false,
 158                                                                .alphaToOneEnable = false,
 159                                                        },
 160                                                                                                    .pDepthStencilState = ds_state,
 161                                                                                                             .pColorBlendState = cb_state,
 162                                                                                                             .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 163                                                                /* The meta clear pipeline declares all state as dynamic.
 164                                                                 * As a consequence, vkCmdBindPipeline writes no dynamic state
 165                                                                 * to the cmd buffer. Therefore, at the end of the meta clear,
 166                                                                 * we need only restore dynamic state was vkCmdSet.
 167                                                                 */
 168                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 169                                                                .dynamicStateCount = 8,
 170                                                                .pDynamicStates = (VkDynamicState[]) {
 171                                                                        /* Everything except stencil write mask */
 172                                                                        VK_DYNAMIC_STATE_VIEWPORT,
 173                                                                        VK_DYNAMIC_STATE_SCISSOR,
 174                                                                        VK_DYNAMIC_STATE_LINE_WIDTH,
 175                                                                        VK_DYNAMIC_STATE_DEPTH_BIAS,
 176                                                                        VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 177                                                                        VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 178                                                                        VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 179                                                                        VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 180                                                                },
 181                                                        },
 182                                                     .layout = layout,
 183                                                     .flags = 0,
 184                                                     .renderPass = radv_render_pass_to_handle(render_pass),
 185                                                     .subpass = 0,
 186                                                 },
 187                                                extra,
 188                                                alloc,
 189                                                pipeline);
 190
 191         ralloc_free(vs_nir);
 192         ralloc_free(fs_nir);
 193
 194         return result;
 195 }
 196
 197 static VkResult
 198 create_color_renderpass(struct radv_device *device,
 199                         VkFormat vk_format,
 200                         uint32_t samples,
 201                         VkRenderPass *pass)
 202 {
 203         mtx_lock(&device->meta_state.mtx);
 204         if (*pass) {
 205                 mtx_unlock (&device->meta_state.mtx);
 206                 return VK_SUCCESS;
 207         }
 208
 209         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 210                                        &(VkRenderPassCreateInfo) {
 211                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 212                                                        .attachmentCount = 1,
 213                                                        .pAttachments = &(VkAttachmentDescription) {
 214                                                        .format = vk_format,
 215                                                        .samples = samples,
 216                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 217                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 218                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 219                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 220                                                },
 221                                                        .subpassCount = 1,
 222                                                                 .pSubpasses = &(VkSubpassDescription) {
 223                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 224                                                        .inputAttachmentCount = 0,
 225                                                        .colorAttachmentCount = 1,
 226                                                        .pColorAttachments = &(VkAttachmentReference) {
 227                                                                .attachment = 0,
 228                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 229                                                        },
 230                                                        .pResolveAttachments = NULL,
 231                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 232                                                                .attachment = VK_ATTACHMENT_UNUSED,
 233                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 234                                                        },
 235                                                        .preserveAttachmentCount = 1,
 236                                                        .pPreserveAttachments = (uint32_t[]) { 0 },
 237                                                },
 238                                                                 .dependencyCount = 0,
 239                                                                          }, &device->meta_state.alloc, pass);
 240         mtx_unlock(&device->meta_state.mtx);
 241         return result;
 242 }
 243
 244 static VkResult
 245 create_color_pipeline(struct radv_device *device,
 246                       uint32_t samples,
 247                       uint32_t frag_output,
 248                       VkPipeline *pipeline,
 249                       VkRenderPass pass)
 250 {
 251         struct nir_shader *vs_nir;
 252         struct nir_shader *fs_nir;
 253         VkResult result;
 254
 255         mtx_lock(&device->meta_state.mtx);
 256         if (*pipeline) {
 257                 mtx_unlock(&device->meta_state.mtx);
 258                 return VK_SUCCESS;
 259         }
 260
 261         build_color_shaders(&vs_nir, &fs_nir, frag_output);
 262
 263         const VkPipelineVertexInputStateCreateInfo vi_state = {
 264                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 265                 .vertexBindingDescriptionCount = 0,
 266                 .vertexAttributeDescriptionCount = 0,
 267         };
 268
 269         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 270                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 271                 .depthTestEnable = false,
 272                 .depthWriteEnable = false,
 273                 .depthBoundsTestEnable = false,
 274                 .stencilTestEnable = false,
 275         };
 276
 277         VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
 278         blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
 279                 .blendEnable = false,
 280                 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
 281                 VK_COLOR_COMPONENT_R_BIT |
 282                 VK_COLOR_COMPONENT_G_BIT |
 283                 VK_COLOR_COMPONENT_B_BIT,
 284         };
 285
 286         const VkPipelineColorBlendStateCreateInfo cb_state = {
 287                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 288                 .logicOpEnable = false,
 289                 .attachmentCount = MAX_RTS,
 290                 .pAttachments = blend_attachment_state
 291         };
 292
 293
 294         struct radv_graphics_pipeline_create_info extra = {
 295                 .use_rectlist = true,
 296         };
 297         result = create_pipeline(device, radv_render_pass_from_handle(pass),
 298                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 299                                  device->meta_state.clear_color_p_layout,
 300                                  &extra, &device->meta_state.alloc, pipeline);
 301
 302         mtx_unlock(&device->meta_state.mtx);
 303         return result;
 304 }
 305
 306 void
 307 radv_device_finish_meta_clear_state(struct radv_device *device)
 308 {
 309         struct radv_meta_state *state = &device->meta_state;
 310
 311         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 312                 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
 313                         radv_DestroyPipeline(radv_device_to_handle(device),
 314                                              state->clear[i].color_pipelines[j],
 315                                              &state->alloc);
 316                         radv_DestroyRenderPass(radv_device_to_handle(device),
 317                                                state->clear[i].render_pass[j],
 318                                                &state->alloc);
 319                 }
 320
 321                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 322                         radv_DestroyPipeline(radv_device_to_handle(device),
 323                                              state->clear[i].depth_only_pipeline[j],
 324                                              &state->alloc);
 325                         radv_DestroyPipeline(radv_device_to_handle(device),
 326                                              state->clear[i].stencil_only_pipeline[j],
 327                                              &state->alloc);
 328                         radv_DestroyPipeline(radv_device_to_handle(device),
 329                                              state->clear[i].depthstencil_pipeline[j],
 330                                              &state->alloc);
 331                 }
 332                 radv_DestroyRenderPass(radv_device_to_handle(device),
 333                                       state->clear[i].depthstencil_rp,
 334                                       &state->alloc);
 335         }
 336         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 337                                    state->clear_color_p_layout,
 338                                    &state->alloc);
 339         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 340                                    state->clear_depth_p_layout,
 341                                    &state->alloc);
 342 }
 343
 344 static void
 345 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 346                  const VkClearAttachment *clear_att,
 347                  const VkClearRect *clear_rect,
 348                  uint32_t view_mask)
 349 {
 350         struct radv_device *device = cmd_buffer->device;
 351         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 352         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 353         const uint32_t subpass_att = clear_att->colorAttachment;
 354         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
 355         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 356         const uint32_t samples = iview->image->info.samples;
 357         const uint32_t samples_log2 = ffs(samples) - 1;
 358         unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
 359         VkClearColorValue clear_value = clear_att->clearValue.color;
 360         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 361         VkPipeline pipeline;
 362
 363         if (fs_key == -1) {
 364                 radv_finishme("color clears incomplete");
 365                 return;
 366         }
 367
 368         if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
 369                 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
 370                                                        samples,
 371                                                        &device->meta_state.clear[samples_log2].render_pass[fs_key]);
 372                 if (ret != VK_SUCCESS) {
 373                         cmd_buffer->record_result = ret;
 374                         return;
 375                 }
 376         }
 377
 378         if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
 379                 VkResult ret = create_color_pipeline(device, samples, 0,
 380                                                      &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
 381                                                      device->meta_state.clear[samples_log2].render_pass[fs_key]);
 382                 if (ret != VK_SUCCESS) {
 383                         cmd_buffer->record_result = ret;
 384                         return;
 385                 }
 386         }
 387
 388         pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
 389         if (!pipeline) {
 390                 radv_finishme("color clears incomplete");
 391                 return;
 392         }
 393         assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
 394         assert(pipeline);
 395         assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 396         assert(clear_att->colorAttachment < subpass->color_count);
 397
 398         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 399                               device->meta_state.clear_color_p_layout,
 400                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
 401                               &clear_value);
 402
 403         struct radv_subpass clear_subpass = {
 404                 .color_count = 1,
 405                 .color_attachments = (struct radv_subpass_attachment[]) {
 406                         subpass->color_attachments[clear_att->colorAttachment]
 407                 },
 408                 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
 409         };
 410
 411         radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
 412
 413         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 414                              pipeline);
 415
 416         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 417                         .x = clear_rect->rect.offset.x,
 418                         .y = clear_rect->rect.offset.y,
 419                         .width = clear_rect->rect.extent.width,
 420                         .height = clear_rect->rect.extent.height,
 421                         .minDepth = 0.0f,
 422                         .maxDepth = 1.0f
 423                 });
 424
 425         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 426
 427         if (view_mask) {
 428                 unsigned i;
 429                 for_each_bit(i, view_mask)
 430                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 431         } else {
 432                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 433         }
 434
 435         radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
 436 }
 437
 438
 439 static void
 440 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
 441 {
 442         nir_builder vs_b, fs_b;
 443
 444         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
 445         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 446
 447         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
 448         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
 449         const struct glsl_type *position_out_type = glsl_vec4_type();
 450
 451         nir_variable *vs_out_pos =
 452                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
 453                                     "gl_Position");
 454         vs_out_pos->data.location = VARYING_SLOT_POS;
 455
 456         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
 457         nir_intrinsic_set_base(in_color_load, 0);
 458         nir_intrinsic_set_range(in_color_load, 4);
 459         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
 460         in_color_load->num_components = 1;
 461         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
 462         nir_builder_instr_insert(&vs_b, &in_color_load->instr);
 463
 464         nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
 465         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
 466
 467         const struct glsl_type *layer_type = glsl_int_type();
 468         nir_variable *vs_out_layer =
 469                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
 470                                     "v_layer");
 471         vs_out_layer->data.location = VARYING_SLOT_LAYER;
 472         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
 473         nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
 474         nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
 475
 476         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
 477         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 478
 479         *out_vs = vs_b.shader;
 480         *out_fs = fs_b.shader;
 481 }
 482
 483 static VkResult
 484 create_depthstencil_renderpass(struct radv_device *device,
 485                                uint32_t samples,
 486                                VkRenderPass *render_pass)
 487 {
 488         mtx_lock(&device->meta_state.mtx);
 489         if (*render_pass) {
 490                 mtx_unlock(&device->meta_state.mtx);
 491                 return VK_SUCCESS;
 492         }
 493
 494         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 495                                        &(VkRenderPassCreateInfo) {
 496                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 497                                                        .attachmentCount = 1,
 498                                                        .pAttachments = &(VkAttachmentDescription) {
 499                                                        .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
 500                                                        .samples = samples,
 501                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 502                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 503                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 504                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 505                                                },
 506                                                        .subpassCount = 1,
 507                                                                 .pSubpasses = &(VkSubpassDescription) {
 508                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 509                                                        .inputAttachmentCount = 0,
 510                                                        .colorAttachmentCount = 0,
 511                                                        .pColorAttachments = NULL,
 512                                                        .pResolveAttachments = NULL,
 513                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 514                                                                .attachment = 0,
 515                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 516                                                        },
 517                                                        .preserveAttachmentCount = 1,
 518                                                        .pPreserveAttachments = (uint32_t[]) { 0 },
 519                                                },
 520                                                                 .dependencyCount = 0,
 521                                                                          }, &device->meta_state.alloc, render_pass);
 522         mtx_unlock(&device->meta_state.mtx);
 523         return result;
 524 }
 525
 526 static VkResult
 527 create_depthstencil_pipeline(struct radv_device *device,
 528                              VkImageAspectFlags aspects,
 529                              uint32_t samples,
 530                              int index,
 531                              VkPipeline *pipeline,
 532                              VkRenderPass render_pass)
 533 {
 534         struct nir_shader *vs_nir, *fs_nir;
 535         VkResult result;
 536
 537         mtx_lock(&device->meta_state.mtx);
 538         if (*pipeline) {
 539                 mtx_unlock(&device->meta_state.mtx);
 540                 return VK_SUCCESS;
 541         }
 542
 543         build_depthstencil_shader(&vs_nir, &fs_nir);
 544
 545         const VkPipelineVertexInputStateCreateInfo vi_state = {
 546                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 547                 .vertexBindingDescriptionCount = 0,
 548                 .vertexAttributeDescriptionCount = 0,
 549         };
 550
 551         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 552                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 553                 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 554                 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
 555                 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 556                 .depthBoundsTestEnable = false,
 557                 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
 558                 .front = {
 559                         .passOp = VK_STENCIL_OP_REPLACE,
 560                         .compareOp = VK_COMPARE_OP_ALWAYS,
 561                         .writeMask = UINT32_MAX,
 562                         .reference = 0, /* dynamic */
 563                 },
 564                 .back = { 0 /* dont care */ },
 565         };
 566
 567         const VkPipelineColorBlendStateCreateInfo cb_state = {
 568                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 569                 .logicOpEnable = false,
 570                 .attachmentCount = 0,
 571                 .pAttachments = NULL,
 572         };
 573
 574         struct radv_graphics_pipeline_create_info extra = {
 575                 .use_rectlist = true,
 576         };
 577
 578         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
 579                 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 580                 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 581         }
 582         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 583                 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 584                 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 585         }
 586         result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
 587                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 588                                  device->meta_state.clear_depth_p_layout,
 589                                  &extra, &device->meta_state.alloc, pipeline);
 590
 591         mtx_unlock(&device->meta_state.mtx);
 592         return result;
 593 }
 594
 595 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 596                                       const struct radv_image_view *iview,
 597                                       VkImageAspectFlags aspects,
 598                                       VkImageLayout layout,
 599                                       const VkClearRect *clear_rect,
 600                                       VkClearDepthStencilValue clear_value)
 601 {
 602         uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
 603                                                            cmd_buffer->queue_family_index,
 604                                                            cmd_buffer->queue_family_index);
 605         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 606             clear_rect->rect.extent.width != iview->extent.width ||
 607             clear_rect->rect.extent.height != iview->extent.height)
 608                 return false;
 609         if (radv_image_is_tc_compat_htile(iview->image) &&
 610             (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
 611               clear_value.depth != 1.0) ||
 612              ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
 613                 return false;
 614         if (radv_image_has_htile(iview->image) &&
 615             iview->base_mip == 0 &&
 616             iview->base_layer == 0 &&
 617             radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
 618             !radv_image_extent_compare(iview->image, &iview->extent))
 619                 return true;
 620         return false;
 621 }
 622
 623 static VkPipeline
 624 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
 625                            struct radv_meta_state *meta_state,
 626                            const struct radv_image_view *iview,
 627                            int samples_log2,
 628                            VkImageAspectFlags aspects,
 629                            VkImageLayout layout,
 630                            const VkClearRect *clear_rect,
 631                            VkClearDepthStencilValue clear_value)
 632 {
 633         bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
 634         int index = DEPTH_CLEAR_SLOW;
 635         VkPipeline *pipeline;
 636
 637         if (fast) {
 638                 /* we don't know the previous clear values, so we always have
 639                  * the NO_EXPCLEAR path */
 640                 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
 641         }
 642
 643         switch (aspects) {
 644         case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
 645                 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
 646                 break;
 647         case VK_IMAGE_ASPECT_DEPTH_BIT:
 648                 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
 649                 break;
 650         case VK_IMAGE_ASPECT_STENCIL_BIT:
 651                 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
 652                 break;
 653         default:
 654                 unreachable("expected depth or stencil aspect");
 655         }
 656
 657         if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
 658                 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
 659                                                               &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 660                 if (ret != VK_SUCCESS) {
 661                         cmd_buffer->record_result = ret;
 662                         return VK_NULL_HANDLE;
 663                 }
 664         }
 665
 666         if (*pipeline == VK_NULL_HANDLE) {
 667                 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
 668                                                             pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 669                 if (ret != VK_SUCCESS) {
 670                         cmd_buffer->record_result = ret;
 671                         return VK_NULL_HANDLE;
 672                 }
 673         }
 674         return *pipeline;
 675 }
 676
 677 static void
 678 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 679                         const VkClearAttachment *clear_att,
 680                         const VkClearRect *clear_rect)
 681 {
 682         struct radv_device *device = cmd_buffer->device;
 683         struct radv_meta_state *meta_state = &device->meta_state;
 684         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 685         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 686         const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
 687         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 688         VkImageAspectFlags aspects = clear_att->aspectMask;
 689         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 690         const uint32_t samples = iview->image->info.samples;
 691         const uint32_t samples_log2 = ffs(samples) - 1;
 692         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 693
 694         assert(pass_att != VK_ATTACHMENT_UNUSED);
 695
 696         if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
 697                 clear_value.depth = 1.0f;
 698
 699         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 700                               device->meta_state.clear_depth_p_layout,
 701                               VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
 702                               &clear_value.depth);
 703
 704         uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
 705         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 706                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 707                                                   clear_value.stencil);
 708         }
 709
 710         VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
 711                                                          meta_state,
 712                                                          iview,
 713                                                          samples_log2,
 714                                                          aspects,
 715                                                          subpass->depth_stencil_attachment.layout,
 716                                                          clear_rect,
 717                                                          clear_value);
 718         if (!pipeline)
 719                 return;
 720
 721         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 722                              pipeline);
 723
 724         if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
 725                                       subpass->depth_stencil_attachment.layout,
 726                                       clear_rect, clear_value))
 727                 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
 728                                               clear_value, aspects);
 729
 730         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 731                         .x = clear_rect->rect.offset.x,
 732                         .y = clear_rect->rect.offset.y,
 733                         .width = clear_rect->rect.extent.width,
 734                         .height = clear_rect->rect.extent.height,
 735                         .minDepth = 0.0f,
 736                         .maxDepth = 1.0f
 737                 });
 738
 739         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 740
 741         radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 742
 743         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 744                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 745                                                   prev_reference);
 746         }
 747 }
 748
 749 static uint32_t
 750 radv_get_htile_fast_clear_value(const struct radv_image *image,
 751                                 VkClearDepthStencilValue value)
 752 {
 753         uint32_t clear_value;
 754
 755         if (!image->surface.has_stencil) {
 756                 clear_value = value.depth ? 0xfffffff0 : 0;
 757         } else {
 758                 clear_value = value.depth ? 0xfffc0000 : 0;
 759         }
 760
 761         return clear_value;
 762 }
 763
 764 static bool
 765 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
 766 {
 767         return value.depth == 1.0f || value.depth == 0.0f;
 768 }
 769
 770 static bool
 771 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
 772 {
 773         return value.stencil == 0;
 774 }
 775
 776 static bool
 777 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
 778                       const VkClearAttachment *clear_att,
 779                       const VkClearRect *clear_rect,
 780                       enum radv_cmd_flush_bits *pre_flush,
 781                       enum radv_cmd_flush_bits *post_flush)
 782 {
 783         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 784         const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
 785         VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
 786         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 787         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 788         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 789         VkImageAspectFlags aspects = clear_att->aspectMask;
 790         uint32_t clear_word, flush_bits;
 791
 792         if (!radv_image_has_htile(iview->image))
 793                 return false;
 794
 795         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
 796                 return false;
 797
 798         if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
 799                 return false;
 800
 801         /* don't fast clear 3D */
 802         if (iview->image->type == VK_IMAGE_TYPE_3D)
 803                 return false;
 804
 805         /* all layers are bound */
 806         if (iview->base_layer > 0)
 807                 return false;
 808         if (iview->image->info.array_size != iview->layer_count)
 809                 return false;
 810
 811         if (!radv_image_extent_compare(iview->image, &iview->extent))
 812                 return false;
 813
 814         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 815             clear_rect->rect.extent.width != iview->image->info.width ||
 816             clear_rect->rect.extent.height != iview->image->info.height)
 817                 return false;
 818
 819         if (clear_rect->baseArrayLayer != 0)
 820                 return false;
 821         if (clear_rect->layerCount != iview->image->info.array_size)
 822                 return false;
 823
 824         if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
 825             ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 826              !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)))
 827                 return false;
 828
 829         if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
 830             !radv_is_fast_clear_depth_allowed(clear_value)) ||
 831             ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 832              !radv_is_fast_clear_stencil_allowed(clear_value)))
 833                 return false;
 834
 835         /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
 836          * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
 837          * fast HTILE clears don't seem to work.
 838          */
 839         if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
 840             iview->image->vk_format == VK_FORMAT_D16_UNORM)
 841                 return false;
 842
 843         clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
 844
 845         if (pre_flush) {
 846                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 847                                                  RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
 848                 *pre_flush |= cmd_buffer->state.flush_bits;
 849         } else
 850                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 851                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
 852
 853         flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
 854                                       iview->image->offset + iview->image->htile_offset,
 855                                       iview->image->surface.htile_size, clear_word);
 856
 857         radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
 858         if (post_flush) {
 859                 *post_flush |= flush_bits;
 860         } else {
 861                 cmd_buffer->state.flush_bits |= flush_bits;
 862         }
 863
 864         return true;
 865 }
 866
 867 VkResult
 868 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
 869 {
 870         VkResult res;
 871         struct radv_meta_state *state = &device->meta_state;
 872
 873         VkPipelineLayoutCreateInfo pl_color_create_info = {
 874                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
 875                 .setLayoutCount = 0,
 876                 .pushConstantRangeCount = 1,
 877                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
 878         };
 879
 880         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
 881                                         &pl_color_create_info,
 882                                         &device->meta_state.alloc,
 883                                         &device->meta_state.clear_color_p_layout);
 884         if (res != VK_SUCCESS)
 885                 goto fail;
 886
 887         VkPipelineLayoutCreateInfo pl_depth_create_info = {
 888                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
 889                 .setLayoutCount = 0,
 890                 .pushConstantRangeCount = 1,
 891                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
 892         };
 893
 894         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
 895                                         &pl_depth_create_info,
 896                                         &device->meta_state.alloc,
 897                                         &device->meta_state.clear_depth_p_layout);
 898         if (res != VK_SUCCESS)
 899                 goto fail;
 900
 901         if (on_demand)
 902                 return VK_SUCCESS;
 903
 904         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 905                 uint32_t samples = 1 << i;
 906                 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
 907                         VkFormat format = radv_fs_key_format_exemplars[j];
 908                         unsigned fs_key = radv_format_meta_fs_key(format);
 909                         assert(!state->clear[i].color_pipelines[fs_key]);
 910
 911                         res = create_color_renderpass(device, format, samples,
 912                                                       &state->clear[i].render_pass[fs_key]);
 913                         if (res != VK_SUCCESS)
 914                                 goto fail;
 915
 916                         res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
 917                                                     state->clear[i].render_pass[fs_key]);
 918                         if (res != VK_SUCCESS)
 919                                 goto fail;
 920
 921                 }
 922
 923                 res = create_depthstencil_renderpass(device,
 924                                                      samples,
 925                                                      &state->clear[i].depthstencil_rp);
 926                 if (res != VK_SUCCESS)
 927                         goto fail;
 928
 929                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 930                         res = create_depthstencil_pipeline(device,
 931                                                            VK_IMAGE_ASPECT_DEPTH_BIT,
 932                                                            samples,
 933                                                            j,
 934                                                            &state->clear[i].depth_only_pipeline[j],
 935                                                            state->clear[i].depthstencil_rp);
 936                         if (res != VK_SUCCESS)
 937                                 goto fail;
 938
 939                         res = create_depthstencil_pipeline(device,
 940                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
 941                                                            samples,
 942                                                            j,
 943                                                            &state->clear[i].stencil_only_pipeline[j],
 944                                                            state->clear[i].depthstencil_rp);
 945                         if (res != VK_SUCCESS)
 946                                 goto fail;
 947
 948                         res = create_depthstencil_pipeline(device,
 949                                                            VK_IMAGE_ASPECT_DEPTH_BIT |
 950                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
 951                                                            samples,
 952                                                            j,
 953                                                            &state->clear[i].depthstencil_pipeline[j],
 954                                                            state->clear[i].depthstencil_rp);
 955                         if (res != VK_SUCCESS)
 956                                 goto fail;
 957                 }
 958         }
 959         return VK_SUCCESS;
 960
 961 fail:
 962         radv_device_finish_meta_clear_state(device);
 963         return res;
 964 }
 965
 966 static uint32_t
 967 radv_get_cmask_fast_clear_value(const struct radv_image *image)
 968 {
 969         uint32_t value = 0; /* Default value when no DCC. */
 970
 971         /* The fast-clear value is different for images that have both DCC and
 972          * CMASK metadata.
 973          */
 974         if (radv_image_has_dcc(image)) {
 975                 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
 976                 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
 977         }
 978
 979         return value;
 980 }
 981
 982 uint32_t
 983 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
 984                  struct radv_image *image, uint32_t value)
 985 {
 986         return radv_fill_buffer(cmd_buffer, image->bo,
 987                                 image->offset + image->cmask.offset,
 988                                 image->cmask.size, value);
 989 }
 990
 991 uint32_t
 992 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 993                struct radv_image *image, uint32_t value)
 994 {
 995         return radv_fill_buffer(cmd_buffer, image->bo,
 996                                 image->offset + image->dcc_offset,
 997                                 image->surface.dcc_size, value);
 998 }
 999
1000 static void vi_get_fast_clear_parameters(VkFormat format,
1001                                          const VkClearColorValue *clear_value,
1002                                          uint32_t* reset_value,
1003                                          bool *can_avoid_fast_clear_elim)
1004 {
1005         bool values[4] = {};
1006         int extra_channel;
1007         bool main_value = false;
1008         bool extra_value = false;
1009         int i;
1010         *can_avoid_fast_clear_elim = false;
1011
1012         *reset_value = 0x20202020U;
1013
1014         const struct vk_format_description *desc = vk_format_description(format);
1015         if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1016             format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1017             format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1018                 extra_channel = -1;
1019         else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1020                 if (radv_translate_colorswap(format, false) <= 1)
1021                         extra_channel = desc->nr_channels - 1;
1022                 else
1023                         extra_channel = 0;
1024         } else
1025                 return;
1026
1027         for (i = 0; i < 4; i++) {
1028                 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1029                 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1030                     desc->swizzle[i] > VK_SWIZZLE_W)
1031                         continue;
1032
1033                 if (desc->channel[i].pure_integer &&
1034                     desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1035                         /* Use the maximum value for clamping the clear color. */
1036                         int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1037
1038                         values[i] = clear_value->int32[i] != 0;
1039                         if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1040                                 return;
1041                 } else if (desc->channel[i].pure_integer &&
1042                            desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1043                         /* Use the maximum value for clamping the clear color. */
1044                         unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1045
1046                         values[i] = clear_value->uint32[i] != 0U;
1047                         if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1048                                 return;
1049                 } else {
1050                         values[i] = clear_value->float32[i] != 0.0F;
1051                         if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1052                                 return;
1053                 }
1054
1055                 if (index == extra_channel)
1056                         extra_value = values[i];
1057                 else
1058                         main_value = values[i];
1059         }
1060
1061         for (int i = 0; i < 4; ++i)
1062                 if (values[i] != main_value &&
1063                     desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1064                     desc->swizzle[i] >= VK_SWIZZLE_X &&
1065                     desc->swizzle[i] <= VK_SWIZZLE_W)
1066                         return;
1067
1068         *can_avoid_fast_clear_elim = true;
1069         if (main_value)
1070                 *reset_value |= 0x80808080U;
1071
1072         if (extra_value)
1073                 *reset_value |= 0x40404040U;
1074         return;
1075 }
1076
1077 static bool
1078 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
1079                       const VkClearAttachment *clear_att,
1080                       const VkClearRect *clear_rect,
1081                       enum radv_cmd_flush_bits *pre_flush,
1082                       enum radv_cmd_flush_bits *post_flush,
1083                       uint32_t view_mask)
1084 {
1085         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1086         const uint32_t subpass_att = clear_att->colorAttachment;
1087         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1088         VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1089         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1090         const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
1091         VkClearColorValue clear_value = clear_att->clearValue.color;
1092         uint32_t clear_color[2], flush_bits = 0;
1093         uint32_t cmask_clear_value;
1094         bool ret;
1095
1096         if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image))
1097                 return false;
1098
1099         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
1100                 return false;
1101
1102         if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1103                 return false;
1104
1105         /* don't fast clear 3D */
1106         if (iview->image->type == VK_IMAGE_TYPE_3D)
1107                 return false;
1108
1109         /* all layers are bound */
1110         if (iview->base_layer > 0)
1111                 return false;
1112         if (iview->image->info.array_size != iview->layer_count)
1113                 return false;
1114
1115         if (iview->image->info.levels > 1)
1116                 return false;
1117
1118         if (!radv_image_extent_compare(iview->image, &iview->extent))
1119                 return false;
1120
1121         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1122             clear_rect->rect.extent.width != iview->image->info.width ||
1123             clear_rect->rect.extent.height != iview->image->info.height)
1124                 return false;
1125
1126         if (view_mask && (iview->image->info.array_size >= 32 ||
1127                          (1u << iview->image->info.array_size) - 1u != view_mask))
1128                 return false;
1129         if (!view_mask && clear_rect->baseArrayLayer != 0)
1130                 return false;
1131         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1132                 return false;
1133
1134         /* RB+ doesn't work with CMASK fast clear on Stoney. */
1135         if (!radv_image_has_dcc(iview->image) &&
1136             cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1137                 return false;
1138
1139         /* DCC */
1140         ret = radv_format_pack_clear_color(iview->vk_format,
1141                                            clear_color, &clear_value);
1142         if (ret == false)
1143                 return false;
1144
1145         if (pre_flush) {
1146                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1147                                                  RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1148                 *pre_flush |= cmd_buffer->state.flush_bits;
1149         } else
1150                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1151                                                 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1152
1153         cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1154
1155         /* clear cmask buffer */
1156         if (radv_image_has_dcc(iview->image)) {
1157                 uint32_t reset_value;
1158                 bool can_avoid_fast_clear_elim;
1159                 bool need_decompress_pass = false;
1160
1161                 vi_get_fast_clear_parameters(iview->vk_format,
1162                                              &clear_value, &reset_value,
1163                                              &can_avoid_fast_clear_elim);
1164
1165                 if (iview->image->info.samples > 1) {
1166                         /* DCC fast clear with MSAA should clear CMASK. */
1167                         /* FIXME: This doesn't work for now. There is a
1168                          * hardware bug with fast clears and DCC for MSAA
1169                          * textures. AMDVLK has a workaround but it doesn't
1170                          * seem to work here. Note that we might emit useless
1171                          * CB flushes but that shouldn't matter.
1172                          */
1173                         if (!can_avoid_fast_clear_elim)
1174                                 return false;
1175
1176                         assert(radv_image_has_cmask(iview->image));
1177
1178                         flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1179                                                       cmask_clear_value);
1180
1181                         need_decompress_pass = true;
1182                 }
1183
1184                 if (!can_avoid_fast_clear_elim)
1185                         need_decompress_pass = true;
1186
1187                 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1188
1189                 radv_update_fce_metadata(cmd_buffer, iview->image,
1190                                          need_decompress_pass);
1191         } else {
1192                 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1193                                               cmask_clear_value);
1194         }
1195
1196         if (post_flush) {
1197                 *post_flush |= flush_bits;
1198         } else {
1199                 cmd_buffer->state.flush_bits |= flush_bits;
1200         }
1201
1202         radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1203                                          clear_color);
1204
1205         return true;
1206 }
1207
1208 /**
1209  * The parameters mean that same as those in vkCmdClearAttachments.
1210  */
1211 static void
1212 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1213            const VkClearAttachment *clear_att,
1214            const VkClearRect *clear_rect,
1215            enum radv_cmd_flush_bits *pre_flush,
1216            enum radv_cmd_flush_bits *post_flush,
1217            uint32_t view_mask)
1218 {
1219         if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1220                 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1221                                            pre_flush, post_flush, view_mask))
1222                         emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1223         } else {
1224                 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1225                                                 VK_IMAGE_ASPECT_STENCIL_BIT));
1226                 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1227                                            pre_flush, post_flush))
1228                         emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1229         }
1230 }
1231
1232 static inline bool
1233 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1234 {
1235         uint32_t view_mask = cmd_state->subpass->view_mask;
1236         return (a != VK_ATTACHMENT_UNUSED &&
1237                 cmd_state->attachments[a].pending_clear_aspects &&
1238                 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1239 }
1240
1241 static bool
1242 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1243 {
1244         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1245         uint32_t a;
1246
1247         if (!cmd_state->subpass)
1248                 return false;
1249
1250         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1251                 a = cmd_state->subpass->color_attachments[i].attachment;
1252                 if (radv_attachment_needs_clear(cmd_state, a))
1253                         return true;
1254         }
1255
1256         a = cmd_state->subpass->depth_stencil_attachment.attachment;
1257         return radv_attachment_needs_clear(cmd_state, a);
1258 }
1259
1260 static void
1261 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1262                               struct radv_attachment_state *attachment,
1263                               const VkClearAttachment *clear_att,
1264                               enum radv_cmd_flush_bits *pre_flush,
1265                               enum radv_cmd_flush_bits *post_flush)
1266 {
1267         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1268         uint32_t view_mask = cmd_state->subpass->view_mask;
1269
1270         VkClearRect clear_rect = {
1271                 .rect = cmd_state->render_area,
1272                 .baseArrayLayer = 0,
1273                 .layerCount = cmd_state->framebuffer->layers,
1274         };
1275
1276         emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1277                    view_mask & ~attachment->cleared_views);
1278         if (view_mask)
1279                 attachment->cleared_views |= view_mask;
1280         else
1281                 attachment->pending_clear_aspects = 0;
1282 }
1283
1284 /**
1285  * Emit any pending attachment clears for the current subpass.
1286  *
1287  * @see radv_attachment_state::pending_clear_aspects
1288  */
1289 void
1290 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1291 {
1292         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1293         struct radv_meta_saved_state saved_state;
1294         enum radv_cmd_flush_bits pre_flush = 0;
1295         enum radv_cmd_flush_bits post_flush = 0;
1296
1297         if (!radv_subpass_needs_clear(cmd_buffer))
1298                 return;
1299
1300         radv_meta_save(&saved_state, cmd_buffer,
1301                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1302                        RADV_META_SAVE_CONSTANTS);
1303
1304         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1305                 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1306
1307                 if (!radv_attachment_needs_clear(cmd_state, a))
1308                         continue;
1309
1310                 assert(cmd_state->attachments[a].pending_clear_aspects ==
1311                        VK_IMAGE_ASPECT_COLOR_BIT);
1312
1313                 VkClearAttachment clear_att = {
1314                         .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1315                         .colorAttachment = i, /* Use attachment index relative to subpass */
1316                         .clearValue = cmd_state->attachments[a].clear_value,
1317                 };
1318
1319                 radv_subpass_clear_attachment(cmd_buffer,
1320                                               &cmd_state->attachments[a],
1321                                               &clear_att, &pre_flush,
1322                                               &post_flush);
1323         }
1324
1325         uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1326         if (radv_attachment_needs_clear(cmd_state, ds)) {
1327                 VkClearAttachment clear_att = {
1328                         .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1329                         .clearValue = cmd_state->attachments[ds].clear_value,
1330                 };
1331
1332                 radv_subpass_clear_attachment(cmd_buffer,
1333                                               &cmd_state->attachments[ds],
1334                                               &clear_att, &pre_flush,
1335                                               &post_flush);
1336         }
1337
1338         radv_meta_restore(&saved_state, cmd_buffer);
1339         cmd_buffer->state.flush_bits |= post_flush;
1340 }
1341
1342 static void
1343 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1344                        struct radv_image *image,
1345                        VkImageLayout image_layout,
1346                        const VkImageSubresourceRange *range,
1347                        VkFormat format, int level, int layer,
1348                        const VkClearValue *clear_val)
1349 {
1350         VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1351         struct radv_image_view iview;
1352         uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1353         uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1354
1355         radv_image_view_init(&iview, cmd_buffer->device,
1356                              &(VkImageViewCreateInfo) {
1357                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1358                                              .image = radv_image_to_handle(image),
1359                                              .viewType = radv_meta_get_view_type(image),
1360                                              .format = format,
1361                                              .subresourceRange = {
1362                                              .aspectMask = range->aspectMask,
1363                                              .baseMipLevel = range->baseMipLevel + level,
1364                                              .levelCount = 1,
1365                                              .baseArrayLayer = range->baseArrayLayer + layer,
1366                                              .layerCount = 1
1367                                      },
1368                              });
1369
1370         VkFramebuffer fb;
1371         radv_CreateFramebuffer(device_h,
1372                                &(VkFramebufferCreateInfo) {
1373                                        .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1374                                                .attachmentCount = 1,
1375                                                .pAttachments = (VkImageView[]) {
1376                                                radv_image_view_to_handle(&iview),
1377                                        },
1378                                                .width = width,
1379                                                .height = height,
1380                                                .layers = 1
1381                                },
1382                                &cmd_buffer->pool->alloc,
1383                                &fb);
1384
1385         VkAttachmentDescription att_desc = {
1386                 .format = iview.vk_format,
1387                 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1388                 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1389                 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1390                 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1391                 .initialLayout = image_layout,
1392                 .finalLayout = image_layout,
1393         };
1394
1395         VkSubpassDescription subpass_desc = {
1396                 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1397                 .inputAttachmentCount = 0,
1398                 .colorAttachmentCount = 0,
1399                 .pColorAttachments = NULL,
1400                 .pResolveAttachments = NULL,
1401                 .pDepthStencilAttachment = NULL,
1402                 .preserveAttachmentCount = 0,
1403                 .pPreserveAttachments = NULL,
1404         };
1405
1406         const VkAttachmentReference att_ref = {
1407                 .attachment = 0,
1408                 .layout = image_layout,
1409         };
1410
1411         if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1412                 subpass_desc.colorAttachmentCount = 1;
1413                 subpass_desc.pColorAttachments = &att_ref;
1414         } else {
1415                 subpass_desc.pDepthStencilAttachment = &att_ref;
1416         }
1417
1418         VkRenderPass pass;
1419         radv_CreateRenderPass(device_h,
1420                               &(VkRenderPassCreateInfo) {
1421                                       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1422                                               .attachmentCount = 1,
1423                                               .pAttachments = &att_desc,
1424                                               .subpassCount = 1,
1425                                               .pSubpasses = &subpass_desc,
1426                                               },
1427                               &cmd_buffer->pool->alloc,
1428                               &pass);
1429
1430         radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1431                                 &(VkRenderPassBeginInfo) {
1432                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1433                                                 .renderArea = {
1434                                                 .offset = { 0, 0, },
1435                                                 .extent = {
1436                                                         .width = width,
1437                                                         .height = height,
1438                                                 },
1439                                         },
1440                                                 .renderPass = pass,
1441                                                 .framebuffer = fb,
1442                                                 .clearValueCount = 0,
1443                                                 .pClearValues = NULL,
1444                                                 },
1445                                 VK_SUBPASS_CONTENTS_INLINE);
1446
1447         VkClearAttachment clear_att = {
1448                 .aspectMask = range->aspectMask,
1449                 .colorAttachment = 0,
1450                 .clearValue = *clear_val,
1451         };
1452
1453         VkClearRect clear_rect = {
1454                 .rect = {
1455                         .offset = { 0, 0 },
1456                         .extent = { width, height },
1457                 },
1458                 .baseArrayLayer = range->baseArrayLayer,
1459                 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1460         };
1461
1462         emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1463
1464         radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1465         radv_DestroyRenderPass(device_h, pass,
1466                                &cmd_buffer->pool->alloc);
1467         radv_DestroyFramebuffer(device_h, fb,
1468                                 &cmd_buffer->pool->alloc);
1469 }
1470 static void
1471 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1472                      struct radv_image *image,
1473                      VkImageLayout image_layout,
1474                      const VkClearValue *clear_value,
1475                      uint32_t range_count,
1476                      const VkImageSubresourceRange *ranges,
1477                      bool cs)
1478 {
1479         VkFormat format = image->vk_format;
1480         VkClearValue internal_clear_value = *clear_value;
1481
1482         if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1483                 uint32_t value;
1484                 format = VK_FORMAT_R32_UINT;
1485                 value = float3_to_rgb9e5(clear_value->color.float32);
1486                 internal_clear_value.color.uint32[0] = value;
1487         }
1488
1489         if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1490                 uint8_t r, g;
1491                 format = VK_FORMAT_R8_UINT;
1492                 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1493                 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1494                 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1495         }
1496
1497         for (uint32_t r = 0; r < range_count; r++) {
1498                 const VkImageSubresourceRange *range = &ranges[r];
1499                 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1500                         const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1501                                 radv_minify(image->info.depth, range->baseMipLevel + l) :
1502                                 radv_get_layerCount(image, range);
1503                         for (uint32_t s = 0; s < layer_count; ++s) {
1504
1505                                 if (cs ||
1506                                     (format == VK_FORMAT_R32G32B32_UINT ||
1507                                      format == VK_FORMAT_R32G32B32_SINT ||
1508                                      format == VK_FORMAT_R32G32B32_SFLOAT)) {
1509                                         struct radv_meta_blit2d_surf surf;
1510                                         surf.format = format;
1511                                         surf.image = image;
1512                                         surf.level = range->baseMipLevel + l;
1513                                         surf.layer = range->baseArrayLayer + s;
1514                                         surf.aspect_mask = range->aspectMask;
1515                                         radv_meta_clear_image_cs(cmd_buffer, &surf,
1516                                                                  &internal_clear_value.color);
1517                                 } else {
1518                                         radv_clear_image_layer(cmd_buffer, image, image_layout,
1519                                                                range, format, l, s, &internal_clear_value);
1520                                 }
1521                         }
1522                 }
1523         }
1524 }
1525
1526 void radv_CmdClearColorImage(
1527         VkCommandBuffer                             commandBuffer,
1528         VkImage                                     image_h,
1529         VkImageLayout                               imageLayout,
1530         const VkClearColorValue*                    pColor,
1531         uint32_t                                    rangeCount,
1532         const VkImageSubresourceRange*              pRanges)
1533 {
1534         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1535         RADV_FROM_HANDLE(radv_image, image, image_h);
1536         struct radv_meta_saved_state saved_state;
1537         bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1538
1539         if (cs) {
1540                 radv_meta_save(&saved_state, cmd_buffer,
1541                                RADV_META_SAVE_COMPUTE_PIPELINE |
1542                                RADV_META_SAVE_CONSTANTS |
1543                                RADV_META_SAVE_DESCRIPTORS);
1544         } else {
1545                 radv_meta_save(&saved_state, cmd_buffer,
1546                                RADV_META_SAVE_GRAPHICS_PIPELINE |
1547                                RADV_META_SAVE_CONSTANTS);
1548         }
1549
1550         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1551                              (const VkClearValue *) pColor,
1552                              rangeCount, pRanges, cs);
1553
1554         radv_meta_restore(&saved_state, cmd_buffer);
1555 }
1556
1557 void radv_CmdClearDepthStencilImage(
1558         VkCommandBuffer                             commandBuffer,
1559         VkImage                                     image_h,
1560         VkImageLayout                               imageLayout,
1561         const VkClearDepthStencilValue*             pDepthStencil,
1562         uint32_t                                    rangeCount,
1563         const VkImageSubresourceRange*              pRanges)
1564 {
1565         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1566         RADV_FROM_HANDLE(radv_image, image, image_h);
1567         struct radv_meta_saved_state saved_state;
1568
1569         radv_meta_save(&saved_state, cmd_buffer,
1570                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1571                        RADV_META_SAVE_CONSTANTS);
1572
1573         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1574                              (const VkClearValue *) pDepthStencil,
1575                              rangeCount, pRanges, false);
1576
1577         radv_meta_restore(&saved_state, cmd_buffer);
1578 }
1579
1580 void radv_CmdClearAttachments(
1581         VkCommandBuffer                             commandBuffer,
1582         uint32_t                                    attachmentCount,
1583         const VkClearAttachment*                    pAttachments,
1584         uint32_t                                    rectCount,
1585         const VkClearRect*                          pRects)
1586 {
1587         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1588         struct radv_meta_saved_state saved_state;
1589         enum radv_cmd_flush_bits pre_flush = 0;
1590         enum radv_cmd_flush_bits post_flush = 0;
1591
1592         if (!cmd_buffer->state.subpass)
1593                 return;
1594
1595         radv_meta_save(&saved_state, cmd_buffer,
1596                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1597                        RADV_META_SAVE_CONSTANTS);
1598
1599         /* FINISHME: We can do better than this dumb loop. It thrashes too much
1600          * state.
1601          */
1602         for (uint32_t a = 0; a < attachmentCount; ++a) {
1603                 for (uint32_t r = 0; r < rectCount; ++r) {
1604                         emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1605                                    cmd_buffer->state.subpass->view_mask);
1606                 }
1607         }
1608
1609         radv_meta_restore(&saved_state, cmd_buffer);
1610         cmd_buffer->state.flush_bits |= post_flush;
1611 }