2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
34 DEPTH_CLEAR_FAST_EXPCLEAR
,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
39 build_color_shaders(struct nir_shader
**out_vs
,
40 struct nir_shader
**out_fs
,
46 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
47 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
49 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_color_vs");
50 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_color_fs");
52 const struct glsl_type
*position_type
= glsl_vec4_type();
53 const struct glsl_type
*color_type
= glsl_vec4_type();
55 nir_variable
*vs_out_pos
=
56 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_type
,
58 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
60 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(fs_b
.shader
, nir_intrinsic_load_push_constant
);
61 nir_intrinsic_set_base(in_color_load
, 0);
62 nir_intrinsic_set_range(in_color_load
, 16);
63 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&fs_b
, 0));
64 in_color_load
->num_components
= 4;
65 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b
, &in_color_load
->instr
);
68 nir_variable
*fs_out_color
=
69 nir_variable_create(fs_b
.shader
, nir_var_shader_out
, color_type
,
71 fs_out_color
->data
.location
= FRAG_RESULT_DATA0
+ frag_output
;
73 nir_store_var(&fs_b
, fs_out_color
, &in_color_load
->dest
.ssa
, 0xf);
75 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&vs_b
);
76 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
78 const struct glsl_type
*layer_type
= glsl_int_type();
79 nir_variable
*vs_out_layer
=
80 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
82 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
83 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
84 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
85 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
87 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
88 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
90 *out_vs
= vs_b
.shader
;
91 *out_fs
= fs_b
.shader
;
95 create_pipeline(struct radv_device
*device
,
96 struct radv_render_pass
*render_pass
,
98 struct nir_shader
*vs_nir
,
99 struct nir_shader
*fs_nir
,
100 const VkPipelineVertexInputStateCreateInfo
*vi_state
,
101 const VkPipelineDepthStencilStateCreateInfo
*ds_state
,
102 const VkPipelineColorBlendStateCreateInfo
*cb_state
,
103 const VkPipelineLayout layout
,
104 const struct radv_graphics_pipeline_create_info
*extra
,
105 const VkAllocationCallbacks
*alloc
,
106 VkPipeline
*pipeline
)
108 VkDevice device_h
= radv_device_to_handle(device
);
111 struct radv_shader_module vs_m
= { .nir
= vs_nir
};
112 struct radv_shader_module fs_m
= { .nir
= fs_nir
};
114 result
= radv_graphics_pipeline_create(device_h
,
115 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
116 &(VkGraphicsPipelineCreateInfo
) {
117 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
118 .stageCount
= fs_nir
? 2 : 1,
119 .pStages
= (VkPipelineShaderStageCreateInfo
[]) {
121 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
122 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
123 .module
= radv_shader_module_to_handle(&vs_m
),
127 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
128 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
129 .module
= radv_shader_module_to_handle(&fs_m
),
133 .pVertexInputState
= vi_state
,
134 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
135 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
136 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
137 .primitiveRestartEnable
= false,
139 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
140 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
144 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
145 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
146 .rasterizerDiscardEnable
= false,
147 .polygonMode
= VK_POLYGON_MODE_FILL
,
148 .cullMode
= VK_CULL_MODE_NONE
,
149 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
,
150 .depthBiasEnable
= false,
152 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
153 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
154 .rasterizationSamples
= samples
,
155 .sampleShadingEnable
= false,
157 .alphaToCoverageEnable
= false,
158 .alphaToOneEnable
= false,
160 .pDepthStencilState
= ds_state
,
161 .pColorBlendState
= cb_state
,
162 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
168 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
169 .dynamicStateCount
= 8,
170 .pDynamicStates
= (VkDynamicState
[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT
,
173 VK_DYNAMIC_STATE_SCISSOR
,
174 VK_DYNAMIC_STATE_LINE_WIDTH
,
175 VK_DYNAMIC_STATE_DEPTH_BIAS
,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
184 .renderPass
= radv_render_pass_to_handle(render_pass
),
198 create_color_renderpass(struct radv_device
*device
,
203 mtx_lock(&device
->meta_state
.mtx
);
205 mtx_unlock (&device
->meta_state
.mtx
);
209 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
210 &(VkRenderPassCreateInfo
) {
211 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
212 .attachmentCount
= 1,
213 .pAttachments
= &(VkAttachmentDescription
) {
216 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
217 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
218 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
219 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
222 .pSubpasses
= &(VkSubpassDescription
) {
223 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
224 .inputAttachmentCount
= 0,
225 .colorAttachmentCount
= 1,
226 .pColorAttachments
= &(VkAttachmentReference
) {
228 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
230 .pResolveAttachments
= NULL
,
231 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
232 .attachment
= VK_ATTACHMENT_UNUSED
,
233 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
235 .preserveAttachmentCount
= 0,
236 .pPreserveAttachments
= NULL
,
238 .dependencyCount
= 0,
239 }, &device
->meta_state
.alloc
, pass
);
240 mtx_unlock(&device
->meta_state
.mtx
);
245 create_color_pipeline(struct radv_device
*device
,
247 uint32_t frag_output
,
248 VkPipeline
*pipeline
,
251 struct nir_shader
*vs_nir
;
252 struct nir_shader
*fs_nir
;
255 mtx_lock(&device
->meta_state
.mtx
);
257 mtx_unlock(&device
->meta_state
.mtx
);
261 build_color_shaders(&vs_nir
, &fs_nir
, frag_output
);
263 const VkPipelineVertexInputStateCreateInfo vi_state
= {
264 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
265 .vertexBindingDescriptionCount
= 0,
266 .vertexAttributeDescriptionCount
= 0,
269 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
270 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
271 .depthTestEnable
= false,
272 .depthWriteEnable
= false,
273 .depthBoundsTestEnable
= false,
274 .stencilTestEnable
= false,
277 VkPipelineColorBlendAttachmentState blend_attachment_state
[MAX_RTS
] = { 0 };
278 blend_attachment_state
[frag_output
] = (VkPipelineColorBlendAttachmentState
) {
279 .blendEnable
= false,
280 .colorWriteMask
= VK_COLOR_COMPONENT_A_BIT
|
281 VK_COLOR_COMPONENT_R_BIT
|
282 VK_COLOR_COMPONENT_G_BIT
|
283 VK_COLOR_COMPONENT_B_BIT
,
286 const VkPipelineColorBlendStateCreateInfo cb_state
= {
287 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
288 .logicOpEnable
= false,
289 .attachmentCount
= MAX_RTS
,
290 .pAttachments
= blend_attachment_state
294 struct radv_graphics_pipeline_create_info extra
= {
295 .use_rectlist
= true,
297 result
= create_pipeline(device
, radv_render_pass_from_handle(pass
),
298 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
299 device
->meta_state
.clear_color_p_layout
,
300 &extra
, &device
->meta_state
.alloc
, pipeline
);
302 mtx_unlock(&device
->meta_state
.mtx
);
307 finish_meta_clear_htile_mask_state(struct radv_device
*device
)
309 struct radv_meta_state
*state
= &device
->meta_state
;
311 radv_DestroyPipeline(radv_device_to_handle(device
),
312 state
->clear_htile_mask_pipeline
,
314 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
315 state
->clear_htile_mask_p_layout
,
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
318 state
->clear_htile_mask_ds_layout
,
323 radv_device_finish_meta_clear_state(struct radv_device
*device
)
325 struct radv_meta_state
*state
= &device
->meta_state
;
327 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
328 for (uint32_t j
= 0; j
< ARRAY_SIZE(state
->clear
[i
].color_pipelines
); ++j
) {
329 radv_DestroyPipeline(radv_device_to_handle(device
),
330 state
->clear
[i
].color_pipelines
[j
],
332 radv_DestroyRenderPass(radv_device_to_handle(device
),
333 state
->clear
[i
].render_pass
[j
],
337 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
338 radv_DestroyPipeline(radv_device_to_handle(device
),
339 state
->clear
[i
].depth_only_pipeline
[j
],
341 radv_DestroyPipeline(radv_device_to_handle(device
),
342 state
->clear
[i
].stencil_only_pipeline
[j
],
344 radv_DestroyPipeline(radv_device_to_handle(device
),
345 state
->clear
[i
].depthstencil_pipeline
[j
],
348 radv_DestroyRenderPass(radv_device_to_handle(device
),
349 state
->clear
[i
].depthstencil_rp
,
352 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
353 state
->clear_color_p_layout
,
355 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
356 state
->clear_depth_p_layout
,
359 finish_meta_clear_htile_mask_state(device
);
363 emit_color_clear(struct radv_cmd_buffer
*cmd_buffer
,
364 const VkClearAttachment
*clear_att
,
365 const VkClearRect
*clear_rect
,
368 struct radv_device
*device
= cmd_buffer
->device
;
369 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
370 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
371 const uint32_t subpass_att
= clear_att
->colorAttachment
;
372 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
373 const struct radv_image_view
*iview
= fb
? fb
->attachments
[pass_att
].attachment
: NULL
;
374 uint32_t samples
, samples_log2
;
377 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
378 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
381 /* When a framebuffer is bound to the current command buffer, get the
382 * number of samples from it. Otherwise, get the number of samples from
383 * the render pass because it's likely a secondary command buffer.
386 samples
= iview
->image
->info
.samples
;
387 format
= iview
->vk_format
;
389 samples
= cmd_buffer
->state
.pass
->attachments
[pass_att
].samples
;
390 format
= cmd_buffer
->state
.pass
->attachments
[pass_att
].format
;
393 samples_log2
= ffs(samples
) - 1;
394 fs_key
= radv_format_meta_fs_key(format
);
397 radv_finishme("color clears incomplete");
401 if (device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
] == VK_NULL_HANDLE
) {
402 VkResult ret
= create_color_renderpass(device
, radv_fs_key_format_exemplars
[fs_key
],
404 &device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
405 if (ret
!= VK_SUCCESS
) {
406 cmd_buffer
->record_result
= ret
;
411 if (device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
] == VK_NULL_HANDLE
) {
412 VkResult ret
= create_color_pipeline(device
, samples
, 0,
413 &device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
],
414 device
->meta_state
.clear
[samples_log2
].render_pass
[fs_key
]);
415 if (ret
!= VK_SUCCESS
) {
416 cmd_buffer
->record_result
= ret
;
421 pipeline
= device
->meta_state
.clear
[samples_log2
].color_pipelines
[fs_key
];
423 radv_finishme("color clears incomplete");
426 assert(samples_log2
< ARRAY_SIZE(device
->meta_state
.clear
));
428 assert(clear_att
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
429 assert(clear_att
->colorAttachment
< subpass
->color_count
);
431 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
432 device
->meta_state
.clear_color_p_layout
,
433 VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16,
436 struct radv_subpass clear_subpass
= {
438 .color_attachments
= (struct radv_subpass_attachment
[]) {
439 subpass
->color_attachments
[clear_att
->colorAttachment
]
441 .depth_stencil_attachment
= NULL
,
444 radv_cmd_buffer_set_subpass(cmd_buffer
, &clear_subpass
);
446 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
449 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
450 .x
= clear_rect
->rect
.offset
.x
,
451 .y
= clear_rect
->rect
.offset
.y
,
452 .width
= clear_rect
->rect
.extent
.width
,
453 .height
= clear_rect
->rect
.extent
.height
,
458 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
462 for_each_bit(i
, view_mask
)
463 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
465 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
468 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
473 build_depthstencil_shader(struct nir_shader
**out_vs
, struct nir_shader
**out_fs
)
475 nir_builder vs_b
, fs_b
;
477 nir_builder_init_simple_shader(&vs_b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
478 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
480 vs_b
.shader
->info
.name
= ralloc_strdup(vs_b
.shader
, "meta_clear_depthstencil_vs");
481 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "meta_clear_depthstencil_fs");
482 const struct glsl_type
*position_out_type
= glsl_vec4_type();
484 nir_variable
*vs_out_pos
=
485 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, position_out_type
,
487 vs_out_pos
->data
.location
= VARYING_SLOT_POS
;
489 nir_intrinsic_instr
*in_color_load
= nir_intrinsic_instr_create(vs_b
.shader
, nir_intrinsic_load_push_constant
);
490 nir_intrinsic_set_base(in_color_load
, 0);
491 nir_intrinsic_set_range(in_color_load
, 4);
492 in_color_load
->src
[0] = nir_src_for_ssa(nir_imm_int(&vs_b
, 0));
493 in_color_load
->num_components
= 1;
494 nir_ssa_dest_init(&in_color_load
->instr
, &in_color_load
->dest
, 1, 32, "depth value");
495 nir_builder_instr_insert(&vs_b
, &in_color_load
->instr
);
497 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices_comp2(&vs_b
, &in_color_load
->dest
.ssa
);
498 nir_store_var(&vs_b
, vs_out_pos
, outvec
, 0xf);
500 const struct glsl_type
*layer_type
= glsl_int_type();
501 nir_variable
*vs_out_layer
=
502 nir_variable_create(vs_b
.shader
, nir_var_shader_out
, layer_type
,
504 vs_out_layer
->data
.location
= VARYING_SLOT_LAYER
;
505 vs_out_layer
->data
.interpolation
= INTERP_MODE_FLAT
;
506 nir_ssa_def
*inst_id
= nir_load_instance_id(&vs_b
);
507 nir_ssa_def
*base_instance
= nir_load_base_instance(&vs_b
);
509 nir_ssa_def
*layer_id
= nir_iadd(&vs_b
, inst_id
, base_instance
);
510 nir_store_var(&vs_b
, vs_out_layer
, layer_id
, 0x1);
512 *out_vs
= vs_b
.shader
;
513 *out_fs
= fs_b
.shader
;
517 create_depthstencil_renderpass(struct radv_device
*device
,
519 VkRenderPass
*render_pass
)
521 mtx_lock(&device
->meta_state
.mtx
);
523 mtx_unlock(&device
->meta_state
.mtx
);
527 VkResult result
= radv_CreateRenderPass(radv_device_to_handle(device
),
528 &(VkRenderPassCreateInfo
) {
529 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
530 .attachmentCount
= 1,
531 .pAttachments
= &(VkAttachmentDescription
) {
532 .format
= VK_FORMAT_D32_SFLOAT_S8_UINT
,
534 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
535 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
536 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
537 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
540 .pSubpasses
= &(VkSubpassDescription
) {
541 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
542 .inputAttachmentCount
= 0,
543 .colorAttachmentCount
= 0,
544 .pColorAttachments
= NULL
,
545 .pResolveAttachments
= NULL
,
546 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
548 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
550 .preserveAttachmentCount
= 0,
551 .pPreserveAttachments
= NULL
,
553 .dependencyCount
= 0,
554 }, &device
->meta_state
.alloc
, render_pass
);
555 mtx_unlock(&device
->meta_state
.mtx
);
560 create_depthstencil_pipeline(struct radv_device
*device
,
561 VkImageAspectFlags aspects
,
564 VkPipeline
*pipeline
,
565 VkRenderPass render_pass
)
567 struct nir_shader
*vs_nir
, *fs_nir
;
570 mtx_lock(&device
->meta_state
.mtx
);
572 mtx_unlock(&device
->meta_state
.mtx
);
576 build_depthstencil_shader(&vs_nir
, &fs_nir
);
578 const VkPipelineVertexInputStateCreateInfo vi_state
= {
579 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
580 .vertexBindingDescriptionCount
= 0,
581 .vertexAttributeDescriptionCount
= 0,
584 const VkPipelineDepthStencilStateCreateInfo ds_state
= {
585 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
586 .depthTestEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
587 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
588 .depthWriteEnable
= (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
),
589 .depthBoundsTestEnable
= false,
590 .stencilTestEnable
= (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
),
592 .passOp
= VK_STENCIL_OP_REPLACE
,
593 .compareOp
= VK_COMPARE_OP_ALWAYS
,
594 .writeMask
= UINT32_MAX
,
595 .reference
= 0, /* dynamic */
597 .back
= { 0 /* dont care */ },
600 const VkPipelineColorBlendStateCreateInfo cb_state
= {
601 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
602 .logicOpEnable
= false,
603 .attachmentCount
= 0,
604 .pAttachments
= NULL
,
607 struct radv_graphics_pipeline_create_info extra
= {
608 .use_rectlist
= true,
611 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
612 extra
.db_depth_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
613 extra
.db_depth_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
615 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
616 extra
.db_stencil_clear
= index
== DEPTH_CLEAR_SLOW
? false : true;
617 extra
.db_stencil_disable_expclear
= index
== DEPTH_CLEAR_FAST_NO_EXPCLEAR
? true : false;
619 result
= create_pipeline(device
, radv_render_pass_from_handle(render_pass
),
620 samples
, vs_nir
, fs_nir
, &vi_state
, &ds_state
, &cb_state
,
621 device
->meta_state
.clear_depth_p_layout
,
622 &extra
, &device
->meta_state
.alloc
, pipeline
);
624 mtx_unlock(&device
->meta_state
.mtx
);
628 static bool depth_view_can_fast_clear(struct radv_cmd_buffer
*cmd_buffer
,
629 const struct radv_image_view
*iview
,
630 VkImageAspectFlags aspects
,
631 VkImageLayout layout
,
632 const VkClearRect
*clear_rect
,
633 VkClearDepthStencilValue clear_value
)
638 uint32_t queue_mask
= radv_image_queue_family_mask(iview
->image
,
639 cmd_buffer
->queue_family_index
,
640 cmd_buffer
->queue_family_index
);
641 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
642 clear_rect
->rect
.extent
.width
!= iview
->extent
.width
||
643 clear_rect
->rect
.extent
.height
!= iview
->extent
.height
)
645 if (radv_image_is_tc_compat_htile(iview
->image
) &&
646 (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) && clear_value
.depth
!= 0.0 &&
647 clear_value
.depth
!= 1.0) ||
648 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) && clear_value
.stencil
!= 0)))
650 if (radv_image_has_htile(iview
->image
) &&
651 iview
->base_mip
== 0 &&
652 iview
->base_layer
== 0 &&
653 iview
->layer_count
== iview
->image
->info
.array_size
&&
654 radv_layout_is_htile_compressed(iview
->image
, layout
, queue_mask
) &&
655 radv_image_extent_compare(iview
->image
, &iview
->extent
))
661 pick_depthstencil_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
662 struct radv_meta_state
*meta_state
,
663 const struct radv_image_view
*iview
,
665 VkImageAspectFlags aspects
,
666 VkImageLayout layout
,
667 const VkClearRect
*clear_rect
,
668 VkClearDepthStencilValue clear_value
)
670 bool fast
= depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
, layout
, clear_rect
, clear_value
);
671 int index
= DEPTH_CLEAR_SLOW
;
672 VkPipeline
*pipeline
;
675 /* we don't know the previous clear values, so we always have
676 * the NO_EXPCLEAR path */
677 index
= DEPTH_CLEAR_FAST_NO_EXPCLEAR
;
681 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
682 pipeline
= &meta_state
->clear
[samples_log2
].depthstencil_pipeline
[index
];
684 case VK_IMAGE_ASPECT_DEPTH_BIT
:
685 pipeline
= &meta_state
->clear
[samples_log2
].depth_only_pipeline
[index
];
687 case VK_IMAGE_ASPECT_STENCIL_BIT
:
688 pipeline
= &meta_state
->clear
[samples_log2
].stencil_only_pipeline
[index
];
691 unreachable("expected depth or stencil aspect");
694 if (cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
== VK_NULL_HANDLE
) {
695 VkResult ret
= create_depthstencil_renderpass(cmd_buffer
->device
, 1u << samples_log2
,
696 &cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
697 if (ret
!= VK_SUCCESS
) {
698 cmd_buffer
->record_result
= ret
;
699 return VK_NULL_HANDLE
;
703 if (*pipeline
== VK_NULL_HANDLE
) {
704 VkResult ret
= create_depthstencil_pipeline(cmd_buffer
->device
, aspects
, 1u << samples_log2
, index
,
705 pipeline
, cmd_buffer
->device
->meta_state
.clear
[samples_log2
].depthstencil_rp
);
706 if (ret
!= VK_SUCCESS
) {
707 cmd_buffer
->record_result
= ret
;
708 return VK_NULL_HANDLE
;
715 emit_depthstencil_clear(struct radv_cmd_buffer
*cmd_buffer
,
716 const VkClearAttachment
*clear_att
,
717 const VkClearRect
*clear_rect
,
720 struct radv_device
*device
= cmd_buffer
->device
;
721 struct radv_meta_state
*meta_state
= &device
->meta_state
;
722 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
723 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
724 const uint32_t pass_att
= subpass
->depth_stencil_attachment
->attachment
;
725 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
726 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
727 const struct radv_image_view
*iview
= fb
? fb
->attachments
[pass_att
].attachment
: NULL
;
728 uint32_t samples
, samples_log2
;
729 VkCommandBuffer cmd_buffer_h
= radv_cmd_buffer_to_handle(cmd_buffer
);
731 /* When a framebuffer is bound to the current command buffer, get the
732 * number of samples from it. Otherwise, get the number of samples from
733 * the render pass because it's likely a secondary command buffer.
736 samples
= iview
->image
->info
.samples
;
738 samples
= cmd_buffer
->state
.pass
->attachments
[pass_att
].samples
;
741 samples_log2
= ffs(samples
) - 1;
743 assert(pass_att
!= VK_ATTACHMENT_UNUSED
);
745 if (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
746 clear_value
.depth
= 1.0f
;
748 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
749 device
->meta_state
.clear_depth_p_layout
,
750 VK_SHADER_STAGE_VERTEX_BIT
, 0, 4,
753 uint32_t prev_reference
= cmd_buffer
->state
.dynamic
.stencil_reference
.front
;
754 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
755 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
756 clear_value
.stencil
);
759 VkPipeline pipeline
= pick_depthstencil_pipeline(cmd_buffer
,
764 subpass
->depth_stencil_attachment
->layout
,
770 radv_CmdBindPipeline(cmd_buffer_h
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
773 if (depth_view_can_fast_clear(cmd_buffer
, iview
, aspects
,
774 subpass
->depth_stencil_attachment
->layout
,
775 clear_rect
, clear_value
))
776 radv_update_ds_clear_metadata(cmd_buffer
, iview
->image
,
777 clear_value
, aspects
);
779 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
780 .x
= clear_rect
->rect
.offset
.x
,
781 .y
= clear_rect
->rect
.offset
.y
,
782 .width
= clear_rect
->rect
.extent
.width
,
783 .height
= clear_rect
->rect
.extent
.height
,
788 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &clear_rect
->rect
);
792 for_each_bit(i
, view_mask
)
793 radv_CmdDraw(cmd_buffer_h
, 3, 1, 0, i
);
795 radv_CmdDraw(cmd_buffer_h
, 3, clear_rect
->layerCount
, 0, clear_rect
->baseArrayLayer
);
798 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
799 radv_CmdSetStencilReference(cmd_buffer_h
, VK_STENCIL_FACE_FRONT_BIT
,
805 clear_htile_mask(struct radv_cmd_buffer
*cmd_buffer
,
806 struct radeon_winsys_bo
*bo
, uint64_t offset
, uint64_t size
,
807 uint32_t htile_value
, uint32_t htile_mask
)
809 struct radv_device
*device
= cmd_buffer
->device
;
810 struct radv_meta_state
*state
= &device
->meta_state
;
811 uint64_t block_count
= round_up_u64(size
, 1024);
812 struct radv_meta_saved_state saved_state
;
814 radv_meta_save(&saved_state
, cmd_buffer
,
815 RADV_META_SAVE_COMPUTE_PIPELINE
|
816 RADV_META_SAVE_CONSTANTS
|
817 RADV_META_SAVE_DESCRIPTORS
);
819 struct radv_buffer dst_buffer
= {
825 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
826 VK_PIPELINE_BIND_POINT_COMPUTE
,
827 state
->clear_htile_mask_pipeline
);
829 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_COMPUTE
,
830 state
->clear_htile_mask_p_layout
,
832 1, /* descriptorWriteCount */
833 (VkWriteDescriptorSet
[]) {
835 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
837 .dstArrayElement
= 0,
838 .descriptorCount
= 1,
839 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
840 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
841 .buffer
= radv_buffer_to_handle(&dst_buffer
),
848 const unsigned constants
[2] = {
849 htile_value
& htile_mask
,
853 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
854 state
->clear_htile_mask_p_layout
,
855 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8,
858 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer
), block_count
, 1, 1);
860 radv_meta_restore(&saved_state
, cmd_buffer
);
862 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
863 RADV_CMD_FLAG_INV_VMEM_L1
|
864 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
;
868 radv_get_htile_fast_clear_value(const struct radv_image
*image
,
869 VkClearDepthStencilValue value
)
871 uint32_t clear_value
;
873 if (!image
->planes
[0].surface
.has_stencil
) {
874 clear_value
= value
.depth
? 0xfffffff0 : 0;
876 clear_value
= value
.depth
? 0xfffc0000 : 0;
883 radv_get_htile_mask(const struct radv_image
*image
, VkImageAspectFlags aspects
)
887 if (!image
->planes
[0].surface
.has_stencil
) {
888 /* All the HTILE buffer is used when there is no stencil. */
891 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
893 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)
901 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value
)
903 return value
.depth
== 1.0f
|| value
.depth
== 0.0f
;
907 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value
)
909 return value
.stencil
== 0;
913 * Determine if the given image can be fast cleared.
916 radv_image_can_fast_clear(struct radv_device
*device
, struct radv_image
*image
)
918 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
)
921 if (vk_format_is_color(image
->vk_format
)) {
922 if (!radv_image_has_cmask(image
) && !radv_image_has_dcc(image
))
925 /* RB+ doesn't work with CMASK fast clear on Stoney. */
926 if (!radv_image_has_dcc(image
) &&
927 device
->physical_device
->rad_info
.family
== CHIP_STONEY
)
930 if (!radv_image_has_htile(image
))
934 /* Do not fast clears 3D images. */
935 if (image
->type
== VK_IMAGE_TYPE_3D
)
942 * Determine if the given image view can be fast cleared.
945 radv_image_view_can_fast_clear(struct radv_device
*device
,
946 const struct radv_image_view
*iview
)
948 struct radv_image
*image
;
952 image
= iview
->image
;
954 /* Only fast clear if the image itself can be fast cleared. */
955 if (!radv_image_can_fast_clear(device
, image
))
958 /* Only fast clear if all layers are bound. */
959 if (iview
->base_layer
> 0 ||
960 iview
->layer_count
!= image
->info
.array_size
)
963 /* Only fast clear if the view covers the whole image. */
964 if (!radv_image_extent_compare(image
, &iview
->extent
))
971 radv_can_fast_clear_depth(struct radv_cmd_buffer
*cmd_buffer
,
972 const struct radv_image_view
*iview
,
973 VkImageLayout image_layout
,
974 VkImageAspectFlags aspects
,
975 const VkClearRect
*clear_rect
,
976 const VkClearDepthStencilValue clear_value
,
979 if (!radv_image_view_can_fast_clear(cmd_buffer
->device
, iview
))
982 if (!radv_layout_is_htile_compressed(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
985 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
986 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
987 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
990 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
991 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
993 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
995 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
998 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
< GFX9
&&
999 (!(aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) ||
1000 ((vk_format_aspects(iview
->image
->vk_format
) & VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1001 !(aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
))))
1004 if (((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1005 !radv_is_fast_clear_depth_allowed(clear_value
)) ||
1006 ((aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1007 !radv_is_fast_clear_stencil_allowed(clear_value
)))
1014 radv_fast_clear_depth(struct radv_cmd_buffer
*cmd_buffer
,
1015 const struct radv_image_view
*iview
,
1016 const VkClearAttachment
*clear_att
,
1017 enum radv_cmd_flush_bits
*pre_flush
,
1018 enum radv_cmd_flush_bits
*post_flush
)
1020 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
1021 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
1022 uint32_t clear_word
, flush_bits
;
1023 uint32_t htile_mask
;
1025 clear_word
= radv_get_htile_fast_clear_value(iview
->image
, clear_value
);
1026 htile_mask
= radv_get_htile_mask(iview
->image
, aspects
);
1029 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1030 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
) & ~ *pre_flush
;
1031 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1034 if (htile_mask
== UINT_MAX
) {
1035 /* Clear the whole HTILE buffer. */
1036 flush_bits
= radv_fill_buffer(cmd_buffer
, iview
->image
->bo
,
1037 iview
->image
->offset
+ iview
->image
->htile_offset
,
1038 iview
->image
->planes
[0].surface
.htile_size
, clear_word
);
1040 /* Only clear depth or stencil bytes in the HTILE buffer. */
1041 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
);
1042 flush_bits
= clear_htile_mask(cmd_buffer
, iview
->image
->bo
,
1043 iview
->image
->offset
+ iview
->image
->htile_offset
,
1044 iview
->image
->planes
[0].surface
.htile_size
, clear_word
,
1048 radv_update_ds_clear_metadata(cmd_buffer
, iview
->image
, clear_value
, aspects
);
1050 *post_flush
|= flush_bits
;
1055 build_clear_htile_mask_shader()
1059 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
1060 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_clear_htile_mask");
1061 b
.shader
->info
.cs
.local_size
[0] = 64;
1062 b
.shader
->info
.cs
.local_size
[1] = 1;
1063 b
.shader
->info
.cs
.local_size
[2] = 1;
1065 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
1066 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
1067 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
1068 b
.shader
->info
.cs
.local_size
[0],
1069 b
.shader
->info
.cs
.local_size
[1],
1070 b
.shader
->info
.cs
.local_size
[2], 0);
1072 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
1074 nir_ssa_def
*offset
= nir_imul(&b
, global_id
, nir_imm_int(&b
, 16));
1075 offset
= nir_channel(&b
, offset
, 0);
1077 nir_intrinsic_instr
*buf
=
1078 nir_intrinsic_instr_create(b
.shader
,
1079 nir_intrinsic_vulkan_resource_index
);
1081 buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
1082 buf
->num_components
= 1;
1083 nir_intrinsic_set_desc_set(buf
, 0);
1084 nir_intrinsic_set_binding(buf
, 0);
1085 nir_ssa_dest_init(&buf
->instr
, &buf
->dest
, buf
->num_components
, 32, NULL
);
1086 nir_builder_instr_insert(&b
, &buf
->instr
);
1088 nir_intrinsic_instr
*constants
=
1089 nir_intrinsic_instr_create(b
.shader
,
1090 nir_intrinsic_load_push_constant
);
1091 nir_intrinsic_set_base(constants
, 0);
1092 nir_intrinsic_set_range(constants
, 8);
1093 constants
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
1094 constants
->num_components
= 2;
1095 nir_ssa_dest_init(&constants
->instr
, &constants
->dest
, 2, 32, "constants");
1096 nir_builder_instr_insert(&b
, &constants
->instr
);
1098 nir_intrinsic_instr
*load
=
1099 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
1100 load
->src
[0] = nir_src_for_ssa(&buf
->dest
.ssa
);
1101 load
->src
[1] = nir_src_for_ssa(offset
);
1102 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1103 load
->num_components
= 4;
1104 nir_builder_instr_insert(&b
, &load
->instr
);
1106 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1108 nir_iand(&b
, &load
->dest
.ssa
,
1109 nir_channel(&b
, &constants
->dest
.ssa
, 1));
1110 data
= nir_ior(&b
, data
, nir_channel(&b
, &constants
->dest
.ssa
, 0));
1112 nir_intrinsic_instr
*store
=
1113 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
1114 store
->src
[0] = nir_src_for_ssa(data
);
1115 store
->src
[1] = nir_src_for_ssa(&buf
->dest
.ssa
);
1116 store
->src
[2] = nir_src_for_ssa(offset
);
1117 nir_intrinsic_set_write_mask(store
, 0xf);
1118 nir_intrinsic_set_access(store
, ACCESS_NON_READABLE
);
1119 store
->num_components
= 4;
1120 nir_builder_instr_insert(&b
, &store
->instr
);
1126 init_meta_clear_htile_mask_state(struct radv_device
*device
)
1128 struct radv_meta_state
*state
= &device
->meta_state
;
1129 struct radv_shader_module cs
= { .nir
= NULL
};
1132 cs
.nir
= build_clear_htile_mask_shader();
1134 VkDescriptorSetLayoutCreateInfo ds_layout_info
= {
1135 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1136 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1138 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1141 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
1142 .descriptorCount
= 1,
1143 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
1144 .pImmutableSamplers
= NULL
1149 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1150 &ds_layout_info
, &state
->alloc
,
1151 &state
->clear_htile_mask_ds_layout
);
1152 if (result
!= VK_SUCCESS
)
1155 VkPipelineLayoutCreateInfo p_layout_info
= {
1156 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1157 .setLayoutCount
= 1,
1158 .pSetLayouts
= &state
->clear_htile_mask_ds_layout
,
1159 .pushConstantRangeCount
= 1,
1160 .pPushConstantRanges
= &(VkPushConstantRange
){
1161 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 8,
1165 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1166 &p_layout_info
, &state
->alloc
,
1167 &state
->clear_htile_mask_p_layout
);
1168 if (result
!= VK_SUCCESS
)
1171 VkPipelineShaderStageCreateInfo shader_stage
= {
1172 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1173 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1174 .module
= radv_shader_module_to_handle(&cs
),
1176 .pSpecializationInfo
= NULL
,
1179 VkComputePipelineCreateInfo pipeline_info
= {
1180 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1181 .stage
= shader_stage
,
1183 .layout
= state
->clear_htile_mask_p_layout
,
1186 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1187 radv_pipeline_cache_to_handle(&state
->cache
),
1188 1, &pipeline_info
, NULL
,
1189 &state
->clear_htile_mask_pipeline
);
1191 ralloc_free(cs
.nir
);
1194 ralloc_free(cs
.nir
);
1199 radv_device_init_meta_clear_state(struct radv_device
*device
, bool on_demand
)
1202 struct radv_meta_state
*state
= &device
->meta_state
;
1204 VkPipelineLayoutCreateInfo pl_color_create_info
= {
1205 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1206 .setLayoutCount
= 0,
1207 .pushConstantRangeCount
= 1,
1208 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_FRAGMENT_BIT
, 0, 16},
1211 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1212 &pl_color_create_info
,
1213 &device
->meta_state
.alloc
,
1214 &device
->meta_state
.clear_color_p_layout
);
1215 if (res
!= VK_SUCCESS
)
1218 VkPipelineLayoutCreateInfo pl_depth_create_info
= {
1219 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1220 .setLayoutCount
= 0,
1221 .pushConstantRangeCount
= 1,
1222 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_VERTEX_BIT
, 0, 4},
1225 res
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1226 &pl_depth_create_info
,
1227 &device
->meta_state
.alloc
,
1228 &device
->meta_state
.clear_depth_p_layout
);
1229 if (res
!= VK_SUCCESS
)
1232 res
= init_meta_clear_htile_mask_state(device
);
1233 if (res
!= VK_SUCCESS
)
1239 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->clear
); ++i
) {
1240 uint32_t samples
= 1 << i
;
1241 for (uint32_t j
= 0; j
< NUM_META_FS_KEYS
; ++j
) {
1242 VkFormat format
= radv_fs_key_format_exemplars
[j
];
1243 unsigned fs_key
= radv_format_meta_fs_key(format
);
1244 assert(!state
->clear
[i
].color_pipelines
[fs_key
]);
1246 res
= create_color_renderpass(device
, format
, samples
,
1247 &state
->clear
[i
].render_pass
[fs_key
]);
1248 if (res
!= VK_SUCCESS
)
1251 res
= create_color_pipeline(device
, samples
, 0, &state
->clear
[i
].color_pipelines
[fs_key
],
1252 state
->clear
[i
].render_pass
[fs_key
]);
1253 if (res
!= VK_SUCCESS
)
1258 res
= create_depthstencil_renderpass(device
,
1260 &state
->clear
[i
].depthstencil_rp
);
1261 if (res
!= VK_SUCCESS
)
1264 for (uint32_t j
= 0; j
< NUM_DEPTH_CLEAR_PIPELINES
; j
++) {
1265 res
= create_depthstencil_pipeline(device
,
1266 VK_IMAGE_ASPECT_DEPTH_BIT
,
1269 &state
->clear
[i
].depth_only_pipeline
[j
],
1270 state
->clear
[i
].depthstencil_rp
);
1271 if (res
!= VK_SUCCESS
)
1274 res
= create_depthstencil_pipeline(device
,
1275 VK_IMAGE_ASPECT_STENCIL_BIT
,
1278 &state
->clear
[i
].stencil_only_pipeline
[j
],
1279 state
->clear
[i
].depthstencil_rp
);
1280 if (res
!= VK_SUCCESS
)
1283 res
= create_depthstencil_pipeline(device
,
1284 VK_IMAGE_ASPECT_DEPTH_BIT
|
1285 VK_IMAGE_ASPECT_STENCIL_BIT
,
1288 &state
->clear
[i
].depthstencil_pipeline
[j
],
1289 state
->clear
[i
].depthstencil_rp
);
1290 if (res
!= VK_SUCCESS
)
1297 radv_device_finish_meta_clear_state(device
);
1302 radv_get_cmask_fast_clear_value(const struct radv_image
*image
)
1304 uint32_t value
= 0; /* Default value when no DCC. */
1306 /* The fast-clear value is different for images that have both DCC and
1309 if (radv_image_has_dcc(image
)) {
1310 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1311 return image
->info
.samples
> 1 ? 0xcccccccc : 0xffffffff;
1318 radv_clear_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1319 struct radv_image
*image
, uint32_t value
)
1321 return radv_fill_buffer(cmd_buffer
, image
->bo
,
1322 image
->offset
+ image
->cmask
.offset
,
1323 image
->cmask
.size
, value
);
1328 radv_clear_fmask(struct radv_cmd_buffer
*cmd_buffer
,
1329 struct radv_image
*image
, uint32_t value
)
1331 return radv_fill_buffer(cmd_buffer
, image
->bo
,
1332 image
->offset
+ image
->fmask
.offset
,
1333 image
->fmask
.size
, value
);
1337 radv_clear_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1338 struct radv_image
*image
, uint32_t value
)
1340 /* Mark the image as being compressed. */
1341 radv_update_dcc_metadata(cmd_buffer
, image
, true);
1343 return radv_fill_buffer(cmd_buffer
, image
->bo
,
1344 image
->offset
+ image
->dcc_offset
,
1345 image
->planes
[0].surface
.dcc_size
, value
);
1349 radv_clear_htile(struct radv_cmd_buffer
*cmd_buffer
, struct radv_image
*image
,
1350 const VkImageSubresourceRange
*range
, uint32_t value
)
1352 unsigned layer_count
= radv_get_layerCount(image
, range
);
1353 uint64_t size
= image
->planes
[0].surface
.htile_slice_size
* layer_count
;
1354 uint64_t offset
= image
->offset
+ image
->htile_offset
+
1355 image
->planes
[0].surface
.htile_slice_size
* range
->baseArrayLayer
;
1357 return radv_fill_buffer(cmd_buffer
, image
->bo
, offset
, size
, value
);
1360 static void vi_get_fast_clear_parameters(VkFormat format
,
1361 const VkClearColorValue
*clear_value
,
1362 uint32_t* reset_value
,
1363 bool *can_avoid_fast_clear_elim
)
1365 bool values
[4] = {};
1367 bool main_value
= false;
1368 bool extra_value
= false;
1370 *can_avoid_fast_clear_elim
= false;
1372 *reset_value
= 0x20202020U
;
1374 const struct vk_format_description
*desc
= vk_format_description(format
);
1375 if (format
== VK_FORMAT_B10G11R11_UFLOAT_PACK32
||
1376 format
== VK_FORMAT_R5G6B5_UNORM_PACK16
||
1377 format
== VK_FORMAT_B5G6R5_UNORM_PACK16
)
1379 else if (desc
->layout
== VK_FORMAT_LAYOUT_PLAIN
) {
1380 if (radv_translate_colorswap(format
, false) <= 1)
1381 extra_channel
= desc
->nr_channels
- 1;
1387 for (i
= 0; i
< 4; i
++) {
1388 int index
= desc
->swizzle
[i
] - VK_SWIZZLE_X
;
1389 if (desc
->swizzle
[i
] < VK_SWIZZLE_X
||
1390 desc
->swizzle
[i
] > VK_SWIZZLE_W
)
1393 if (desc
->channel
[i
].pure_integer
&&
1394 desc
->channel
[i
].type
== VK_FORMAT_TYPE_SIGNED
) {
1395 /* Use the maximum value for clamping the clear color. */
1396 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
1398 values
[i
] = clear_value
->int32
[i
] != 0;
1399 if (clear_value
->int32
[i
] != 0 && MIN2(clear_value
->int32
[i
], max
) != max
)
1401 } else if (desc
->channel
[i
].pure_integer
&&
1402 desc
->channel
[i
].type
== VK_FORMAT_TYPE_UNSIGNED
) {
1403 /* Use the maximum value for clamping the clear color. */
1404 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
1406 values
[i
] = clear_value
->uint32
[i
] != 0U;
1407 if (clear_value
->uint32
[i
] != 0U && MIN2(clear_value
->uint32
[i
], max
) != max
)
1410 values
[i
] = clear_value
->float32
[i
] != 0.0F
;
1411 if (clear_value
->float32
[i
] != 0.0F
&& clear_value
->float32
[i
] != 1.0F
)
1415 if (index
== extra_channel
)
1416 extra_value
= values
[i
];
1418 main_value
= values
[i
];
1421 for (int i
= 0; i
< 4; ++i
)
1422 if (values
[i
] != main_value
&&
1423 desc
->swizzle
[i
] - VK_SWIZZLE_X
!= extra_channel
&&
1424 desc
->swizzle
[i
] >= VK_SWIZZLE_X
&&
1425 desc
->swizzle
[i
] <= VK_SWIZZLE_W
)
1428 *can_avoid_fast_clear_elim
= true;
1430 *reset_value
|= 0x80808080U
;
1433 *reset_value
|= 0x40404040U
;
1438 radv_can_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1439 const struct radv_image_view
*iview
,
1440 VkImageLayout image_layout
,
1441 const VkClearRect
*clear_rect
,
1442 VkClearColorValue clear_value
,
1445 uint32_t clear_color
[2];
1447 if (!radv_image_view_can_fast_clear(cmd_buffer
->device
, iview
))
1450 if (!radv_layout_can_fast_clear(iview
->image
, image_layout
, radv_image_queue_family_mask(iview
->image
, cmd_buffer
->queue_family_index
, cmd_buffer
->queue_family_index
)))
1453 if (clear_rect
->rect
.offset
.x
|| clear_rect
->rect
.offset
.y
||
1454 clear_rect
->rect
.extent
.width
!= iview
->image
->info
.width
||
1455 clear_rect
->rect
.extent
.height
!= iview
->image
->info
.height
)
1458 if (view_mask
&& (iview
->image
->info
.array_size
>= 32 ||
1459 (1u << iview
->image
->info
.array_size
) - 1u != view_mask
))
1461 if (!view_mask
&& clear_rect
->baseArrayLayer
!= 0)
1463 if (!view_mask
&& clear_rect
->layerCount
!= iview
->image
->info
.array_size
)
1467 if (!radv_format_pack_clear_color(iview
->vk_format
,
1468 clear_color
, &clear_value
))
1471 if (radv_image_has_dcc(iview
->image
)) {
1472 bool can_avoid_fast_clear_elim
;
1473 uint32_t reset_value
;
1475 vi_get_fast_clear_parameters(iview
->vk_format
,
1476 &clear_value
, &reset_value
,
1477 &can_avoid_fast_clear_elim
);
1479 if (iview
->image
->info
.samples
> 1) {
1480 /* DCC fast clear with MSAA should clear CMASK. */
1481 /* FIXME: This doesn't work for now. There is a
1482 * hardware bug with fast clears and DCC for MSAA
1483 * textures. AMDVLK has a workaround but it doesn't
1484 * seem to work here. Note that we might emit useless
1485 * CB flushes but that shouldn't matter.
1487 if (!can_avoid_fast_clear_elim
)
1497 radv_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
1498 const struct radv_image_view
*iview
,
1499 const VkClearAttachment
*clear_att
,
1500 uint32_t subpass_att
,
1501 enum radv_cmd_flush_bits
*pre_flush
,
1502 enum radv_cmd_flush_bits
*post_flush
)
1504 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1505 uint32_t clear_color
[2], flush_bits
= 0;
1506 uint32_t cmask_clear_value
;
1509 cmd_buffer
->state
.flush_bits
|= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1510 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
) & ~ *pre_flush
;
1511 *pre_flush
|= cmd_buffer
->state
.flush_bits
;
1515 radv_format_pack_clear_color(iview
->vk_format
, clear_color
, &clear_value
);
1517 cmask_clear_value
= radv_get_cmask_fast_clear_value(iview
->image
);
1519 /* clear cmask buffer */
1520 if (radv_image_has_dcc(iview
->image
)) {
1521 uint32_t reset_value
;
1522 bool can_avoid_fast_clear_elim
;
1523 bool need_decompress_pass
= false;
1525 vi_get_fast_clear_parameters(iview
->vk_format
,
1526 &clear_value
, &reset_value
,
1527 &can_avoid_fast_clear_elim
);
1529 if (radv_image_has_cmask(iview
->image
)) {
1530 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1533 need_decompress_pass
= true;
1536 if (!can_avoid_fast_clear_elim
)
1537 need_decompress_pass
= true;
1539 flush_bits
|= radv_clear_dcc(cmd_buffer
, iview
->image
, reset_value
);
1541 radv_update_fce_metadata(cmd_buffer
, iview
->image
,
1542 need_decompress_pass
);
1544 flush_bits
= radv_clear_cmask(cmd_buffer
, iview
->image
,
1549 *post_flush
|= flush_bits
;
1552 radv_update_color_clear_metadata(cmd_buffer
, iview
->image
, subpass_att
,
1557 * The parameters mean that same as those in vkCmdClearAttachments.
1560 emit_clear(struct radv_cmd_buffer
*cmd_buffer
,
1561 const VkClearAttachment
*clear_att
,
1562 const VkClearRect
*clear_rect
,
1563 enum radv_cmd_flush_bits
*pre_flush
,
1564 enum radv_cmd_flush_bits
*post_flush
,
1567 const struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1568 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1569 VkImageAspectFlags aspects
= clear_att
->aspectMask
;
1571 if (aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1572 const uint32_t subpass_att
= clear_att
->colorAttachment
;
1573 assert(subpass_att
< subpass
->color_count
);
1574 const uint32_t pass_att
= subpass
->color_attachments
[subpass_att
].attachment
;
1575 if (pass_att
== VK_ATTACHMENT_UNUSED
)
1578 VkImageLayout image_layout
= subpass
->color_attachments
[subpass_att
].layout
;
1579 const struct radv_image_view
*iview
= fb
? fb
->attachments
[pass_att
].attachment
: NULL
;
1580 VkClearColorValue clear_value
= clear_att
->clearValue
.color
;
1582 if (radv_can_fast_clear_color(cmd_buffer
, iview
, image_layout
,
1583 clear_rect
, clear_value
, view_mask
)) {
1584 radv_fast_clear_color(cmd_buffer
, iview
, clear_att
,
1585 subpass_att
, pre_flush
,
1588 emit_color_clear(cmd_buffer
, clear_att
, clear_rect
, view_mask
);
1591 const uint32_t pass_att
= subpass
->depth_stencil_attachment
->attachment
;
1592 if (pass_att
== VK_ATTACHMENT_UNUSED
)
1595 VkImageLayout image_layout
= subpass
->depth_stencil_attachment
->layout
;
1596 const struct radv_image_view
*iview
= fb
? fb
->attachments
[pass_att
].attachment
: NULL
;
1597 VkClearDepthStencilValue clear_value
= clear_att
->clearValue
.depthStencil
;
1599 assert(aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1600 VK_IMAGE_ASPECT_STENCIL_BIT
));
1602 if (radv_can_fast_clear_depth(cmd_buffer
, iview
, image_layout
,
1603 aspects
, clear_rect
, clear_value
,
1605 radv_fast_clear_depth(cmd_buffer
, iview
, clear_att
,
1606 pre_flush
, post_flush
);
1608 emit_depthstencil_clear(cmd_buffer
, clear_att
, clear_rect
,
1615 radv_attachment_needs_clear(struct radv_cmd_state
*cmd_state
, uint32_t a
)
1617 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1618 return (a
!= VK_ATTACHMENT_UNUSED
&&
1619 cmd_state
->attachments
[a
].pending_clear_aspects
&&
1620 (!view_mask
|| (view_mask
& ~cmd_state
->attachments
[a
].cleared_views
)));
1624 radv_subpass_needs_clear(struct radv_cmd_buffer
*cmd_buffer
)
1626 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1629 if (!cmd_state
->subpass
)
1632 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1633 a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1634 if (radv_attachment_needs_clear(cmd_state
, a
))
1638 if (!cmd_state
->subpass
->depth_stencil_attachment
)
1641 a
= cmd_state
->subpass
->depth_stencil_attachment
->attachment
;
1642 return radv_attachment_needs_clear(cmd_state
, a
);
1646 radv_subpass_clear_attachment(struct radv_cmd_buffer
*cmd_buffer
,
1647 struct radv_attachment_state
*attachment
,
1648 const VkClearAttachment
*clear_att
,
1649 enum radv_cmd_flush_bits
*pre_flush
,
1650 enum radv_cmd_flush_bits
*post_flush
)
1652 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1653 uint32_t view_mask
= cmd_state
->subpass
->view_mask
;
1655 VkClearRect clear_rect
= {
1656 .rect
= cmd_state
->render_area
,
1657 .baseArrayLayer
= 0,
1658 .layerCount
= cmd_state
->framebuffer
->layers
,
1661 emit_clear(cmd_buffer
, clear_att
, &clear_rect
, pre_flush
, post_flush
,
1662 view_mask
& ~attachment
->cleared_views
);
1664 attachment
->cleared_views
|= view_mask
;
1666 attachment
->pending_clear_aspects
= 0;
1670 * Emit any pending attachment clears for the current subpass.
1672 * @see radv_attachment_state::pending_clear_aspects
1675 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
)
1677 struct radv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1678 struct radv_meta_saved_state saved_state
;
1679 enum radv_cmd_flush_bits pre_flush
= 0;
1680 enum radv_cmd_flush_bits post_flush
= 0;
1682 if (!radv_subpass_needs_clear(cmd_buffer
))
1685 radv_meta_save(&saved_state
, cmd_buffer
,
1686 RADV_META_SAVE_GRAPHICS_PIPELINE
|
1687 RADV_META_SAVE_CONSTANTS
);
1689 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1690 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1692 if (!radv_attachment_needs_clear(cmd_state
, a
))
1695 assert(cmd_state
->attachments
[a
].pending_clear_aspects
==
1696 VK_IMAGE_ASPECT_COLOR_BIT
);
1698 VkClearAttachment clear_att
= {
1699 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
1700 .colorAttachment
= i
, /* Use attachment index relative to subpass */
1701 .clearValue
= cmd_state
->attachments
[a
].clear_value
,
1704 radv_subpass_clear_attachment(cmd_buffer
,
1705 &cmd_state
->attachments
[a
],
1706 &clear_att
, &pre_flush
,
1710 if (cmd_state
->subpass
->depth_stencil_attachment
) {
1711 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
->attachment
;
1712 if (radv_attachment_needs_clear(cmd_state
, ds
)) {
1713 VkClearAttachment clear_att
= {
1714 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1715 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1718 radv_subpass_clear_attachment(cmd_buffer
,
1719 &cmd_state
->attachments
[ds
],
1720 &clear_att
, &pre_flush
,
1725 radv_meta_restore(&saved_state
, cmd_buffer
);
1726 cmd_buffer
->state
.flush_bits
|= post_flush
;
1730 radv_clear_image_layer(struct radv_cmd_buffer
*cmd_buffer
,
1731 struct radv_image
*image
,
1732 VkImageLayout image_layout
,
1733 const VkImageSubresourceRange
*range
,
1734 VkFormat format
, int level
, int layer
,
1735 const VkClearValue
*clear_val
)
1737 VkDevice device_h
= radv_device_to_handle(cmd_buffer
->device
);
1738 struct radv_image_view iview
;
1739 uint32_t width
= radv_minify(image
->info
.width
, range
->baseMipLevel
+ level
);
1740 uint32_t height
= radv_minify(image
->info
.height
, range
->baseMipLevel
+ level
);
1742 radv_image_view_init(&iview
, cmd_buffer
->device
,
1743 &(VkImageViewCreateInfo
) {
1744 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1745 .image
= radv_image_to_handle(image
),
1746 .viewType
= radv_meta_get_view_type(image
),
1748 .subresourceRange
= {
1749 .aspectMask
= range
->aspectMask
,
1750 .baseMipLevel
= range
->baseMipLevel
+ level
,
1752 .baseArrayLayer
= range
->baseArrayLayer
+ layer
,
1758 radv_CreateFramebuffer(device_h
,
1759 &(VkFramebufferCreateInfo
) {
1760 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
1761 .attachmentCount
= 1,
1762 .pAttachments
= (VkImageView
[]) {
1763 radv_image_view_to_handle(&iview
),
1769 &cmd_buffer
->pool
->alloc
,
1772 VkAttachmentDescription att_desc
= {
1773 .format
= iview
.vk_format
,
1774 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1775 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1776 .stencilLoadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1777 .stencilStoreOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1778 .initialLayout
= image_layout
,
1779 .finalLayout
= image_layout
,
1782 VkSubpassDescription subpass_desc
= {
1783 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1784 .inputAttachmentCount
= 0,
1785 .colorAttachmentCount
= 0,
1786 .pColorAttachments
= NULL
,
1787 .pResolveAttachments
= NULL
,
1788 .pDepthStencilAttachment
= NULL
,
1789 .preserveAttachmentCount
= 0,
1790 .pPreserveAttachments
= NULL
,
1793 const VkAttachmentReference att_ref
= {
1795 .layout
= image_layout
,
1798 if (range
->aspectMask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
1799 subpass_desc
.colorAttachmentCount
= 1;
1800 subpass_desc
.pColorAttachments
= &att_ref
;
1802 subpass_desc
.pDepthStencilAttachment
= &att_ref
;
1806 radv_CreateRenderPass(device_h
,
1807 &(VkRenderPassCreateInfo
) {
1808 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1809 .attachmentCount
= 1,
1810 .pAttachments
= &att_desc
,
1812 .pSubpasses
= &subpass_desc
,
1814 &cmd_buffer
->pool
->alloc
,
1817 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
1818 &(VkRenderPassBeginInfo
) {
1819 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
1821 .offset
= { 0, 0, },
1829 .clearValueCount
= 0,
1830 .pClearValues
= NULL
,
1832 VK_SUBPASS_CONTENTS_INLINE
);
1834 VkClearAttachment clear_att
= {
1835 .aspectMask
= range
->aspectMask
,
1836 .colorAttachment
= 0,
1837 .clearValue
= *clear_val
,
1840 VkClearRect clear_rect
= {
1843 .extent
= { width
, height
},
1845 .baseArrayLayer
= range
->baseArrayLayer
,
1846 .layerCount
= 1, /* FINISHME: clear multi-layer framebuffer */
1849 emit_clear(cmd_buffer
, &clear_att
, &clear_rect
, NULL
, NULL
, 0);
1851 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
1852 radv_DestroyRenderPass(device_h
, pass
,
1853 &cmd_buffer
->pool
->alloc
);
1854 radv_DestroyFramebuffer(device_h
, fb
,
1855 &cmd_buffer
->pool
->alloc
);
1859 * Return TRUE if a fast color or depth clear has been performed.
1862 radv_fast_clear_range(struct radv_cmd_buffer
*cmd_buffer
,
1863 struct radv_image
*image
,
1865 VkImageLayout image_layout
,
1866 const VkImageSubresourceRange
*range
,
1867 const VkClearValue
*clear_val
)
1869 struct radv_image_view iview
;
1871 radv_image_view_init(&iview
, cmd_buffer
->device
,
1872 &(VkImageViewCreateInfo
) {
1873 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
1874 .image
= radv_image_to_handle(image
),
1875 .viewType
= radv_meta_get_view_type(image
),
1876 .format
= image
->vk_format
,
1877 .subresourceRange
= {
1878 .aspectMask
= range
->aspectMask
,
1879 .baseMipLevel
= range
->baseMipLevel
,
1880 .levelCount
= range
->levelCount
,
1881 .baseArrayLayer
= range
->baseArrayLayer
,
1882 .layerCount
= range
->layerCount
,
1886 VkClearRect clear_rect
= {
1890 radv_minify(image
->info
.width
, range
->baseMipLevel
),
1891 radv_minify(image
->info
.height
, range
->baseMipLevel
),
1894 .baseArrayLayer
= range
->baseArrayLayer
,
1895 .layerCount
= range
->layerCount
,
1898 VkClearAttachment clear_att
= {
1899 .aspectMask
= range
->aspectMask
,
1900 .colorAttachment
= 0,
1901 .clearValue
= *clear_val
,
1904 if (vk_format_is_color(format
)) {
1905 if (radv_can_fast_clear_color(cmd_buffer
, &iview
,
1906 image_layout
, &clear_rect
,
1907 clear_att
.clearValue
.color
, 0)) {
1908 radv_fast_clear_color(cmd_buffer
, &iview
, &clear_att
,
1909 clear_att
.colorAttachment
,
1914 if (radv_can_fast_clear_depth(cmd_buffer
, &iview
, image_layout
,
1915 range
->aspectMask
, &clear_rect
,
1916 clear_att
.clearValue
.depthStencil
, 0)) {
1917 radv_fast_clear_depth(cmd_buffer
, &iview
, &clear_att
,
1927 radv_cmd_clear_image(struct radv_cmd_buffer
*cmd_buffer
,
1928 struct radv_image
*image
,
1929 VkImageLayout image_layout
,
1930 const VkClearValue
*clear_value
,
1931 uint32_t range_count
,
1932 const VkImageSubresourceRange
*ranges
,
1935 VkFormat format
= image
->vk_format
;
1936 VkClearValue internal_clear_value
= *clear_value
;
1938 if (format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
) {
1940 format
= VK_FORMAT_R32_UINT
;
1941 value
= float3_to_rgb9e5(clear_value
->color
.float32
);
1942 internal_clear_value
.color
.uint32
[0] = value
;
1945 if (format
== VK_FORMAT_R4G4_UNORM_PACK8
) {
1947 format
= VK_FORMAT_R8_UINT
;
1948 r
= float_to_ubyte(clear_value
->color
.float32
[0]) >> 4;
1949 g
= float_to_ubyte(clear_value
->color
.float32
[1]) >> 4;
1950 internal_clear_value
.color
.uint32
[0] = (r
<< 4) | (g
& 0xf);
1953 if (format
== VK_FORMAT_R32G32B32_UINT
||
1954 format
== VK_FORMAT_R32G32B32_SINT
||
1955 format
== VK_FORMAT_R32G32B32_SFLOAT
)
1958 for (uint32_t r
= 0; r
< range_count
; r
++) {
1959 const VkImageSubresourceRange
*range
= &ranges
[r
];
1961 /* Try to perform a fast clear first, otherwise fallback to
1965 radv_fast_clear_range(cmd_buffer
, image
, format
,
1966 image_layout
, range
,
1967 &internal_clear_value
)) {
1971 for (uint32_t l
= 0; l
< radv_get_levelCount(image
, range
); ++l
) {
1972 const uint32_t layer_count
= image
->type
== VK_IMAGE_TYPE_3D
?
1973 radv_minify(image
->info
.depth
, range
->baseMipLevel
+ l
) :
1974 radv_get_layerCount(image
, range
);
1975 for (uint32_t s
= 0; s
< layer_count
; ++s
) {
1978 struct radv_meta_blit2d_surf surf
;
1979 surf
.format
= format
;
1981 surf
.level
= range
->baseMipLevel
+ l
;
1982 surf
.layer
= range
->baseArrayLayer
+ s
;
1983 surf
.aspect_mask
= range
->aspectMask
;
1984 radv_meta_clear_image_cs(cmd_buffer
, &surf
,
1985 &internal_clear_value
.color
);
1987 radv_clear_image_layer(cmd_buffer
, image
, image_layout
,
1988 range
, format
, l
, s
, &internal_clear_value
);
1995 void radv_CmdClearColorImage(
1996 VkCommandBuffer commandBuffer
,
1998 VkImageLayout imageLayout
,
1999 const VkClearColorValue
* pColor
,
2000 uint32_t rangeCount
,
2001 const VkImageSubresourceRange
* pRanges
)
2003 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2004 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
2005 struct radv_meta_saved_state saved_state
;
2006 bool cs
= cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
;
2009 radv_meta_save(&saved_state
, cmd_buffer
,
2010 RADV_META_SAVE_COMPUTE_PIPELINE
|
2011 RADV_META_SAVE_CONSTANTS
|
2012 RADV_META_SAVE_DESCRIPTORS
);
2014 radv_meta_save(&saved_state
, cmd_buffer
,
2015 RADV_META_SAVE_GRAPHICS_PIPELINE
|
2016 RADV_META_SAVE_CONSTANTS
);
2019 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
2020 (const VkClearValue
*) pColor
,
2021 rangeCount
, pRanges
, cs
);
2023 radv_meta_restore(&saved_state
, cmd_buffer
);
2026 void radv_CmdClearDepthStencilImage(
2027 VkCommandBuffer commandBuffer
,
2029 VkImageLayout imageLayout
,
2030 const VkClearDepthStencilValue
* pDepthStencil
,
2031 uint32_t rangeCount
,
2032 const VkImageSubresourceRange
* pRanges
)
2034 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2035 RADV_FROM_HANDLE(radv_image
, image
, image_h
);
2036 struct radv_meta_saved_state saved_state
;
2038 radv_meta_save(&saved_state
, cmd_buffer
,
2039 RADV_META_SAVE_GRAPHICS_PIPELINE
|
2040 RADV_META_SAVE_CONSTANTS
);
2042 radv_cmd_clear_image(cmd_buffer
, image
, imageLayout
,
2043 (const VkClearValue
*) pDepthStencil
,
2044 rangeCount
, pRanges
, false);
2046 radv_meta_restore(&saved_state
, cmd_buffer
);
2049 void radv_CmdClearAttachments(
2050 VkCommandBuffer commandBuffer
,
2051 uint32_t attachmentCount
,
2052 const VkClearAttachment
* pAttachments
,
2054 const VkClearRect
* pRects
)
2056 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2057 struct radv_meta_saved_state saved_state
;
2058 enum radv_cmd_flush_bits pre_flush
= 0;
2059 enum radv_cmd_flush_bits post_flush
= 0;
2061 if (!cmd_buffer
->state
.subpass
)
2064 radv_meta_save(&saved_state
, cmd_buffer
,
2065 RADV_META_SAVE_GRAPHICS_PIPELINE
|
2066 RADV_META_SAVE_CONSTANTS
);
2068 /* FINISHME: We can do better than this dumb loop. It thrashes too much
2071 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
2072 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
2073 emit_clear(cmd_buffer
, &pAttachments
[a
], &pRects
[r
], &pre_flush
, &post_flush
,
2074 cmd_buffer
->state
.subpass
->view_mask
);
2078 radv_meta_restore(&saved_state
, cmd_buffer
);
2079 cmd_buffer
->state
.flush_bits
|= post_flush
;