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radv: don't check for linear images in emit_fast_color_clear()
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
85 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 return radv_CreateRenderPass(radv_device_to_handle(device),
204 &(VkRenderPassCreateInfo) {
205 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
206 .attachmentCount = 1,
207 .pAttachments = &(VkAttachmentDescription) {
208 .format = vk_format,
209 .samples = samples,
210 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
211 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
212 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
213 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
214 },
215 .subpassCount = 1,
216 .pSubpasses = &(VkSubpassDescription) {
217 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
218 .inputAttachmentCount = 0,
219 .colorAttachmentCount = 1,
220 .pColorAttachments = &(VkAttachmentReference) {
221 .attachment = 0,
222 .layout = VK_IMAGE_LAYOUT_GENERAL,
223 },
224 .pResolveAttachments = NULL,
225 .pDepthStencilAttachment = &(VkAttachmentReference) {
226 .attachment = VK_ATTACHMENT_UNUSED,
227 .layout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .preserveAttachmentCount = 1,
230 .pPreserveAttachments = (uint32_t[]) { 0 },
231 },
232 .dependencyCount = 0,
233 }, &device->meta_state.alloc, pass);
234 }
235
236 static VkResult
237 create_color_pipeline(struct radv_device *device,
238 uint32_t samples,
239 uint32_t frag_output,
240 VkPipeline *pipeline,
241 VkRenderPass pass)
242 {
243 struct nir_shader *vs_nir;
244 struct nir_shader *fs_nir;
245 VkResult result;
246 build_color_shaders(&vs_nir, &fs_nir, frag_output);
247
248 const VkPipelineVertexInputStateCreateInfo vi_state = {
249 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
250 .vertexBindingDescriptionCount = 0,
251 .vertexAttributeDescriptionCount = 0,
252 };
253
254 const VkPipelineDepthStencilStateCreateInfo ds_state = {
255 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
256 .depthTestEnable = false,
257 .depthWriteEnable = false,
258 .depthBoundsTestEnable = false,
259 .stencilTestEnable = false,
260 };
261
262 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
263 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
264 .blendEnable = false,
265 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
266 VK_COLOR_COMPONENT_R_BIT |
267 VK_COLOR_COMPONENT_G_BIT |
268 VK_COLOR_COMPONENT_B_BIT,
269 };
270
271 const VkPipelineColorBlendStateCreateInfo cb_state = {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
273 .logicOpEnable = false,
274 .attachmentCount = MAX_RTS,
275 .pAttachments = blend_attachment_state
276 };
277
278
279 struct radv_graphics_pipeline_create_info extra = {
280 .use_rectlist = true,
281 };
282 result = create_pipeline(device, radv_render_pass_from_handle(pass),
283 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
284 device->meta_state.clear_color_p_layout,
285 &extra, &device->meta_state.alloc, pipeline);
286
287 return result;
288 }
289
290 void
291 radv_device_finish_meta_clear_state(struct radv_device *device)
292 {
293 struct radv_meta_state *state = &device->meta_state;
294
295 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
296 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
297 radv_DestroyPipeline(radv_device_to_handle(device),
298 state->clear[i].color_pipelines[j],
299 &state->alloc);
300 radv_DestroyRenderPass(radv_device_to_handle(device),
301 state->clear[i].render_pass[j],
302 &state->alloc);
303 }
304
305 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
306 radv_DestroyPipeline(radv_device_to_handle(device),
307 state->clear[i].depth_only_pipeline[j],
308 &state->alloc);
309 radv_DestroyPipeline(radv_device_to_handle(device),
310 state->clear[i].stencil_only_pipeline[j],
311 &state->alloc);
312 radv_DestroyPipeline(radv_device_to_handle(device),
313 state->clear[i].depthstencil_pipeline[j],
314 &state->alloc);
315 }
316 radv_DestroyRenderPass(radv_device_to_handle(device),
317 state->clear[i].depthstencil_rp,
318 &state->alloc);
319 }
320 radv_DestroyPipelineLayout(radv_device_to_handle(device),
321 state->clear_color_p_layout,
322 &state->alloc);
323 radv_DestroyPipelineLayout(radv_device_to_handle(device),
324 state->clear_depth_p_layout,
325 &state->alloc);
326 }
327
328 static void
329 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
330 const VkClearAttachment *clear_att,
331 const VkClearRect *clear_rect,
332 uint32_t view_mask)
333 {
334 struct radv_device *device = cmd_buffer->device;
335 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
336 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
337 const uint32_t subpass_att = clear_att->colorAttachment;
338 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
339 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
340 const uint32_t samples = iview->image->info.samples;
341 const uint32_t samples_log2 = ffs(samples) - 1;
342 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
343 VkClearColorValue clear_value = clear_att->clearValue.color;
344 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
345 VkPipeline pipeline;
346
347 if (fs_key == -1) {
348 radv_finishme("color clears incomplete");
349 return;
350 }
351
352 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
353 if (!pipeline) {
354 radv_finishme("color clears incomplete");
355 return;
356 }
357 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
358 assert(pipeline);
359 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
360 assert(clear_att->colorAttachment < subpass->color_count);
361
362 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
363 device->meta_state.clear_color_p_layout,
364 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
365 &clear_value);
366
367 struct radv_subpass clear_subpass = {
368 .color_count = 1,
369 .color_attachments = (VkAttachmentReference[]) {
370 subpass->color_attachments[clear_att->colorAttachment]
371 },
372 .depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
373 };
374
375 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
376
377 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
378 pipeline);
379
380 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
381 .x = clear_rect->rect.offset.x,
382 .y = clear_rect->rect.offset.y,
383 .width = clear_rect->rect.extent.width,
384 .height = clear_rect->rect.extent.height,
385 .minDepth = 0.0f,
386 .maxDepth = 1.0f
387 });
388
389 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
390
391 if (view_mask) {
392 unsigned i;
393 for_each_bit(i, view_mask)
394 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
395 } else {
396 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
397 }
398
399 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
400 }
401
402
403 static void
404 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
405 {
406 nir_builder vs_b, fs_b;
407
408 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
409 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
410
411 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
412 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
413 const struct glsl_type *position_out_type = glsl_vec4_type();
414
415 nir_variable *vs_out_pos =
416 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
417 "gl_Position");
418 vs_out_pos->data.location = VARYING_SLOT_POS;
419
420 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
421 nir_intrinsic_set_base(in_color_load, 0);
422 nir_intrinsic_set_range(in_color_load, 4);
423 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
424 in_color_load->num_components = 1;
425 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
426 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
427
428 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
429 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
430
431 const struct glsl_type *layer_type = glsl_int_type();
432 nir_variable *vs_out_layer =
433 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
434 "v_layer");
435 vs_out_layer->data.location = VARYING_SLOT_LAYER;
436 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
437 nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
438 nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
439
440 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
441 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
442
443 *out_vs = vs_b.shader;
444 *out_fs = fs_b.shader;
445 }
446
447 static VkResult
448 create_depthstencil_renderpass(struct radv_device *device,
449 uint32_t samples,
450 VkRenderPass *render_pass)
451 {
452 return radv_CreateRenderPass(radv_device_to_handle(device),
453 &(VkRenderPassCreateInfo) {
454 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
455 .attachmentCount = 1,
456 .pAttachments = &(VkAttachmentDescription) {
457 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
458 .samples = samples,
459 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
460 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
461 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
462 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
463 },
464 .subpassCount = 1,
465 .pSubpasses = &(VkSubpassDescription) {
466 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
467 .inputAttachmentCount = 0,
468 .colorAttachmentCount = 0,
469 .pColorAttachments = NULL,
470 .pResolveAttachments = NULL,
471 .pDepthStencilAttachment = &(VkAttachmentReference) {
472 .attachment = 0,
473 .layout = VK_IMAGE_LAYOUT_GENERAL,
474 },
475 .preserveAttachmentCount = 1,
476 .pPreserveAttachments = (uint32_t[]) { 0 },
477 },
478 .dependencyCount = 0,
479 }, &device->meta_state.alloc, render_pass);
480 }
481
482 static VkResult
483 create_depthstencil_pipeline(struct radv_device *device,
484 VkImageAspectFlags aspects,
485 uint32_t samples,
486 int index,
487 VkPipeline *pipeline,
488 VkRenderPass render_pass)
489 {
490 struct nir_shader *vs_nir, *fs_nir;
491 VkResult result;
492 build_depthstencil_shader(&vs_nir, &fs_nir);
493
494 const VkPipelineVertexInputStateCreateInfo vi_state = {
495 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
496 .vertexBindingDescriptionCount = 0,
497 .vertexAttributeDescriptionCount = 0,
498 };
499
500 const VkPipelineDepthStencilStateCreateInfo ds_state = {
501 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
502 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
503 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
504 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
505 .depthBoundsTestEnable = false,
506 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
507 .front = {
508 .passOp = VK_STENCIL_OP_REPLACE,
509 .compareOp = VK_COMPARE_OP_ALWAYS,
510 .writeMask = UINT32_MAX,
511 .reference = 0, /* dynamic */
512 },
513 .back = { 0 /* dont care */ },
514 };
515
516 const VkPipelineColorBlendStateCreateInfo cb_state = {
517 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
518 .logicOpEnable = false,
519 .attachmentCount = 0,
520 .pAttachments = NULL,
521 };
522
523 struct radv_graphics_pipeline_create_info extra = {
524 .use_rectlist = true,
525 };
526
527 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
528 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
529 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
530 }
531 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
532 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
533 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
534 }
535 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
536 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
537 device->meta_state.clear_depth_p_layout,
538 &extra, &device->meta_state.alloc, pipeline);
539 return result;
540 }
541
542 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
543 const struct radv_image_view *iview,
544 VkImageAspectFlags aspects,
545 VkImageLayout layout,
546 const VkClearRect *clear_rect,
547 VkClearDepthStencilValue clear_value)
548 {
549 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
550 cmd_buffer->queue_family_index,
551 cmd_buffer->queue_family_index);
552 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
553 clear_rect->rect.extent.width != iview->extent.width ||
554 clear_rect->rect.extent.height != iview->extent.height)
555 return false;
556 if (radv_image_is_tc_compat_htile(iview->image) &&
557 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
558 clear_value.depth != 1.0) ||
559 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
560 return false;
561 if (radv_image_has_htile(iview->image) &&
562 iview->base_mip == 0 &&
563 iview->base_layer == 0 &&
564 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
565 !radv_image_extent_compare(iview->image, &iview->extent))
566 return true;
567 return false;
568 }
569
570 static VkPipeline
571 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
572 struct radv_meta_state *meta_state,
573 const struct radv_image_view *iview,
574 int samples_log2,
575 VkImageAspectFlags aspects,
576 VkImageLayout layout,
577 const VkClearRect *clear_rect,
578 VkClearDepthStencilValue clear_value)
579 {
580 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
581 int index = DEPTH_CLEAR_SLOW;
582
583 if (fast) {
584 /* we don't know the previous clear values, so we always have
585 * the NO_EXPCLEAR path */
586 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
587 }
588
589 switch (aspects) {
590 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
591 return meta_state->clear[samples_log2].depthstencil_pipeline[index];
592 case VK_IMAGE_ASPECT_DEPTH_BIT:
593 return meta_state->clear[samples_log2].depth_only_pipeline[index];
594 case VK_IMAGE_ASPECT_STENCIL_BIT:
595 return meta_state->clear[samples_log2].stencil_only_pipeline[index];
596 }
597 unreachable("expected depth or stencil aspect");
598 }
599
600 static void
601 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
602 const VkClearAttachment *clear_att,
603 const VkClearRect *clear_rect)
604 {
605 struct radv_device *device = cmd_buffer->device;
606 struct radv_meta_state *meta_state = &device->meta_state;
607 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
608 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
609 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
610 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
611 VkImageAspectFlags aspects = clear_att->aspectMask;
612 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
613 const uint32_t samples = iview->image->info.samples;
614 const uint32_t samples_log2 = ffs(samples) - 1;
615 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
616
617 assert(pass_att != VK_ATTACHMENT_UNUSED);
618
619 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
620 clear_value.depth = 1.0f;
621
622 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
623 device->meta_state.clear_depth_p_layout,
624 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
625 &clear_value.depth);
626
627 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
628 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
629 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
630 clear_value.stencil);
631 }
632
633 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
634 meta_state,
635 iview,
636 samples_log2,
637 aspects,
638 subpass->depth_stencil_attachment.layout,
639 clear_rect,
640 clear_value);
641
642 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
643 pipeline);
644
645 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
646 subpass->depth_stencil_attachment.layout,
647 clear_rect, clear_value))
648 radv_set_ds_clear_metadata(cmd_buffer, iview->image,
649 clear_value, aspects);
650
651 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
652 .x = clear_rect->rect.offset.x,
653 .y = clear_rect->rect.offset.y,
654 .width = clear_rect->rect.extent.width,
655 .height = clear_rect->rect.extent.height,
656 .minDepth = 0.0f,
657 .maxDepth = 1.0f
658 });
659
660 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
661
662 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
663
664 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
665 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
666 prev_reference);
667 }
668 }
669
670 static bool
671 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
672 const VkClearAttachment *clear_att,
673 const VkClearRect *clear_rect,
674 enum radv_cmd_flush_bits *pre_flush,
675 enum radv_cmd_flush_bits *post_flush)
676 {
677 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
678 const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
679 VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
680 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
681 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
682 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
683 VkImageAspectFlags aspects = clear_att->aspectMask;
684 uint32_t clear_word, flush_bits;
685
686 if (!radv_image_has_htile(iview->image))
687 return false;
688
689 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
690 return false;
691
692 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
693 goto fail;
694
695 /* don't fast clear 3D */
696 if (iview->image->type == VK_IMAGE_TYPE_3D)
697 goto fail;
698
699 /* all layers are bound */
700 if (iview->base_layer > 0)
701 goto fail;
702 if (iview->image->info.array_size != iview->layer_count)
703 goto fail;
704
705 if (!radv_image_extent_compare(iview->image, &iview->extent))
706 goto fail;
707
708 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
709 clear_rect->rect.extent.width != iview->image->info.width ||
710 clear_rect->rect.extent.height != iview->image->info.height)
711 goto fail;
712
713 if (clear_rect->baseArrayLayer != 0)
714 goto fail;
715 if (clear_rect->layerCount != iview->image->info.array_size)
716 goto fail;
717
718 if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
719 goto fail;
720
721 /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
722 * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
723 * fast HTILE clears don't seem to work.
724 */
725 if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
726 iview->image->vk_format == VK_FORMAT_D16_UNORM)
727 goto fail;
728
729 if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
730 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
731 goto fail;
732 clear_word = clear_value.depth ? 0xfffc0000 : 0;
733 } else
734 clear_word = clear_value.depth ? 0xfffffff0 : 0;
735
736 if (pre_flush) {
737 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
738 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
739 *pre_flush |= cmd_buffer->state.flush_bits;
740 } else
741 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
742 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
743
744 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
745 iview->image->offset + iview->image->htile_offset,
746 iview->image->surface.htile_size, clear_word);
747
748 radv_set_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
749 if (post_flush) {
750 *post_flush |= flush_bits;
751 } else {
752 cmd_buffer->state.flush_bits |= flush_bits;
753 }
754
755 return true;
756 fail:
757 return false;
758 }
759
760 static VkFormat pipeline_formats[] = {
761 VK_FORMAT_R8G8B8A8_UNORM,
762 VK_FORMAT_R8G8B8A8_UINT,
763 VK_FORMAT_R8G8B8A8_SINT,
764 VK_FORMAT_A2R10G10B10_UINT_PACK32,
765 VK_FORMAT_A2R10G10B10_SINT_PACK32,
766 VK_FORMAT_R16G16B16A16_UNORM,
767 VK_FORMAT_R16G16B16A16_SNORM,
768 VK_FORMAT_R16G16B16A16_UINT,
769 VK_FORMAT_R16G16B16A16_SINT,
770 VK_FORMAT_R32_SFLOAT,
771 VK_FORMAT_R32G32_SFLOAT,
772 VK_FORMAT_R32G32B32A32_SFLOAT
773 };
774
775 VkResult
776 radv_device_init_meta_clear_state(struct radv_device *device)
777 {
778 VkResult res;
779 struct radv_meta_state *state = &device->meta_state;
780
781 VkPipelineLayoutCreateInfo pl_color_create_info = {
782 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
783 .setLayoutCount = 0,
784 .pushConstantRangeCount = 1,
785 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
786 };
787
788 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
789 &pl_color_create_info,
790 &device->meta_state.alloc,
791 &device->meta_state.clear_color_p_layout);
792 if (res != VK_SUCCESS)
793 goto fail;
794
795 VkPipelineLayoutCreateInfo pl_depth_create_info = {
796 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
797 .setLayoutCount = 0,
798 .pushConstantRangeCount = 1,
799 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
800 };
801
802 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
803 &pl_depth_create_info,
804 &device->meta_state.alloc,
805 &device->meta_state.clear_depth_p_layout);
806 if (res != VK_SUCCESS)
807 goto fail;
808
809 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
810 uint32_t samples = 1 << i;
811 for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
812 VkFormat format = pipeline_formats[j];
813 unsigned fs_key = radv_format_meta_fs_key(format);
814 assert(!state->clear[i].color_pipelines[fs_key]);
815
816 res = create_color_renderpass(device, format, samples,
817 &state->clear[i].render_pass[fs_key]);
818 if (res != VK_SUCCESS)
819 goto fail;
820
821 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
822 state->clear[i].render_pass[fs_key]);
823 if (res != VK_SUCCESS)
824 goto fail;
825
826 }
827
828 res = create_depthstencil_renderpass(device,
829 samples,
830 &state->clear[i].depthstencil_rp);
831 if (res != VK_SUCCESS)
832 goto fail;
833
834 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
835 res = create_depthstencil_pipeline(device,
836 VK_IMAGE_ASPECT_DEPTH_BIT,
837 samples,
838 j,
839 &state->clear[i].depth_only_pipeline[j],
840 state->clear[i].depthstencil_rp);
841 if (res != VK_SUCCESS)
842 goto fail;
843
844 res = create_depthstencil_pipeline(device,
845 VK_IMAGE_ASPECT_STENCIL_BIT,
846 samples,
847 j,
848 &state->clear[i].stencil_only_pipeline[j],
849 state->clear[i].depthstencil_rp);
850 if (res != VK_SUCCESS)
851 goto fail;
852
853 res = create_depthstencil_pipeline(device,
854 VK_IMAGE_ASPECT_DEPTH_BIT |
855 VK_IMAGE_ASPECT_STENCIL_BIT,
856 samples,
857 j,
858 &state->clear[i].depthstencil_pipeline[j],
859 state->clear[i].depthstencil_rp);
860 if (res != VK_SUCCESS)
861 goto fail;
862 }
863 }
864 return VK_SUCCESS;
865
866 fail:
867 radv_device_finish_meta_clear_state(device);
868 return res;
869 }
870
871 static uint32_t
872 radv_get_cmask_fast_clear_value(const struct radv_image *image)
873 {
874 uint32_t value = 0; /* Default value when no DCC. */
875
876 /* The fast-clear value is different for images that have both DCC and
877 * CMASK metadata.
878 */
879 if (radv_image_has_dcc(image)) {
880 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
881 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
882 }
883
884 return value;
885 }
886
887 uint32_t
888 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
889 struct radv_image *image, uint32_t value)
890 {
891 return radv_fill_buffer(cmd_buffer, image->bo,
892 image->offset + image->cmask.offset,
893 image->cmask.size, value);
894 }
895
896 uint32_t
897 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
898 struct radv_image *image, uint32_t value)
899 {
900 return radv_fill_buffer(cmd_buffer, image->bo,
901 image->offset + image->dcc_offset,
902 image->surface.dcc_size, value);
903 }
904
905 static void vi_get_fast_clear_parameters(VkFormat format,
906 const VkClearColorValue *clear_value,
907 uint32_t* reset_value,
908 bool *can_avoid_fast_clear_elim)
909 {
910 bool values[4] = {};
911 int extra_channel;
912 bool main_value = false;
913 bool extra_value = false;
914 int i;
915 *can_avoid_fast_clear_elim = false;
916
917 *reset_value = 0x20202020U;
918
919 const struct vk_format_description *desc = vk_format_description(format);
920 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
921 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
922 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
923 extra_channel = -1;
924 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
925 if (radv_translate_colorswap(format, false) <= 1)
926 extra_channel = desc->nr_channels - 1;
927 else
928 extra_channel = 0;
929 } else
930 return;
931
932 for (i = 0; i < 4; i++) {
933 int index = desc->swizzle[i] - VK_SWIZZLE_X;
934 if (desc->swizzle[i] < VK_SWIZZLE_X ||
935 desc->swizzle[i] > VK_SWIZZLE_W)
936 continue;
937
938 if (desc->channel[i].pure_integer &&
939 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
940 /* Use the maximum value for clamping the clear color. */
941 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
942
943 values[i] = clear_value->int32[i] != 0;
944 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
945 return;
946 } else if (desc->channel[i].pure_integer &&
947 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
948 /* Use the maximum value for clamping the clear color. */
949 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
950
951 values[i] = clear_value->uint32[i] != 0U;
952 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
953 return;
954 } else {
955 values[i] = clear_value->float32[i] != 0.0F;
956 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
957 return;
958 }
959
960 if (index == extra_channel)
961 extra_value = values[i];
962 else
963 main_value = values[i];
964 }
965
966 for (int i = 0; i < 4; ++i)
967 if (values[i] != main_value &&
968 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
969 desc->swizzle[i] >= VK_SWIZZLE_X &&
970 desc->swizzle[i] <= VK_SWIZZLE_W)
971 return;
972
973 *can_avoid_fast_clear_elim = true;
974 if (main_value)
975 *reset_value |= 0x80808080U;
976
977 if (extra_value)
978 *reset_value |= 0x40404040U;
979 return;
980 }
981
982 static bool
983 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
984 const VkClearAttachment *clear_att,
985 const VkClearRect *clear_rect,
986 enum radv_cmd_flush_bits *pre_flush,
987 enum radv_cmd_flush_bits *post_flush,
988 uint32_t view_mask)
989 {
990 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
991 const uint32_t subpass_att = clear_att->colorAttachment;
992 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
993 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
994 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
995 const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
996 VkClearColorValue clear_value = clear_att->clearValue.color;
997 uint32_t clear_color[2], flush_bits;
998 uint32_t cmask_clear_value;
999 bool ret;
1000
1001 if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image))
1002 return false;
1003
1004 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
1005 return false;
1006
1007 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1008 goto fail;
1009
1010 /* don't fast clear 3D */
1011 if (iview->image->type == VK_IMAGE_TYPE_3D)
1012 goto fail;
1013
1014 /* all layers are bound */
1015 if (iview->base_layer > 0)
1016 goto fail;
1017 if (iview->image->info.array_size != iview->layer_count)
1018 goto fail;
1019
1020 if (iview->image->info.levels > 1)
1021 goto fail;
1022
1023 if (!radv_image_extent_compare(iview->image, &iview->extent))
1024 goto fail;
1025
1026 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1027 clear_rect->rect.extent.width != iview->image->info.width ||
1028 clear_rect->rect.extent.height != iview->image->info.height)
1029 goto fail;
1030
1031 if (view_mask && (iview->image->info.array_size >= 32 ||
1032 (1u << iview->image->info.array_size) - 1u != view_mask))
1033 goto fail;
1034 if (!view_mask && clear_rect->baseArrayLayer != 0)
1035 goto fail;
1036 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1037 goto fail;
1038
1039 /* RB+ doesn't work with CMASK fast clear on Stoney. */
1040 if (!radv_image_has_dcc(iview->image) &&
1041 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1042 goto fail;
1043
1044 /* DCC */
1045 ret = radv_format_pack_clear_color(iview->vk_format,
1046 clear_color, &clear_value);
1047 if (ret == false)
1048 goto fail;
1049
1050 if (pre_flush) {
1051 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1052 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1053 *pre_flush |= cmd_buffer->state.flush_bits;
1054 } else
1055 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1056 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1057
1058 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1059
1060 /* clear cmask buffer */
1061 if (radv_image_has_dcc(iview->image)) {
1062 uint32_t reset_value;
1063 bool can_avoid_fast_clear_elim;
1064 bool need_decompress_pass = false;
1065
1066 vi_get_fast_clear_parameters(iview->vk_format,
1067 &clear_value, &reset_value,
1068 &can_avoid_fast_clear_elim);
1069
1070 if (iview->image->info.samples > 1) {
1071 /* DCC fast clear with MSAA should clear CMASK. */
1072 /* FIXME: This doesn't work for now. There is a
1073 * hardware bug with fast clears and DCC for MSAA
1074 * textures. AMDVLK has a workaround but it doesn't
1075 * seem to work here. Note that we might emit useless
1076 * CB flushes but that shouldn't matter.
1077 */
1078 if (!can_avoid_fast_clear_elim)
1079 goto fail;
1080
1081 assert(radv_image_has_cmask(iview->image));
1082
1083 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1084 cmask_clear_value);
1085
1086 need_decompress_pass = true;
1087 }
1088
1089 if (!can_avoid_fast_clear_elim)
1090 need_decompress_pass = true;
1091
1092 flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1093
1094 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1095 need_decompress_pass);
1096 } else {
1097 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1098 cmask_clear_value);
1099 }
1100
1101 if (post_flush) {
1102 *post_flush |= flush_bits;
1103 } else {
1104 cmd_buffer->state.flush_bits |= flush_bits;
1105 }
1106
1107 radv_set_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1108 clear_color);
1109
1110 return true;
1111 fail:
1112 return false;
1113 }
1114
1115 /**
1116 * The parameters mean that same as those in vkCmdClearAttachments.
1117 */
1118 static void
1119 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1120 const VkClearAttachment *clear_att,
1121 const VkClearRect *clear_rect,
1122 enum radv_cmd_flush_bits *pre_flush,
1123 enum radv_cmd_flush_bits *post_flush,
1124 uint32_t view_mask)
1125 {
1126 if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1127 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1128 pre_flush, post_flush, view_mask))
1129 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1130 } else {
1131 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1132 VK_IMAGE_ASPECT_STENCIL_BIT));
1133 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1134 pre_flush, post_flush))
1135 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1136 }
1137 }
1138
1139 static inline bool
1140 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1141 {
1142 uint32_t view_mask = cmd_state->subpass->view_mask;
1143 return (a != VK_ATTACHMENT_UNUSED &&
1144 cmd_state->attachments[a].pending_clear_aspects &&
1145 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1146 }
1147
1148 static bool
1149 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1150 {
1151 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1152 uint32_t a;
1153
1154 if (!cmd_state->subpass)
1155 return false;
1156
1157 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1158 a = cmd_state->subpass->color_attachments[i].attachment;
1159 if (radv_attachment_needs_clear(cmd_state, a))
1160 return true;
1161 }
1162
1163 a = cmd_state->subpass->depth_stencil_attachment.attachment;
1164 return radv_attachment_needs_clear(cmd_state, a);
1165 }
1166
1167 static void
1168 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1169 struct radv_attachment_state *attachment,
1170 const VkClearAttachment *clear_att,
1171 enum radv_cmd_flush_bits *pre_flush,
1172 enum radv_cmd_flush_bits *post_flush)
1173 {
1174 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1175 uint32_t view_mask = cmd_state->subpass->view_mask;
1176
1177 VkClearRect clear_rect = {
1178 .rect = cmd_state->render_area,
1179 .baseArrayLayer = 0,
1180 .layerCount = cmd_state->framebuffer->layers,
1181 };
1182
1183 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1184 view_mask & ~attachment->cleared_views);
1185 if (view_mask)
1186 attachment->cleared_views |= view_mask;
1187 else
1188 attachment->pending_clear_aspects = 0;
1189 }
1190
1191 /**
1192 * Emit any pending attachment clears for the current subpass.
1193 *
1194 * @see radv_attachment_state::pending_clear_aspects
1195 */
1196 void
1197 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1198 {
1199 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1200 struct radv_meta_saved_state saved_state;
1201 enum radv_cmd_flush_bits pre_flush = 0;
1202 enum radv_cmd_flush_bits post_flush = 0;
1203
1204 if (!radv_subpass_needs_clear(cmd_buffer))
1205 return;
1206
1207 radv_meta_save(&saved_state, cmd_buffer,
1208 RADV_META_SAVE_GRAPHICS_PIPELINE |
1209 RADV_META_SAVE_CONSTANTS);
1210
1211 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1212 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1213
1214 if (!radv_attachment_needs_clear(cmd_state, a))
1215 continue;
1216
1217 assert(cmd_state->attachments[a].pending_clear_aspects ==
1218 VK_IMAGE_ASPECT_COLOR_BIT);
1219
1220 VkClearAttachment clear_att = {
1221 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1222 .colorAttachment = i, /* Use attachment index relative to subpass */
1223 .clearValue = cmd_state->attachments[a].clear_value,
1224 };
1225
1226 radv_subpass_clear_attachment(cmd_buffer,
1227 &cmd_state->attachments[a],
1228 &clear_att, &pre_flush,
1229 &post_flush);
1230 }
1231
1232 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1233 if (radv_attachment_needs_clear(cmd_state, ds)) {
1234 VkClearAttachment clear_att = {
1235 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1236 .clearValue = cmd_state->attachments[ds].clear_value,
1237 };
1238
1239 radv_subpass_clear_attachment(cmd_buffer,
1240 &cmd_state->attachments[ds],
1241 &clear_att, &pre_flush,
1242 &post_flush);
1243 }
1244
1245 radv_meta_restore(&saved_state, cmd_buffer);
1246 cmd_buffer->state.flush_bits |= post_flush;
1247 }
1248
1249 static void
1250 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1251 struct radv_image *image,
1252 VkImageLayout image_layout,
1253 const VkImageSubresourceRange *range,
1254 VkFormat format, int level, int layer,
1255 const VkClearValue *clear_val)
1256 {
1257 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1258 struct radv_image_view iview;
1259 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1260 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1261
1262 radv_image_view_init(&iview, cmd_buffer->device,
1263 &(VkImageViewCreateInfo) {
1264 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1265 .image = radv_image_to_handle(image),
1266 .viewType = radv_meta_get_view_type(image),
1267 .format = format,
1268 .subresourceRange = {
1269 .aspectMask = range->aspectMask,
1270 .baseMipLevel = range->baseMipLevel + level,
1271 .levelCount = 1,
1272 .baseArrayLayer = range->baseArrayLayer + layer,
1273 .layerCount = 1
1274 },
1275 });
1276
1277 VkFramebuffer fb;
1278 radv_CreateFramebuffer(device_h,
1279 &(VkFramebufferCreateInfo) {
1280 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1281 .attachmentCount = 1,
1282 .pAttachments = (VkImageView[]) {
1283 radv_image_view_to_handle(&iview),
1284 },
1285 .width = width,
1286 .height = height,
1287 .layers = 1
1288 },
1289 &cmd_buffer->pool->alloc,
1290 &fb);
1291
1292 VkAttachmentDescription att_desc = {
1293 .format = iview.vk_format,
1294 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1295 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1296 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1297 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1298 .initialLayout = image_layout,
1299 .finalLayout = image_layout,
1300 };
1301
1302 VkSubpassDescription subpass_desc = {
1303 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1304 .inputAttachmentCount = 0,
1305 .colorAttachmentCount = 0,
1306 .pColorAttachments = NULL,
1307 .pResolveAttachments = NULL,
1308 .pDepthStencilAttachment = NULL,
1309 .preserveAttachmentCount = 0,
1310 .pPreserveAttachments = NULL,
1311 };
1312
1313 const VkAttachmentReference att_ref = {
1314 .attachment = 0,
1315 .layout = image_layout,
1316 };
1317
1318 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1319 subpass_desc.colorAttachmentCount = 1;
1320 subpass_desc.pColorAttachments = &att_ref;
1321 } else {
1322 subpass_desc.pDepthStencilAttachment = &att_ref;
1323 }
1324
1325 VkRenderPass pass;
1326 radv_CreateRenderPass(device_h,
1327 &(VkRenderPassCreateInfo) {
1328 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1329 .attachmentCount = 1,
1330 .pAttachments = &att_desc,
1331 .subpassCount = 1,
1332 .pSubpasses = &subpass_desc,
1333 },
1334 &cmd_buffer->pool->alloc,
1335 &pass);
1336
1337 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1338 &(VkRenderPassBeginInfo) {
1339 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1340 .renderArea = {
1341 .offset = { 0, 0, },
1342 .extent = {
1343 .width = width,
1344 .height = height,
1345 },
1346 },
1347 .renderPass = pass,
1348 .framebuffer = fb,
1349 .clearValueCount = 0,
1350 .pClearValues = NULL,
1351 },
1352 VK_SUBPASS_CONTENTS_INLINE);
1353
1354 VkClearAttachment clear_att = {
1355 .aspectMask = range->aspectMask,
1356 .colorAttachment = 0,
1357 .clearValue = *clear_val,
1358 };
1359
1360 VkClearRect clear_rect = {
1361 .rect = {
1362 .offset = { 0, 0 },
1363 .extent = { width, height },
1364 },
1365 .baseArrayLayer = range->baseArrayLayer,
1366 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1367 };
1368
1369 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1370
1371 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1372 radv_DestroyRenderPass(device_h, pass,
1373 &cmd_buffer->pool->alloc);
1374 radv_DestroyFramebuffer(device_h, fb,
1375 &cmd_buffer->pool->alloc);
1376 }
1377 static void
1378 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1379 struct radv_image *image,
1380 VkImageLayout image_layout,
1381 const VkClearValue *clear_value,
1382 uint32_t range_count,
1383 const VkImageSubresourceRange *ranges,
1384 bool cs)
1385 {
1386 VkFormat format = image->vk_format;
1387 VkClearValue internal_clear_value = *clear_value;
1388
1389 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1390 uint32_t value;
1391 format = VK_FORMAT_R32_UINT;
1392 value = float3_to_rgb9e5(clear_value->color.float32);
1393 internal_clear_value.color.uint32[0] = value;
1394 }
1395
1396 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1397 uint8_t r, g;
1398 format = VK_FORMAT_R8_UINT;
1399 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1400 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1401 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1402 }
1403
1404 for (uint32_t r = 0; r < range_count; r++) {
1405 const VkImageSubresourceRange *range = &ranges[r];
1406 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1407 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1408 radv_minify(image->info.depth, range->baseMipLevel + l) :
1409 radv_get_layerCount(image, range);
1410 for (uint32_t s = 0; s < layer_count; ++s) {
1411
1412 if (cs) {
1413 struct radv_meta_blit2d_surf surf;
1414 surf.format = format;
1415 surf.image = image;
1416 surf.level = range->baseMipLevel + l;
1417 surf.layer = range->baseArrayLayer + s;
1418 surf.aspect_mask = range->aspectMask;
1419 radv_meta_clear_image_cs(cmd_buffer, &surf,
1420 &internal_clear_value.color);
1421 } else {
1422 radv_clear_image_layer(cmd_buffer, image, image_layout,
1423 range, format, l, s, &internal_clear_value);
1424 }
1425 }
1426 }
1427 }
1428 }
1429
1430 void radv_CmdClearColorImage(
1431 VkCommandBuffer commandBuffer,
1432 VkImage image_h,
1433 VkImageLayout imageLayout,
1434 const VkClearColorValue* pColor,
1435 uint32_t rangeCount,
1436 const VkImageSubresourceRange* pRanges)
1437 {
1438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1439 RADV_FROM_HANDLE(radv_image, image, image_h);
1440 struct radv_meta_saved_state saved_state;
1441 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1442
1443 if (cs) {
1444 radv_meta_save(&saved_state, cmd_buffer,
1445 RADV_META_SAVE_COMPUTE_PIPELINE |
1446 RADV_META_SAVE_CONSTANTS |
1447 RADV_META_SAVE_DESCRIPTORS);
1448 } else {
1449 radv_meta_save(&saved_state, cmd_buffer,
1450 RADV_META_SAVE_GRAPHICS_PIPELINE |
1451 RADV_META_SAVE_CONSTANTS);
1452 }
1453
1454 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1455 (const VkClearValue *) pColor,
1456 rangeCount, pRanges, cs);
1457
1458 radv_meta_restore(&saved_state, cmd_buffer);
1459 }
1460
1461 void radv_CmdClearDepthStencilImage(
1462 VkCommandBuffer commandBuffer,
1463 VkImage image_h,
1464 VkImageLayout imageLayout,
1465 const VkClearDepthStencilValue* pDepthStencil,
1466 uint32_t rangeCount,
1467 const VkImageSubresourceRange* pRanges)
1468 {
1469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1470 RADV_FROM_HANDLE(radv_image, image, image_h);
1471 struct radv_meta_saved_state saved_state;
1472
1473 radv_meta_save(&saved_state, cmd_buffer,
1474 RADV_META_SAVE_GRAPHICS_PIPELINE |
1475 RADV_META_SAVE_CONSTANTS);
1476
1477 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1478 (const VkClearValue *) pDepthStencil,
1479 rangeCount, pRanges, false);
1480
1481 radv_meta_restore(&saved_state, cmd_buffer);
1482 }
1483
1484 void radv_CmdClearAttachments(
1485 VkCommandBuffer commandBuffer,
1486 uint32_t attachmentCount,
1487 const VkClearAttachment* pAttachments,
1488 uint32_t rectCount,
1489 const VkClearRect* pRects)
1490 {
1491 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1492 struct radv_meta_saved_state saved_state;
1493 enum radv_cmd_flush_bits pre_flush = 0;
1494 enum radv_cmd_flush_bits post_flush = 0;
1495
1496 if (!cmd_buffer->state.subpass)
1497 return;
1498
1499 radv_meta_save(&saved_state, cmd_buffer,
1500 RADV_META_SAVE_GRAPHICS_PIPELINE |
1501 RADV_META_SAVE_CONSTANTS);
1502
1503 /* FINISHME: We can do better than this dumb loop. It thrashes too much
1504 * state.
1505 */
1506 for (uint32_t a = 0; a < attachmentCount; ++a) {
1507 for (uint32_t r = 0; r < rectCount; ++r) {
1508 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1509 cmd_buffer->state.subpass->view_mask);
1510 }
1511 }
1512
1513 radv_meta_restore(&saved_state, cmd_buffer);
1514 cmd_buffer->state.flush_bits |= post_flush;
1515 }