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radv: merge radv_dcc_clear_level() into radv_clear_dcc()
[mesa.git] / src / amd / vulkan / radv_meta_clear.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_debug.h"
25 #include "radv_meta.h"
26 #include "radv_private.h"
27 #include "nir/nir_builder.h"
28
29 #include "util/format_rgb9e5.h"
30 #include "vk_format.h"
31
32 enum {
33 DEPTH_CLEAR_SLOW,
34 DEPTH_CLEAR_FAST_EXPCLEAR,
35 DEPTH_CLEAR_FAST_NO_EXPCLEAR
36 };
37
38 static void
39 build_color_shaders(struct nir_shader **out_vs,
40 struct nir_shader **out_fs,
41 uint32_t frag_output)
42 {
43 nir_builder vs_b;
44 nir_builder fs_b;
45
46 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
47 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
48
49 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
50 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
51
52 const struct glsl_type *position_type = glsl_vec4_type();
53 const struct glsl_type *color_type = glsl_vec4_type();
54
55 nir_variable *vs_out_pos =
56 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
57 "gl_Position");
58 vs_out_pos->data.location = VARYING_SLOT_POS;
59
60 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
61 nir_intrinsic_set_base(in_color_load, 0);
62 nir_intrinsic_set_range(in_color_load, 16);
63 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
64 in_color_load->num_components = 4;
65 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
66 nir_builder_instr_insert(&fs_b, &in_color_load->instr);
67
68 nir_variable *fs_out_color =
69 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
70 "f_color");
71 fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
72
73 nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
74
75 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
76 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
77
78 const struct glsl_type *layer_type = glsl_int_type();
79 nir_variable *vs_out_layer =
80 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
81 "v_layer");
82 vs_out_layer->data.location = VARYING_SLOT_LAYER;
83 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
84 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
85 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
86
87 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
88 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
89
90 *out_vs = vs_b.shader;
91 *out_fs = fs_b.shader;
92 }
93
94 static VkResult
95 create_pipeline(struct radv_device *device,
96 struct radv_render_pass *render_pass,
97 uint32_t samples,
98 struct nir_shader *vs_nir,
99 struct nir_shader *fs_nir,
100 const VkPipelineVertexInputStateCreateInfo *vi_state,
101 const VkPipelineDepthStencilStateCreateInfo *ds_state,
102 const VkPipelineColorBlendStateCreateInfo *cb_state,
103 const VkPipelineLayout layout,
104 const struct radv_graphics_pipeline_create_info *extra,
105 const VkAllocationCallbacks *alloc,
106 VkPipeline *pipeline)
107 {
108 VkDevice device_h = radv_device_to_handle(device);
109 VkResult result;
110
111 struct radv_shader_module vs_m = { .nir = vs_nir };
112 struct radv_shader_module fs_m = { .nir = fs_nir };
113
114 result = radv_graphics_pipeline_create(device_h,
115 radv_pipeline_cache_to_handle(&device->meta_state.cache),
116 &(VkGraphicsPipelineCreateInfo) {
117 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
118 .stageCount = fs_nir ? 2 : 1,
119 .pStages = (VkPipelineShaderStageCreateInfo[]) {
120 {
121 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
122 .stage = VK_SHADER_STAGE_VERTEX_BIT,
123 .module = radv_shader_module_to_handle(&vs_m),
124 .pName = "main",
125 },
126 {
127 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
128 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
129 .module = radv_shader_module_to_handle(&fs_m),
130 .pName = "main",
131 },
132 },
133 .pVertexInputState = vi_state,
134 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
136 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
137 .primitiveRestartEnable = false,
138 },
139 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
140 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
141 .viewportCount = 1,
142 .scissorCount = 1,
143 },
144 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
145 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
146 .rasterizerDiscardEnable = false,
147 .polygonMode = VK_POLYGON_MODE_FILL,
148 .cullMode = VK_CULL_MODE_NONE,
149 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
150 .depthBiasEnable = false,
151 },
152 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
153 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
154 .rasterizationSamples = samples,
155 .sampleShadingEnable = false,
156 .pSampleMask = NULL,
157 .alphaToCoverageEnable = false,
158 .alphaToOneEnable = false,
159 },
160 .pDepthStencilState = ds_state,
161 .pColorBlendState = cb_state,
162 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
163 /* The meta clear pipeline declares all state as dynamic.
164 * As a consequence, vkCmdBindPipeline writes no dynamic state
165 * to the cmd buffer. Therefore, at the end of the meta clear,
166 * we need only restore dynamic state was vkCmdSet.
167 */
168 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
169 .dynamicStateCount = 8,
170 .pDynamicStates = (VkDynamicState[]) {
171 /* Everything except stencil write mask */
172 VK_DYNAMIC_STATE_VIEWPORT,
173 VK_DYNAMIC_STATE_SCISSOR,
174 VK_DYNAMIC_STATE_LINE_WIDTH,
175 VK_DYNAMIC_STATE_DEPTH_BIAS,
176 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
177 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
178 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
179 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
180 },
181 },
182 .layout = layout,
183 .flags = 0,
184 .renderPass = radv_render_pass_to_handle(render_pass),
185 .subpass = 0,
186 },
187 extra,
188 alloc,
189 pipeline);
190
191 ralloc_free(vs_nir);
192 ralloc_free(fs_nir);
193
194 return result;
195 }
196
197 static VkResult
198 create_color_renderpass(struct radv_device *device,
199 VkFormat vk_format,
200 uint32_t samples,
201 VkRenderPass *pass)
202 {
203 mtx_lock(&device->meta_state.mtx);
204 if (*pass) {
205 mtx_unlock (&device->meta_state.mtx);
206 return VK_SUCCESS;
207 }
208
209 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
210 &(VkRenderPassCreateInfo) {
211 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
212 .attachmentCount = 1,
213 .pAttachments = &(VkAttachmentDescription) {
214 .format = vk_format,
215 .samples = samples,
216 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
217 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
218 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
219 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
220 },
221 .subpassCount = 1,
222 .pSubpasses = &(VkSubpassDescription) {
223 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
224 .inputAttachmentCount = 0,
225 .colorAttachmentCount = 1,
226 .pColorAttachments = &(VkAttachmentReference) {
227 .attachment = 0,
228 .layout = VK_IMAGE_LAYOUT_GENERAL,
229 },
230 .pResolveAttachments = NULL,
231 .pDepthStencilAttachment = &(VkAttachmentReference) {
232 .attachment = VK_ATTACHMENT_UNUSED,
233 .layout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .preserveAttachmentCount = 0,
236 .pPreserveAttachments = NULL,
237 },
238 .dependencyCount = 0,
239 }, &device->meta_state.alloc, pass);
240 mtx_unlock(&device->meta_state.mtx);
241 return result;
242 }
243
244 static VkResult
245 create_color_pipeline(struct radv_device *device,
246 uint32_t samples,
247 uint32_t frag_output,
248 VkPipeline *pipeline,
249 VkRenderPass pass)
250 {
251 struct nir_shader *vs_nir;
252 struct nir_shader *fs_nir;
253 VkResult result;
254
255 mtx_lock(&device->meta_state.mtx);
256 if (*pipeline) {
257 mtx_unlock(&device->meta_state.mtx);
258 return VK_SUCCESS;
259 }
260
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
262
263 const VkPipelineVertexInputStateCreateInfo vi_state = {
264 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
265 .vertexBindingDescriptionCount = 0,
266 .vertexAttributeDescriptionCount = 0,
267 };
268
269 const VkPipelineDepthStencilStateCreateInfo ds_state = {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
271 .depthTestEnable = false,
272 .depthWriteEnable = false,
273 .depthBoundsTestEnable = false,
274 .stencilTestEnable = false,
275 };
276
277 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
278 blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
279 .blendEnable = false,
280 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
281 VK_COLOR_COMPONENT_R_BIT |
282 VK_COLOR_COMPONENT_G_BIT |
283 VK_COLOR_COMPONENT_B_BIT,
284 };
285
286 const VkPipelineColorBlendStateCreateInfo cb_state = {
287 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
288 .logicOpEnable = false,
289 .attachmentCount = MAX_RTS,
290 .pAttachments = blend_attachment_state
291 };
292
293
294 struct radv_graphics_pipeline_create_info extra = {
295 .use_rectlist = true,
296 };
297 result = create_pipeline(device, radv_render_pass_from_handle(pass),
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
299 device->meta_state.clear_color_p_layout,
300 &extra, &device->meta_state.alloc, pipeline);
301
302 mtx_unlock(&device->meta_state.mtx);
303 return result;
304 }
305
306 static void
307 finish_meta_clear_htile_mask_state(struct radv_device *device)
308 {
309 struct radv_meta_state *state = &device->meta_state;
310
311 radv_DestroyPipeline(radv_device_to_handle(device),
312 state->clear_htile_mask_pipeline,
313 &state->alloc);
314 radv_DestroyPipelineLayout(radv_device_to_handle(device),
315 state->clear_htile_mask_p_layout,
316 &state->alloc);
317 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
318 state->clear_htile_mask_ds_layout,
319 &state->alloc);
320 }
321
322 void
323 radv_device_finish_meta_clear_state(struct radv_device *device)
324 {
325 struct radv_meta_state *state = &device->meta_state;
326
327 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
328 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
329 radv_DestroyPipeline(radv_device_to_handle(device),
330 state->clear[i].color_pipelines[j],
331 &state->alloc);
332 radv_DestroyRenderPass(radv_device_to_handle(device),
333 state->clear[i].render_pass[j],
334 &state->alloc);
335 }
336
337 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
338 radv_DestroyPipeline(radv_device_to_handle(device),
339 state->clear[i].depth_only_pipeline[j],
340 &state->alloc);
341 radv_DestroyPipeline(radv_device_to_handle(device),
342 state->clear[i].stencil_only_pipeline[j],
343 &state->alloc);
344 radv_DestroyPipeline(radv_device_to_handle(device),
345 state->clear[i].depthstencil_pipeline[j],
346 &state->alloc);
347 }
348 radv_DestroyRenderPass(radv_device_to_handle(device),
349 state->clear[i].depthstencil_rp,
350 &state->alloc);
351 }
352 radv_DestroyPipelineLayout(radv_device_to_handle(device),
353 state->clear_color_p_layout,
354 &state->alloc);
355 radv_DestroyPipelineLayout(radv_device_to_handle(device),
356 state->clear_depth_p_layout,
357 &state->alloc);
358
359 finish_meta_clear_htile_mask_state(device);
360 }
361
362 static void
363 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
364 const VkClearAttachment *clear_att,
365 const VkClearRect *clear_rect,
366 uint32_t view_mask)
367 {
368 struct radv_device *device = cmd_buffer->device;
369 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
370 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
371 const uint32_t subpass_att = clear_att->colorAttachment;
372 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
373 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
374 uint32_t samples, samples_log2;
375 VkFormat format;
376 unsigned fs_key;
377 VkClearColorValue clear_value = clear_att->clearValue.color;
378 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
379 VkPipeline pipeline;
380
381 /* When a framebuffer is bound to the current command buffer, get the
382 * number of samples from it. Otherwise, get the number of samples from
383 * the render pass because it's likely a secondary command buffer.
384 */
385 if (iview) {
386 samples = iview->image->info.samples;
387 format = iview->vk_format;
388 } else {
389 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
390 format = cmd_buffer->state.pass->attachments[pass_att].format;
391 }
392
393 samples_log2 = ffs(samples) - 1;
394 fs_key = radv_format_meta_fs_key(format);
395
396 if (fs_key == -1) {
397 radv_finishme("color clears incomplete");
398 return;
399 }
400
401 if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
402 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
403 samples,
404 &device->meta_state.clear[samples_log2].render_pass[fs_key]);
405 if (ret != VK_SUCCESS) {
406 cmd_buffer->record_result = ret;
407 return;
408 }
409 }
410
411 if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
412 VkResult ret = create_color_pipeline(device, samples, 0,
413 &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
414 device->meta_state.clear[samples_log2].render_pass[fs_key]);
415 if (ret != VK_SUCCESS) {
416 cmd_buffer->record_result = ret;
417 return;
418 }
419 }
420
421 pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
422 if (!pipeline) {
423 radv_finishme("color clears incomplete");
424 return;
425 }
426 assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
427 assert(pipeline);
428 assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
429 assert(clear_att->colorAttachment < subpass->color_count);
430
431 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
432 device->meta_state.clear_color_p_layout,
433 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
434 &clear_value);
435
436 struct radv_subpass clear_subpass = {
437 .color_count = 1,
438 .color_attachments = (struct radv_subpass_attachment[]) {
439 subpass->color_attachments[clear_att->colorAttachment]
440 },
441 .depth_stencil_attachment = NULL,
442 };
443
444 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
445
446 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
447 pipeline);
448
449 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
450 .x = clear_rect->rect.offset.x,
451 .y = clear_rect->rect.offset.y,
452 .width = clear_rect->rect.extent.width,
453 .height = clear_rect->rect.extent.height,
454 .minDepth = 0.0f,
455 .maxDepth = 1.0f
456 });
457
458 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
459
460 if (view_mask) {
461 unsigned i;
462 for_each_bit(i, view_mask)
463 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
464 } else {
465 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
466 }
467
468 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
469 }
470
471
472 static void
473 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
474 {
475 nir_builder vs_b, fs_b;
476
477 nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
478 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
479
480 vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
481 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
482 const struct glsl_type *position_out_type = glsl_vec4_type();
483
484 nir_variable *vs_out_pos =
485 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
486 "gl_Position");
487 vs_out_pos->data.location = VARYING_SLOT_POS;
488
489 nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
490 nir_intrinsic_set_base(in_color_load, 0);
491 nir_intrinsic_set_range(in_color_load, 4);
492 in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
493 in_color_load->num_components = 1;
494 nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
495 nir_builder_instr_insert(&vs_b, &in_color_load->instr);
496
497 nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
498 nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
499
500 const struct glsl_type *layer_type = glsl_int_type();
501 nir_variable *vs_out_layer =
502 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
503 "v_layer");
504 vs_out_layer->data.location = VARYING_SLOT_LAYER;
505 vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
506 nir_ssa_def *inst_id = nir_load_instance_id(&vs_b);
507 nir_ssa_def *base_instance = nir_load_base_instance(&vs_b);
508
509 nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
510 nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
511
512 *out_vs = vs_b.shader;
513 *out_fs = fs_b.shader;
514 }
515
516 static VkResult
517 create_depthstencil_renderpass(struct radv_device *device,
518 uint32_t samples,
519 VkRenderPass *render_pass)
520 {
521 mtx_lock(&device->meta_state.mtx);
522 if (*render_pass) {
523 mtx_unlock(&device->meta_state.mtx);
524 return VK_SUCCESS;
525 }
526
527 VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
528 &(VkRenderPassCreateInfo) {
529 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
530 .attachmentCount = 1,
531 .pAttachments = &(VkAttachmentDescription) {
532 .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
533 .samples = samples,
534 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
535 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
536 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
537 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
538 },
539 .subpassCount = 1,
540 .pSubpasses = &(VkSubpassDescription) {
541 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
542 .inputAttachmentCount = 0,
543 .colorAttachmentCount = 0,
544 .pColorAttachments = NULL,
545 .pResolveAttachments = NULL,
546 .pDepthStencilAttachment = &(VkAttachmentReference) {
547 .attachment = 0,
548 .layout = VK_IMAGE_LAYOUT_GENERAL,
549 },
550 .preserveAttachmentCount = 0,
551 .pPreserveAttachments = NULL,
552 },
553 .dependencyCount = 0,
554 }, &device->meta_state.alloc, render_pass);
555 mtx_unlock(&device->meta_state.mtx);
556 return result;
557 }
558
559 static VkResult
560 create_depthstencil_pipeline(struct radv_device *device,
561 VkImageAspectFlags aspects,
562 uint32_t samples,
563 int index,
564 VkPipeline *pipeline,
565 VkRenderPass render_pass)
566 {
567 struct nir_shader *vs_nir, *fs_nir;
568 VkResult result;
569
570 mtx_lock(&device->meta_state.mtx);
571 if (*pipeline) {
572 mtx_unlock(&device->meta_state.mtx);
573 return VK_SUCCESS;
574 }
575
576 build_depthstencil_shader(&vs_nir, &fs_nir);
577
578 const VkPipelineVertexInputStateCreateInfo vi_state = {
579 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
580 .vertexBindingDescriptionCount = 0,
581 .vertexAttributeDescriptionCount = 0,
582 };
583
584 const VkPipelineDepthStencilStateCreateInfo ds_state = {
585 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
586 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
587 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
588 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
589 .depthBoundsTestEnable = false,
590 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
591 .front = {
592 .passOp = VK_STENCIL_OP_REPLACE,
593 .compareOp = VK_COMPARE_OP_ALWAYS,
594 .writeMask = UINT32_MAX,
595 .reference = 0, /* dynamic */
596 },
597 .back = { 0 /* dont care */ },
598 };
599
600 const VkPipelineColorBlendStateCreateInfo cb_state = {
601 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
602 .logicOpEnable = false,
603 .attachmentCount = 0,
604 .pAttachments = NULL,
605 };
606
607 struct radv_graphics_pipeline_create_info extra = {
608 .use_rectlist = true,
609 };
610
611 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
612 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
613 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
614 }
615 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
616 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
617 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
618 }
619 result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
620 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
621 device->meta_state.clear_depth_p_layout,
622 &extra, &device->meta_state.alloc, pipeline);
623
624 mtx_unlock(&device->meta_state.mtx);
625 return result;
626 }
627
628 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
629 const struct radv_image_view *iview,
630 VkImageAspectFlags aspects,
631 VkImageLayout layout,
632 const VkClearRect *clear_rect,
633 VkClearDepthStencilValue clear_value)
634 {
635 if (!iview)
636 return false;
637
638 uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
639 cmd_buffer->queue_family_index,
640 cmd_buffer->queue_family_index);
641 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
642 clear_rect->rect.extent.width != iview->extent.width ||
643 clear_rect->rect.extent.height != iview->extent.height)
644 return false;
645 if (radv_image_is_tc_compat_htile(iview->image) &&
646 (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
647 clear_value.depth != 1.0) ||
648 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
649 return false;
650 if (radv_image_has_htile(iview->image) &&
651 iview->base_mip == 0 &&
652 iview->base_layer == 0 &&
653 iview->layer_count == iview->image->info.array_size &&
654 radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
655 radv_image_extent_compare(iview->image, &iview->extent))
656 return true;
657 return false;
658 }
659
660 static VkPipeline
661 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
662 struct radv_meta_state *meta_state,
663 const struct radv_image_view *iview,
664 int samples_log2,
665 VkImageAspectFlags aspects,
666 VkImageLayout layout,
667 const VkClearRect *clear_rect,
668 VkClearDepthStencilValue clear_value)
669 {
670 bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
671 int index = DEPTH_CLEAR_SLOW;
672 VkPipeline *pipeline;
673
674 if (fast) {
675 /* we don't know the previous clear values, so we always have
676 * the NO_EXPCLEAR path */
677 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
678 }
679
680 switch (aspects) {
681 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
682 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
683 break;
684 case VK_IMAGE_ASPECT_DEPTH_BIT:
685 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
686 break;
687 case VK_IMAGE_ASPECT_STENCIL_BIT:
688 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
689 break;
690 default:
691 unreachable("expected depth or stencil aspect");
692 }
693
694 if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
695 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
696 &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
697 if (ret != VK_SUCCESS) {
698 cmd_buffer->record_result = ret;
699 return VK_NULL_HANDLE;
700 }
701 }
702
703 if (*pipeline == VK_NULL_HANDLE) {
704 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
705 pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
706 if (ret != VK_SUCCESS) {
707 cmd_buffer->record_result = ret;
708 return VK_NULL_HANDLE;
709 }
710 }
711 return *pipeline;
712 }
713
714 static void
715 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
716 const VkClearAttachment *clear_att,
717 const VkClearRect *clear_rect,
718 struct radv_subpass_attachment *ds_att,
719 uint32_t view_mask)
720 {
721 struct radv_device *device = cmd_buffer->device;
722 struct radv_meta_state *meta_state = &device->meta_state;
723 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
724 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
725 const uint32_t pass_att = ds_att->attachment;
726 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
727 VkImageAspectFlags aspects = clear_att->aspectMask;
728 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
729 uint32_t samples, samples_log2;
730 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
731
732 /* When a framebuffer is bound to the current command buffer, get the
733 * number of samples from it. Otherwise, get the number of samples from
734 * the render pass because it's likely a secondary command buffer.
735 */
736 if (iview) {
737 samples = iview->image->info.samples;
738 } else {
739 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
740 }
741
742 samples_log2 = ffs(samples) - 1;
743
744 assert(pass_att != VK_ATTACHMENT_UNUSED);
745
746 if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
747 clear_value.depth = 1.0f;
748
749 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
750 device->meta_state.clear_depth_p_layout,
751 VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
752 &clear_value.depth);
753
754 uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
755 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
756 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
757 clear_value.stencil);
758 }
759
760 VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
761 meta_state,
762 iview,
763 samples_log2,
764 aspects,
765 ds_att->layout,
766 clear_rect,
767 clear_value);
768 if (!pipeline)
769 return;
770
771 struct radv_subpass clear_subpass = {
772 .color_count = 0,
773 .color_attachments = NULL,
774 .depth_stencil_attachment = ds_att,
775 };
776
777 radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass);
778
779 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
780 pipeline);
781
782 if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
783 ds_att->layout, clear_rect, clear_value))
784 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
785 clear_value, aspects);
786
787 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
788 .x = clear_rect->rect.offset.x,
789 .y = clear_rect->rect.offset.y,
790 .width = clear_rect->rect.extent.width,
791 .height = clear_rect->rect.extent.height,
792 .minDepth = 0.0f,
793 .maxDepth = 1.0f
794 });
795
796 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
797
798 if (view_mask) {
799 unsigned i;
800 for_each_bit(i, view_mask)
801 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
802 } else {
803 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
804 }
805
806 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
807 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
808 prev_reference);
809 }
810
811 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
812 }
813
814 static uint32_t
815 clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
816 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
817 uint32_t htile_value, uint32_t htile_mask)
818 {
819 struct radv_device *device = cmd_buffer->device;
820 struct radv_meta_state *state = &device->meta_state;
821 uint64_t block_count = round_up_u64(size, 1024);
822 struct radv_meta_saved_state saved_state;
823
824 radv_meta_save(&saved_state, cmd_buffer,
825 RADV_META_SAVE_COMPUTE_PIPELINE |
826 RADV_META_SAVE_CONSTANTS |
827 RADV_META_SAVE_DESCRIPTORS);
828
829 struct radv_buffer dst_buffer = {
830 .bo = bo,
831 .offset = offset,
832 .size = size
833 };
834
835 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
836 VK_PIPELINE_BIND_POINT_COMPUTE,
837 state->clear_htile_mask_pipeline);
838
839 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
840 state->clear_htile_mask_p_layout,
841 0, /* set */
842 1, /* descriptorWriteCount */
843 (VkWriteDescriptorSet[]) {
844 {
845 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
846 .dstBinding = 0,
847 .dstArrayElement = 0,
848 .descriptorCount = 1,
849 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
850 .pBufferInfo = &(VkDescriptorBufferInfo) {
851 .buffer = radv_buffer_to_handle(&dst_buffer),
852 .offset = 0,
853 .range = size
854 }
855 }
856 });
857
858 const unsigned constants[2] = {
859 htile_value & htile_mask,
860 ~htile_mask,
861 };
862
863 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
864 state->clear_htile_mask_p_layout,
865 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
866 constants);
867
868 radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
869
870 radv_meta_restore(&saved_state, cmd_buffer);
871
872 return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
873 RADV_CMD_FLAG_INV_VCACHE |
874 RADV_CMD_FLAG_WB_L2;
875 }
876
877 static uint32_t
878 radv_get_htile_fast_clear_value(const struct radv_image *image,
879 VkClearDepthStencilValue value)
880 {
881 uint32_t clear_value;
882
883 if (!image->planes[0].surface.has_stencil) {
884 clear_value = value.depth ? 0xfffffff0 : 0;
885 } else {
886 clear_value = value.depth ? 0xfffc0000 : 0;
887 }
888
889 return clear_value;
890 }
891
892 static uint32_t
893 radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects)
894 {
895 uint32_t mask = 0;
896
897 if (!image->planes[0].surface.has_stencil) {
898 /* All the HTILE buffer is used when there is no stencil. */
899 mask = UINT32_MAX;
900 } else {
901 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
902 mask |= 0xfffffc0f;
903 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
904 mask |= 0x000003f0;
905 }
906
907 return mask;
908 }
909
910 static bool
911 radv_is_fast_clear_depth_allowed(VkClearDepthStencilValue value)
912 {
913 return value.depth == 1.0f || value.depth == 0.0f;
914 }
915
916 static bool
917 radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value)
918 {
919 return value.stencil == 0;
920 }
921
922 /**
923 * Determine if the given image can be fast cleared.
924 */
925 static bool
926 radv_image_can_fast_clear(struct radv_device *device, struct radv_image *image)
927 {
928 if (device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
929 return false;
930
931 if (vk_format_is_color(image->vk_format)) {
932 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
933 return false;
934
935 /* RB+ doesn't work with CMASK fast clear on Stoney. */
936 if (!radv_image_has_dcc(image) &&
937 device->physical_device->rad_info.family == CHIP_STONEY)
938 return false;
939 } else {
940 if (!radv_image_has_htile(image))
941 return false;
942 }
943
944 /* Do not fast clears 3D images. */
945 if (image->type == VK_IMAGE_TYPE_3D)
946 return false;
947
948 return true;
949 }
950
951 /**
952 * Determine if the given image view can be fast cleared.
953 */
954 static bool
955 radv_image_view_can_fast_clear(struct radv_device *device,
956 const struct radv_image_view *iview)
957 {
958 struct radv_image *image;
959
960 if (!iview)
961 return false;
962 image = iview->image;
963
964 /* Only fast clear if the image itself can be fast cleared. */
965 if (!radv_image_can_fast_clear(device, image))
966 return false;
967
968 /* Only fast clear if all layers are bound. */
969 if (iview->base_layer > 0 ||
970 iview->layer_count != image->info.array_size)
971 return false;
972
973 /* Only fast clear if the view covers the whole image. */
974 if (!radv_image_extent_compare(image, &iview->extent))
975 return false;
976
977 return true;
978 }
979
980 static bool
981 radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
982 const struct radv_image_view *iview,
983 VkImageLayout image_layout,
984 VkImageAspectFlags aspects,
985 const VkClearRect *clear_rect,
986 const VkClearDepthStencilValue clear_value,
987 uint32_t view_mask)
988 {
989 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
990 return false;
991
992 if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
993 return false;
994
995 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
996 clear_rect->rect.extent.width != iview->image->info.width ||
997 clear_rect->rect.extent.height != iview->image->info.height)
998 return false;
999
1000 if (view_mask && (iview->image->info.array_size >= 32 ||
1001 (1u << iview->image->info.array_size) - 1u != view_mask))
1002 return false;
1003 if (!view_mask && clear_rect->baseArrayLayer != 0)
1004 return false;
1005 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1006 return false;
1007
1008 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 &&
1009 (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ||
1010 ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1011 !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))))
1012 return false;
1013
1014 if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1015 !radv_is_fast_clear_depth_allowed(clear_value)) ||
1016 ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1017 !radv_is_fast_clear_stencil_allowed(clear_value)))
1018 return false;
1019
1020 return true;
1021 }
1022
1023 static void
1024 radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
1025 const struct radv_image_view *iview,
1026 const VkClearAttachment *clear_att,
1027 enum radv_cmd_flush_bits *pre_flush,
1028 enum radv_cmd_flush_bits *post_flush)
1029 {
1030 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1031 VkImageAspectFlags aspects = clear_att->aspectMask;
1032 uint32_t clear_word, flush_bits;
1033 uint32_t htile_mask;
1034
1035 clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
1036 htile_mask = radv_get_htile_mask(iview->image, aspects);
1037
1038 if (pre_flush) {
1039 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1040 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
1041 *pre_flush |= cmd_buffer->state.flush_bits;
1042 }
1043
1044 if (htile_mask == UINT_MAX) {
1045 /* Clear the whole HTILE buffer. */
1046 flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
1047 iview->image->offset + iview->image->htile_offset,
1048 iview->image->planes[0].surface.htile_size, clear_word);
1049 } else {
1050 /* Only clear depth or stencil bytes in the HTILE buffer. */
1051 assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
1052 flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
1053 iview->image->offset + iview->image->htile_offset,
1054 iview->image->planes[0].surface.htile_size, clear_word,
1055 htile_mask);
1056 }
1057
1058 radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
1059 if (post_flush) {
1060 *post_flush |= flush_bits;
1061 }
1062 }
1063
1064 static nir_shader *
1065 build_clear_htile_mask_shader()
1066 {
1067 nir_builder b;
1068
1069 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1070 b.shader->info.name = ralloc_strdup(b.shader, "meta_clear_htile_mask");
1071 b.shader->info.cs.local_size[0] = 64;
1072 b.shader->info.cs.local_size[1] = 1;
1073 b.shader->info.cs.local_size[2] = 1;
1074
1075 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
1076 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
1077 nir_ssa_def *block_size = nir_imm_ivec4(&b,
1078 b.shader->info.cs.local_size[0],
1079 b.shader->info.cs.local_size[1],
1080 b.shader->info.cs.local_size[2], 0);
1081
1082 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
1083
1084 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
1085 offset = nir_channel(&b, offset, 0);
1086
1087 nir_intrinsic_instr *buf =
1088 nir_intrinsic_instr_create(b.shader,
1089 nir_intrinsic_vulkan_resource_index);
1090
1091 buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1092 buf->num_components = 1;
1093 nir_intrinsic_set_desc_set(buf, 0);
1094 nir_intrinsic_set_binding(buf, 0);
1095 nir_ssa_dest_init(&buf->instr, &buf->dest, buf->num_components, 32, NULL);
1096 nir_builder_instr_insert(&b, &buf->instr);
1097
1098 nir_intrinsic_instr *constants =
1099 nir_intrinsic_instr_create(b.shader,
1100 nir_intrinsic_load_push_constant);
1101 nir_intrinsic_set_base(constants, 0);
1102 nir_intrinsic_set_range(constants, 8);
1103 constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
1104 constants->num_components = 2;
1105 nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
1106 nir_builder_instr_insert(&b, &constants->instr);
1107
1108 nir_intrinsic_instr *load =
1109 nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
1110 load->src[0] = nir_src_for_ssa(&buf->dest.ssa);
1111 load->src[1] = nir_src_for_ssa(offset);
1112 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1113 load->num_components = 4;
1114 nir_builder_instr_insert(&b, &load->instr);
1115
1116 /* data = (data & ~htile_mask) | (htile_value & htile_mask) */
1117 nir_ssa_def *data =
1118 nir_iand(&b, &load->dest.ssa,
1119 nir_channel(&b, &constants->dest.ssa, 1));
1120 data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
1121
1122 nir_intrinsic_instr *store =
1123 nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
1124 store->src[0] = nir_src_for_ssa(data);
1125 store->src[1] = nir_src_for_ssa(&buf->dest.ssa);
1126 store->src[2] = nir_src_for_ssa(offset);
1127 nir_intrinsic_set_write_mask(store, 0xf);
1128 nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
1129 store->num_components = 4;
1130 nir_builder_instr_insert(&b, &store->instr);
1131
1132 return b.shader;
1133 }
1134
1135 static VkResult
1136 init_meta_clear_htile_mask_state(struct radv_device *device)
1137 {
1138 struct radv_meta_state *state = &device->meta_state;
1139 struct radv_shader_module cs = { .nir = NULL };
1140 VkResult result;
1141
1142 cs.nir = build_clear_htile_mask_shader();
1143
1144 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1145 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1146 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1147 .bindingCount = 1,
1148 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1149 {
1150 .binding = 0,
1151 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1152 .descriptorCount = 1,
1153 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
1154 .pImmutableSamplers = NULL
1155 },
1156 }
1157 };
1158
1159 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1160 &ds_layout_info, &state->alloc,
1161 &state->clear_htile_mask_ds_layout);
1162 if (result != VK_SUCCESS)
1163 goto fail;
1164
1165 VkPipelineLayoutCreateInfo p_layout_info = {
1166 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1167 .setLayoutCount = 1,
1168 .pSetLayouts = &state->clear_htile_mask_ds_layout,
1169 .pushConstantRangeCount = 1,
1170 .pPushConstantRanges = &(VkPushConstantRange){
1171 VK_SHADER_STAGE_COMPUTE_BIT, 0, 8,
1172 },
1173 };
1174
1175 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1176 &p_layout_info, &state->alloc,
1177 &state->clear_htile_mask_p_layout);
1178 if (result != VK_SUCCESS)
1179 goto fail;
1180
1181 VkPipelineShaderStageCreateInfo shader_stage = {
1182 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1183 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1184 .module = radv_shader_module_to_handle(&cs),
1185 .pName = "main",
1186 .pSpecializationInfo = NULL,
1187 };
1188
1189 VkComputePipelineCreateInfo pipeline_info = {
1190 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1191 .stage = shader_stage,
1192 .flags = 0,
1193 .layout = state->clear_htile_mask_p_layout,
1194 };
1195
1196 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1197 radv_pipeline_cache_to_handle(&state->cache),
1198 1, &pipeline_info, NULL,
1199 &state->clear_htile_mask_pipeline);
1200
1201 ralloc_free(cs.nir);
1202 return result;
1203 fail:
1204 ralloc_free(cs.nir);
1205 return result;
1206 }
1207
1208 VkResult
1209 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
1210 {
1211 VkResult res;
1212 struct radv_meta_state *state = &device->meta_state;
1213
1214 VkPipelineLayoutCreateInfo pl_color_create_info = {
1215 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1216 .setLayoutCount = 0,
1217 .pushConstantRangeCount = 1,
1218 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
1219 };
1220
1221 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1222 &pl_color_create_info,
1223 &device->meta_state.alloc,
1224 &device->meta_state.clear_color_p_layout);
1225 if (res != VK_SUCCESS)
1226 goto fail;
1227
1228 VkPipelineLayoutCreateInfo pl_depth_create_info = {
1229 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1230 .setLayoutCount = 0,
1231 .pushConstantRangeCount = 1,
1232 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
1233 };
1234
1235 res = radv_CreatePipelineLayout(radv_device_to_handle(device),
1236 &pl_depth_create_info,
1237 &device->meta_state.alloc,
1238 &device->meta_state.clear_depth_p_layout);
1239 if (res != VK_SUCCESS)
1240 goto fail;
1241
1242 res = init_meta_clear_htile_mask_state(device);
1243 if (res != VK_SUCCESS)
1244 goto fail;
1245
1246 if (on_demand)
1247 return VK_SUCCESS;
1248
1249 for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
1250 uint32_t samples = 1 << i;
1251 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
1252 VkFormat format = radv_fs_key_format_exemplars[j];
1253 unsigned fs_key = radv_format_meta_fs_key(format);
1254 assert(!state->clear[i].color_pipelines[fs_key]);
1255
1256 res = create_color_renderpass(device, format, samples,
1257 &state->clear[i].render_pass[fs_key]);
1258 if (res != VK_SUCCESS)
1259 goto fail;
1260
1261 res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
1262 state->clear[i].render_pass[fs_key]);
1263 if (res != VK_SUCCESS)
1264 goto fail;
1265
1266 }
1267
1268 res = create_depthstencil_renderpass(device,
1269 samples,
1270 &state->clear[i].depthstencil_rp);
1271 if (res != VK_SUCCESS)
1272 goto fail;
1273
1274 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
1275 res = create_depthstencil_pipeline(device,
1276 VK_IMAGE_ASPECT_DEPTH_BIT,
1277 samples,
1278 j,
1279 &state->clear[i].depth_only_pipeline[j],
1280 state->clear[i].depthstencil_rp);
1281 if (res != VK_SUCCESS)
1282 goto fail;
1283
1284 res = create_depthstencil_pipeline(device,
1285 VK_IMAGE_ASPECT_STENCIL_BIT,
1286 samples,
1287 j,
1288 &state->clear[i].stencil_only_pipeline[j],
1289 state->clear[i].depthstencil_rp);
1290 if (res != VK_SUCCESS)
1291 goto fail;
1292
1293 res = create_depthstencil_pipeline(device,
1294 VK_IMAGE_ASPECT_DEPTH_BIT |
1295 VK_IMAGE_ASPECT_STENCIL_BIT,
1296 samples,
1297 j,
1298 &state->clear[i].depthstencil_pipeline[j],
1299 state->clear[i].depthstencil_rp);
1300 if (res != VK_SUCCESS)
1301 goto fail;
1302 }
1303 }
1304 return VK_SUCCESS;
1305
1306 fail:
1307 radv_device_finish_meta_clear_state(device);
1308 return res;
1309 }
1310
1311 static uint32_t
1312 radv_get_cmask_fast_clear_value(const struct radv_image *image)
1313 {
1314 uint32_t value = 0; /* Default value when no DCC. */
1315
1316 /* The fast-clear value is different for images that have both DCC and
1317 * CMASK metadata.
1318 */
1319 if (radv_image_has_dcc(image)) {
1320 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
1321 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
1322 }
1323
1324 return value;
1325 }
1326
1327 uint32_t
1328 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
1329 struct radv_image *image,
1330 const VkImageSubresourceRange *range, uint32_t value)
1331 {
1332 uint64_t offset = image->offset + image->cmask.offset;
1333 uint64_t size;
1334
1335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1336 /* TODO: clear layers. */
1337 size = image->cmask.size;
1338 } else {
1339 offset += image->cmask.slice_size * range->baseArrayLayer;
1340 size = image->cmask.slice_size * radv_get_layerCount(image, range);
1341 }
1342
1343 return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1344 }
1345
1346
1347 uint32_t
1348 radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
1349 struct radv_image *image,
1350 const VkImageSubresourceRange *range, uint32_t value)
1351 {
1352 uint64_t offset = image->offset + image->fmask.offset;
1353 uint64_t size;
1354
1355 /* MSAA images do not support mipmap levels. */
1356 assert(range->baseMipLevel == 0 &&
1357 radv_get_levelCount(image, range) == 1);
1358
1359 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1360 /* TODO: clear layers. */
1361 size = image->fmask.size;
1362 } else {
1363 offset += image->fmask.slice_size * range->baseArrayLayer;
1364 size = image->fmask.slice_size * radv_get_layerCount(image, range);
1365 }
1366
1367 return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1368 }
1369
1370 uint32_t
1371 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
1372 struct radv_image *image,
1373 const VkImageSubresourceRange *range, uint32_t value)
1374 {
1375 uint32_t level_count = radv_get_levelCount(image, range);
1376 uint32_t flush_bits = 0;
1377
1378 /* Mark the image as being compressed. */
1379 radv_update_dcc_metadata(cmd_buffer, image, range, true);
1380
1381 for (uint32_t l = 0; l < level_count; l++) {
1382 uint64_t offset = image->offset + image->dcc_offset;
1383 uint32_t level = range->baseMipLevel + l;
1384 uint64_t size;
1385
1386 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1387 /* Mipmap levels aren't implemented. */
1388 assert(level == 0);
1389 size = image->planes[0].surface.dcc_size;
1390 } else {
1391 const struct legacy_surf_level *surf_level =
1392 &image->planes[0].surface.u.legacy.level[level];
1393
1394 /* If dcc_fast_clear_size is 0 (which might happens for
1395 * mipmaps) the fill buffer operation below is a no-op.
1396 * This can only happen during initialization as the
1397 * fast clear path fallbacks to slow clears if one
1398 * level can't be fast cleared.
1399 */
1400 offset += surf_level->dcc_offset;
1401 size = surf_level->dcc_fast_clear_size;
1402 }
1403
1404 flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
1405 size, value);
1406 }
1407
1408 return flush_bits;
1409 }
1410
1411 uint32_t
1412 radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1413 const VkImageSubresourceRange *range, uint32_t value)
1414 {
1415 unsigned layer_count = radv_get_layerCount(image, range);
1416 uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
1417 uint64_t offset = image->offset + image->htile_offset +
1418 image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
1419
1420 return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
1421 }
1422
1423 static void vi_get_fast_clear_parameters(VkFormat format,
1424 const VkClearColorValue *clear_value,
1425 uint32_t* reset_value,
1426 bool *can_avoid_fast_clear_elim)
1427 {
1428 bool values[4] = {};
1429 int extra_channel;
1430 bool main_value = false;
1431 bool extra_value = false;
1432 int i;
1433 *can_avoid_fast_clear_elim = false;
1434
1435 *reset_value = 0x20202020U;
1436
1437 const struct vk_format_description *desc = vk_format_description(format);
1438 if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1439 format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1440 format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1441 extra_channel = -1;
1442 else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1443 if (radv_translate_colorswap(format, false) <= 1)
1444 extra_channel = desc->nr_channels - 1;
1445 else
1446 extra_channel = 0;
1447 } else
1448 return;
1449
1450 for (i = 0; i < 4; i++) {
1451 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1452 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1453 desc->swizzle[i] > VK_SWIZZLE_W)
1454 continue;
1455
1456 if (desc->channel[i].pure_integer &&
1457 desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1458 /* Use the maximum value for clamping the clear color. */
1459 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1460
1461 values[i] = clear_value->int32[i] != 0;
1462 if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1463 return;
1464 } else if (desc->channel[i].pure_integer &&
1465 desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1466 /* Use the maximum value for clamping the clear color. */
1467 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1468
1469 values[i] = clear_value->uint32[i] != 0U;
1470 if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1471 return;
1472 } else {
1473 values[i] = clear_value->float32[i] != 0.0F;
1474 if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1475 return;
1476 }
1477
1478 if (index == extra_channel)
1479 extra_value = values[i];
1480 else
1481 main_value = values[i];
1482 }
1483
1484 for (int i = 0; i < 4; ++i)
1485 if (values[i] != main_value &&
1486 desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1487 desc->swizzle[i] >= VK_SWIZZLE_X &&
1488 desc->swizzle[i] <= VK_SWIZZLE_W)
1489 return;
1490
1491 *can_avoid_fast_clear_elim = true;
1492 if (main_value)
1493 *reset_value |= 0x80808080U;
1494
1495 if (extra_value)
1496 *reset_value |= 0x40404040U;
1497 return;
1498 }
1499
1500 static bool
1501 radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1502 const struct radv_image_view *iview,
1503 VkImageLayout image_layout,
1504 const VkClearRect *clear_rect,
1505 VkClearColorValue clear_value,
1506 uint32_t view_mask)
1507 {
1508 uint32_t clear_color[2];
1509
1510 if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
1511 return false;
1512
1513 if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1514 return false;
1515
1516 if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1517 clear_rect->rect.extent.width != iview->image->info.width ||
1518 clear_rect->rect.extent.height != iview->image->info.height)
1519 return false;
1520
1521 if (view_mask && (iview->image->info.array_size >= 32 ||
1522 (1u << iview->image->info.array_size) - 1u != view_mask))
1523 return false;
1524 if (!view_mask && clear_rect->baseArrayLayer != 0)
1525 return false;
1526 if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1527 return false;
1528
1529 /* DCC */
1530 if (!radv_format_pack_clear_color(iview->vk_format,
1531 clear_color, &clear_value))
1532 return false;
1533
1534 if (radv_dcc_enabled(iview->image, iview->base_mip)) {
1535 bool can_avoid_fast_clear_elim;
1536 uint32_t reset_value;
1537
1538 vi_get_fast_clear_parameters(iview->vk_format,
1539 &clear_value, &reset_value,
1540 &can_avoid_fast_clear_elim);
1541
1542 if (iview->image->info.samples > 1) {
1543 /* DCC fast clear with MSAA should clear CMASK. */
1544 /* FIXME: This doesn't work for now. There is a
1545 * hardware bug with fast clears and DCC for MSAA
1546 * textures. AMDVLK has a workaround but it doesn't
1547 * seem to work here. Note that we might emit useless
1548 * CB flushes but that shouldn't matter.
1549 */
1550 if (!can_avoid_fast_clear_elim)
1551 return false;
1552 }
1553
1554 if (iview->image->info.levels > 1 &&
1555 cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
1556 for (uint32_t l = 0; l < iview->level_count; l++) {
1557 uint32_t level = iview->base_mip + l;
1558 struct legacy_surf_level *surf_level =
1559 &iview->image->planes[0].surface.u.legacy.level[level];
1560
1561 /* Do not fast clears if one level can't be
1562 * fast cleared.
1563 */
1564 if (!surf_level->dcc_fast_clear_size)
1565 return false;
1566 }
1567 }
1568 }
1569
1570 return true;
1571 }
1572
1573
1574 static void
1575 radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1576 const struct radv_image_view *iview,
1577 const VkClearAttachment *clear_att,
1578 uint32_t subpass_att,
1579 enum radv_cmd_flush_bits *pre_flush,
1580 enum radv_cmd_flush_bits *post_flush)
1581 {
1582 VkClearColorValue clear_value = clear_att->clearValue.color;
1583 uint32_t clear_color[2], flush_bits = 0;
1584 uint32_t cmask_clear_value;
1585 VkImageSubresourceRange range = {
1586 .aspectMask = iview->aspect_mask,
1587 .baseMipLevel = iview->base_mip,
1588 .levelCount = iview->level_count,
1589 .baseArrayLayer = iview->base_layer,
1590 .layerCount = iview->layer_count,
1591 };
1592
1593 if (pre_flush) {
1594 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1595 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1596 *pre_flush |= cmd_buffer->state.flush_bits;
1597 }
1598
1599 /* DCC */
1600 radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
1601
1602 cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1603
1604 /* clear cmask buffer */
1605 if (radv_dcc_enabled(iview->image, iview->base_mip)) {
1606 uint32_t reset_value;
1607 bool can_avoid_fast_clear_elim;
1608 bool need_decompress_pass = false;
1609
1610 vi_get_fast_clear_parameters(iview->vk_format,
1611 &clear_value, &reset_value,
1612 &can_avoid_fast_clear_elim);
1613
1614 if (radv_image_has_cmask(iview->image)) {
1615 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1616 &range, cmask_clear_value);
1617
1618 need_decompress_pass = true;
1619 }
1620
1621 if (!can_avoid_fast_clear_elim)
1622 need_decompress_pass = true;
1623
1624 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, &range,
1625 reset_value);
1626
1627 radv_update_fce_metadata(cmd_buffer, iview->image, &range,
1628 need_decompress_pass);
1629 } else {
1630 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1631 &range, cmask_clear_value);
1632 }
1633
1634 if (post_flush) {
1635 *post_flush |= flush_bits;
1636 }
1637
1638 radv_update_color_clear_metadata(cmd_buffer, iview, subpass_att,
1639 clear_color);
1640 }
1641
1642 /**
1643 * The parameters mean that same as those in vkCmdClearAttachments.
1644 */
1645 static void
1646 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1647 const VkClearAttachment *clear_att,
1648 const VkClearRect *clear_rect,
1649 enum radv_cmd_flush_bits *pre_flush,
1650 enum radv_cmd_flush_bits *post_flush,
1651 uint32_t view_mask,
1652 bool ds_resolve_clear)
1653 {
1654 const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1655 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1656 VkImageAspectFlags aspects = clear_att->aspectMask;
1657
1658 if (aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
1659 const uint32_t subpass_att = clear_att->colorAttachment;
1660 assert(subpass_att < subpass->color_count);
1661 const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1662 if (pass_att == VK_ATTACHMENT_UNUSED)
1663 return;
1664
1665 VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1666 const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
1667 VkClearColorValue clear_value = clear_att->clearValue.color;
1668
1669 if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
1670 clear_rect, clear_value, view_mask)) {
1671 radv_fast_clear_color(cmd_buffer, iview, clear_att,
1672 subpass_att, pre_flush,
1673 post_flush);
1674 } else {
1675 emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1676 }
1677 } else {
1678 struct radv_subpass_attachment *ds_att = subpass->depth_stencil_attachment;
1679
1680 if (ds_resolve_clear)
1681 ds_att = subpass->ds_resolve_attachment;
1682
1683 if (ds_att->attachment == VK_ATTACHMENT_UNUSED)
1684 return;
1685
1686 VkImageLayout image_layout = ds_att->layout;
1687 const struct radv_image_view *iview = fb ? fb->attachments[ds_att->attachment].attachment : NULL;
1688 VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
1689
1690 assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1691 VK_IMAGE_ASPECT_STENCIL_BIT));
1692
1693 if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
1694 aspects, clear_rect, clear_value,
1695 view_mask)) {
1696 radv_fast_clear_depth(cmd_buffer, iview, clear_att,
1697 pre_flush, post_flush);
1698 } else {
1699 emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect,
1700 ds_att, view_mask);
1701 }
1702 }
1703 }
1704
1705 static inline bool
1706 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1707 {
1708 uint32_t view_mask = cmd_state->subpass->view_mask;
1709 return (a != VK_ATTACHMENT_UNUSED &&
1710 cmd_state->attachments[a].pending_clear_aspects &&
1711 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1712 }
1713
1714 static bool
1715 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1716 {
1717 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1718 uint32_t a;
1719
1720 if (!cmd_state->subpass)
1721 return false;
1722
1723 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1724 a = cmd_state->subpass->color_attachments[i].attachment;
1725 if (radv_attachment_needs_clear(cmd_state, a))
1726 return true;
1727 }
1728
1729 if (cmd_state->subpass->depth_stencil_attachment) {
1730 a = cmd_state->subpass->depth_stencil_attachment->attachment;
1731 if (radv_attachment_needs_clear(cmd_state, a))
1732 return true;
1733 }
1734
1735 if (!cmd_state->subpass->ds_resolve_attachment)
1736 return false;
1737
1738 a = cmd_state->subpass->ds_resolve_attachment->attachment;
1739 return radv_attachment_needs_clear(cmd_state, a);
1740 }
1741
1742 static void
1743 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1744 struct radv_attachment_state *attachment,
1745 const VkClearAttachment *clear_att,
1746 enum radv_cmd_flush_bits *pre_flush,
1747 enum radv_cmd_flush_bits *post_flush,
1748 bool ds_resolve_clear)
1749 {
1750 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1751 uint32_t view_mask = cmd_state->subpass->view_mask;
1752
1753 VkClearRect clear_rect = {
1754 .rect = cmd_state->render_area,
1755 .baseArrayLayer = 0,
1756 .layerCount = cmd_state->framebuffer->layers,
1757 };
1758
1759 emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1760 view_mask & ~attachment->cleared_views, ds_resolve_clear);
1761 if (view_mask)
1762 attachment->cleared_views |= view_mask;
1763 else
1764 attachment->pending_clear_aspects = 0;
1765 }
1766
1767 /**
1768 * Emit any pending attachment clears for the current subpass.
1769 *
1770 * @see radv_attachment_state::pending_clear_aspects
1771 */
1772 void
1773 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1774 {
1775 struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1776 struct radv_meta_saved_state saved_state;
1777 enum radv_cmd_flush_bits pre_flush = 0;
1778 enum radv_cmd_flush_bits post_flush = 0;
1779
1780 if (!radv_subpass_needs_clear(cmd_buffer))
1781 return;
1782
1783 radv_meta_save(&saved_state, cmd_buffer,
1784 RADV_META_SAVE_GRAPHICS_PIPELINE |
1785 RADV_META_SAVE_CONSTANTS);
1786
1787 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1788 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1789
1790 if (!radv_attachment_needs_clear(cmd_state, a))
1791 continue;
1792
1793 assert(cmd_state->attachments[a].pending_clear_aspects ==
1794 VK_IMAGE_ASPECT_COLOR_BIT);
1795
1796 VkClearAttachment clear_att = {
1797 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1798 .colorAttachment = i, /* Use attachment index relative to subpass */
1799 .clearValue = cmd_state->attachments[a].clear_value,
1800 };
1801
1802 radv_subpass_clear_attachment(cmd_buffer,
1803 &cmd_state->attachments[a],
1804 &clear_att, &pre_flush,
1805 &post_flush, false);
1806 }
1807
1808 if (cmd_state->subpass->depth_stencil_attachment) {
1809 uint32_t ds = cmd_state->subpass->depth_stencil_attachment->attachment;
1810 if (radv_attachment_needs_clear(cmd_state, ds)) {
1811 VkClearAttachment clear_att = {
1812 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1813 .clearValue = cmd_state->attachments[ds].clear_value,
1814 };
1815
1816 radv_subpass_clear_attachment(cmd_buffer,
1817 &cmd_state->attachments[ds],
1818 &clear_att, &pre_flush,
1819 &post_flush, false);
1820 }
1821 }
1822
1823 if (cmd_state->subpass->ds_resolve_attachment) {
1824 uint32_t ds_resolve = cmd_state->subpass->ds_resolve_attachment->attachment;
1825 if (radv_attachment_needs_clear(cmd_state, ds_resolve)) {
1826 VkClearAttachment clear_att = {
1827 .aspectMask = cmd_state->attachments[ds_resolve].pending_clear_aspects,
1828 .clearValue = cmd_state->attachments[ds_resolve].clear_value,
1829 };
1830
1831 radv_subpass_clear_attachment(cmd_buffer,
1832 &cmd_state->attachments[ds_resolve],
1833 &clear_att, &pre_flush,
1834 &post_flush, true);
1835 }
1836 }
1837
1838 radv_meta_restore(&saved_state, cmd_buffer);
1839 cmd_buffer->state.flush_bits |= post_flush;
1840 }
1841
1842 static void
1843 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1844 struct radv_image *image,
1845 VkImageLayout image_layout,
1846 const VkImageSubresourceRange *range,
1847 VkFormat format, int level, int layer,
1848 const VkClearValue *clear_val)
1849 {
1850 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1851 struct radv_image_view iview;
1852 uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1853 uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1854
1855 radv_image_view_init(&iview, cmd_buffer->device,
1856 &(VkImageViewCreateInfo) {
1857 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1858 .image = radv_image_to_handle(image),
1859 .viewType = radv_meta_get_view_type(image),
1860 .format = format,
1861 .subresourceRange = {
1862 .aspectMask = range->aspectMask,
1863 .baseMipLevel = range->baseMipLevel + level,
1864 .levelCount = 1,
1865 .baseArrayLayer = range->baseArrayLayer + layer,
1866 .layerCount = 1
1867 },
1868 });
1869
1870 VkFramebuffer fb;
1871 radv_CreateFramebuffer(device_h,
1872 &(VkFramebufferCreateInfo) {
1873 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1874 .attachmentCount = 1,
1875 .pAttachments = (VkImageView[]) {
1876 radv_image_view_to_handle(&iview),
1877 },
1878 .width = width,
1879 .height = height,
1880 .layers = 1
1881 },
1882 &cmd_buffer->pool->alloc,
1883 &fb);
1884
1885 VkAttachmentDescription att_desc = {
1886 .format = iview.vk_format,
1887 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1888 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1889 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1890 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1891 .initialLayout = image_layout,
1892 .finalLayout = image_layout,
1893 };
1894
1895 VkSubpassDescription subpass_desc = {
1896 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1897 .inputAttachmentCount = 0,
1898 .colorAttachmentCount = 0,
1899 .pColorAttachments = NULL,
1900 .pResolveAttachments = NULL,
1901 .pDepthStencilAttachment = NULL,
1902 .preserveAttachmentCount = 0,
1903 .pPreserveAttachments = NULL,
1904 };
1905
1906 const VkAttachmentReference att_ref = {
1907 .attachment = 0,
1908 .layout = image_layout,
1909 };
1910
1911 if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1912 subpass_desc.colorAttachmentCount = 1;
1913 subpass_desc.pColorAttachments = &att_ref;
1914 } else {
1915 subpass_desc.pDepthStencilAttachment = &att_ref;
1916 }
1917
1918 VkRenderPass pass;
1919 radv_CreateRenderPass(device_h,
1920 &(VkRenderPassCreateInfo) {
1921 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1922 .attachmentCount = 1,
1923 .pAttachments = &att_desc,
1924 .subpassCount = 1,
1925 .pSubpasses = &subpass_desc,
1926 },
1927 &cmd_buffer->pool->alloc,
1928 &pass);
1929
1930 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1931 &(VkRenderPassBeginInfo) {
1932 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1933 .renderArea = {
1934 .offset = { 0, 0, },
1935 .extent = {
1936 .width = width,
1937 .height = height,
1938 },
1939 },
1940 .renderPass = pass,
1941 .framebuffer = fb,
1942 .clearValueCount = 0,
1943 .pClearValues = NULL,
1944 },
1945 VK_SUBPASS_CONTENTS_INLINE);
1946
1947 VkClearAttachment clear_att = {
1948 .aspectMask = range->aspectMask,
1949 .colorAttachment = 0,
1950 .clearValue = *clear_val,
1951 };
1952
1953 VkClearRect clear_rect = {
1954 .rect = {
1955 .offset = { 0, 0 },
1956 .extent = { width, height },
1957 },
1958 .baseArrayLayer = range->baseArrayLayer,
1959 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1960 };
1961
1962 emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false);
1963
1964 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1965 radv_DestroyRenderPass(device_h, pass,
1966 &cmd_buffer->pool->alloc);
1967 radv_DestroyFramebuffer(device_h, fb,
1968 &cmd_buffer->pool->alloc);
1969 }
1970
1971 /**
1972 * Return TRUE if a fast color or depth clear has been performed.
1973 */
1974 static bool
1975 radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
1976 struct radv_image *image,
1977 VkFormat format,
1978 VkImageLayout image_layout,
1979 const VkImageSubresourceRange *range,
1980 const VkClearValue *clear_val)
1981 {
1982 struct radv_image_view iview;
1983
1984 radv_image_view_init(&iview, cmd_buffer->device,
1985 &(VkImageViewCreateInfo) {
1986 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1987 .image = radv_image_to_handle(image),
1988 .viewType = radv_meta_get_view_type(image),
1989 .format = image->vk_format,
1990 .subresourceRange = {
1991 .aspectMask = range->aspectMask,
1992 .baseMipLevel = range->baseMipLevel,
1993 .levelCount = range->levelCount,
1994 .baseArrayLayer = range->baseArrayLayer,
1995 .layerCount = range->layerCount,
1996 },
1997 });
1998
1999 VkClearRect clear_rect = {
2000 .rect = {
2001 .offset = { 0, 0 },
2002 .extent = {
2003 radv_minify(image->info.width, range->baseMipLevel),
2004 radv_minify(image->info.height, range->baseMipLevel),
2005 },
2006 },
2007 .baseArrayLayer = range->baseArrayLayer,
2008 .layerCount = range->layerCount,
2009 };
2010
2011 VkClearAttachment clear_att = {
2012 .aspectMask = range->aspectMask,
2013 .colorAttachment = 0,
2014 .clearValue = *clear_val,
2015 };
2016
2017 if (vk_format_is_color(format)) {
2018 if (radv_can_fast_clear_color(cmd_buffer, &iview,
2019 image_layout, &clear_rect,
2020 clear_att.clearValue.color, 0)) {
2021 radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
2022 clear_att.colorAttachment,
2023 NULL, NULL);
2024 return true;
2025 }
2026 } else {
2027 if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
2028 range->aspectMask, &clear_rect,
2029 clear_att.clearValue.depthStencil, 0)) {
2030 radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
2031 NULL, NULL);
2032 return true;
2033 }
2034 }
2035
2036 return false;
2037 }
2038
2039 static void
2040 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
2041 struct radv_image *image,
2042 VkImageLayout image_layout,
2043 const VkClearValue *clear_value,
2044 uint32_t range_count,
2045 const VkImageSubresourceRange *ranges,
2046 bool cs)
2047 {
2048 VkFormat format = image->vk_format;
2049 VkClearValue internal_clear_value = *clear_value;
2050
2051 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
2052 uint32_t value;
2053 format = VK_FORMAT_R32_UINT;
2054 value = float3_to_rgb9e5(clear_value->color.float32);
2055 internal_clear_value.color.uint32[0] = value;
2056 }
2057
2058 if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
2059 uint8_t r, g;
2060 format = VK_FORMAT_R8_UINT;
2061 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
2062 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
2063 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
2064 }
2065
2066 if (format == VK_FORMAT_R32G32B32_UINT ||
2067 format == VK_FORMAT_R32G32B32_SINT ||
2068 format == VK_FORMAT_R32G32B32_SFLOAT)
2069 cs = true;
2070
2071 for (uint32_t r = 0; r < range_count; r++) {
2072 const VkImageSubresourceRange *range = &ranges[r];
2073
2074 /* Try to perform a fast clear first, otherwise fallback to
2075 * the legacy path.
2076 */
2077 if (!cs &&
2078 radv_fast_clear_range(cmd_buffer, image, format,
2079 image_layout, range,
2080 &internal_clear_value)) {
2081 continue;
2082 }
2083
2084 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
2085 const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
2086 radv_minify(image->info.depth, range->baseMipLevel + l) :
2087 radv_get_layerCount(image, range);
2088 for (uint32_t s = 0; s < layer_count; ++s) {
2089
2090 if (cs) {
2091 struct radv_meta_blit2d_surf surf;
2092 surf.format = format;
2093 surf.image = image;
2094 surf.level = range->baseMipLevel + l;
2095 surf.layer = range->baseArrayLayer + s;
2096 surf.aspect_mask = range->aspectMask;
2097 radv_meta_clear_image_cs(cmd_buffer, &surf,
2098 &internal_clear_value.color);
2099 } else {
2100 radv_clear_image_layer(cmd_buffer, image, image_layout,
2101 range, format, l, s, &internal_clear_value);
2102 }
2103 }
2104 }
2105 }
2106 }
2107
2108 void radv_CmdClearColorImage(
2109 VkCommandBuffer commandBuffer,
2110 VkImage image_h,
2111 VkImageLayout imageLayout,
2112 const VkClearColorValue* pColor,
2113 uint32_t rangeCount,
2114 const VkImageSubresourceRange* pRanges)
2115 {
2116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2117 RADV_FROM_HANDLE(radv_image, image, image_h);
2118 struct radv_meta_saved_state saved_state;
2119 bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
2120
2121 if (cs) {
2122 radv_meta_save(&saved_state, cmd_buffer,
2123 RADV_META_SAVE_COMPUTE_PIPELINE |
2124 RADV_META_SAVE_CONSTANTS |
2125 RADV_META_SAVE_DESCRIPTORS);
2126 } else {
2127 radv_meta_save(&saved_state, cmd_buffer,
2128 RADV_META_SAVE_GRAPHICS_PIPELINE |
2129 RADV_META_SAVE_CONSTANTS);
2130 }
2131
2132 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2133 (const VkClearValue *) pColor,
2134 rangeCount, pRanges, cs);
2135
2136 radv_meta_restore(&saved_state, cmd_buffer);
2137 }
2138
2139 void radv_CmdClearDepthStencilImage(
2140 VkCommandBuffer commandBuffer,
2141 VkImage image_h,
2142 VkImageLayout imageLayout,
2143 const VkClearDepthStencilValue* pDepthStencil,
2144 uint32_t rangeCount,
2145 const VkImageSubresourceRange* pRanges)
2146 {
2147 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2148 RADV_FROM_HANDLE(radv_image, image, image_h);
2149 struct radv_meta_saved_state saved_state;
2150
2151 radv_meta_save(&saved_state, cmd_buffer,
2152 RADV_META_SAVE_GRAPHICS_PIPELINE |
2153 RADV_META_SAVE_CONSTANTS);
2154
2155 radv_cmd_clear_image(cmd_buffer, image, imageLayout,
2156 (const VkClearValue *) pDepthStencil,
2157 rangeCount, pRanges, false);
2158
2159 radv_meta_restore(&saved_state, cmd_buffer);
2160 }
2161
2162 void radv_CmdClearAttachments(
2163 VkCommandBuffer commandBuffer,
2164 uint32_t attachmentCount,
2165 const VkClearAttachment* pAttachments,
2166 uint32_t rectCount,
2167 const VkClearRect* pRects)
2168 {
2169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2170 struct radv_meta_saved_state saved_state;
2171 enum radv_cmd_flush_bits pre_flush = 0;
2172 enum radv_cmd_flush_bits post_flush = 0;
2173
2174 if (!cmd_buffer->state.subpass)
2175 return;
2176
2177 radv_meta_save(&saved_state, cmd_buffer,
2178 RADV_META_SAVE_GRAPHICS_PIPELINE |
2179 RADV_META_SAVE_CONSTANTS);
2180
2181 /* FINISHME: We can do better than this dumb loop. It thrashes too much
2182 * state.
2183 */
2184 for (uint32_t a = 0; a < attachmentCount; ++a) {
2185 for (uint32_t r = 0; r < rectCount; ++r) {
2186 emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
2187 cmd_buffer->state.subpass->view_mask, false);
2188 }
2189 }
2190
2191 radv_meta_restore(&saved_state, cmd_buffer);
2192 cmd_buffer->state.flush_bits |= post_flush;
2193 }