854b88a3622edaabdad9792286ce464965379337
[mesa.git] / src / amd / vulkan / radv_meta_decompress.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "radv_meta.h"
28 #include "radv_private.h"
29 #include "nir/nir_builder.h"
30 #include "sid.h"
31 /**
32 * Vertex attributes used by all pipelines.
33 */
34 struct vertex_attrs {
35 float position[2]; /**< 3DPRIM_RECTLIST */
36 };
37
38 /* passthrough vertex shader */
39 static nir_shader *
40 build_nir_vs(void)
41 {
42 const struct glsl_type *vec4 = glsl_vec4_type();
43
44 nir_builder b;
45 nir_variable *a_position;
46 nir_variable *v_position;
47
48 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
49 b.shader->info->name = ralloc_strdup(b.shader, "meta_depth_decomp_vs");
50
51 a_position = nir_variable_create(b.shader, nir_var_shader_in, vec4,
52 "a_position");
53 a_position->data.location = VERT_ATTRIB_GENERIC0;
54
55 v_position = nir_variable_create(b.shader, nir_var_shader_out, vec4,
56 "gl_Position");
57 v_position->data.location = VARYING_SLOT_POS;
58
59 nir_copy_var(&b, v_position, a_position);
60
61 return b.shader;
62 }
63
64 /* simple passthrough shader */
65 static nir_shader *
66 build_nir_fs(void)
67 {
68 nir_builder b;
69
70 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
71 b.shader->info->name = ralloc_asprintf(b.shader,
72 "meta_depth_decomp_noop_fs");
73
74 return b.shader;
75 }
76
77 static VkResult
78 create_pass(struct radv_device *device)
79 {
80 VkResult result;
81 VkDevice device_h = radv_device_to_handle(device);
82 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
83 VkAttachmentDescription attachment;
84
85 attachment.format = VK_FORMAT_UNDEFINED;
86 attachment.samples = 1;
87 attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
88 attachment.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
89 attachment.initialLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
90 attachment.finalLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
91
92 result = radv_CreateRenderPass(device_h,
93 &(VkRenderPassCreateInfo) {
94 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
95 .attachmentCount = 1,
96 .pAttachments = &attachment,
97 .subpassCount = 1,
98 .pSubpasses = &(VkSubpassDescription) {
99 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
100 .inputAttachmentCount = 0,
101 .colorAttachmentCount = 0,
102 .pColorAttachments = NULL,
103 .pResolveAttachments = NULL,
104 .pDepthStencilAttachment = &(VkAttachmentReference) {
105 .attachment = 0,
106 .layout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL,
107 },
108 .preserveAttachmentCount = 0,
109 .pPreserveAttachments = NULL,
110 },
111 .dependencyCount = 0,
112 },
113 alloc,
114 &device->meta_state.depth_decomp.pass);
115
116 return result;
117 }
118
119 static VkResult
120 create_pipeline(struct radv_device *device,
121 VkShaderModule vs_module_h)
122 {
123 VkResult result;
124 VkDevice device_h = radv_device_to_handle(device);
125
126 struct radv_shader_module fs_module = {
127 .nir = build_nir_fs(),
128 };
129
130 if (!fs_module.nir) {
131 /* XXX: Need more accurate error */
132 result = VK_ERROR_OUT_OF_HOST_MEMORY;
133 goto cleanup;
134 }
135
136 const VkGraphicsPipelineCreateInfo pipeline_create_info = {
137 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
138 .stageCount = 2,
139 .pStages = (VkPipelineShaderStageCreateInfo[]) {
140 {
141 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
142 .stage = VK_SHADER_STAGE_VERTEX_BIT,
143 .module = vs_module_h,
144 .pName = "main",
145 },
146 {
147 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
148 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
149 .module = radv_shader_module_to_handle(&fs_module),
150 .pName = "main",
151 },
152 },
153 .pVertexInputState = &(VkPipelineVertexInputStateCreateInfo) {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
155 .vertexBindingDescriptionCount = 1,
156 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
157 {
158 .binding = 0,
159 .stride = sizeof(struct vertex_attrs),
160 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
161 },
162 },
163 .vertexAttributeDescriptionCount = 1,
164 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
165 {
166 /* Position */
167 .location = 0,
168 .binding = 0,
169 .format = VK_FORMAT_R32G32_SFLOAT,
170 .offset = offsetof(struct vertex_attrs, position),
171 },
172 },
173 },
174 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
175 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
176 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
177 .primitiveRestartEnable = false,
178 },
179 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
180 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
181 .viewportCount = 1,
182 .scissorCount = 1,
183 },
184 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
185 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
186 .depthClampEnable = false,
187 .rasterizerDiscardEnable = false,
188 .polygonMode = VK_POLYGON_MODE_FILL,
189 .cullMode = VK_CULL_MODE_NONE,
190 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
191 },
192 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
193 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
194 .rasterizationSamples = 1,
195 .sampleShadingEnable = false,
196 .pSampleMask = NULL,
197 .alphaToCoverageEnable = false,
198 .alphaToOneEnable = false,
199 },
200 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
201 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
202 .logicOpEnable = false,
203 .attachmentCount = 0,
204 .pAttachments = NULL,
205 },
206 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
207 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
208 .depthTestEnable = false,
209 .depthWriteEnable = false,
210 .depthBoundsTestEnable = false,
211 .stencilTestEnable = false,
212 },
213 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
214 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
215 .dynamicStateCount = 2,
216 .pDynamicStates = (VkDynamicState[]) {
217 VK_DYNAMIC_STATE_VIEWPORT,
218 VK_DYNAMIC_STATE_SCISSOR,
219 },
220 },
221 .renderPass = device->meta_state.depth_decomp.pass,
222 .subpass = 0,
223 };
224
225 result = radv_graphics_pipeline_create(device_h,
226 radv_pipeline_cache_to_handle(&device->meta_state.cache),
227 &pipeline_create_info,
228 &(struct radv_graphics_pipeline_create_info) {
229 .use_rectlist = true,
230 .db_flush_depth_inplace = true,
231 .db_flush_stencil_inplace = true,
232 },
233 &device->meta_state.alloc,
234 &device->meta_state.depth_decomp.decompress_pipeline);
235 if (result != VK_SUCCESS)
236 goto cleanup;
237
238 result = radv_graphics_pipeline_create(device_h,
239 radv_pipeline_cache_to_handle(&device->meta_state.cache),
240 &pipeline_create_info,
241 &(struct radv_graphics_pipeline_create_info) {
242 .use_rectlist = true,
243 .db_flush_depth_inplace = true,
244 .db_flush_stencil_inplace = true,
245 .db_resummarize = true,
246 },
247 &device->meta_state.alloc,
248 &device->meta_state.depth_decomp.resummarize_pipeline);
249 if (result != VK_SUCCESS)
250 goto cleanup;
251
252 goto cleanup;
253
254 cleanup:
255 ralloc_free(fs_module.nir);
256 return result;
257 }
258
259 void
260 radv_device_finish_meta_depth_decomp_state(struct radv_device *device)
261 {
262 struct radv_meta_state *state = &device->meta_state;
263 VkDevice device_h = radv_device_to_handle(device);
264 VkRenderPass pass_h = device->meta_state.depth_decomp.pass;
265 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
266
267 if (pass_h)
268 radv_DestroyRenderPass(device_h, pass_h,
269 &device->meta_state.alloc);
270
271 VkPipeline pipeline_h = state->depth_decomp.decompress_pipeline;
272 if (pipeline_h) {
273 radv_DestroyPipeline(device_h, pipeline_h, alloc);
274 }
275 pipeline_h = state->depth_decomp.resummarize_pipeline;
276 if (pipeline_h) {
277 radv_DestroyPipeline(device_h, pipeline_h, alloc);
278 }
279 }
280
281 VkResult
282 radv_device_init_meta_depth_decomp_state(struct radv_device *device)
283 {
284 VkResult res = VK_SUCCESS;
285
286 zero(device->meta_state.depth_decomp);
287
288 struct radv_shader_module vs_module = { .nir = build_nir_vs() };
289 if (!vs_module.nir) {
290 /* XXX: Need more accurate error */
291 res = VK_ERROR_OUT_OF_HOST_MEMORY;
292 goto fail;
293 }
294
295 res = create_pass(device);
296 if (res != VK_SUCCESS)
297 goto fail;
298
299 VkShaderModule vs_module_h = radv_shader_module_to_handle(&vs_module);
300 res = create_pipeline(device, vs_module_h);
301 if (res != VK_SUCCESS)
302 goto fail;
303
304 goto cleanup;
305
306 fail:
307 radv_device_finish_meta_depth_decomp_state(device);
308
309 cleanup:
310 ralloc_free(vs_module.nir);
311
312 return res;
313 }
314
315 static void
316 emit_depth_decomp(struct radv_cmd_buffer *cmd_buffer,
317 const VkOffset2D *dest_offset,
318 const VkExtent2D *depth_decomp_extent,
319 VkPipeline pipeline_h)
320 {
321 struct radv_device *device = cmd_buffer->device;
322 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
323 uint32_t offset;
324 const struct vertex_attrs vertex_data[3] = {
325 {
326 .position = {
327 -1.0,
328 -1.0,
329 },
330 },
331 {
332 .position = {
333 -1.0,
334 1.0,
335 },
336 },
337 {
338 .position = {
339 1.0,
340 -1.0,
341 },
342 },
343 };
344
345 radv_cmd_buffer_upload_data(cmd_buffer, sizeof(vertex_data), 16, vertex_data, &offset);
346 struct radv_buffer vertex_buffer = {
347 .device = device,
348 .size = sizeof(vertex_data),
349 .bo = cmd_buffer->upload.upload_bo,
350 .offset = offset,
351 };
352
353 VkBuffer vertex_buffer_h = radv_buffer_to_handle(&vertex_buffer);
354
355 radv_CmdBindVertexBuffers(cmd_buffer_h,
356 /*firstBinding*/ 0,
357 /*bindingCount*/ 1,
358 (VkBuffer[]) { vertex_buffer_h },
359 (VkDeviceSize[]) { 0 });
360
361 RADV_FROM_HANDLE(radv_pipeline, pipeline, pipeline_h);
362
363 if (cmd_buffer->state.pipeline != pipeline) {
364 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
365 pipeline_h);
366 }
367
368 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
369 .x = dest_offset->x,
370 .y = dest_offset->y,
371 .width = depth_decomp_extent->width,
372 .height = depth_decomp_extent->height,
373 .minDepth = 0.0f,
374 .maxDepth = 1.0f
375 });
376
377 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
378 .offset = *dest_offset,
379 .extent = *depth_decomp_extent,
380 });
381
382 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
383 }
384
385
386 static void radv_process_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
387 struct radv_image *image,
388 VkImageSubresourceRange *subresourceRange,
389 VkPipeline pipeline_h)
390 {
391 struct radv_meta_saved_state saved_state;
392 struct radv_meta_saved_pass_state saved_pass_state;
393 VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
394 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
395 uint32_t width = radv_minify(image->extent.width,
396 subresourceRange->baseMipLevel);
397 uint32_t height = radv_minify(image->extent.height,
398 subresourceRange->baseMipLevel);
399
400 if (!image->surface.htile_size)
401 return;
402 radv_meta_save_pass(&saved_pass_state, cmd_buffer);
403
404 radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
405
406 for (uint32_t layer = 0; layer < radv_get_layerCount(image, subresourceRange); layer++) {
407 struct radv_image_view iview;
408
409 radv_image_view_init(&iview, cmd_buffer->device,
410 &(VkImageViewCreateInfo) {
411 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
412 .image = radv_image_to_handle(image),
413 .format = image->vk_format,
414 .subresourceRange = {
415 .aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT,
416 .baseMipLevel = subresourceRange->baseMipLevel,
417 .levelCount = 1,
418 .baseArrayLayer = subresourceRange->baseArrayLayer + layer,
419 .layerCount = 1,
420 },
421 },
422 cmd_buffer, VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
423
424
425 VkFramebuffer fb_h;
426 radv_CreateFramebuffer(device_h,
427 &(VkFramebufferCreateInfo) {
428 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
429 .attachmentCount = 1,
430 .pAttachments = (VkImageView[]) {
431 radv_image_view_to_handle(&iview)
432 },
433 .width = width,
434 .height = height,
435 .layers = 1
436 },
437 &cmd_buffer->pool->alloc,
438 &fb_h);
439
440 radv_CmdBeginRenderPass(cmd_buffer_h,
441 &(VkRenderPassBeginInfo) {
442 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
443 .renderPass = cmd_buffer->device->meta_state.depth_decomp.pass,
444 .framebuffer = fb_h,
445 .renderArea = {
446 .offset = {
447 0,
448 0,
449 },
450 .extent = {
451 width,
452 height,
453 }
454 },
455 .clearValueCount = 0,
456 .pClearValues = NULL,
457 },
458 VK_SUBPASS_CONTENTS_INLINE);
459
460 emit_depth_decomp(cmd_buffer, &(VkOffset2D){0, 0 }, &(VkExtent2D){width, height}, pipeline_h);
461 radv_CmdEndRenderPass(cmd_buffer_h);
462
463 radv_DestroyFramebuffer(device_h, fb_h,
464 &cmd_buffer->pool->alloc);
465 }
466 radv_meta_restore(&saved_state, cmd_buffer);
467 radv_meta_restore_pass(&saved_pass_state, cmd_buffer);
468 }
469
470 void radv_decompress_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
471 struct radv_image *image,
472 VkImageSubresourceRange *subresourceRange)
473 {
474 assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
475 radv_process_depth_image_inplace(cmd_buffer, image, subresourceRange,
476 cmd_buffer->device->meta_state.depth_decomp.decompress_pipeline);
477 }
478
479 void radv_resummarize_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
480 struct radv_image *image,
481 VkImageSubresourceRange *subresourceRange)
482 {
483 assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
484 radv_process_depth_image_inplace(cmd_buffer, image, subresourceRange,
485 cmd_buffer->device->meta_state.depth_decomp.resummarize_pipeline);
486 }