radv/meta: don't need vertex info for resolve shader.
[mesa.git] / src / amd / vulkan / radv_meta_resolve_fs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
48
49 nir_store_var(&b, pos_out, outvec, 0xf);
50 return b.shader;
51 }
52
53 static nir_shader *
54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
55 {
56 nir_builder b;
57 char name[64];
58 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
59 const struct glsl_type *vec4 = glsl_vec4_type();
60 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
61 false,
62 false,
63 GLSL_TYPE_FLOAT);
64
65 snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
66 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
67 b.shader->info.name = ralloc_strdup(b.shader, name);
68
69 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
70 sampler_type, "s_tex");
71 input_img->data.descriptor_set = 0;
72 input_img->data.binding = 0;
73
74 nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
75 fs_pos_in->data.location = VARYING_SLOT_POS;
76
77 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
78 vec4, "f_color");
79 color_out->data.location = FRAG_RESULT_DATA0;
80
81 nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
83 nir_intrinsic_set_base(src_offset, 0);
84 nir_intrinsic_set_range(src_offset, 8);
85 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
86 src_offset->num_components = 2;
87 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
88 nir_builder_instr_insert(&b, &src_offset->instr);
89
90 nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
91
92 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
93 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
94
95 radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb,samples,
96 input_img, color, img_coord);
97
98 nir_ssa_def *outval = nir_load_var(&b, color);
99 nir_store_var(&b, color_out, outval, 0xf);
100 return b.shader;
101 }
102
103
104 static VkResult
105 create_layout(struct radv_device *device)
106 {
107 VkResult result;
108 /*
109 * one descriptors for the image being sampled
110 */
111 VkDescriptorSetLayoutCreateInfo ds_create_info = {
112 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
113 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
114 .bindingCount = 1,
115 .pBindings = (VkDescriptorSetLayoutBinding[]) {
116 {
117 .binding = 0,
118 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
119 .descriptorCount = 1,
120 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
121 .pImmutableSamplers = NULL
122 },
123 }
124 };
125
126 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
127 &ds_create_info,
128 &device->meta_state.alloc,
129 &device->meta_state.resolve_fragment.ds_layout);
130 if (result != VK_SUCCESS)
131 goto fail;
132
133
134 VkPipelineLayoutCreateInfo pl_create_info = {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
136 .setLayoutCount = 1,
137 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
138 .pushConstantRangeCount = 1,
139 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
140 };
141
142 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
143 &pl_create_info,
144 &device->meta_state.alloc,
145 &device->meta_state.resolve_fragment.p_layout);
146 if (result != VK_SUCCESS)
147 goto fail;
148 return VK_SUCCESS;
149 fail:
150 return result;
151 }
152
153 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
155 .vertexBindingDescriptionCount = 0,
156 .vertexAttributeDescriptionCount = 0,
157 };
158
159 static VkFormat pipeline_formats[] = {
160 VK_FORMAT_R8G8B8A8_UNORM,
161 VK_FORMAT_R8G8B8A8_UINT,
162 VK_FORMAT_R8G8B8A8_SINT,
163 VK_FORMAT_R16G16B16A16_UNORM,
164 VK_FORMAT_R16G16B16A16_SNORM,
165 VK_FORMAT_R16G16B16A16_UINT,
166 VK_FORMAT_R16G16B16A16_SINT,
167 VK_FORMAT_R32_SFLOAT,
168 VK_FORMAT_R32G32_SFLOAT,
169 VK_FORMAT_R32G32B32A32_SFLOAT
170 };
171
172 static VkResult
173 create_resolve_pipeline(struct radv_device *device,
174 int samples_log2,
175 VkFormat format)
176 {
177 VkResult result;
178 bool is_integer = false, is_srgb = false;
179 uint32_t samples = 1 << samples_log2;
180 unsigned fs_key = radv_format_meta_fs_key(format);
181 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
182 vi_create_info = &normal_vi_create_info;
183 if (vk_format_is_int(format))
184 is_integer = true;
185 else if (vk_format_is_srgb(format))
186 is_srgb = true;
187
188 struct radv_shader_module fs = { .nir = NULL };
189 fs.nir = build_resolve_fragment_shader(device, is_integer, is_srgb, samples);
190 struct radv_shader_module vs = {
191 .nir = build_nir_vertex_shader(),
192 };
193
194 VkRenderPass *rp = is_srgb ?
195 &device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
196 &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
197
198 assert(!*rp);
199
200 VkPipeline *pipeline = is_srgb ?
201 &device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
202 &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
203 assert(!*pipeline);
204
205 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
206 {
207 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
208 .stage = VK_SHADER_STAGE_VERTEX_BIT,
209 .module = radv_shader_module_to_handle(&vs),
210 .pName = "main",
211 .pSpecializationInfo = NULL
212 }, {
213 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
214 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
215 .module = radv_shader_module_to_handle(&fs),
216 .pName = "main",
217 .pSpecializationInfo = NULL
218 },
219 };
220
221
222 result = radv_CreateRenderPass(radv_device_to_handle(device),
223 &(VkRenderPassCreateInfo) {
224 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
225 .attachmentCount = 1,
226 .pAttachments = &(VkAttachmentDescription) {
227 .format = format,
228 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
229 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
230 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
231 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
232 },
233 .subpassCount = 1,
234 .pSubpasses = &(VkSubpassDescription) {
235 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
236 .inputAttachmentCount = 0,
237 .colorAttachmentCount = 1,
238 .pColorAttachments = &(VkAttachmentReference) {
239 .attachment = 0,
240 .layout = VK_IMAGE_LAYOUT_GENERAL,
241 },
242 .pResolveAttachments = NULL,
243 .pDepthStencilAttachment = &(VkAttachmentReference) {
244 .attachment = VK_ATTACHMENT_UNUSED,
245 .layout = VK_IMAGE_LAYOUT_GENERAL,
246 },
247 .preserveAttachmentCount = 1,
248 .pPreserveAttachments = (uint32_t[]) { 0 },
249 },
250 .dependencyCount = 0,
251 }, &device->meta_state.alloc, rp);
252
253
254 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
255 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
256 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
257 .pStages = pipeline_shader_stages,
258 .pVertexInputState = vi_create_info,
259 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
260 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
261 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
262 .primitiveRestartEnable = false,
263 },
264 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
265 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
266 .viewportCount = 1,
267 .scissorCount = 1,
268 },
269 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
271 .rasterizerDiscardEnable = false,
272 .polygonMode = VK_POLYGON_MODE_FILL,
273 .cullMode = VK_CULL_MODE_NONE,
274 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
275 },
276 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
277 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
278 .rasterizationSamples = 1,
279 .sampleShadingEnable = false,
280 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
281 },
282 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
283 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
284 .attachmentCount = 1,
285 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
286 { .colorWriteMask =
287 VK_COLOR_COMPONENT_A_BIT |
288 VK_COLOR_COMPONENT_R_BIT |
289 VK_COLOR_COMPONENT_G_BIT |
290 VK_COLOR_COMPONENT_B_BIT },
291 }
292 },
293 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
294 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
295 .dynamicStateCount = 9,
296 .pDynamicStates = (VkDynamicState[]) {
297 VK_DYNAMIC_STATE_VIEWPORT,
298 VK_DYNAMIC_STATE_SCISSOR,
299 VK_DYNAMIC_STATE_LINE_WIDTH,
300 VK_DYNAMIC_STATE_DEPTH_BIAS,
301 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
302 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
303 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
304 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
305 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
306 },
307 },
308 .flags = 0,
309 .layout = device->meta_state.resolve_fragment.p_layout,
310 .renderPass = *rp,
311 .subpass = 0,
312 };
313
314 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
315 .use_rectlist = true
316 };
317
318 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
319 radv_pipeline_cache_to_handle(&device->meta_state.cache),
320 &vk_pipeline_info, &radv_pipeline_info,
321 &device->meta_state.alloc,
322 pipeline);
323
324 ralloc_free(vs.nir);
325 ralloc_free(fs.nir);
326 if (result != VK_SUCCESS)
327 goto fail;
328
329 return VK_SUCCESS;
330 fail:
331 ralloc_free(vs.nir);
332 ralloc_free(fs.nir);
333 return result;
334 }
335
336 VkResult
337 radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
338 {
339 struct radv_meta_state *state = &device->meta_state;
340 VkResult res;
341 memset(&state->resolve_fragment, 0, sizeof(state->resolve_fragment));
342
343 res = create_layout(device);
344 if (res != VK_SUCCESS)
345 return res;
346
347 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
348 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
349 res = create_resolve_pipeline(device, i, pipeline_formats[j]);
350 }
351
352 res = create_resolve_pipeline(device, i, VK_FORMAT_R8G8B8A8_SRGB);
353 }
354
355 return res;
356 }
357
358 void
359 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
360 {
361 struct radv_meta_state *state = &device->meta_state;
362 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
363 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
364 radv_DestroyRenderPass(radv_device_to_handle(device),
365 state->resolve_fragment.rc[i].render_pass[j],
366 &state->alloc);
367 radv_DestroyPipeline(radv_device_to_handle(device),
368 state->resolve_fragment.rc[i].pipeline[j],
369 &state->alloc);
370 }
371 radv_DestroyRenderPass(radv_device_to_handle(device),
372 state->resolve_fragment.rc[i].srgb_render_pass,
373 &state->alloc);
374 radv_DestroyPipeline(radv_device_to_handle(device),
375 state->resolve_fragment.rc[i].srgb_pipeline,
376 &state->alloc);
377 }
378
379 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
380 state->resolve_fragment.ds_layout,
381 &state->alloc);
382 radv_DestroyPipelineLayout(radv_device_to_handle(device),
383 state->resolve_fragment.p_layout,
384 &state->alloc);
385 }
386
387 static void
388 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
389 struct radv_image_view *src_iview,
390 struct radv_image_view *dest_iview,
391 const VkOffset2D *src_offset,
392 const VkOffset2D *dest_offset,
393 const VkExtent2D *resolve_extent)
394 {
395 struct radv_device *device = cmd_buffer->device;
396 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
397 const uint32_t samples = src_iview->image->info.samples;
398 const uint32_t samples_log2 = ffs(samples) - 1;
399 radv_meta_push_descriptor_set(cmd_buffer,
400 VK_PIPELINE_BIND_POINT_GRAPHICS,
401 cmd_buffer->device->meta_state.resolve_fragment.p_layout,
402 0, /* set */
403 1, /* descriptorWriteCount */
404 (VkWriteDescriptorSet[]) {
405 {
406 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
407 .dstBinding = 0,
408 .dstArrayElement = 0,
409 .descriptorCount = 1,
410 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
411 .pImageInfo = (VkDescriptorImageInfo[]) {
412 {
413 .sampler = VK_NULL_HANDLE,
414 .imageView = radv_image_view_to_handle(src_iview),
415 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
416 },
417 }
418 },
419 });
420
421 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
422
423 unsigned push_constants[2] = {
424 src_offset->x,
425 src_offset->y,
426 };
427 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
428 device->meta_state.resolve_fragment.p_layout,
429 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
430 push_constants);
431
432 unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
433 VkPipeline pipeline_h = vk_format_is_srgb(dest_iview->vk_format) ?
434 device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
435 device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
436
437 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
438 pipeline_h);
439
440 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
441 .x = dest_offset->x,
442 .y = dest_offset->y,
443 .width = resolve_extent->width,
444 .height = resolve_extent->height,
445 .minDepth = 0.0f,
446 .maxDepth = 1.0f
447 });
448
449 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
450 .offset = *dest_offset,
451 .extent = *resolve_extent,
452 });
453
454 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
455 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
456 }
457
458 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
459 struct radv_image *src_image,
460 VkImageLayout src_image_layout,
461 struct radv_image *dest_image,
462 VkImageLayout dest_image_layout,
463 uint32_t region_count,
464 const VkImageResolve *regions)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radv_meta_saved_state saved_state;
468 const uint32_t samples = src_image->info.samples;
469 const uint32_t samples_log2 = ffs(samples) - 1;
470 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
471 VkRenderPass rp;
472 for (uint32_t r = 0; r < region_count; ++r) {
473 const VkImageResolve *region = &regions[r];
474 const uint32_t src_base_layer =
475 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
476 &region->srcOffset);
477 VkImageSubresourceRange range;
478 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
479 range.baseMipLevel = region->srcSubresource.mipLevel;
480 range.levelCount = 1;
481 range.baseArrayLayer = src_base_layer;
482 range.layerCount = region->srcSubresource.layerCount;
483 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
484 }
485
486 rp = vk_format_is_srgb(dest_image->vk_format) ?
487 device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
488 device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
489 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
490
491 for (uint32_t r = 0; r < region_count; ++r) {
492 const VkImageResolve *region = &regions[r];
493
494 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
495 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
496 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
497
498 const uint32_t src_base_layer =
499 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
500 &region->srcOffset);
501
502 const uint32_t dest_base_layer =
503 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
504 &region->dstOffset);
505
506 const struct VkExtent3D extent =
507 radv_sanitize_image_extent(src_image->type, region->extent);
508 const struct VkOffset3D srcOffset =
509 radv_sanitize_image_offset(src_image->type, region->srcOffset);
510 const struct VkOffset3D dstOffset =
511 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
512
513 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
514 ++layer) {
515
516 struct radv_image_view src_iview;
517 radv_image_view_init(&src_iview, cmd_buffer->device,
518 &(VkImageViewCreateInfo) {
519 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
520 .image = radv_image_to_handle(src_image),
521 .viewType = radv_meta_get_view_type(src_image),
522 .format = src_image->vk_format,
523 .subresourceRange = {
524 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
525 .baseMipLevel = region->srcSubresource.mipLevel,
526 .levelCount = 1,
527 .baseArrayLayer = src_base_layer + layer,
528 .layerCount = 1,
529 },
530 });
531
532 struct radv_image_view dest_iview;
533 radv_image_view_init(&dest_iview, cmd_buffer->device,
534 &(VkImageViewCreateInfo) {
535 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
536 .image = radv_image_to_handle(dest_image),
537 .viewType = radv_meta_get_view_type(dest_image),
538 .format = dest_image->vk_format,
539 .subresourceRange = {
540 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
541 .baseMipLevel = region->dstSubresource.mipLevel,
542 .levelCount = 1,
543 .baseArrayLayer = dest_base_layer + layer,
544 .layerCount = 1,
545 },
546 });
547
548
549 VkFramebuffer fb;
550 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
551 &(VkFramebufferCreateInfo) {
552 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
553 .attachmentCount = 1,
554 .pAttachments = (VkImageView[]) {
555 radv_image_view_to_handle(&dest_iview),
556 },
557 .width = extent.width,
558 .height = extent.height,
559 .layers = 1
560 }, &cmd_buffer->pool->alloc, &fb);
561
562 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
563 &(VkRenderPassBeginInfo) {
564 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
565 .renderPass = rp,
566 .framebuffer = fb,
567 .renderArea = {
568 .offset = { dstOffset.x, dstOffset.y, },
569 .extent = { extent.width, extent.height },
570 },
571 .clearValueCount = 0,
572 .pClearValues = NULL,
573 }, VK_SUBPASS_CONTENTS_INLINE);
574
575
576
577 emit_resolve(cmd_buffer,
578 &src_iview,
579 &dest_iview,
580 &(VkOffset2D) { srcOffset.x, srcOffset.y },
581 &(VkOffset2D) { dstOffset.x, dstOffset.y },
582 &(VkExtent2D) { extent.width, extent.height });
583
584 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
585
586 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
587 }
588 }
589
590 radv_meta_restore(&saved_state, cmd_buffer);
591 }
592
593
594 /**
595 * Emit any needed resolves for the current subpass.
596 */
597 void
598 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
599 {
600 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
601 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
602 struct radv_meta_saved_state saved_state;
603
604 /* FINISHME(perf): Skip clears for resolve attachments.
605 *
606 * From the Vulkan 1.0 spec:
607 *
608 * If the first use of an attachment in a render pass is as a resolve
609 * attachment, then the loadOp is effectively ignored as the resolve is
610 * guaranteed to overwrite all pixels in the render area.
611 */
612
613 if (!subpass->has_resolve)
614 return;
615
616 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
617
618 for (uint32_t i = 0; i < subpass->color_count; ++i) {
619 VkAttachmentReference src_att = subpass->color_attachments[i];
620 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
621 struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
622 struct radv_image *dst_img = dest_iview->image;
623 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
624 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
625 continue;
626
627 if (dst_img->surface.dcc_size) {
628 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
629 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
630 }
631 {
632 VkImageSubresourceRange range;
633 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
634 range.baseMipLevel = 0;
635 range.levelCount = 1;
636 range.baseArrayLayer = 0;
637 range.layerCount = 1;
638 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
639 }
640
641 struct radv_subpass resolve_subpass = {
642 .color_count = 1,
643 .color_attachments = (VkAttachmentReference[]) { dest_att },
644 .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
645 };
646
647 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
648
649 /* Subpass resolves must respect the render area. We can ignore the
650 * render area here because vkCmdBeginRenderPass set the render area
651 * with 3DSTATE_DRAWING_RECTANGLE.
652 *
653 * XXX(chadv): Does the hardware really respect
654 * 3DSTATE_DRAWING_RECTANGLE when draing a 3DPRIM_RECTLIST?
655 */
656 emit_resolve(cmd_buffer,
657 src_iview,
658 dest_iview,
659 &(VkOffset2D) { 0, 0 },
660 &(VkOffset2D) { 0, 0 },
661 &(VkExtent2D) { fb->width, fb->height });
662 }
663
664 cmd_buffer->state.subpass = subpass;
665 radv_meta_restore(&saved_state, cmd_buffer);
666 }