radv/meta: add resolve pass using fragment/vertex shaders
[mesa.git] / src / amd / vulkan / radv_meta_resolve_fs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info->name = ralloc_strdup(b.shader, "meta_resolve_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
48
49 nir_store_var(&b, pos_out, outvec, 0xf);
50 return b.shader;
51 }
52
53 static nir_shader *
54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
55 {
56 nir_builder b;
57 char name[64];
58 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
59 const struct glsl_type *vec4 = glsl_vec4_type();
60 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
61 false,
62 false,
63 GLSL_TYPE_FLOAT);
64
65 snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
66 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
67 b.shader->info->name = ralloc_strdup(b.shader, name);
68
69 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
70 sampler_type, "s_tex");
71 input_img->data.descriptor_set = 0;
72 input_img->data.binding = 0;
73
74 nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
75 fs_pos_in->data.location = VARYING_SLOT_POS;
76
77 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
78 vec4, "f_color");
79 color_out->data.location = FRAG_RESULT_DATA0;
80
81 nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
83 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
84 src_offset->num_components = 2;
85 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
86 nir_builder_instr_insert(&b, &src_offset->instr);
87
88 nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
89
90 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
91 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
92
93 radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb,samples,
94 input_img, color, img_coord);
95
96 nir_ssa_def *outval = nir_load_var(&b, color);
97 nir_store_var(&b, color_out, outval, 0xf);
98 return b.shader;
99 }
100
101
102 static VkResult
103 create_layout(struct radv_device *device)
104 {
105 VkResult result;
106 /*
107 * one descriptors for the image being sampled
108 */
109 VkDescriptorSetLayoutCreateInfo ds_create_info = {
110 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
111 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
112 .bindingCount = 1,
113 .pBindings = (VkDescriptorSetLayoutBinding[]) {
114 {
115 .binding = 0,
116 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
117 .descriptorCount = 1,
118 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
119 .pImmutableSamplers = NULL
120 },
121 }
122 };
123
124 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
125 &ds_create_info,
126 &device->meta_state.alloc,
127 &device->meta_state.resolve_fragment.ds_layout);
128 if (result != VK_SUCCESS)
129 goto fail;
130
131
132 VkPipelineLayoutCreateInfo pl_create_info = {
133 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
134 .setLayoutCount = 1,
135 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
136 .pushConstantRangeCount = 1,
137 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
138 };
139
140 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
141 &pl_create_info,
142 &device->meta_state.alloc,
143 &device->meta_state.resolve_fragment.p_layout);
144 if (result != VK_SUCCESS)
145 goto fail;
146 return VK_SUCCESS;
147 fail:
148 return result;
149 }
150
151 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
152 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
153 .vertexBindingDescriptionCount = 1,
154 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
155 {
156 .binding = 0,
157 .stride = 2 * sizeof(float),
158 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
159 },
160 },
161 .vertexAttributeDescriptionCount = 1,
162 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
163 {
164 /* Texture Coordinate */
165 .location = 0,
166 .binding = 0,
167 .format = VK_FORMAT_R32G32_SFLOAT,
168 .offset = 0
169 },
170 },
171 };
172
173 static VkFormat pipeline_formats[] = {
174 VK_FORMAT_R8G8B8A8_UNORM,
175 VK_FORMAT_R8G8B8A8_UINT,
176 VK_FORMAT_R8G8B8A8_SINT,
177 VK_FORMAT_R8G8B8A8_SRGB,
178 VK_FORMAT_R16G16B16A16_UNORM,
179 VK_FORMAT_R16G16B16A16_SNORM,
180 VK_FORMAT_R16G16B16A16_UINT,
181 VK_FORMAT_R16G16B16A16_SINT,
182 VK_FORMAT_R32_SFLOAT,
183 VK_FORMAT_R32G32_SFLOAT,
184 VK_FORMAT_R32G32B32A32_SFLOAT
185 };
186
187 static VkResult
188 create_resolve_pipeline(struct radv_device *device,
189 int samples_log2,
190 VkFormat format)
191 {
192 VkResult result;
193 bool is_integer = false, is_srgb = false;
194 uint32_t samples = 1 << samples_log2;
195 unsigned fs_key = radv_format_meta_fs_key(format);
196 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
197 vi_create_info = &normal_vi_create_info;
198 if (vk_format_is_int(format))
199 is_integer = true;
200 else if (vk_format_is_srgb(format))
201 is_srgb = true;
202
203 struct radv_shader_module fs = { .nir = NULL };
204 fs.nir = build_resolve_fragment_shader(device, is_integer, is_srgb, samples);
205 struct radv_shader_module vs = {
206 .nir = build_nir_vertex_shader(),
207 };
208
209 /* compute shader */
210
211 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
212 {
213 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
214 .stage = VK_SHADER_STAGE_VERTEX_BIT,
215 .module = radv_shader_module_to_handle(&vs),
216 .pName = "main",
217 .pSpecializationInfo = NULL
218 }, {
219 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
220 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
221 .module = radv_shader_module_to_handle(&fs),
222 .pName = "main",
223 .pSpecializationInfo = NULL
224 },
225 };
226
227 result = radv_CreateRenderPass(radv_device_to_handle(device),
228 &(VkRenderPassCreateInfo) {
229 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
230 .attachmentCount = 1,
231 .pAttachments = &(VkAttachmentDescription) {
232 .format = format,
233 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
234 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
235 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
236 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
237 },
238 .subpassCount = 1,
239 .pSubpasses = &(VkSubpassDescription) {
240 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
241 .inputAttachmentCount = 0,
242 .colorAttachmentCount = 1,
243 .pColorAttachments = &(VkAttachmentReference) {
244 .attachment = 0,
245 .layout = VK_IMAGE_LAYOUT_GENERAL,
246 },
247 .pResolveAttachments = NULL,
248 .pDepthStencilAttachment = &(VkAttachmentReference) {
249 .attachment = VK_ATTACHMENT_UNUSED,
250 .layout = VK_IMAGE_LAYOUT_GENERAL,
251 },
252 .preserveAttachmentCount = 1,
253 .pPreserveAttachments = (uint32_t[]) { 0 },
254 },
255 .dependencyCount = 0,
256 }, &device->meta_state.alloc, &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key]);
257
258
259 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
260 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
261 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
262 .pStages = pipeline_shader_stages,
263 .pVertexInputState = vi_create_info,
264 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
265 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
266 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
267 .primitiveRestartEnable = false,
268 },
269 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
270 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
271 .viewportCount = 1,
272 .scissorCount = 1,
273 },
274 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
275 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
276 .rasterizerDiscardEnable = false,
277 .polygonMode = VK_POLYGON_MODE_FILL,
278 .cullMode = VK_CULL_MODE_NONE,
279 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
280 },
281 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
282 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
283 .rasterizationSamples = 1,
284 .sampleShadingEnable = false,
285 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
286 },
287 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
288 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
289 .attachmentCount = 1,
290 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
291 { .colorWriteMask =
292 VK_COLOR_COMPONENT_A_BIT |
293 VK_COLOR_COMPONENT_R_BIT |
294 VK_COLOR_COMPONENT_G_BIT |
295 VK_COLOR_COMPONENT_B_BIT },
296 }
297 },
298 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
299 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
300 .dynamicStateCount = 9,
301 .pDynamicStates = (VkDynamicState[]) {
302 VK_DYNAMIC_STATE_VIEWPORT,
303 VK_DYNAMIC_STATE_SCISSOR,
304 VK_DYNAMIC_STATE_LINE_WIDTH,
305 VK_DYNAMIC_STATE_DEPTH_BIAS,
306 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
307 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
308 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
309 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
310 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
311 },
312 },
313 .flags = 0,
314 .layout = device->meta_state.resolve_fragment.p_layout,
315 .renderPass = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key],
316 .subpass = 0,
317 };
318
319 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
320 .use_rectlist = true
321 };
322
323 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
324 radv_pipeline_cache_to_handle(&device->meta_state.cache),
325 &vk_pipeline_info, &radv_pipeline_info,
326 &device->meta_state.alloc,
327 &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key]);
328
329
330 ralloc_free(vs.nir);
331 ralloc_free(fs.nir);
332 if (result != VK_SUCCESS)
333 goto fail;
334
335 return VK_SUCCESS;
336 fail:
337 ralloc_free(vs.nir);
338 ralloc_free(fs.nir);
339 return result;
340 }
341
342 VkResult
343 radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
344 {
345 struct radv_meta_state *state = &device->meta_state;
346 VkResult res;
347 memset(&state->resolve_fragment, 0, sizeof(state->resolve_fragment));
348
349 res = create_layout(device);
350 if (res != VK_SUCCESS)
351 return res;
352
353 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
354 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
355 res = create_resolve_pipeline(device, i, pipeline_formats[j]);
356 }
357 }
358
359 return res;
360 }
361
362 void
363 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
364 {
365 struct radv_meta_state *state = &device->meta_state;
366 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
367 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
368 radv_DestroyRenderPass(radv_device_to_handle(device),
369 state->resolve_fragment.rc[i].render_pass[j],
370 &state->alloc);
371 radv_DestroyPipeline(radv_device_to_handle(device),
372 state->resolve_fragment.rc[i].pipeline[j],
373 &state->alloc);
374 }
375
376 }
377
378 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
379 state->resolve_fragment.ds_layout,
380 &state->alloc);
381 radv_DestroyPipelineLayout(radv_device_to_handle(device),
382 state->resolve_fragment.p_layout,
383 &state->alloc);
384 }
385
386 static void
387 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
388 struct radv_image_view *src_iview,
389 const VkOffset2D *src_offset,
390 const VkOffset2D *dest_offset,
391 const VkExtent2D *resolve_extent)
392 {
393 struct radv_device *device = cmd_buffer->device;
394 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
395 const uint32_t samples = src_iview->image->info.samples;
396 const uint32_t samples_log2 = ffs(samples) - 1;
397 radv_meta_push_descriptor_set(cmd_buffer,
398 VK_PIPELINE_BIND_POINT_GRAPHICS,
399 cmd_buffer->device->meta_state.resolve_fragment.p_layout,
400 0, /* set */
401 1, /* descriptorWriteCount */
402 (VkWriteDescriptorSet[]) {
403 {
404 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
405 .dstBinding = 0,
406 .dstArrayElement = 0,
407 .descriptorCount = 1,
408 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
409 .pImageInfo = (VkDescriptorImageInfo[]) {
410 {
411 .sampler = VK_NULL_HANDLE,
412 .imageView = radv_image_view_to_handle(src_iview),
413 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
414 },
415 }
416 },
417 });
418
419 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
420
421 unsigned push_constants[2] = {
422 src_offset->x,
423 src_offset->y,
424 };
425 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
426 device->meta_state.resolve_fragment.p_layout,
427 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
428 push_constants);
429
430 unsigned fs_key = radv_format_meta_fs_key(src_iview->vk_format);
431 VkPipeline pipeline_h = device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
432
433 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
434 pipeline_h);
435
436 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
437 .x = dest_offset->x,
438 .y = dest_offset->y,
439 .width = resolve_extent->width,
440 .height = resolve_extent->height,
441 .minDepth = 0.0f,
442 .maxDepth = 1.0f
443 });
444
445 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
446 .offset = *dest_offset,
447 .extent = *resolve_extent,
448 });
449
450 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
451 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
452 }
453
454 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
455 struct radv_image *src_image,
456 VkImageLayout src_image_layout,
457 struct radv_image *dest_image,
458 VkImageLayout dest_image_layout,
459 uint32_t region_count,
460 const VkImageResolve *regions)
461 {
462 struct radv_device *device = cmd_buffer->device;
463 struct radv_meta_saved_state saved_state;
464 const uint32_t samples = src_image->info.samples;
465 const uint32_t samples_log2 = ffs(samples) - 1;
466 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
467 for (uint32_t r = 0; r < region_count; ++r) {
468 const VkImageResolve *region = &regions[r];
469 const uint32_t src_base_layer =
470 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
471 &region->srcOffset);
472 VkImageSubresourceRange range;
473 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
474 range.baseMipLevel = region->srcSubresource.mipLevel;
475 range.levelCount = 1;
476 range.baseArrayLayer = src_base_layer;
477 range.layerCount = region->srcSubresource.layerCount;
478 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
479 }
480
481 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
482
483 for (uint32_t r = 0; r < region_count; ++r) {
484 const VkImageResolve *region = &regions[r];
485
486 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
487 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
488 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
489
490 const uint32_t src_base_layer =
491 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
492 &region->srcOffset);
493
494 const uint32_t dest_base_layer =
495 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
496 &region->dstOffset);
497
498 const struct VkExtent3D extent =
499 radv_sanitize_image_extent(src_image->type, region->extent);
500 const struct VkOffset3D srcOffset =
501 radv_sanitize_image_offset(src_image->type, region->srcOffset);
502 const struct VkOffset3D dstOffset =
503 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
504
505 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
506 ++layer) {
507
508 struct radv_image_view src_iview;
509 radv_image_view_init(&src_iview, cmd_buffer->device,
510 &(VkImageViewCreateInfo) {
511 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
512 .image = radv_image_to_handle(src_image),
513 .viewType = radv_meta_get_view_type(src_image),
514 .format = src_image->vk_format,
515 .subresourceRange = {
516 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
517 .baseMipLevel = region->srcSubresource.mipLevel,
518 .levelCount = 1,
519 .baseArrayLayer = src_base_layer + layer,
520 .layerCount = 1,
521 },
522 },
523 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
524
525 struct radv_image_view dest_iview;
526 radv_image_view_init(&dest_iview, cmd_buffer->device,
527 &(VkImageViewCreateInfo) {
528 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
529 .image = radv_image_to_handle(dest_image),
530 .viewType = radv_meta_get_view_type(dest_image),
531 .format = dest_image->vk_format,
532 .subresourceRange = {
533 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
534 .baseMipLevel = region->dstSubresource.mipLevel,
535 .levelCount = 1,
536 .baseArrayLayer = dest_base_layer + layer,
537 .layerCount = 1,
538 },
539 },
540 cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
541
542
543 VkFramebuffer fb;
544 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
545 &(VkFramebufferCreateInfo) {
546 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
547 .attachmentCount = 1,
548 .pAttachments = (VkImageView[]) {
549 radv_image_view_to_handle(&dest_iview),
550 },
551 .width = extent.width,
552 .height = extent.height,
553 .layers = 1
554 }, &cmd_buffer->pool->alloc, &fb);
555
556 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
557 &(VkRenderPassBeginInfo) {
558 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
559 .renderPass = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key],
560 .framebuffer = fb,
561 .renderArea = {
562 .offset = { dstOffset.x, dstOffset.y, },
563 .extent = { extent.width, extent.height },
564 },
565 .clearValueCount = 0,
566 .pClearValues = NULL,
567 }, VK_SUBPASS_CONTENTS_INLINE);
568
569
570
571 emit_resolve(cmd_buffer,
572 &src_iview,
573 &(VkOffset2D) { srcOffset.x, srcOffset.y },
574 &(VkOffset2D) { dstOffset.x, dstOffset.y },
575 &(VkExtent2D) { extent.width, extent.height });
576
577 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
578
579 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
580 }
581 }
582
583 radv_meta_restore(&saved_state, cmd_buffer);
584 }
585
586
587 /**
588 * Emit any needed resolves for the current subpass.
589 */
590 void
591 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
592 {
593 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
594 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
595 struct radv_meta_saved_state saved_state;
596
597 /* FINISHME(perf): Skip clears for resolve attachments.
598 *
599 * From the Vulkan 1.0 spec:
600 *
601 * If the first use of an attachment in a render pass is as a resolve
602 * attachment, then the loadOp is effectively ignored as the resolve is
603 * guaranteed to overwrite all pixels in the render area.
604 */
605
606 if (!subpass->has_resolve)
607 return;
608
609 radv_meta_save_graphics_reset_vport_scissor(&saved_state, cmd_buffer);
610
611 for (uint32_t i = 0; i < subpass->color_count; ++i) {
612 VkAttachmentReference src_att = subpass->color_attachments[i];
613 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
614 struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
615 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
616 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
617 continue;
618
619 if (dst_img->surface.dcc_size) {
620 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
621 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
622 }
623 {
624 VkImageSubresourceRange range;
625 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
626 range.baseMipLevel = 0;
627 range.levelCount = 1;
628 range.baseArrayLayer = 0;
629 range.layerCount = 1;
630 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
631 }
632
633 struct radv_subpass resolve_subpass = {
634 .color_count = 1,
635 .color_attachments = (VkAttachmentReference[]) { dest_att },
636 .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
637 };
638
639 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
640
641 /* Subpass resolves must respect the render area. We can ignore the
642 * render area here because vkCmdBeginRenderPass set the render area
643 * with 3DSTATE_DRAWING_RECTANGLE.
644 *
645 * XXX(chadv): Does the hardware really respect
646 * 3DSTATE_DRAWING_RECTANGLE when draing a 3DPRIM_RECTLIST?
647 */
648 emit_resolve(cmd_buffer,
649 src_iview,
650 &(VkOffset2D) { 0, 0 },
651 &(VkOffset2D) { 0, 0 },
652 &(VkExtent2D) { fb->width, fb->height });
653 }
654
655 cmd_buffer->state.subpass = subpass;
656 radv_meta_restore(&saved_state, cmd_buffer);
657 }