nir: Embed the shader_info in the nir_shader again
[mesa.git] / src / amd / vulkan / radv_meta_resolve_fs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
48
49 nir_store_var(&b, pos_out, outvec, 0xf);
50 return b.shader;
51 }
52
53 static nir_shader *
54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
55 {
56 nir_builder b;
57 char name[64];
58 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
59 const struct glsl_type *vec4 = glsl_vec4_type();
60 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
61 false,
62 false,
63 GLSL_TYPE_FLOAT);
64
65 snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
66 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
67 b.shader->info.name = ralloc_strdup(b.shader, name);
68
69 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
70 sampler_type, "s_tex");
71 input_img->data.descriptor_set = 0;
72 input_img->data.binding = 0;
73
74 nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
75 fs_pos_in->data.location = VARYING_SLOT_POS;
76
77 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
78 vec4, "f_color");
79 color_out->data.location = FRAG_RESULT_DATA0;
80
81 nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
83 nir_intrinsic_set_base(src_offset, 0);
84 nir_intrinsic_set_range(src_offset, 8);
85 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
86 src_offset->num_components = 2;
87 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
88 nir_builder_instr_insert(&b, &src_offset->instr);
89
90 nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
91
92 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
93 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
94
95 radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb,samples,
96 input_img, color, img_coord);
97
98 nir_ssa_def *outval = nir_load_var(&b, color);
99 nir_store_var(&b, color_out, outval, 0xf);
100 return b.shader;
101 }
102
103
104 static VkResult
105 create_layout(struct radv_device *device)
106 {
107 VkResult result;
108 /*
109 * one descriptors for the image being sampled
110 */
111 VkDescriptorSetLayoutCreateInfo ds_create_info = {
112 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
113 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
114 .bindingCount = 1,
115 .pBindings = (VkDescriptorSetLayoutBinding[]) {
116 {
117 .binding = 0,
118 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
119 .descriptorCount = 1,
120 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
121 .pImmutableSamplers = NULL
122 },
123 }
124 };
125
126 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
127 &ds_create_info,
128 &device->meta_state.alloc,
129 &device->meta_state.resolve_fragment.ds_layout);
130 if (result != VK_SUCCESS)
131 goto fail;
132
133
134 VkPipelineLayoutCreateInfo pl_create_info = {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
136 .setLayoutCount = 1,
137 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
138 .pushConstantRangeCount = 1,
139 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
140 };
141
142 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
143 &pl_create_info,
144 &device->meta_state.alloc,
145 &device->meta_state.resolve_fragment.p_layout);
146 if (result != VK_SUCCESS)
147 goto fail;
148 return VK_SUCCESS;
149 fail:
150 return result;
151 }
152
153 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
155 .vertexBindingDescriptionCount = 1,
156 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
157 {
158 .binding = 0,
159 .stride = 2 * sizeof(float),
160 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
161 },
162 },
163 .vertexAttributeDescriptionCount = 1,
164 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
165 {
166 /* Texture Coordinate */
167 .location = 0,
168 .binding = 0,
169 .format = VK_FORMAT_R32G32_SFLOAT,
170 .offset = 0
171 },
172 },
173 };
174
175 static VkFormat pipeline_formats[] = {
176 VK_FORMAT_R8G8B8A8_UNORM,
177 VK_FORMAT_R8G8B8A8_UINT,
178 VK_FORMAT_R8G8B8A8_SINT,
179 VK_FORMAT_R8G8B8A8_SRGB,
180 VK_FORMAT_R16G16B16A16_UNORM,
181 VK_FORMAT_R16G16B16A16_SNORM,
182 VK_FORMAT_R16G16B16A16_UINT,
183 VK_FORMAT_R16G16B16A16_SINT,
184 VK_FORMAT_R32_SFLOAT,
185 VK_FORMAT_R32G32_SFLOAT,
186 VK_FORMAT_R32G32B32A32_SFLOAT
187 };
188
189 static VkResult
190 create_resolve_pipeline(struct radv_device *device,
191 int samples_log2,
192 VkFormat format)
193 {
194 VkResult result;
195 bool is_integer = false, is_srgb = false;
196 uint32_t samples = 1 << samples_log2;
197 unsigned fs_key = radv_format_meta_fs_key(format);
198 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
199 vi_create_info = &normal_vi_create_info;
200 if (vk_format_is_int(format))
201 is_integer = true;
202 else if (vk_format_is_srgb(format))
203 is_srgb = true;
204
205 struct radv_shader_module fs = { .nir = NULL };
206 fs.nir = build_resolve_fragment_shader(device, is_integer, is_srgb, samples);
207 struct radv_shader_module vs = {
208 .nir = build_nir_vertex_shader(),
209 };
210
211 /* compute shader */
212
213 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
214 {
215 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
216 .stage = VK_SHADER_STAGE_VERTEX_BIT,
217 .module = radv_shader_module_to_handle(&vs),
218 .pName = "main",
219 .pSpecializationInfo = NULL
220 }, {
221 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
222 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
223 .module = radv_shader_module_to_handle(&fs),
224 .pName = "main",
225 .pSpecializationInfo = NULL
226 },
227 };
228
229 result = radv_CreateRenderPass(radv_device_to_handle(device),
230 &(VkRenderPassCreateInfo) {
231 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
232 .attachmentCount = 1,
233 .pAttachments = &(VkAttachmentDescription) {
234 .format = format,
235 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
236 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
237 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
238 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
239 },
240 .subpassCount = 1,
241 .pSubpasses = &(VkSubpassDescription) {
242 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
243 .inputAttachmentCount = 0,
244 .colorAttachmentCount = 1,
245 .pColorAttachments = &(VkAttachmentReference) {
246 .attachment = 0,
247 .layout = VK_IMAGE_LAYOUT_GENERAL,
248 },
249 .pResolveAttachments = NULL,
250 .pDepthStencilAttachment = &(VkAttachmentReference) {
251 .attachment = VK_ATTACHMENT_UNUSED,
252 .layout = VK_IMAGE_LAYOUT_GENERAL,
253 },
254 .preserveAttachmentCount = 1,
255 .pPreserveAttachments = (uint32_t[]) { 0 },
256 },
257 .dependencyCount = 0,
258 }, &device->meta_state.alloc, &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key]);
259
260
261 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
262 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
263 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
264 .pStages = pipeline_shader_stages,
265 .pVertexInputState = vi_create_info,
266 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
267 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
268 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
269 .primitiveRestartEnable = false,
270 },
271 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
273 .viewportCount = 1,
274 .scissorCount = 1,
275 },
276 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
277 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
278 .rasterizerDiscardEnable = false,
279 .polygonMode = VK_POLYGON_MODE_FILL,
280 .cullMode = VK_CULL_MODE_NONE,
281 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
282 },
283 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
284 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
285 .rasterizationSamples = 1,
286 .sampleShadingEnable = false,
287 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
288 },
289 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
290 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
291 .attachmentCount = 1,
292 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
293 { .colorWriteMask =
294 VK_COLOR_COMPONENT_A_BIT |
295 VK_COLOR_COMPONENT_R_BIT |
296 VK_COLOR_COMPONENT_G_BIT |
297 VK_COLOR_COMPONENT_B_BIT },
298 }
299 },
300 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
301 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
302 .dynamicStateCount = 9,
303 .pDynamicStates = (VkDynamicState[]) {
304 VK_DYNAMIC_STATE_VIEWPORT,
305 VK_DYNAMIC_STATE_SCISSOR,
306 VK_DYNAMIC_STATE_LINE_WIDTH,
307 VK_DYNAMIC_STATE_DEPTH_BIAS,
308 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
309 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
310 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
311 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
312 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
313 },
314 },
315 .flags = 0,
316 .layout = device->meta_state.resolve_fragment.p_layout,
317 .renderPass = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key],
318 .subpass = 0,
319 };
320
321 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
322 .use_rectlist = true
323 };
324
325 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
326 radv_pipeline_cache_to_handle(&device->meta_state.cache),
327 &vk_pipeline_info, &radv_pipeline_info,
328 &device->meta_state.alloc,
329 &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key]);
330
331
332 ralloc_free(vs.nir);
333 ralloc_free(fs.nir);
334 if (result != VK_SUCCESS)
335 goto fail;
336
337 return VK_SUCCESS;
338 fail:
339 ralloc_free(vs.nir);
340 ralloc_free(fs.nir);
341 return result;
342 }
343
344 VkResult
345 radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
346 {
347 struct radv_meta_state *state = &device->meta_state;
348 VkResult res;
349 memset(&state->resolve_fragment, 0, sizeof(state->resolve_fragment));
350
351 res = create_layout(device);
352 if (res != VK_SUCCESS)
353 return res;
354
355 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
356 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
357 res = create_resolve_pipeline(device, i, pipeline_formats[j]);
358 }
359 }
360
361 return res;
362 }
363
364 void
365 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
366 {
367 struct radv_meta_state *state = &device->meta_state;
368 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
369 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
370 radv_DestroyRenderPass(radv_device_to_handle(device),
371 state->resolve_fragment.rc[i].render_pass[j],
372 &state->alloc);
373 radv_DestroyPipeline(radv_device_to_handle(device),
374 state->resolve_fragment.rc[i].pipeline[j],
375 &state->alloc);
376 }
377
378 }
379
380 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
381 state->resolve_fragment.ds_layout,
382 &state->alloc);
383 radv_DestroyPipelineLayout(radv_device_to_handle(device),
384 state->resolve_fragment.p_layout,
385 &state->alloc);
386 }
387
388 static void
389 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
390 struct radv_image_view *src_iview,
391 const VkOffset2D *src_offset,
392 const VkOffset2D *dest_offset,
393 const VkExtent2D *resolve_extent)
394 {
395 struct radv_device *device = cmd_buffer->device;
396 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
397 const uint32_t samples = src_iview->image->info.samples;
398 const uint32_t samples_log2 = ffs(samples) - 1;
399 radv_meta_push_descriptor_set(cmd_buffer,
400 VK_PIPELINE_BIND_POINT_GRAPHICS,
401 cmd_buffer->device->meta_state.resolve_fragment.p_layout,
402 0, /* set */
403 1, /* descriptorWriteCount */
404 (VkWriteDescriptorSet[]) {
405 {
406 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
407 .dstBinding = 0,
408 .dstArrayElement = 0,
409 .descriptorCount = 1,
410 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
411 .pImageInfo = (VkDescriptorImageInfo[]) {
412 {
413 .sampler = VK_NULL_HANDLE,
414 .imageView = radv_image_view_to_handle(src_iview),
415 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
416 },
417 }
418 },
419 });
420
421 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
422
423 unsigned push_constants[2] = {
424 src_offset->x,
425 src_offset->y,
426 };
427 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
428 device->meta_state.resolve_fragment.p_layout,
429 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
430 push_constants);
431
432 unsigned fs_key = radv_format_meta_fs_key(src_iview->vk_format);
433 VkPipeline pipeline_h = device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
434
435 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
436 pipeline_h);
437
438 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
439 .x = dest_offset->x,
440 .y = dest_offset->y,
441 .width = resolve_extent->width,
442 .height = resolve_extent->height,
443 .minDepth = 0.0f,
444 .maxDepth = 1.0f
445 });
446
447 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
448 .offset = *dest_offset,
449 .extent = *resolve_extent,
450 });
451
452 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
453 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
454 }
455
456 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
457 struct radv_image *src_image,
458 VkImageLayout src_image_layout,
459 struct radv_image *dest_image,
460 VkImageLayout dest_image_layout,
461 uint32_t region_count,
462 const VkImageResolve *regions)
463 {
464 struct radv_device *device = cmd_buffer->device;
465 struct radv_meta_saved_state saved_state;
466 const uint32_t samples = src_image->info.samples;
467 const uint32_t samples_log2 = ffs(samples) - 1;
468 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
469 for (uint32_t r = 0; r < region_count; ++r) {
470 const VkImageResolve *region = &regions[r];
471 const uint32_t src_base_layer =
472 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
473 &region->srcOffset);
474 VkImageSubresourceRange range;
475 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
476 range.baseMipLevel = region->srcSubresource.mipLevel;
477 range.levelCount = 1;
478 range.baseArrayLayer = src_base_layer;
479 range.layerCount = region->srcSubresource.layerCount;
480 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
481 }
482
483 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
484
485 for (uint32_t r = 0; r < region_count; ++r) {
486 const VkImageResolve *region = &regions[r];
487
488 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
489 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
490 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
491
492 const uint32_t src_base_layer =
493 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
494 &region->srcOffset);
495
496 const uint32_t dest_base_layer =
497 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
498 &region->dstOffset);
499
500 const struct VkExtent3D extent =
501 radv_sanitize_image_extent(src_image->type, region->extent);
502 const struct VkOffset3D srcOffset =
503 radv_sanitize_image_offset(src_image->type, region->srcOffset);
504 const struct VkOffset3D dstOffset =
505 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
506
507 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
508 ++layer) {
509
510 struct radv_image_view src_iview;
511 radv_image_view_init(&src_iview, cmd_buffer->device,
512 &(VkImageViewCreateInfo) {
513 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
514 .image = radv_image_to_handle(src_image),
515 .viewType = radv_meta_get_view_type(src_image),
516 .format = src_image->vk_format,
517 .subresourceRange = {
518 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
519 .baseMipLevel = region->srcSubresource.mipLevel,
520 .levelCount = 1,
521 .baseArrayLayer = src_base_layer + layer,
522 .layerCount = 1,
523 },
524 },
525 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
526
527 struct radv_image_view dest_iview;
528 radv_image_view_init(&dest_iview, cmd_buffer->device,
529 &(VkImageViewCreateInfo) {
530 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
531 .image = radv_image_to_handle(dest_image),
532 .viewType = radv_meta_get_view_type(dest_image),
533 .format = dest_image->vk_format,
534 .subresourceRange = {
535 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
536 .baseMipLevel = region->dstSubresource.mipLevel,
537 .levelCount = 1,
538 .baseArrayLayer = dest_base_layer + layer,
539 .layerCount = 1,
540 },
541 },
542 cmd_buffer, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
543
544
545 VkFramebuffer fb;
546 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
547 &(VkFramebufferCreateInfo) {
548 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
549 .attachmentCount = 1,
550 .pAttachments = (VkImageView[]) {
551 radv_image_view_to_handle(&dest_iview),
552 },
553 .width = extent.width,
554 .height = extent.height,
555 .layers = 1
556 }, &cmd_buffer->pool->alloc, &fb);
557
558 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
559 &(VkRenderPassBeginInfo) {
560 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
561 .renderPass = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key],
562 .framebuffer = fb,
563 .renderArea = {
564 .offset = { dstOffset.x, dstOffset.y, },
565 .extent = { extent.width, extent.height },
566 },
567 .clearValueCount = 0,
568 .pClearValues = NULL,
569 }, VK_SUBPASS_CONTENTS_INLINE);
570
571
572
573 emit_resolve(cmd_buffer,
574 &src_iview,
575 &(VkOffset2D) { srcOffset.x, srcOffset.y },
576 &(VkOffset2D) { dstOffset.x, dstOffset.y },
577 &(VkExtent2D) { extent.width, extent.height });
578
579 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
580
581 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
582 }
583 }
584
585 radv_meta_restore(&saved_state, cmd_buffer);
586 }
587
588
589 /**
590 * Emit any needed resolves for the current subpass.
591 */
592 void
593 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
594 {
595 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
596 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
597 struct radv_meta_saved_state saved_state;
598
599 /* FINISHME(perf): Skip clears for resolve attachments.
600 *
601 * From the Vulkan 1.0 spec:
602 *
603 * If the first use of an attachment in a render pass is as a resolve
604 * attachment, then the loadOp is effectively ignored as the resolve is
605 * guaranteed to overwrite all pixels in the render area.
606 */
607
608 if (!subpass->has_resolve)
609 return;
610
611 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
612
613 for (uint32_t i = 0; i < subpass->color_count; ++i) {
614 VkAttachmentReference src_att = subpass->color_attachments[i];
615 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
616 struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
617 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
618 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
619 continue;
620
621 if (dst_img->surface.dcc_size) {
622 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
623 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
624 }
625 {
626 VkImageSubresourceRange range;
627 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
628 range.baseMipLevel = 0;
629 range.levelCount = 1;
630 range.baseArrayLayer = 0;
631 range.layerCount = 1;
632 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
633 }
634
635 struct radv_subpass resolve_subpass = {
636 .color_count = 1,
637 .color_attachments = (VkAttachmentReference[]) { dest_att },
638 .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
639 };
640
641 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
642
643 /* Subpass resolves must respect the render area. We can ignore the
644 * render area here because vkCmdBeginRenderPass set the render area
645 * with 3DSTATE_DRAWING_RECTANGLE.
646 *
647 * XXX(chadv): Does the hardware really respect
648 * 3DSTATE_DRAWING_RECTANGLE when draing a 3DPRIM_RECTLIST?
649 */
650 emit_resolve(cmd_buffer,
651 src_iview,
652 &(VkOffset2D) { 0, 0 },
653 &(VkOffset2D) { 0, 0 },
654 &(VkExtent2D) { fb->width, fb->height });
655 }
656
657 cmd_buffer->state.subpass = subpass;
658 radv_meta_restore(&saved_state, cmd_buffer);
659 }