radv: handle 10-bit format clamping workaround.
[mesa.git] / src / amd / vulkan / radv_meta_resolve_fs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
48
49 nir_store_var(&b, pos_out, outvec, 0xf);
50 return b.shader;
51 }
52
53 static nir_shader *
54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
55 {
56 nir_builder b;
57 char name[64];
58 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
59 const struct glsl_type *vec4 = glsl_vec4_type();
60 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
61 false,
62 false,
63 GLSL_TYPE_FLOAT);
64
65 snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
66 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
67 b.shader->info.name = ralloc_strdup(b.shader, name);
68
69 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
70 sampler_type, "s_tex");
71 input_img->data.descriptor_set = 0;
72 input_img->data.binding = 0;
73
74 nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
75 fs_pos_in->data.location = VARYING_SLOT_POS;
76
77 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
78 vec4, "f_color");
79 color_out->data.location = FRAG_RESULT_DATA0;
80
81 nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
83 nir_intrinsic_set_base(src_offset, 0);
84 nir_intrinsic_set_range(src_offset, 8);
85 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
86 src_offset->num_components = 2;
87 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
88 nir_builder_instr_insert(&b, &src_offset->instr);
89
90 nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
91
92 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
93 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
94
95 radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb,samples,
96 input_img, color, img_coord);
97
98 nir_ssa_def *outval = nir_load_var(&b, color);
99 nir_store_var(&b, color_out, outval, 0xf);
100 return b.shader;
101 }
102
103
104 static VkResult
105 create_layout(struct radv_device *device)
106 {
107 VkResult result;
108 /*
109 * one descriptors for the image being sampled
110 */
111 VkDescriptorSetLayoutCreateInfo ds_create_info = {
112 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
113 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
114 .bindingCount = 1,
115 .pBindings = (VkDescriptorSetLayoutBinding[]) {
116 {
117 .binding = 0,
118 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
119 .descriptorCount = 1,
120 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
121 .pImmutableSamplers = NULL
122 },
123 }
124 };
125
126 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
127 &ds_create_info,
128 &device->meta_state.alloc,
129 &device->meta_state.resolve_fragment.ds_layout);
130 if (result != VK_SUCCESS)
131 goto fail;
132
133
134 VkPipelineLayoutCreateInfo pl_create_info = {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
136 .setLayoutCount = 1,
137 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
138 .pushConstantRangeCount = 1,
139 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
140 };
141
142 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
143 &pl_create_info,
144 &device->meta_state.alloc,
145 &device->meta_state.resolve_fragment.p_layout);
146 if (result != VK_SUCCESS)
147 goto fail;
148 return VK_SUCCESS;
149 fail:
150 return result;
151 }
152
153 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
155 .vertexBindingDescriptionCount = 0,
156 .vertexAttributeDescriptionCount = 0,
157 };
158
159 static VkFormat pipeline_formats[] = {
160 VK_FORMAT_R8G8B8A8_UNORM,
161 VK_FORMAT_R8G8B8A8_UINT,
162 VK_FORMAT_R8G8B8A8_SINT,
163 VK_FORMAT_A2R10G10B10_UINT_PACK32,
164 VK_FORMAT_A2R10G10B10_SINT_PACK32,
165 VK_FORMAT_R16G16B16A16_UNORM,
166 VK_FORMAT_R16G16B16A16_SNORM,
167 VK_FORMAT_R16G16B16A16_UINT,
168 VK_FORMAT_R16G16B16A16_SINT,
169 VK_FORMAT_R32_SFLOAT,
170 VK_FORMAT_R32G32_SFLOAT,
171 VK_FORMAT_R32G32B32A32_SFLOAT
172 };
173
174 static VkResult
175 create_resolve_pipeline(struct radv_device *device,
176 int samples_log2,
177 VkFormat format)
178 {
179 VkResult result;
180 bool is_integer = false, is_srgb = false;
181 uint32_t samples = 1 << samples_log2;
182 unsigned fs_key = radv_format_meta_fs_key(format);
183 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
184 vi_create_info = &normal_vi_create_info;
185 if (vk_format_is_int(format))
186 is_integer = true;
187 else if (vk_format_is_srgb(format))
188 is_srgb = true;
189
190 struct radv_shader_module fs = { .nir = NULL };
191 fs.nir = build_resolve_fragment_shader(device, is_integer, is_srgb, samples);
192 struct radv_shader_module vs = {
193 .nir = build_nir_vertex_shader(),
194 };
195
196 VkRenderPass *rp = is_srgb ?
197 &device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
198 &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
199
200 assert(!*rp);
201
202 VkPipeline *pipeline = is_srgb ?
203 &device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
204 &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
205 assert(!*pipeline);
206
207 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
208 {
209 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
210 .stage = VK_SHADER_STAGE_VERTEX_BIT,
211 .module = radv_shader_module_to_handle(&vs),
212 .pName = "main",
213 .pSpecializationInfo = NULL
214 }, {
215 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
216 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
217 .module = radv_shader_module_to_handle(&fs),
218 .pName = "main",
219 .pSpecializationInfo = NULL
220 },
221 };
222
223
224 result = radv_CreateRenderPass(radv_device_to_handle(device),
225 &(VkRenderPassCreateInfo) {
226 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
227 .attachmentCount = 1,
228 .pAttachments = &(VkAttachmentDescription) {
229 .format = format,
230 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
231 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
232 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
233 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
234 },
235 .subpassCount = 1,
236 .pSubpasses = &(VkSubpassDescription) {
237 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
238 .inputAttachmentCount = 0,
239 .colorAttachmentCount = 1,
240 .pColorAttachments = &(VkAttachmentReference) {
241 .attachment = 0,
242 .layout = VK_IMAGE_LAYOUT_GENERAL,
243 },
244 .pResolveAttachments = NULL,
245 .pDepthStencilAttachment = &(VkAttachmentReference) {
246 .attachment = VK_ATTACHMENT_UNUSED,
247 .layout = VK_IMAGE_LAYOUT_GENERAL,
248 },
249 .preserveAttachmentCount = 1,
250 .pPreserveAttachments = (uint32_t[]) { 0 },
251 },
252 .dependencyCount = 0,
253 }, &device->meta_state.alloc, rp);
254
255
256 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
257 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
258 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
259 .pStages = pipeline_shader_stages,
260 .pVertexInputState = vi_create_info,
261 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
262 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
263 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
264 .primitiveRestartEnable = false,
265 },
266 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
267 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
268 .viewportCount = 1,
269 .scissorCount = 1,
270 },
271 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
272 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
273 .rasterizerDiscardEnable = false,
274 .polygonMode = VK_POLYGON_MODE_FILL,
275 .cullMode = VK_CULL_MODE_NONE,
276 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
277 },
278 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
279 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
280 .rasterizationSamples = 1,
281 .sampleShadingEnable = false,
282 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
283 },
284 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
285 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
286 .attachmentCount = 1,
287 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
288 { .colorWriteMask =
289 VK_COLOR_COMPONENT_A_BIT |
290 VK_COLOR_COMPONENT_R_BIT |
291 VK_COLOR_COMPONENT_G_BIT |
292 VK_COLOR_COMPONENT_B_BIT },
293 }
294 },
295 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
296 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
297 .dynamicStateCount = 9,
298 .pDynamicStates = (VkDynamicState[]) {
299 VK_DYNAMIC_STATE_VIEWPORT,
300 VK_DYNAMIC_STATE_SCISSOR,
301 VK_DYNAMIC_STATE_LINE_WIDTH,
302 VK_DYNAMIC_STATE_DEPTH_BIAS,
303 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
304 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
305 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
306 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
307 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
308 },
309 },
310 .flags = 0,
311 .layout = device->meta_state.resolve_fragment.p_layout,
312 .renderPass = *rp,
313 .subpass = 0,
314 };
315
316 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
317 .use_rectlist = true
318 };
319
320 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
321 radv_pipeline_cache_to_handle(&device->meta_state.cache),
322 &vk_pipeline_info, &radv_pipeline_info,
323 &device->meta_state.alloc,
324 pipeline);
325
326 ralloc_free(vs.nir);
327 ralloc_free(fs.nir);
328 if (result != VK_SUCCESS)
329 goto fail;
330
331 return VK_SUCCESS;
332 fail:
333 ralloc_free(vs.nir);
334 ralloc_free(fs.nir);
335 return result;
336 }
337
338 VkResult
339 radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
340 {
341 struct radv_meta_state *state = &device->meta_state;
342 VkResult res;
343 memset(&state->resolve_fragment, 0, sizeof(state->resolve_fragment));
344
345 res = create_layout(device);
346 if (res != VK_SUCCESS)
347 return res;
348
349 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
350 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
351 res = create_resolve_pipeline(device, i, pipeline_formats[j]);
352 }
353
354 res = create_resolve_pipeline(device, i, VK_FORMAT_R8G8B8A8_SRGB);
355 }
356
357 return res;
358 }
359
360 void
361 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
362 {
363 struct radv_meta_state *state = &device->meta_state;
364 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
365 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
366 radv_DestroyRenderPass(radv_device_to_handle(device),
367 state->resolve_fragment.rc[i].render_pass[j],
368 &state->alloc);
369 radv_DestroyPipeline(radv_device_to_handle(device),
370 state->resolve_fragment.rc[i].pipeline[j],
371 &state->alloc);
372 }
373 radv_DestroyRenderPass(radv_device_to_handle(device),
374 state->resolve_fragment.rc[i].srgb_render_pass,
375 &state->alloc);
376 radv_DestroyPipeline(radv_device_to_handle(device),
377 state->resolve_fragment.rc[i].srgb_pipeline,
378 &state->alloc);
379 }
380
381 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
382 state->resolve_fragment.ds_layout,
383 &state->alloc);
384 radv_DestroyPipelineLayout(radv_device_to_handle(device),
385 state->resolve_fragment.p_layout,
386 &state->alloc);
387 }
388
389 static void
390 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
391 struct radv_image_view *src_iview,
392 struct radv_image_view *dest_iview,
393 const VkOffset2D *src_offset,
394 const VkOffset2D *dest_offset,
395 const VkExtent2D *resolve_extent)
396 {
397 struct radv_device *device = cmd_buffer->device;
398 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
399 const uint32_t samples = src_iview->image->info.samples;
400 const uint32_t samples_log2 = ffs(samples) - 1;
401 radv_meta_push_descriptor_set(cmd_buffer,
402 VK_PIPELINE_BIND_POINT_GRAPHICS,
403 cmd_buffer->device->meta_state.resolve_fragment.p_layout,
404 0, /* set */
405 1, /* descriptorWriteCount */
406 (VkWriteDescriptorSet[]) {
407 {
408 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
409 .dstBinding = 0,
410 .dstArrayElement = 0,
411 .descriptorCount = 1,
412 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
413 .pImageInfo = (VkDescriptorImageInfo[]) {
414 {
415 .sampler = VK_NULL_HANDLE,
416 .imageView = radv_image_view_to_handle(src_iview),
417 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
418 },
419 }
420 },
421 });
422
423 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
424
425 unsigned push_constants[2] = {
426 src_offset->x,
427 src_offset->y,
428 };
429 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
430 device->meta_state.resolve_fragment.p_layout,
431 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
432 push_constants);
433
434 unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
435 VkPipeline pipeline_h = vk_format_is_srgb(dest_iview->vk_format) ?
436 device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
437 device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
438
439 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
440 pipeline_h);
441
442 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
443 .x = dest_offset->x,
444 .y = dest_offset->y,
445 .width = resolve_extent->width,
446 .height = resolve_extent->height,
447 .minDepth = 0.0f,
448 .maxDepth = 1.0f
449 });
450
451 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
452 .offset = *dest_offset,
453 .extent = *resolve_extent,
454 });
455
456 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
457 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
458 }
459
460 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
461 struct radv_image *src_image,
462 VkImageLayout src_image_layout,
463 struct radv_image *dest_image,
464 VkImageLayout dest_image_layout,
465 uint32_t region_count,
466 const VkImageResolve *regions)
467 {
468 struct radv_device *device = cmd_buffer->device;
469 struct radv_meta_saved_state saved_state;
470 const uint32_t samples = src_image->info.samples;
471 const uint32_t samples_log2 = ffs(samples) - 1;
472 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
473 VkRenderPass rp;
474 for (uint32_t r = 0; r < region_count; ++r) {
475 const VkImageResolve *region = &regions[r];
476 const uint32_t src_base_layer =
477 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
478 &region->srcOffset);
479 VkImageSubresourceRange range;
480 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
481 range.baseMipLevel = region->srcSubresource.mipLevel;
482 range.levelCount = 1;
483 range.baseArrayLayer = src_base_layer;
484 range.layerCount = region->srcSubresource.layerCount;
485 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
486 }
487
488 rp = vk_format_is_srgb(dest_image->vk_format) ?
489 device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
490 device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
491 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
492
493 for (uint32_t r = 0; r < region_count; ++r) {
494 const VkImageResolve *region = &regions[r];
495
496 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
497 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
498 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
499
500 const uint32_t src_base_layer =
501 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
502 &region->srcOffset);
503
504 const uint32_t dest_base_layer =
505 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
506 &region->dstOffset);
507
508 const struct VkExtent3D extent =
509 radv_sanitize_image_extent(src_image->type, region->extent);
510 const struct VkOffset3D srcOffset =
511 radv_sanitize_image_offset(src_image->type, region->srcOffset);
512 const struct VkOffset3D dstOffset =
513 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
514
515 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
516 ++layer) {
517
518 struct radv_image_view src_iview;
519 radv_image_view_init(&src_iview, cmd_buffer->device,
520 &(VkImageViewCreateInfo) {
521 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
522 .image = radv_image_to_handle(src_image),
523 .viewType = radv_meta_get_view_type(src_image),
524 .format = src_image->vk_format,
525 .subresourceRange = {
526 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
527 .baseMipLevel = region->srcSubresource.mipLevel,
528 .levelCount = 1,
529 .baseArrayLayer = src_base_layer + layer,
530 .layerCount = 1,
531 },
532 });
533
534 struct radv_image_view dest_iview;
535 radv_image_view_init(&dest_iview, cmd_buffer->device,
536 &(VkImageViewCreateInfo) {
537 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
538 .image = radv_image_to_handle(dest_image),
539 .viewType = radv_meta_get_view_type(dest_image),
540 .format = dest_image->vk_format,
541 .subresourceRange = {
542 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
543 .baseMipLevel = region->dstSubresource.mipLevel,
544 .levelCount = 1,
545 .baseArrayLayer = dest_base_layer + layer,
546 .layerCount = 1,
547 },
548 });
549
550
551 VkFramebuffer fb;
552 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
553 &(VkFramebufferCreateInfo) {
554 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
555 .attachmentCount = 1,
556 .pAttachments = (VkImageView[]) {
557 radv_image_view_to_handle(&dest_iview),
558 },
559 .width = extent.width,
560 .height = extent.height,
561 .layers = 1
562 }, &cmd_buffer->pool->alloc, &fb);
563
564 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
565 &(VkRenderPassBeginInfo) {
566 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
567 .renderPass = rp,
568 .framebuffer = fb,
569 .renderArea = {
570 .offset = { dstOffset.x, dstOffset.y, },
571 .extent = { extent.width, extent.height },
572 },
573 .clearValueCount = 0,
574 .pClearValues = NULL,
575 }, VK_SUBPASS_CONTENTS_INLINE);
576
577
578
579 emit_resolve(cmd_buffer,
580 &src_iview,
581 &dest_iview,
582 &(VkOffset2D) { srcOffset.x, srcOffset.y },
583 &(VkOffset2D) { dstOffset.x, dstOffset.y },
584 &(VkExtent2D) { extent.width, extent.height });
585
586 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
587
588 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
589 }
590 }
591
592 radv_meta_restore(&saved_state, cmd_buffer);
593 }
594
595
596 /**
597 * Emit any needed resolves for the current subpass.
598 */
599 void
600 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
601 {
602 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
603 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
604 struct radv_meta_saved_state saved_state;
605
606 /* FINISHME(perf): Skip clears for resolve attachments.
607 *
608 * From the Vulkan 1.0 spec:
609 *
610 * If the first use of an attachment in a render pass is as a resolve
611 * attachment, then the loadOp is effectively ignored as the resolve is
612 * guaranteed to overwrite all pixels in the render area.
613 */
614
615 if (!subpass->has_resolve)
616 return;
617
618 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
619
620 for (uint32_t i = 0; i < subpass->color_count; ++i) {
621 VkAttachmentReference src_att = subpass->color_attachments[i];
622 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
623
624 if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
625 dest_att.attachment == VK_ATTACHMENT_UNUSED)
626 continue;
627
628 struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
629 struct radv_image *dst_img = dest_iview->image;
630 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
631
632 if (dst_img->surface.dcc_size) {
633 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
634 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
635 }
636 {
637 VkImageSubresourceRange range;
638 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
639 range.baseMipLevel = 0;
640 range.levelCount = 1;
641 range.baseArrayLayer = 0;
642 range.layerCount = 1;
643 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
644 }
645
646 struct radv_subpass resolve_subpass = {
647 .color_count = 1,
648 .color_attachments = (VkAttachmentReference[]) { dest_att },
649 .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
650 };
651
652 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
653
654 /* Subpass resolves must respect the render area. We can ignore the
655 * render area here because vkCmdBeginRenderPass set the render area
656 * with 3DSTATE_DRAWING_RECTANGLE.
657 *
658 * XXX(chadv): Does the hardware really respect
659 * 3DSTATE_DRAWING_RECTANGLE when draing a 3DPRIM_RECTLIST?
660 */
661 emit_resolve(cmd_buffer,
662 src_iview,
663 dest_iview,
664 &(VkOffset2D) { 0, 0 },
665 &(VkOffset2D) { 0, 0 },
666 &(VkExtent2D) { fb->width, fb->height });
667 }
668
669 cmd_buffer->state.subpass = subpass;
670 radv_meta_restore(&saved_state, cmd_buffer);
671 }