radv: Remove some intel comments from the resolve code.
[mesa.git] / src / amd / vulkan / radv_meta_resolve_fs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
48
49 nir_store_var(&b, pos_out, outvec, 0xf);
50 return b.shader;
51 }
52
53 static nir_shader *
54 build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples)
55 {
56 nir_builder b;
57 char name[64];
58 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
59 const struct glsl_type *vec4 = glsl_vec4_type();
60 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
61 false,
62 false,
63 GLSL_TYPE_FLOAT);
64
65 snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
66 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
67 b.shader->info.name = ralloc_strdup(b.shader, name);
68
69 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
70 sampler_type, "s_tex");
71 input_img->data.descriptor_set = 0;
72 input_img->data.binding = 0;
73
74 nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
75 fs_pos_in->data.location = VARYING_SLOT_POS;
76
77 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
78 vec4, "f_color");
79 color_out->data.location = FRAG_RESULT_DATA0;
80
81 nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
82 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
83 nir_intrinsic_set_base(src_offset, 0);
84 nir_intrinsic_set_range(src_offset, 8);
85 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
86 src_offset->num_components = 2;
87 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
88 nir_builder_instr_insert(&b, &src_offset->instr);
89
90 nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
91
92 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
93 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
94
95 radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
96 color, img_coord);
97
98 nir_ssa_def *outval = nir_load_var(&b, color);
99 nir_store_var(&b, color_out, outval, 0xf);
100 return b.shader;
101 }
102
103
104 static VkResult
105 create_layout(struct radv_device *device)
106 {
107 VkResult result;
108 /*
109 * one descriptors for the image being sampled
110 */
111 VkDescriptorSetLayoutCreateInfo ds_create_info = {
112 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
113 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
114 .bindingCount = 1,
115 .pBindings = (VkDescriptorSetLayoutBinding[]) {
116 {
117 .binding = 0,
118 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
119 .descriptorCount = 1,
120 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
121 .pImmutableSamplers = NULL
122 },
123 }
124 };
125
126 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
127 &ds_create_info,
128 &device->meta_state.alloc,
129 &device->meta_state.resolve_fragment.ds_layout);
130 if (result != VK_SUCCESS)
131 goto fail;
132
133
134 VkPipelineLayoutCreateInfo pl_create_info = {
135 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
136 .setLayoutCount = 1,
137 .pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
138 .pushConstantRangeCount = 1,
139 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
140 };
141
142 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
143 &pl_create_info,
144 &device->meta_state.alloc,
145 &device->meta_state.resolve_fragment.p_layout);
146 if (result != VK_SUCCESS)
147 goto fail;
148 return VK_SUCCESS;
149 fail:
150 return result;
151 }
152
153 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
154 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
155 .vertexBindingDescriptionCount = 0,
156 .vertexAttributeDescriptionCount = 0,
157 };
158
159 static VkFormat pipeline_formats[] = {
160 VK_FORMAT_R8G8B8A8_UNORM,
161 VK_FORMAT_R8G8B8A8_UINT,
162 VK_FORMAT_R8G8B8A8_SINT,
163 VK_FORMAT_A2R10G10B10_UINT_PACK32,
164 VK_FORMAT_A2R10G10B10_SINT_PACK32,
165 VK_FORMAT_R16G16B16A16_UNORM,
166 VK_FORMAT_R16G16B16A16_SNORM,
167 VK_FORMAT_R16G16B16A16_UINT,
168 VK_FORMAT_R16G16B16A16_SINT,
169 VK_FORMAT_R32_SFLOAT,
170 VK_FORMAT_R32G32_SFLOAT,
171 VK_FORMAT_R32G32B32A32_SFLOAT
172 };
173
174 static VkResult
175 create_resolve_pipeline(struct radv_device *device,
176 int samples_log2,
177 VkFormat format)
178 {
179 VkResult result;
180 bool is_integer = false;
181 uint32_t samples = 1 << samples_log2;
182 unsigned fs_key = radv_format_meta_fs_key(format);
183 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
184 vi_create_info = &normal_vi_create_info;
185 if (vk_format_is_int(format))
186 is_integer = true;
187
188 struct radv_shader_module fs = { .nir = NULL };
189 fs.nir = build_resolve_fragment_shader(device, is_integer, samples);
190 struct radv_shader_module vs = {
191 .nir = build_nir_vertex_shader(),
192 };
193
194 VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
195
196 assert(!*rp);
197
198 VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
199 assert(!*pipeline);
200
201 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
202 {
203 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
204 .stage = VK_SHADER_STAGE_VERTEX_BIT,
205 .module = radv_shader_module_to_handle(&vs),
206 .pName = "main",
207 .pSpecializationInfo = NULL
208 }, {
209 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
210 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
211 .module = radv_shader_module_to_handle(&fs),
212 .pName = "main",
213 .pSpecializationInfo = NULL
214 },
215 };
216
217
218 result = radv_CreateRenderPass(radv_device_to_handle(device),
219 &(VkRenderPassCreateInfo) {
220 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
221 .attachmentCount = 1,
222 .pAttachments = &(VkAttachmentDescription) {
223 .format = format,
224 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
225 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
226 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
227 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
228 },
229 .subpassCount = 1,
230 .pSubpasses = &(VkSubpassDescription) {
231 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
232 .inputAttachmentCount = 0,
233 .colorAttachmentCount = 1,
234 .pColorAttachments = &(VkAttachmentReference) {
235 .attachment = 0,
236 .layout = VK_IMAGE_LAYOUT_GENERAL,
237 },
238 .pResolveAttachments = NULL,
239 .pDepthStencilAttachment = &(VkAttachmentReference) {
240 .attachment = VK_ATTACHMENT_UNUSED,
241 .layout = VK_IMAGE_LAYOUT_GENERAL,
242 },
243 .preserveAttachmentCount = 1,
244 .pPreserveAttachments = (uint32_t[]) { 0 },
245 },
246 .dependencyCount = 0,
247 }, &device->meta_state.alloc, rp);
248
249
250 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
251 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
252 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
253 .pStages = pipeline_shader_stages,
254 .pVertexInputState = vi_create_info,
255 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
256 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
257 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
258 .primitiveRestartEnable = false,
259 },
260 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
261 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
262 .viewportCount = 1,
263 .scissorCount = 1,
264 },
265 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
266 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
267 .rasterizerDiscardEnable = false,
268 .polygonMode = VK_POLYGON_MODE_FILL,
269 .cullMode = VK_CULL_MODE_NONE,
270 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
271 },
272 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
273 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
274 .rasterizationSamples = 1,
275 .sampleShadingEnable = false,
276 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
277 },
278 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
279 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
280 .attachmentCount = 1,
281 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
282 { .colorWriteMask =
283 VK_COLOR_COMPONENT_A_BIT |
284 VK_COLOR_COMPONENT_R_BIT |
285 VK_COLOR_COMPONENT_G_BIT |
286 VK_COLOR_COMPONENT_B_BIT },
287 }
288 },
289 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
290 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
291 .dynamicStateCount = 9,
292 .pDynamicStates = (VkDynamicState[]) {
293 VK_DYNAMIC_STATE_VIEWPORT,
294 VK_DYNAMIC_STATE_SCISSOR,
295 VK_DYNAMIC_STATE_LINE_WIDTH,
296 VK_DYNAMIC_STATE_DEPTH_BIAS,
297 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
298 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
299 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
300 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
301 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
302 },
303 },
304 .flags = 0,
305 .layout = device->meta_state.resolve_fragment.p_layout,
306 .renderPass = *rp,
307 .subpass = 0,
308 };
309
310 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
311 .use_rectlist = true
312 };
313
314 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
315 radv_pipeline_cache_to_handle(&device->meta_state.cache),
316 &vk_pipeline_info, &radv_pipeline_info,
317 &device->meta_state.alloc,
318 pipeline);
319
320 ralloc_free(vs.nir);
321 ralloc_free(fs.nir);
322 if (result != VK_SUCCESS)
323 goto fail;
324
325 return VK_SUCCESS;
326 fail:
327 ralloc_free(vs.nir);
328 ralloc_free(fs.nir);
329 return result;
330 }
331
332 VkResult
333 radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
334 {
335 struct radv_meta_state *state = &device->meta_state;
336 VkResult res;
337 memset(&state->resolve_fragment, 0, sizeof(state->resolve_fragment));
338
339 res = create_layout(device);
340 if (res != VK_SUCCESS)
341 return res;
342
343 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
344 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
345 res = create_resolve_pipeline(device, i, pipeline_formats[j]);
346 }
347 }
348
349 return res;
350 }
351
352 void
353 radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
354 {
355 struct radv_meta_state *state = &device->meta_state;
356 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
357 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
358 radv_DestroyRenderPass(radv_device_to_handle(device),
359 state->resolve_fragment.rc[i].render_pass[j],
360 &state->alloc);
361 radv_DestroyPipeline(radv_device_to_handle(device),
362 state->resolve_fragment.rc[i].pipeline[j],
363 &state->alloc);
364 }
365 }
366
367 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
368 state->resolve_fragment.ds_layout,
369 &state->alloc);
370 radv_DestroyPipelineLayout(radv_device_to_handle(device),
371 state->resolve_fragment.p_layout,
372 &state->alloc);
373 }
374
375 static void
376 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
377 struct radv_image_view *src_iview,
378 struct radv_image_view *dest_iview,
379 const VkOffset2D *src_offset,
380 const VkOffset2D *dest_offset,
381 const VkExtent2D *resolve_extent)
382 {
383 struct radv_device *device = cmd_buffer->device;
384 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
385 const uint32_t samples = src_iview->image->info.samples;
386 const uint32_t samples_log2 = ffs(samples) - 1;
387 radv_meta_push_descriptor_set(cmd_buffer,
388 VK_PIPELINE_BIND_POINT_GRAPHICS,
389 cmd_buffer->device->meta_state.resolve_fragment.p_layout,
390 0, /* set */
391 1, /* descriptorWriteCount */
392 (VkWriteDescriptorSet[]) {
393 {
394 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
395 .dstBinding = 0,
396 .dstArrayElement = 0,
397 .descriptorCount = 1,
398 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
399 .pImageInfo = (VkDescriptorImageInfo[]) {
400 {
401 .sampler = VK_NULL_HANDLE,
402 .imageView = radv_image_view_to_handle(src_iview),
403 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
404 },
405 }
406 },
407 });
408
409 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
410
411 unsigned push_constants[2] = {
412 src_offset->x,
413 src_offset->y,
414 };
415 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
416 device->meta_state.resolve_fragment.p_layout,
417 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
418 push_constants);
419
420 unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
421 VkPipeline pipeline_h = device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
422
423 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
424 pipeline_h);
425
426 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
427 .x = dest_offset->x,
428 .y = dest_offset->y,
429 .width = resolve_extent->width,
430 .height = resolve_extent->height,
431 .minDepth = 0.0f,
432 .maxDepth = 1.0f
433 });
434
435 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
436 .offset = *dest_offset,
437 .extent = *resolve_extent,
438 });
439
440 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
441 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
442 }
443
444 void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
445 struct radv_image *src_image,
446 VkImageLayout src_image_layout,
447 struct radv_image *dest_image,
448 VkImageLayout dest_image_layout,
449 uint32_t region_count,
450 const VkImageResolve *regions)
451 {
452 struct radv_device *device = cmd_buffer->device;
453 struct radv_meta_saved_state saved_state;
454 const uint32_t samples = src_image->info.samples;
455 const uint32_t samples_log2 = ffs(samples) - 1;
456 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
457 VkRenderPass rp;
458 for (uint32_t r = 0; r < region_count; ++r) {
459 const VkImageResolve *region = &regions[r];
460 const uint32_t src_base_layer =
461 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
462 &region->srcOffset);
463 VkImageSubresourceRange range;
464 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
465 range.baseMipLevel = region->srcSubresource.mipLevel;
466 range.levelCount = 1;
467 range.baseArrayLayer = src_base_layer;
468 range.layerCount = region->srcSubresource.layerCount;
469 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
470 }
471
472 rp = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
473 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
474
475 for (uint32_t r = 0; r < region_count; ++r) {
476 const VkImageResolve *region = &regions[r];
477
478 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
479 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
480 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
481
482 const uint32_t src_base_layer =
483 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
484 &region->srcOffset);
485
486 const uint32_t dest_base_layer =
487 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
488 &region->dstOffset);
489
490 const struct VkExtent3D extent =
491 radv_sanitize_image_extent(src_image->type, region->extent);
492 const struct VkOffset3D srcOffset =
493 radv_sanitize_image_offset(src_image->type, region->srcOffset);
494 const struct VkOffset3D dstOffset =
495 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
496
497 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
498 ++layer) {
499
500 struct radv_image_view src_iview;
501 radv_image_view_init(&src_iview, cmd_buffer->device,
502 &(VkImageViewCreateInfo) {
503 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
504 .image = radv_image_to_handle(src_image),
505 .viewType = radv_meta_get_view_type(src_image),
506 .format = src_image->vk_format,
507 .subresourceRange = {
508 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
509 .baseMipLevel = region->srcSubresource.mipLevel,
510 .levelCount = 1,
511 .baseArrayLayer = src_base_layer + layer,
512 .layerCount = 1,
513 },
514 });
515
516 struct radv_image_view dest_iview;
517 radv_image_view_init(&dest_iview, cmd_buffer->device,
518 &(VkImageViewCreateInfo) {
519 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
520 .image = radv_image_to_handle(dest_image),
521 .viewType = radv_meta_get_view_type(dest_image),
522 .format = dest_image->vk_format,
523 .subresourceRange = {
524 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
525 .baseMipLevel = region->dstSubresource.mipLevel,
526 .levelCount = 1,
527 .baseArrayLayer = dest_base_layer + layer,
528 .layerCount = 1,
529 },
530 });
531
532
533 VkFramebuffer fb;
534 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
535 &(VkFramebufferCreateInfo) {
536 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
537 .attachmentCount = 1,
538 .pAttachments = (VkImageView[]) {
539 radv_image_view_to_handle(&dest_iview),
540 },
541 .width = extent.width,
542 .height = extent.height,
543 .layers = 1
544 }, &cmd_buffer->pool->alloc, &fb);
545
546 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
547 &(VkRenderPassBeginInfo) {
548 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
549 .renderPass = rp,
550 .framebuffer = fb,
551 .renderArea = {
552 .offset = { dstOffset.x, dstOffset.y, },
553 .extent = { extent.width, extent.height },
554 },
555 .clearValueCount = 0,
556 .pClearValues = NULL,
557 }, VK_SUBPASS_CONTENTS_INLINE);
558
559
560
561 emit_resolve(cmd_buffer,
562 &src_iview,
563 &dest_iview,
564 &(VkOffset2D) { srcOffset.x, srcOffset.y },
565 &(VkOffset2D) { dstOffset.x, dstOffset.y },
566 &(VkExtent2D) { extent.width, extent.height });
567
568 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
569
570 radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
571 }
572 }
573
574 radv_meta_restore(&saved_state, cmd_buffer);
575 }
576
577
578 /**
579 * Emit any needed resolves for the current subpass.
580 */
581 void
582 radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
583 {
584 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
585 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
586 struct radv_meta_saved_state saved_state;
587
588 /* FINISHME(perf): Skip clears for resolve attachments.
589 *
590 * From the Vulkan 1.0 spec:
591 *
592 * If the first use of an attachment in a render pass is as a resolve
593 * attachment, then the loadOp is effectively ignored as the resolve is
594 * guaranteed to overwrite all pixels in the render area.
595 */
596
597 if (!subpass->has_resolve)
598 return;
599
600 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
601
602 for (uint32_t i = 0; i < subpass->color_count; ++i) {
603 VkAttachmentReference src_att = subpass->color_attachments[i];
604 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
605
606 if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
607 dest_att.attachment == VK_ATTACHMENT_UNUSED)
608 continue;
609
610 struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
611 struct radv_image *dst_img = dest_iview->image;
612 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
613
614 if (dst_img->surface.dcc_size) {
615 radv_initialize_dcc(cmd_buffer, dst_img, 0xffffffff);
616 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
617 }
618 {
619 VkImageSubresourceRange range;
620 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
621 range.baseMipLevel = 0;
622 range.levelCount = 1;
623 range.baseArrayLayer = 0;
624 range.layerCount = 1;
625 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
626 }
627
628 struct radv_subpass resolve_subpass = {
629 .color_count = 1,
630 .color_attachments = (VkAttachmentReference[]) { dest_att },
631 .depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
632 };
633
634 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass, false);
635
636 emit_resolve(cmd_buffer,
637 src_iview,
638 dest_iview,
639 &(VkOffset2D) { 0, 0 },
640 &(VkOffset2D) { 0, 0 },
641 &(VkExtent2D) { fb->width, fb->height });
642 }
643
644 cmd_buffer->state.subpass = subpass;
645 radv_meta_restore(&saved_state, cmd_buffer);
646 }