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radv: simplify allocating user SGPRS for descriptor sets
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct radv_nir_compiler_options *options;
52 struct radv_shader_variant_info *shader_info;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 LLVMValueRef gs2vs_offset;
75 LLVMValueRef gs_wave_id;
76 LLVMValueRef gs_vtx_offset[6];
77
78 LLVMValueRef esgs_ring;
79 LLVMValueRef gsvs_ring[4];
80 LLVMValueRef hs_ring_tess_offchip;
81 LLVMValueRef hs_ring_tess_factor;
82
83 LLVMValueRef persp_sample, persp_center, persp_centroid;
84 LLVMValueRef linear_sample, linear_center, linear_centroid;
85
86 /* Streamout */
87 LLVMValueRef streamout_buffers;
88 LLVMValueRef streamout_write_idx;
89 LLVMValueRef streamout_config;
90 LLVMValueRef streamout_offset[4];
91
92 gl_shader_stage stage;
93
94 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
95
96 uint64_t input_mask;
97 uint64_t output_mask;
98
99 bool is_gs_copy_shader;
100 LLVMValueRef gs_next_vertex[4];
101 unsigned gs_max_out_vertices;
102
103 unsigned tes_primitive_mode;
104
105 uint32_t tcs_patch_outputs_read;
106 uint64_t tcs_outputs_read;
107 uint32_t tcs_vertices_per_patch;
108 uint32_t tcs_num_inputs;
109 uint32_t tcs_num_patches;
110 uint32_t max_gsvs_emit_size;
111 uint32_t gsvs_vertex_size;
112 };
113
114 enum radeon_llvm_calling_convention {
115 RADEON_LLVM_AMDGPU_VS = 87,
116 RADEON_LLVM_AMDGPU_GS = 88,
117 RADEON_LLVM_AMDGPU_PS = 89,
118 RADEON_LLVM_AMDGPU_CS = 90,
119 RADEON_LLVM_AMDGPU_HS = 93,
120 };
121
122 static inline struct radv_shader_context *
123 radv_shader_context_from_abi(struct ac_shader_abi *abi)
124 {
125 struct radv_shader_context *ctx = NULL;
126 return container_of(abi, ctx, abi);
127 }
128
129 struct ac_build_if_state
130 {
131 struct radv_shader_context *ctx;
132 LLVMValueRef condition;
133 LLVMBasicBlockRef entry_block;
134 LLVMBasicBlockRef true_block;
135 LLVMBasicBlockRef false_block;
136 LLVMBasicBlockRef merge_block;
137 };
138
139 static LLVMBasicBlockRef
140 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
141 {
142 LLVMBasicBlockRef current_block;
143 LLVMBasicBlockRef next_block;
144 LLVMBasicBlockRef new_block;
145
146 /* get current basic block */
147 current_block = LLVMGetInsertBlock(ctx->ac.builder);
148
149 /* chqeck if there's another block after this one */
150 next_block = LLVMGetNextBasicBlock(current_block);
151 if (next_block) {
152 /* insert the new block before the next block */
153 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
154 }
155 else {
156 /* append new block after current block */
157 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
158 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
159 }
160 return new_block;
161 }
162
163 static void
164 ac_nir_build_if(struct ac_build_if_state *ifthen,
165 struct radv_shader_context *ctx,
166 LLVMValueRef condition)
167 {
168 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
169
170 memset(ifthen, 0, sizeof *ifthen);
171 ifthen->ctx = ctx;
172 ifthen->condition = condition;
173 ifthen->entry_block = block;
174
175 /* create endif/merge basic block for the phi functions */
176 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
177
178 /* create/insert true_block before merge_block */
179 ifthen->true_block =
180 LLVMInsertBasicBlockInContext(ctx->context,
181 ifthen->merge_block,
182 "if-true-block");
183
184 /* successive code goes into the true block */
185 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
186 }
187
188 /**
189 * End a conditional.
190 */
191 static void
192 ac_nir_build_endif(struct ac_build_if_state *ifthen)
193 {
194 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
195
196 /* Insert branch to the merge block from current block */
197 LLVMBuildBr(builder, ifthen->merge_block);
198
199 /*
200 * Now patch in the various branch instructions.
201 */
202
203 /* Insert the conditional branch instruction at the end of entry_block */
204 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
205 if (ifthen->false_block) {
206 /* we have an else clause */
207 LLVMBuildCondBr(builder, ifthen->condition,
208 ifthen->true_block, ifthen->false_block);
209 }
210 else {
211 /* no else clause */
212 LLVMBuildCondBr(builder, ifthen->condition,
213 ifthen->true_block, ifthen->merge_block);
214 }
215
216 /* Resume building code at end of the ifthen->merge_block */
217 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
218 }
219
220
221 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
222 {
223 switch (ctx->stage) {
224 case MESA_SHADER_TESS_CTRL:
225 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
226 case MESA_SHADER_TESS_EVAL:
227 return ctx->tes_rel_patch_id;
228 break;
229 default:
230 unreachable("Illegal stage");
231 }
232 }
233
234 static unsigned
235 get_tcs_num_patches(struct radv_shader_context *ctx)
236 {
237 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
238 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
239 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
240 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
241 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
242 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
243 uint32_t output_vertex_size = num_tcs_outputs * 16;
244 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
245 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
246 unsigned num_patches;
247 unsigned hardware_lds_size;
248
249 /* Ensure that we only need one wave per SIMD so we don't need to check
250 * resource usage. Also ensures that the number of tcs in and out
251 * vertices per threadgroup are at most 256.
252 */
253 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
254 /* Make sure that the data fits in LDS. This assumes the shaders only
255 * use LDS for the inputs and outputs.
256 */
257 hardware_lds_size = 32768;
258
259 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
260 * threadgroup, even though there is more than 32 KiB LDS.
261 *
262 * Test: dEQP-VK.tessellation.shader_input_output.barrier
263 */
264 if (ctx->options->chip_class >= CIK && ctx->options->family != CHIP_STONEY)
265 hardware_lds_size = 65536;
266
267 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
268 /* Make sure the output data fits in the offchip buffer */
269 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
270 /* Not necessary for correctness, but improves performance. The
271 * specific value is taken from the proprietary driver.
272 */
273 num_patches = MIN2(num_patches, 40);
274
275 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
276 if (ctx->options->chip_class == SI) {
277 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
278 num_patches = MIN2(num_patches, one_wave);
279 }
280 return num_patches;
281 }
282
283 static unsigned
284 calculate_tess_lds_size(struct radv_shader_context *ctx)
285 {
286 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
287 unsigned num_tcs_output_cp;
288 unsigned num_tcs_outputs, num_tcs_patch_outputs;
289 unsigned input_vertex_size, output_vertex_size;
290 unsigned input_patch_size, output_patch_size;
291 unsigned pervertex_output_patch_size;
292 unsigned output_patch0_offset;
293 unsigned num_patches;
294 unsigned lds_size;
295
296 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
297 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
298 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
299
300 input_vertex_size = ctx->tcs_num_inputs * 16;
301 output_vertex_size = num_tcs_outputs * 16;
302
303 input_patch_size = num_tcs_input_cp * input_vertex_size;
304
305 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
306 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
307
308 num_patches = ctx->tcs_num_patches;
309 output_patch0_offset = input_patch_size * num_patches;
310
311 lds_size = output_patch0_offset + output_patch_size * num_patches;
312 return lds_size;
313 }
314
315 /* Tessellation shaders pass outputs to the next shader using LDS.
316 *
317 * LS outputs = TCS inputs
318 * TCS outputs = TES inputs
319 *
320 * The LDS layout is:
321 * - TCS inputs for patch 0
322 * - TCS inputs for patch 1
323 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
324 * - ...
325 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
326 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
327 * - TCS outputs for patch 1
328 * - Per-patch TCS outputs for patch 1
329 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
330 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
331 * - ...
332 *
333 * All three shaders VS(LS), TCS, TES share the same LDS space.
334 */
335 static LLVMValueRef
336 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
337 {
338 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
339 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
340 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
341
342 input_patch_size /= 4;
343 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
344 }
345
346 static LLVMValueRef
347 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
348 {
349 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
350 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
353 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
354 output_patch_size /= 4;
355 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
356 }
357
358 static LLVMValueRef
359 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
360 {
361 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
362 uint32_t output_vertex_size = num_tcs_outputs * 16;
363 output_vertex_size /= 4;
364 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
365 }
366
367 static LLVMValueRef
368 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
369 {
370 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
371 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
372 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
373 uint32_t output_patch0_offset = input_patch_size;
374 unsigned num_patches = ctx->tcs_num_patches;
375
376 output_patch0_offset *= num_patches;
377 output_patch0_offset /= 4;
378 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
379 }
380
381 static LLVMValueRef
382 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
383 {
384 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
385 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
386 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
387 uint32_t output_patch0_offset = input_patch_size;
388
389 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
390 uint32_t output_vertex_size = num_tcs_outputs * 16;
391 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
392 unsigned num_patches = ctx->tcs_num_patches;
393
394 output_patch0_offset *= num_patches;
395 output_patch0_offset += pervertex_output_patch_size;
396 output_patch0_offset /= 4;
397 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
398 }
399
400 static LLVMValueRef
401 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
402 {
403 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
404 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
405
406 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
407 }
408
409 static LLVMValueRef
410 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
411 {
412 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
413 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
414 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
415
416 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
417 patch0_offset);
418 }
419
420 static LLVMValueRef
421 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
422 {
423 LLVMValueRef patch0_patch_data_offset =
424 get_tcs_out_patch0_patch_data_offset(ctx);
425 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
426 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
427
428 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
429 patch0_patch_data_offset);
430 }
431
432 #define MAX_ARGS 64
433 struct arg_info {
434 LLVMTypeRef types[MAX_ARGS];
435 LLVMValueRef *assign[MAX_ARGS];
436 unsigned array_params_mask;
437 uint8_t count;
438 uint8_t sgpr_count;
439 uint8_t num_sgprs_used;
440 uint8_t num_vgprs_used;
441 };
442
443 enum ac_arg_regfile {
444 ARG_SGPR,
445 ARG_VGPR,
446 };
447
448 static void
449 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
450 LLVMValueRef *param_ptr)
451 {
452 assert(info->count < MAX_ARGS);
453
454 info->assign[info->count] = param_ptr;
455 info->types[info->count] = type;
456 info->count++;
457
458 if (regfile == ARG_SGPR) {
459 info->num_sgprs_used += ac_get_type_size(type) / 4;
460 info->sgpr_count++;
461 } else {
462 assert(regfile == ARG_VGPR);
463 info->num_vgprs_used += ac_get_type_size(type) / 4;
464 }
465 }
466
467 static inline void
468 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
469 {
470 info->array_params_mask |= (1 << info->count);
471 add_arg(info, ARG_SGPR, type, param_ptr);
472 }
473
474 static void assign_arguments(LLVMValueRef main_function,
475 struct arg_info *info)
476 {
477 unsigned i;
478 for (i = 0; i < info->count; i++) {
479 if (info->assign[i])
480 *info->assign[i] = LLVMGetParam(main_function, i);
481 }
482 }
483
484 static LLVMValueRef
485 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
486 LLVMBuilderRef builder, LLVMTypeRef *return_types,
487 unsigned num_return_elems,
488 struct arg_info *args,
489 unsigned max_workgroup_size,
490 const struct radv_nir_compiler_options *options)
491 {
492 LLVMTypeRef main_function_type, ret_type;
493 LLVMBasicBlockRef main_function_body;
494
495 if (num_return_elems)
496 ret_type = LLVMStructTypeInContext(ctx, return_types,
497 num_return_elems, true);
498 else
499 ret_type = LLVMVoidTypeInContext(ctx);
500
501 /* Setup the function */
502 main_function_type =
503 LLVMFunctionType(ret_type, args->types, args->count, 0);
504 LLVMValueRef main_function =
505 LLVMAddFunction(module, "main", main_function_type);
506 main_function_body =
507 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
508 LLVMPositionBuilderAtEnd(builder, main_function_body);
509
510 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
511 for (unsigned i = 0; i < args->sgpr_count; ++i) {
512 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
513
514 if (args->array_params_mask & (1 << i)) {
515 LLVMValueRef P = LLVMGetParam(main_function, i);
516 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
517 ac_add_attr_dereferenceable(P, UINT64_MAX);
518 }
519 }
520
521 if (options->address32_hi) {
522 ac_llvm_add_target_dep_function_attr(main_function,
523 "amdgpu-32bit-address-high-bits",
524 options->address32_hi);
525 }
526
527 if (max_workgroup_size) {
528 ac_llvm_add_target_dep_function_attr(main_function,
529 "amdgpu-max-work-group-size",
530 max_workgroup_size);
531 }
532 if (options->unsafe_math) {
533 /* These were copied from some LLVM test. */
534 LLVMAddTargetDependentFunctionAttr(main_function,
535 "less-precise-fpmad",
536 "true");
537 LLVMAddTargetDependentFunctionAttr(main_function,
538 "no-infs-fp-math",
539 "true");
540 LLVMAddTargetDependentFunctionAttr(main_function,
541 "no-nans-fp-math",
542 "true");
543 LLVMAddTargetDependentFunctionAttr(main_function,
544 "unsafe-fp-math",
545 "true");
546 LLVMAddTargetDependentFunctionAttr(main_function,
547 "no-signed-zeros-fp-math",
548 "true");
549 }
550 return main_function;
551 }
552
553
554 static void
555 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
556 uint8_t num_sgprs)
557 {
558 ud_info->sgpr_idx = *sgpr_idx;
559 ud_info->num_sgprs = num_sgprs;
560 *sgpr_idx += num_sgprs;
561 }
562
563 static void
564 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
565 uint8_t num_sgprs)
566 {
567 struct radv_userdata_info *ud_info =
568 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
569 assert(ud_info);
570
571 set_loc(ud_info, sgpr_idx, num_sgprs);
572 }
573
574 static void
575 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
576 {
577 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
578
579 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
580 }
581
582 static void
583 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
584 {
585 struct radv_userdata_locations *locs =
586 &ctx->shader_info->user_sgprs_locs;
587 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
588 assert(ud_info);
589
590 set_loc(ud_info, sgpr_idx, 1);
591
592 locs->descriptor_sets_enabled |= 1 << idx;
593 }
594
595 struct user_sgpr_info {
596 bool need_ring_offsets;
597 bool indirect_all_descriptor_sets;
598 };
599
600 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
601 gl_shader_stage stage)
602 {
603 switch (stage) {
604 case MESA_SHADER_VERTEX:
605 if (ctx->shader_info->info.needs_multiview_view_index ||
606 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
607 return true;
608 break;
609 case MESA_SHADER_TESS_EVAL:
610 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
611 return true;
612 break;
613 case MESA_SHADER_GEOMETRY:
614 case MESA_SHADER_TESS_CTRL:
615 if (ctx->shader_info->info.needs_multiview_view_index)
616 return true;
617 break;
618 default:
619 break;
620 }
621 return false;
622 }
623
624 static uint8_t
625 count_vs_user_sgprs(struct radv_shader_context *ctx)
626 {
627 uint8_t count = 0;
628
629 if (ctx->shader_info->info.vs.has_vertex_buffers)
630 count++;
631 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
632
633 return count;
634 }
635
636 static void allocate_user_sgprs(struct radv_shader_context *ctx,
637 gl_shader_stage stage,
638 bool has_previous_stage,
639 gl_shader_stage previous_stage,
640 bool needs_view_index,
641 struct user_sgpr_info *user_sgpr_info)
642 {
643 uint8_t user_sgpr_count = 0;
644
645 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
646
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (stage == MESA_SHADER_GEOMETRY ||
649 stage == MESA_SHADER_VERTEX ||
650 stage == MESA_SHADER_TESS_CTRL ||
651 stage == MESA_SHADER_TESS_EVAL ||
652 ctx->is_gs_copy_shader)
653 user_sgpr_info->need_ring_offsets = true;
654
655 if (stage == MESA_SHADER_FRAGMENT &&
656 ctx->shader_info->info.ps.needs_sample_positions)
657 user_sgpr_info->need_ring_offsets = true;
658
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
661 user_sgpr_count += 2;
662 }
663
664 switch (stage) {
665 case MESA_SHADER_COMPUTE:
666 if (ctx->shader_info->info.cs.uses_grid_size)
667 user_sgpr_count += 3;
668 break;
669 case MESA_SHADER_FRAGMENT:
670 user_sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
671 break;
672 case MESA_SHADER_VERTEX:
673 if (!ctx->is_gs_copy_shader)
674 user_sgpr_count += count_vs_user_sgprs(ctx);
675 break;
676 case MESA_SHADER_TESS_CTRL:
677 if (has_previous_stage) {
678 if (previous_stage == MESA_SHADER_VERTEX)
679 user_sgpr_count += count_vs_user_sgprs(ctx);
680 }
681 break;
682 case MESA_SHADER_TESS_EVAL:
683 break;
684 case MESA_SHADER_GEOMETRY:
685 if (has_previous_stage) {
686 if (previous_stage == MESA_SHADER_VERTEX) {
687 user_sgpr_count += count_vs_user_sgprs(ctx);
688 }
689 }
690 break;
691 default:
692 break;
693 }
694
695 if (needs_view_index)
696 user_sgpr_count++;
697
698 if (ctx->shader_info->info.loads_push_constants)
699 user_sgpr_count++;
700
701 if (ctx->streamout_buffers)
702 user_sgpr_count++;
703
704 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
705 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
706 uint32_t num_desc_set =
707 util_bitcount(ctx->shader_info->info.desc_set_used_mask);
708
709 if (remaining_sgprs < num_desc_set) {
710 user_sgpr_info->indirect_all_descriptor_sets = true;
711 }
712 }
713
714 static void
715 declare_global_input_sgprs(struct radv_shader_context *ctx,
716 const struct user_sgpr_info *user_sgpr_info,
717 struct arg_info *args,
718 LLVMValueRef *desc_sets)
719 {
720 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
721
722 /* 1 for each descriptor set */
723 if (!user_sgpr_info->indirect_all_descriptor_sets) {
724 uint32_t mask = ctx->shader_info->info.desc_set_used_mask;
725
726 while (mask) {
727 int i = u_bit_scan(&mask);
728
729 add_array_arg(args, type, &ctx->descriptor_sets[i]);
730 }
731 } else {
732 add_array_arg(args, ac_array_in_const32_addr_space(type), desc_sets);
733 }
734
735 if (ctx->shader_info->info.loads_push_constants) {
736 /* 1 for push constants and dynamic descriptors */
737 add_array_arg(args, type, &ctx->abi.push_constants);
738 }
739
740 if (ctx->shader_info->info.so.num_outputs) {
741 add_arg(args, ARG_SGPR,
742 ac_array_in_const32_addr_space(ctx->ac.v4i32),
743 &ctx->streamout_buffers);
744 }
745 }
746
747 static void
748 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
749 gl_shader_stage stage,
750 bool has_previous_stage,
751 gl_shader_stage previous_stage,
752 struct arg_info *args)
753 {
754 if (!ctx->is_gs_copy_shader &&
755 (stage == MESA_SHADER_VERTEX ||
756 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
757 if (ctx->shader_info->info.vs.has_vertex_buffers) {
758 add_arg(args, ARG_SGPR,
759 ac_array_in_const32_addr_space(ctx->ac.v4i32),
760 &ctx->vertex_buffers);
761 }
762 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
763 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
764 if (ctx->shader_info->info.vs.needs_draw_id) {
765 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
766 }
767 }
768 }
769
770 static void
771 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
772 {
773 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
774 if (!ctx->is_gs_copy_shader) {
775 if (ctx->options->key.vs.as_ls) {
776 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
777 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
778 } else {
779 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
780 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
781 }
782 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
783 }
784 }
785
786 static void
787 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
788 struct arg_info *args)
789 {
790 int i;
791
792 /* Streamout SGPRs. */
793 if (ctx->shader_info->info.so.num_outputs) {
794 assert(stage == MESA_SHADER_VERTEX ||
795 stage == MESA_SHADER_TESS_EVAL);
796
797 if (stage != MESA_SHADER_TESS_EVAL) {
798 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
799 } else {
800 args->assign[args->count - 1] = &ctx->streamout_config;
801 args->types[args->count - 1] = ctx->ac.i32;
802 }
803
804 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
805 }
806
807 /* A streamout buffer offset is loaded if the stride is non-zero. */
808 for (i = 0; i < 4; i++) {
809 if (!ctx->shader_info->info.so.strides[i])
810 continue;
811
812 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
813 }
814 }
815
816 static void
817 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
818 {
819 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
820 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
821 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
822 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
823 }
824
825 static void
826 set_global_input_locs(struct radv_shader_context *ctx,
827 const struct user_sgpr_info *user_sgpr_info,
828 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
829 {
830 uint32_t mask = ctx->shader_info->info.desc_set_used_mask;
831
832 if (!user_sgpr_info->indirect_all_descriptor_sets) {
833 while (mask) {
834 int i = u_bit_scan(&mask);
835
836 set_loc_desc(ctx, i, user_sgpr_idx);
837 }
838 } else {
839 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
840 user_sgpr_idx);
841
842 while (mask) {
843 int i = u_bit_scan(&mask);
844
845 ctx->descriptor_sets[i] =
846 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
847 LLVMConstInt(ctx->ac.i32, i, false));
848
849 }
850
851 ctx->shader_info->need_indirect_descriptor_sets = true;
852 }
853
854 if (ctx->shader_info->info.loads_push_constants) {
855 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
856 }
857
858 if (ctx->streamout_buffers) {
859 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
860 user_sgpr_idx);
861 }
862 }
863
864 static void
865 set_vs_specific_input_locs(struct radv_shader_context *ctx,
866 gl_shader_stage stage, bool has_previous_stage,
867 gl_shader_stage previous_stage,
868 uint8_t *user_sgpr_idx)
869 {
870 if (!ctx->is_gs_copy_shader &&
871 (stage == MESA_SHADER_VERTEX ||
872 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
873 if (ctx->shader_info->info.vs.has_vertex_buffers) {
874 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
875 user_sgpr_idx);
876 }
877
878 unsigned vs_num = 2;
879 if (ctx->shader_info->info.vs.needs_draw_id)
880 vs_num++;
881
882 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
883 user_sgpr_idx, vs_num);
884 }
885 }
886
887 static void set_llvm_calling_convention(LLVMValueRef func,
888 gl_shader_stage stage)
889 {
890 enum radeon_llvm_calling_convention calling_conv;
891
892 switch (stage) {
893 case MESA_SHADER_VERTEX:
894 case MESA_SHADER_TESS_EVAL:
895 calling_conv = RADEON_LLVM_AMDGPU_VS;
896 break;
897 case MESA_SHADER_GEOMETRY:
898 calling_conv = RADEON_LLVM_AMDGPU_GS;
899 break;
900 case MESA_SHADER_TESS_CTRL:
901 calling_conv = RADEON_LLVM_AMDGPU_HS;
902 break;
903 case MESA_SHADER_FRAGMENT:
904 calling_conv = RADEON_LLVM_AMDGPU_PS;
905 break;
906 case MESA_SHADER_COMPUTE:
907 calling_conv = RADEON_LLVM_AMDGPU_CS;
908 break;
909 default:
910 unreachable("Unhandle shader type");
911 }
912
913 LLVMSetFunctionCallConv(func, calling_conv);
914 }
915
916 static void create_function(struct radv_shader_context *ctx,
917 gl_shader_stage stage,
918 bool has_previous_stage,
919 gl_shader_stage previous_stage)
920 {
921 uint8_t user_sgpr_idx;
922 struct user_sgpr_info user_sgpr_info;
923 struct arg_info args = {};
924 LLVMValueRef desc_sets;
925 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
926 allocate_user_sgprs(ctx, stage, has_previous_stage,
927 previous_stage, needs_view_index, &user_sgpr_info);
928
929 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
930 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
931 &ctx->ring_offsets);
932 }
933
934 switch (stage) {
935 case MESA_SHADER_COMPUTE:
936 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
937 &desc_sets);
938
939 if (ctx->shader_info->info.cs.uses_grid_size) {
940 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
941 &ctx->abi.num_work_groups);
942 }
943
944 for (int i = 0; i < 3; i++) {
945 ctx->abi.workgroup_ids[i] = NULL;
946 if (ctx->shader_info->info.cs.uses_block_id[i]) {
947 add_arg(&args, ARG_SGPR, ctx->ac.i32,
948 &ctx->abi.workgroup_ids[i]);
949 }
950 }
951
952 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
953 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
954 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
955 &ctx->abi.local_invocation_ids);
956 break;
957 case MESA_SHADER_VERTEX:
958 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
959 &desc_sets);
960
961 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
962 previous_stage, &args);
963
964 if (needs_view_index)
965 add_arg(&args, ARG_SGPR, ctx->ac.i32,
966 &ctx->abi.view_index);
967 if (ctx->options->key.vs.as_es) {
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->es2gs_offset);
970 } else if (ctx->options->key.vs.as_ls) {
971 /* no extra parameters */
972 } else {
973 declare_streamout_sgprs(ctx, stage, &args);
974 }
975
976 declare_vs_input_vgprs(ctx, &args);
977 break;
978 case MESA_SHADER_TESS_CTRL:
979 if (has_previous_stage) {
980 // First 6 system regs
981 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
982 add_arg(&args, ARG_SGPR, ctx->ac.i32,
983 &ctx->merged_wave_info);
984 add_arg(&args, ARG_SGPR, ctx->ac.i32,
985 &ctx->tess_factor_offset);
986
987 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
988 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
989 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
990
991 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
992 &desc_sets);
993
994 declare_vs_specific_input_sgprs(ctx, stage,
995 has_previous_stage,
996 previous_stage, &args);
997
998 if (needs_view_index)
999 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1000 &ctx->abi.view_index);
1001
1002 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1003 &ctx->abi.tcs_patch_id);
1004 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1005 &ctx->abi.tcs_rel_ids);
1006
1007 declare_vs_input_vgprs(ctx, &args);
1008 } else {
1009 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1010 &desc_sets);
1011
1012 if (needs_view_index)
1013 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1014 &ctx->abi.view_index);
1015
1016 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1017 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1018 &ctx->tess_factor_offset);
1019 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1020 &ctx->abi.tcs_patch_id);
1021 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1022 &ctx->abi.tcs_rel_ids);
1023 }
1024 break;
1025 case MESA_SHADER_TESS_EVAL:
1026 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1027 &desc_sets);
1028
1029 if (needs_view_index)
1030 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1031 &ctx->abi.view_index);
1032
1033 if (ctx->options->key.tes.as_es) {
1034 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1035 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1036 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1037 &ctx->es2gs_offset);
1038 } else {
1039 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1040 declare_streamout_sgprs(ctx, stage, &args);
1041 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1042 }
1043 declare_tes_input_vgprs(ctx, &args);
1044 break;
1045 case MESA_SHADER_GEOMETRY:
1046 if (has_previous_stage) {
1047 // First 6 system regs
1048 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1049 &ctx->gs2vs_offset);
1050 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1051 &ctx->merged_wave_info);
1052 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1053
1054 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1055 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1056 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1057
1058 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1059 &desc_sets);
1060
1061 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1062 declare_vs_specific_input_sgprs(ctx, stage,
1063 has_previous_stage,
1064 previous_stage,
1065 &args);
1066 }
1067
1068 if (needs_view_index)
1069 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1070 &ctx->abi.view_index);
1071
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->gs_vtx_offset[0]);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->gs_vtx_offset[2]);
1076 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1077 &ctx->abi.gs_prim_id);
1078 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1079 &ctx->abi.gs_invocation_id);
1080 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1081 &ctx->gs_vtx_offset[4]);
1082
1083 if (previous_stage == MESA_SHADER_VERTEX) {
1084 declare_vs_input_vgprs(ctx, &args);
1085 } else {
1086 declare_tes_input_vgprs(ctx, &args);
1087 }
1088 } else {
1089 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1090 &desc_sets);
1091
1092 if (needs_view_index)
1093 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1094 &ctx->abi.view_index);
1095
1096 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1097 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1098 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1099 &ctx->gs_vtx_offset[0]);
1100 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1101 &ctx->gs_vtx_offset[1]);
1102 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1103 &ctx->abi.gs_prim_id);
1104 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1105 &ctx->gs_vtx_offset[2]);
1106 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1107 &ctx->gs_vtx_offset[3]);
1108 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1109 &ctx->gs_vtx_offset[4]);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1111 &ctx->gs_vtx_offset[5]);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1113 &ctx->abi.gs_invocation_id);
1114 }
1115 break;
1116 case MESA_SHADER_FRAGMENT:
1117 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1118 &desc_sets);
1119
1120 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1121 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1122 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1123 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1124 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1125 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1126 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1127 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1128 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1129 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1130 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1131 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1132 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1133 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1134 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1135 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1136 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1137 break;
1138 default:
1139 unreachable("Shader stage not implemented");
1140 }
1141
1142 ctx->main_function = create_llvm_function(
1143 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1144 ctx->max_workgroup_size, ctx->options);
1145 set_llvm_calling_convention(ctx->main_function, stage);
1146
1147
1148 ctx->shader_info->num_input_vgprs = 0;
1149 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1150
1151 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1152
1153 if (ctx->stage != MESA_SHADER_FRAGMENT)
1154 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1155
1156 assign_arguments(ctx->main_function, &args);
1157
1158 user_sgpr_idx = 0;
1159
1160 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1161 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1162 &user_sgpr_idx);
1163 if (ctx->options->supports_spill) {
1164 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1165 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1166 NULL, 0, AC_FUNC_ATTR_READNONE);
1167 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1168 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1169 }
1170 }
1171
1172 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1173 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1174 if (has_previous_stage)
1175 user_sgpr_idx = 0;
1176
1177 set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1178
1179 switch (stage) {
1180 case MESA_SHADER_COMPUTE:
1181 if (ctx->shader_info->info.cs.uses_grid_size) {
1182 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1183 &user_sgpr_idx, 3);
1184 }
1185 break;
1186 case MESA_SHADER_VERTEX:
1187 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1188 previous_stage, &user_sgpr_idx);
1189 if (ctx->abi.view_index)
1190 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1191 break;
1192 case MESA_SHADER_TESS_CTRL:
1193 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1194 previous_stage, &user_sgpr_idx);
1195 if (ctx->abi.view_index)
1196 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1197 break;
1198 case MESA_SHADER_TESS_EVAL:
1199 if (ctx->abi.view_index)
1200 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1201 break;
1202 case MESA_SHADER_GEOMETRY:
1203 if (has_previous_stage) {
1204 if (previous_stage == MESA_SHADER_VERTEX)
1205 set_vs_specific_input_locs(ctx, stage,
1206 has_previous_stage,
1207 previous_stage,
1208 &user_sgpr_idx);
1209 }
1210 if (ctx->abi.view_index)
1211 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1212 break;
1213 case MESA_SHADER_FRAGMENT:
1214 break;
1215 default:
1216 unreachable("Shader stage not implemented");
1217 }
1218
1219 if (stage == MESA_SHADER_TESS_CTRL ||
1220 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1221 /* GFX9 has the ESGS ring buffer in LDS. */
1222 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1223 ac_declare_lds_as_pointer(&ctx->ac);
1224 }
1225
1226 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1227 }
1228
1229
1230 static LLVMValueRef
1231 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1232 unsigned desc_set, unsigned binding)
1233 {
1234 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1235 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1236 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1237 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1238 unsigned base_offset = layout->binding[binding].offset;
1239 LLVMValueRef offset, stride;
1240
1241 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1242 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1243 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1244 layout->binding[binding].dynamic_offset_offset;
1245 desc_ptr = ctx->abi.push_constants;
1246 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1247 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1248 } else
1249 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1250
1251 offset = ac_build_imad(&ctx->ac, index, stride,
1252 LLVMConstInt(ctx->ac.i32, base_offset, false));
1253
1254 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1255 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1256 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1257
1258 return desc_ptr;
1259 }
1260
1261
1262 /* The offchip buffer layout for TCS->TES is
1263 *
1264 * - attribute 0 of patch 0 vertex 0
1265 * - attribute 0 of patch 0 vertex 1
1266 * - attribute 0 of patch 0 vertex 2
1267 * ...
1268 * - attribute 0 of patch 1 vertex 0
1269 * - attribute 0 of patch 1 vertex 1
1270 * ...
1271 * - attribute 1 of patch 0 vertex 0
1272 * - attribute 1 of patch 0 vertex 1
1273 * ...
1274 * - per patch attribute 0 of patch 0
1275 * - per patch attribute 0 of patch 1
1276 * ...
1277 *
1278 * Note that every attribute has 4 components.
1279 */
1280 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1281 {
1282 uint32_t num_patches = ctx->tcs_num_patches;
1283 uint32_t num_tcs_outputs;
1284 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1285 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1286 else
1287 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1288
1289 uint32_t output_vertex_size = num_tcs_outputs * 16;
1290 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1291
1292 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1293 }
1294
1295 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1296 LLVMValueRef vertex_index)
1297 {
1298 LLVMValueRef param_stride;
1299 if (vertex_index)
1300 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1301 else
1302 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1303 return param_stride;
1304 }
1305
1306 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1307 LLVMValueRef vertex_index,
1308 LLVMValueRef param_index)
1309 {
1310 LLVMValueRef base_addr;
1311 LLVMValueRef param_stride, constant16;
1312 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1313 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1314 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1315 param_stride = calc_param_stride(ctx, vertex_index);
1316 if (vertex_index) {
1317 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1318 vertices_per_patch, vertex_index);
1319 } else {
1320 base_addr = rel_patch_id;
1321 }
1322
1323 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1324 LLVMBuildMul(ctx->ac.builder, param_index,
1325 param_stride, ""), "");
1326
1327 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1328
1329 if (!vertex_index) {
1330 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1331
1332 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1333 patch_data_offset, "");
1334 }
1335 return base_addr;
1336 }
1337
1338 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1339 unsigned param,
1340 unsigned const_index,
1341 bool is_compact,
1342 LLVMValueRef vertex_index,
1343 LLVMValueRef indir_index)
1344 {
1345 LLVMValueRef param_index;
1346
1347 if (indir_index)
1348 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1349 indir_index, "");
1350 else {
1351 if (const_index && !is_compact)
1352 param += const_index;
1353 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1354 }
1355 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1356 }
1357
1358 static LLVMValueRef
1359 get_dw_address(struct radv_shader_context *ctx,
1360 LLVMValueRef dw_addr,
1361 unsigned param,
1362 unsigned const_index,
1363 bool compact_const_index,
1364 LLVMValueRef vertex_index,
1365 LLVMValueRef stride,
1366 LLVMValueRef indir_index)
1367
1368 {
1369
1370 if (vertex_index) {
1371 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1372 LLVMBuildMul(ctx->ac.builder,
1373 vertex_index,
1374 stride, ""), "");
1375 }
1376
1377 if (indir_index)
1378 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1379 LLVMBuildMul(ctx->ac.builder, indir_index,
1380 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1381 else if (const_index && !compact_const_index)
1382 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1383 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1384
1385 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1386 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1387
1388 if (const_index && compact_const_index)
1389 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1390 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1391 return dw_addr;
1392 }
1393
1394 static LLVMValueRef
1395 load_tcs_varyings(struct ac_shader_abi *abi,
1396 LLVMTypeRef type,
1397 LLVMValueRef vertex_index,
1398 LLVMValueRef indir_index,
1399 unsigned const_index,
1400 unsigned location,
1401 unsigned driver_location,
1402 unsigned component,
1403 unsigned num_components,
1404 bool is_patch,
1405 bool is_compact,
1406 bool load_input)
1407 {
1408 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1409 LLVMValueRef dw_addr, stride;
1410 LLVMValueRef value[4], result;
1411 unsigned param = shader_io_get_unique_index(location);
1412
1413 if (load_input) {
1414 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1415 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1416 dw_addr = get_tcs_in_current_patch_offset(ctx);
1417 } else {
1418 if (!is_patch) {
1419 stride = get_tcs_out_vertex_stride(ctx);
1420 dw_addr = get_tcs_out_current_patch_offset(ctx);
1421 } else {
1422 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1423 stride = NULL;
1424 }
1425 }
1426
1427 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1428 indir_index);
1429
1430 for (unsigned i = 0; i < num_components + component; i++) {
1431 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1432 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1433 ctx->ac.i32_1, "");
1434 }
1435 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1436 return result;
1437 }
1438
1439 static void
1440 store_tcs_output(struct ac_shader_abi *abi,
1441 const nir_variable *var,
1442 LLVMValueRef vertex_index,
1443 LLVMValueRef param_index,
1444 unsigned const_index,
1445 LLVMValueRef src,
1446 unsigned writemask)
1447 {
1448 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1449 const unsigned location = var->data.location;
1450 const unsigned component = var->data.location_frac;
1451 const bool is_patch = var->data.patch;
1452 const bool is_compact = var->data.compact;
1453 LLVMValueRef dw_addr;
1454 LLVMValueRef stride = NULL;
1455 LLVMValueRef buf_addr = NULL;
1456 unsigned param;
1457 bool store_lds = true;
1458
1459 if (is_patch) {
1460 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1461 store_lds = false;
1462 } else {
1463 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1464 store_lds = false;
1465 }
1466
1467 param = shader_io_get_unique_index(location);
1468 if (location == VARYING_SLOT_CLIP_DIST0 &&
1469 is_compact && const_index > 3) {
1470 const_index -= 3;
1471 param++;
1472 }
1473
1474 if (!is_patch) {
1475 stride = get_tcs_out_vertex_stride(ctx);
1476 dw_addr = get_tcs_out_current_patch_offset(ctx);
1477 } else {
1478 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1479 }
1480
1481 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1482 param_index);
1483 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1484 vertex_index, param_index);
1485
1486 bool is_tess_factor = false;
1487 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1488 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1489 is_tess_factor = true;
1490
1491 unsigned base = is_compact ? const_index : 0;
1492 for (unsigned chan = 0; chan < 8; chan++) {
1493 if (!(writemask & (1 << chan)))
1494 continue;
1495 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1496 value = ac_to_integer(&ctx->ac, value);
1497 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1498
1499 if (store_lds || is_tess_factor) {
1500 LLVMValueRef dw_addr_chan =
1501 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1502 LLVMConstInt(ctx->ac.i32, chan, false), "");
1503 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1504 }
1505
1506 if (!is_tess_factor && writemask != 0xF)
1507 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1508 buf_addr, ctx->oc_lds,
1509 4 * (base + chan), 1, 0, true, false);
1510 }
1511
1512 if (writemask == 0xF) {
1513 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1514 buf_addr, ctx->oc_lds,
1515 (base * 4), 1, 0, true, false);
1516 }
1517 }
1518
1519 static LLVMValueRef
1520 load_tes_input(struct ac_shader_abi *abi,
1521 LLVMTypeRef type,
1522 LLVMValueRef vertex_index,
1523 LLVMValueRef param_index,
1524 unsigned const_index,
1525 unsigned location,
1526 unsigned driver_location,
1527 unsigned component,
1528 unsigned num_components,
1529 bool is_patch,
1530 bool is_compact,
1531 bool load_input)
1532 {
1533 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1534 LLVMValueRef buf_addr;
1535 LLVMValueRef result;
1536 unsigned param = shader_io_get_unique_index(location);
1537
1538 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1539 const_index -= 3;
1540 param++;
1541 }
1542
1543 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1544 is_compact, vertex_index, param_index);
1545
1546 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1547 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1548
1549 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1550 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1551 result = ac_trim_vector(&ctx->ac, result, num_components);
1552 return result;
1553 }
1554
1555 static LLVMValueRef
1556 load_gs_input(struct ac_shader_abi *abi,
1557 unsigned location,
1558 unsigned driver_location,
1559 unsigned component,
1560 unsigned num_components,
1561 unsigned vertex_index,
1562 unsigned const_index,
1563 LLVMTypeRef type)
1564 {
1565 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1566 LLVMValueRef vtx_offset;
1567 unsigned param, vtx_offset_param;
1568 LLVMValueRef value[4], result;
1569
1570 vtx_offset_param = vertex_index;
1571 assert(vtx_offset_param < 6);
1572 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1573 LLVMConstInt(ctx->ac.i32, 4, false), "");
1574
1575 param = shader_io_get_unique_index(location);
1576
1577 for (unsigned i = component; i < num_components + component; i++) {
1578 if (ctx->ac.chip_class >= GFX9) {
1579 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1580 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1581 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1582 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1583 } else {
1584 LLVMValueRef soffset =
1585 LLVMConstInt(ctx->ac.i32,
1586 (param * 4 + i + const_index) * 256,
1587 false);
1588
1589 value[i] = ac_build_buffer_load(&ctx->ac,
1590 ctx->esgs_ring, 1,
1591 ctx->ac.i32_0,
1592 vtx_offset, soffset,
1593 0, 1, 0, true, false);
1594 }
1595
1596 if (ac_get_type_size(type) == 2) {
1597 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1598 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1599 }
1600 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1601 }
1602 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1603 result = ac_to_integer(&ctx->ac, result);
1604 return result;
1605 }
1606
1607
1608 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1609 {
1610 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1611 ac_build_kill_if_false(&ctx->ac, visible);
1612 }
1613
1614 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1615 enum glsl_interp_mode interp, unsigned location)
1616 {
1617 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1618
1619 switch (interp) {
1620 case INTERP_MODE_FLAT:
1621 default:
1622 return NULL;
1623 case INTERP_MODE_SMOOTH:
1624 case INTERP_MODE_NONE:
1625 if (location == INTERP_CENTER)
1626 return ctx->persp_center;
1627 else if (location == INTERP_CENTROID)
1628 return ctx->persp_centroid;
1629 else if (location == INTERP_SAMPLE)
1630 return ctx->persp_sample;
1631 break;
1632 case INTERP_MODE_NOPERSPECTIVE:
1633 if (location == INTERP_CENTER)
1634 return ctx->linear_center;
1635 else if (location == INTERP_CENTROID)
1636 return ctx->linear_centroid;
1637 else if (location == INTERP_SAMPLE)
1638 return ctx->linear_sample;
1639 break;
1640 }
1641 return NULL;
1642 }
1643
1644 static uint32_t
1645 radv_get_sample_pos_offset(uint32_t num_samples)
1646 {
1647 uint32_t sample_pos_offset = 0;
1648
1649 switch (num_samples) {
1650 case 2:
1651 sample_pos_offset = 1;
1652 break;
1653 case 4:
1654 sample_pos_offset = 3;
1655 break;
1656 case 8:
1657 sample_pos_offset = 7;
1658 break;
1659 default:
1660 break;
1661 }
1662 return sample_pos_offset;
1663 }
1664
1665 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1666 LLVMValueRef sample_id)
1667 {
1668 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1669
1670 LLVMValueRef result;
1671 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1672
1673 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1674 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1675
1676 uint32_t sample_pos_offset =
1677 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1678
1679 sample_id =
1680 LLVMBuildAdd(ctx->ac.builder, sample_id,
1681 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1682 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1683
1684 return result;
1685 }
1686
1687
1688 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1689 {
1690 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1691 uint8_t log2_ps_iter_samples;
1692
1693 if (ctx->shader_info->info.ps.force_persample) {
1694 log2_ps_iter_samples =
1695 util_logbase2(ctx->options->key.fs.num_samples);
1696 } else {
1697 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1698 }
1699
1700 /* The bit pattern matches that used by fixed function fragment
1701 * processing. */
1702 static const uint16_t ps_iter_masks[] = {
1703 0xffff, /* not used */
1704 0x5555,
1705 0x1111,
1706 0x0101,
1707 0x0001,
1708 };
1709 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1710
1711 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1712
1713 LLVMValueRef result, sample_id;
1714 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1715 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1716 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1717 return result;
1718 }
1719
1720
1721 static void
1722 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1723 {
1724 LLVMValueRef gs_next_vertex;
1725 LLVMValueRef can_emit;
1726 unsigned offset = 0;
1727 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1728
1729 /* Write vertex attribute values to GSVS ring */
1730 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1731 ctx->gs_next_vertex[stream],
1732 "");
1733
1734 /* If this thread has already emitted the declared maximum number of
1735 * vertices, kill it: excessive vertex emissions are not supposed to
1736 * have any effect, and GS threads have no externally observable
1737 * effects other than emitting vertices.
1738 */
1739 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1740 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1741 ac_build_kill_if_false(&ctx->ac, can_emit);
1742
1743 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1744 unsigned output_usage_mask =
1745 ctx->shader_info->info.gs.output_usage_mask[i];
1746 uint8_t output_stream =
1747 ctx->shader_info->info.gs.output_streams[i];
1748 LLVMValueRef *out_ptr = &addrs[i * 4];
1749 int length = util_last_bit(output_usage_mask);
1750
1751 if (!(ctx->output_mask & (1ull << i)) ||
1752 output_stream != stream)
1753 continue;
1754
1755 for (unsigned j = 0; j < length; j++) {
1756 if (!(output_usage_mask & (1 << j)))
1757 continue;
1758
1759 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1760 out_ptr[j], "");
1761 LLVMValueRef voffset =
1762 LLVMConstInt(ctx->ac.i32, offset *
1763 ctx->gs_max_out_vertices, false);
1764
1765 offset++;
1766
1767 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1768 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1769
1770 out_val = ac_to_integer(&ctx->ac, out_val);
1771 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1772
1773 ac_build_buffer_store_dword(&ctx->ac,
1774 ctx->gsvs_ring[stream],
1775 out_val, 1,
1776 voffset, ctx->gs2vs_offset, 0,
1777 1, 1, true, true);
1778 }
1779 }
1780
1781 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1782 ctx->ac.i32_1, "");
1783 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1784
1785 ac_build_sendmsg(&ctx->ac,
1786 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1787 ctx->gs_wave_id);
1788 }
1789
1790 static void
1791 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1792 {
1793 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1794 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1795 }
1796
1797 static LLVMValueRef
1798 load_tess_coord(struct ac_shader_abi *abi)
1799 {
1800 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1801
1802 LLVMValueRef coord[4] = {
1803 ctx->tes_u,
1804 ctx->tes_v,
1805 ctx->ac.f32_0,
1806 ctx->ac.f32_0,
1807 };
1808
1809 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1810 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1811 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1812
1813 return ac_build_gather_values(&ctx->ac, coord, 3);
1814 }
1815
1816 static LLVMValueRef
1817 load_patch_vertices_in(struct ac_shader_abi *abi)
1818 {
1819 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1820 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1821 }
1822
1823
1824 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1825 {
1826 return abi->base_vertex;
1827 }
1828
1829 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1830 LLVMValueRef buffer_ptr, bool write)
1831 {
1832 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1833 LLVMValueRef result;
1834
1835 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1836
1837 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1838 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1839
1840 return result;
1841 }
1842
1843 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1844 {
1845 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1846 LLVMValueRef result;
1847
1848 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1849
1850 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1851 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1852
1853 return result;
1854 }
1855
1856 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1857 unsigned descriptor_set,
1858 unsigned base_index,
1859 unsigned constant_index,
1860 LLVMValueRef index,
1861 enum ac_descriptor_type desc_type,
1862 bool image, bool write,
1863 bool bindless)
1864 {
1865 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1866 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1867 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1868 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1869 unsigned offset = binding->offset;
1870 unsigned stride = binding->size;
1871 unsigned type_size;
1872 LLVMBuilderRef builder = ctx->ac.builder;
1873 LLVMTypeRef type;
1874
1875 assert(base_index < layout->binding_count);
1876
1877 switch (desc_type) {
1878 case AC_DESC_IMAGE:
1879 type = ctx->ac.v8i32;
1880 type_size = 32;
1881 break;
1882 case AC_DESC_FMASK:
1883 type = ctx->ac.v8i32;
1884 offset += 32;
1885 type_size = 32;
1886 break;
1887 case AC_DESC_SAMPLER:
1888 type = ctx->ac.v4i32;
1889 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1890 offset += 64;
1891
1892 type_size = 16;
1893 break;
1894 case AC_DESC_BUFFER:
1895 type = ctx->ac.v4i32;
1896 type_size = 16;
1897 break;
1898 default:
1899 unreachable("invalid desc_type\n");
1900 }
1901
1902 offset += constant_index * stride;
1903
1904 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1905 (!index || binding->immutable_samplers_equal)) {
1906 if (binding->immutable_samplers_equal)
1907 constant_index = 0;
1908
1909 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1910
1911 LLVMValueRef constants[] = {
1912 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1913 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1914 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1915 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1916 };
1917 return ac_build_gather_values(&ctx->ac, constants, 4);
1918 }
1919
1920 assert(stride % type_size == 0);
1921
1922 if (!index)
1923 index = ctx->ac.i32_0;
1924
1925 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1926
1927 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1928 list = LLVMBuildPointerCast(builder, list,
1929 ac_array_in_const32_addr_space(type), "");
1930
1931 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1932 }
1933
1934 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1935 * so we may need to fix it up. */
1936 static LLVMValueRef
1937 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1938 unsigned adjustment,
1939 LLVMValueRef alpha)
1940 {
1941 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1942 return alpha;
1943
1944 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1945
1946 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1947 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1948 else
1949 alpha = ac_to_integer(&ctx->ac, alpha);
1950
1951 /* For the integer-like cases, do a natural sign extension.
1952 *
1953 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1954 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1955 * exponent.
1956 */
1957 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1958 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1959 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1960 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1961
1962 /* Convert back to the right type. */
1963 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1964 LLVMValueRef clamp;
1965 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1966 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1967 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1968 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1969 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1970 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1971 }
1972
1973 return alpha;
1974 }
1975
1976 static void
1977 handle_vs_input_decl(struct radv_shader_context *ctx,
1978 struct nir_variable *variable)
1979 {
1980 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1981 LLVMValueRef t_offset;
1982 LLVMValueRef t_list;
1983 LLVMValueRef input;
1984 LLVMValueRef buffer_index;
1985 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1986 uint8_t input_usage_mask =
1987 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1988 unsigned num_channels = util_last_bit(input_usage_mask);
1989
1990 variable->data.driver_location = variable->data.location * 4;
1991
1992 enum glsl_base_type type = glsl_get_base_type(variable->type);
1993 for (unsigned i = 0; i < attrib_count; ++i) {
1994 LLVMValueRef output[4];
1995 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1996
1997 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1998 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1999
2000 if (divisor) {
2001 buffer_index = ctx->abi.instance_id;
2002
2003 if (divisor != 1) {
2004 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2005 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2006 }
2007
2008 if (ctx->options->key.vs.as_ls) {
2009 ctx->shader_info->vs.vgpr_comp_cnt =
2010 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
2011 } else {
2012 ctx->shader_info->vs.vgpr_comp_cnt =
2013 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
2014 }
2015 } else {
2016 buffer_index = ctx->ac.i32_0;
2017 }
2018
2019 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2020 } else
2021 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2022 ctx->abi.base_vertex, "");
2023 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
2024
2025 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2026
2027 input = ac_build_buffer_load_format(&ctx->ac, t_list,
2028 buffer_index,
2029 ctx->ac.i32_0,
2030 num_channels, false, true);
2031
2032 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
2033
2034 for (unsigned chan = 0; chan < 4; chan++) {
2035 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2036 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2037 if (type == GLSL_TYPE_FLOAT16) {
2038 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2039 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2040 }
2041 }
2042
2043 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2044 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2045
2046 for (unsigned chan = 0; chan < 4; chan++) {
2047 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2048 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2049 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2050
2051 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2052 }
2053 }
2054 }
2055
2056 static void interp_fs_input(struct radv_shader_context *ctx,
2057 unsigned attr,
2058 LLVMValueRef interp_param,
2059 LLVMValueRef prim_mask,
2060 LLVMValueRef result[4])
2061 {
2062 LLVMValueRef attr_number;
2063 unsigned chan;
2064 LLVMValueRef i, j;
2065 bool interp = !LLVMIsUndef(interp_param);
2066
2067 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2068
2069 /* fs.constant returns the param from the middle vertex, so it's not
2070 * really useful for flat shading. It's meant to be used for custom
2071 * interpolation (but the intrinsic can't fetch from the other two
2072 * vertices).
2073 *
2074 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2075 * to do the right thing. The only reason we use fs.constant is that
2076 * fs.interp cannot be used on integers, because they can be equal
2077 * to NaN.
2078 */
2079 if (interp) {
2080 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2081 ctx->ac.v2f32, "");
2082
2083 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2084 ctx->ac.i32_0, "");
2085 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2086 ctx->ac.i32_1, "");
2087 }
2088
2089 for (chan = 0; chan < 4; chan++) {
2090 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2091
2092 if (interp) {
2093 result[chan] = ac_build_fs_interp(&ctx->ac,
2094 llvm_chan,
2095 attr_number,
2096 prim_mask, i, j);
2097 } else {
2098 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2099 LLVMConstInt(ctx->ac.i32, 2, false),
2100 llvm_chan,
2101 attr_number,
2102 prim_mask);
2103 result[chan] = LLVMBuildBitCast(ctx->ac.builder, result[chan], ctx->ac.i32, "");
2104 result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, result[chan], LLVMTypeOf(interp_param), "");
2105 }
2106 }
2107 }
2108
2109 static void
2110 handle_fs_input_decl(struct radv_shader_context *ctx,
2111 struct nir_variable *variable)
2112 {
2113 int idx = variable->data.location;
2114 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2115 LLVMValueRef interp = NULL;
2116 uint64_t mask;
2117
2118 variable->data.driver_location = idx * 4;
2119 mask = ((1ull << attrib_count) - 1) << variable->data.location;
2120
2121 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2122 unsigned interp_type;
2123 if (variable->data.sample)
2124 interp_type = INTERP_SAMPLE;
2125 else if (variable->data.centroid)
2126 interp_type = INTERP_CENTROID;
2127 else
2128 interp_type = INTERP_CENTER;
2129
2130 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2131 }
2132 bool is_16bit = glsl_type_is_16bit(glsl_without_array(variable->type));
2133 LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
2134 if (interp == NULL)
2135 interp = LLVMGetUndef(type);
2136
2137 for (unsigned i = 0; i < attrib_count; ++i)
2138 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2139
2140 if (idx == VARYING_SLOT_CLIP_DIST0) {
2141 /* Do not account for the number of components inside the array
2142 * of clip/cull distances because this might wrongly set other
2143 * bits like primitive ID or layer.
2144 */
2145 mask = 1ull << VARYING_SLOT_CLIP_DIST0;
2146 }
2147
2148 ctx->input_mask |= mask;
2149 }
2150
2151 static void
2152 handle_vs_inputs(struct radv_shader_context *ctx,
2153 struct nir_shader *nir) {
2154 nir_foreach_variable(variable, &nir->inputs)
2155 handle_vs_input_decl(ctx, variable);
2156 }
2157
2158 static void
2159 prepare_interp_optimize(struct radv_shader_context *ctx,
2160 struct nir_shader *nir)
2161 {
2162 bool uses_center = false;
2163 bool uses_centroid = false;
2164 nir_foreach_variable(variable, &nir->inputs) {
2165 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2166 variable->data.sample)
2167 continue;
2168
2169 if (variable->data.centroid)
2170 uses_centroid = true;
2171 else
2172 uses_center = true;
2173 }
2174
2175 if (uses_center && uses_centroid) {
2176 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2177 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2178 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2179 }
2180 }
2181
2182 static void
2183 handle_fs_inputs(struct radv_shader_context *ctx,
2184 struct nir_shader *nir)
2185 {
2186 prepare_interp_optimize(ctx, nir);
2187
2188 nir_foreach_variable(variable, &nir->inputs)
2189 handle_fs_input_decl(ctx, variable);
2190
2191 unsigned index = 0;
2192
2193 if (ctx->shader_info->info.ps.uses_input_attachments ||
2194 ctx->shader_info->info.needs_multiview_view_index) {
2195 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2196 ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = LLVMGetUndef(ctx->ac.i32);
2197 }
2198
2199 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2200 LLVMValueRef interp_param;
2201 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2202
2203 if (!(ctx->input_mask & (1ull << i)))
2204 continue;
2205
2206 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2207 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2208 interp_param = *inputs;
2209 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2210 inputs);
2211
2212 if (LLVMIsUndef(interp_param))
2213 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2214 if (i >= VARYING_SLOT_VAR0)
2215 ctx->abi.fs_input_attr_indices[i - VARYING_SLOT_VAR0] = index;
2216 ++index;
2217 } else if (i == VARYING_SLOT_CLIP_DIST0) {
2218 int length = ctx->shader_info->info.ps.num_input_clips_culls;
2219
2220 for (unsigned j = 0; j < length; j += 4) {
2221 inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
2222
2223 interp_param = *inputs;
2224 interp_fs_input(ctx, index, interp_param,
2225 ctx->abi.prim_mask, inputs);
2226 ++index;
2227 }
2228 } else if (i == VARYING_SLOT_POS) {
2229 for(int i = 0; i < 3; ++i)
2230 inputs[i] = ctx->abi.frag_pos[i];
2231
2232 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2233 ctx->abi.frag_pos[3]);
2234 }
2235 }
2236 ctx->shader_info->fs.num_interp = index;
2237 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2238
2239 if (ctx->shader_info->info.needs_multiview_view_index)
2240 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2241 }
2242
2243 static void
2244 scan_shader_output_decl(struct radv_shader_context *ctx,
2245 struct nir_variable *variable,
2246 struct nir_shader *shader,
2247 gl_shader_stage stage)
2248 {
2249 int idx = variable->data.location + variable->data.index;
2250 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2251 uint64_t mask_attribs;
2252
2253 variable->data.driver_location = idx * 4;
2254
2255 /* tess ctrl has it's own load/store paths for outputs */
2256 if (stage == MESA_SHADER_TESS_CTRL)
2257 return;
2258
2259 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2260 if (stage == MESA_SHADER_VERTEX ||
2261 stage == MESA_SHADER_TESS_EVAL ||
2262 stage == MESA_SHADER_GEOMETRY) {
2263 if (idx == VARYING_SLOT_CLIP_DIST0) {
2264 if (stage == MESA_SHADER_VERTEX) {
2265 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2266 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2267 ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2268 }
2269 if (stage == MESA_SHADER_TESS_EVAL) {
2270 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2271 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2272 ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2273 }
2274
2275 mask_attribs = 1ull << idx;
2276 }
2277 }
2278
2279 ctx->output_mask |= mask_attribs;
2280 }
2281
2282
2283 /* Initialize arguments for the shader export intrinsic */
2284 static void
2285 si_llvm_init_export_args(struct radv_shader_context *ctx,
2286 LLVMValueRef *values,
2287 unsigned enabled_channels,
2288 unsigned target,
2289 struct ac_export_args *args)
2290 {
2291 /* Specify the channels that are enabled. */
2292 args->enabled_channels = enabled_channels;
2293
2294 /* Specify whether the EXEC mask represents the valid mask */
2295 args->valid_mask = 0;
2296
2297 /* Specify whether this is the last export */
2298 args->done = 0;
2299
2300 /* Specify the target we are exporting */
2301 args->target = target;
2302
2303 args->compr = false;
2304 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2305 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2306 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2307 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2308
2309 if (!values)
2310 return;
2311
2312 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2313 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2314 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2315 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2316 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2317 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2318 unsigned chan;
2319
2320 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2321 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2322 unsigned bits, bool hi) = NULL;
2323
2324 switch(col_format) {
2325 case V_028714_SPI_SHADER_ZERO:
2326 args->enabled_channels = 0; /* writemask */
2327 args->target = V_008DFC_SQ_EXP_NULL;
2328 break;
2329
2330 case V_028714_SPI_SHADER_32_R:
2331 args->enabled_channels = 1;
2332 args->out[0] = values[0];
2333 break;
2334
2335 case V_028714_SPI_SHADER_32_GR:
2336 args->enabled_channels = 0x3;
2337 args->out[0] = values[0];
2338 args->out[1] = values[1];
2339 break;
2340
2341 case V_028714_SPI_SHADER_32_AR:
2342 args->enabled_channels = 0x9;
2343 args->out[0] = values[0];
2344 args->out[3] = values[3];
2345 break;
2346
2347 case V_028714_SPI_SHADER_FP16_ABGR:
2348 args->enabled_channels = 0x5;
2349 packf = ac_build_cvt_pkrtz_f16;
2350 if (is_16bit) {
2351 for (unsigned chan = 0; chan < 4; chan++)
2352 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2353 values[chan],
2354 ctx->ac.f32, "");
2355 }
2356 break;
2357
2358 case V_028714_SPI_SHADER_UNORM16_ABGR:
2359 args->enabled_channels = 0x5;
2360 packf = ac_build_cvt_pknorm_u16;
2361 break;
2362
2363 case V_028714_SPI_SHADER_SNORM16_ABGR:
2364 args->enabled_channels = 0x5;
2365 packf = ac_build_cvt_pknorm_i16;
2366 break;
2367
2368 case V_028714_SPI_SHADER_UINT16_ABGR:
2369 args->enabled_channels = 0x5;
2370 packi = ac_build_cvt_pk_u16;
2371 if (is_16bit) {
2372 for (unsigned chan = 0; chan < 4; chan++)
2373 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2374 values[chan],
2375 ctx->ac.i32, "");
2376 }
2377 break;
2378
2379 case V_028714_SPI_SHADER_SINT16_ABGR:
2380 args->enabled_channels = 0x5;
2381 packi = ac_build_cvt_pk_i16;
2382 if (is_16bit) {
2383 for (unsigned chan = 0; chan < 4; chan++)
2384 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2385 values[chan],
2386 ctx->ac.i32, "");
2387 }
2388 break;
2389
2390 default:
2391 case V_028714_SPI_SHADER_32_ABGR:
2392 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2393 break;
2394 }
2395
2396 /* Pack f16 or norm_i16/u16. */
2397 if (packf) {
2398 for (chan = 0; chan < 2; chan++) {
2399 LLVMValueRef pack_args[2] = {
2400 values[2 * chan],
2401 values[2 * chan + 1]
2402 };
2403 LLVMValueRef packed;
2404
2405 packed = packf(&ctx->ac, pack_args);
2406 args->out[chan] = ac_to_float(&ctx->ac, packed);
2407 }
2408 args->compr = 1; /* COMPR flag */
2409 }
2410
2411 /* Pack i16/u16. */
2412 if (packi) {
2413 for (chan = 0; chan < 2; chan++) {
2414 LLVMValueRef pack_args[2] = {
2415 ac_to_integer(&ctx->ac, values[2 * chan]),
2416 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2417 };
2418 LLVMValueRef packed;
2419
2420 packed = packi(&ctx->ac, pack_args,
2421 is_int8 ? 8 : is_int10 ? 10 : 16,
2422 chan == 1);
2423 args->out[chan] = ac_to_float(&ctx->ac, packed);
2424 }
2425 args->compr = 1; /* COMPR flag */
2426 }
2427 return;
2428 }
2429
2430 if (is_16bit) {
2431 for (unsigned chan = 0; chan < 4; chan++) {
2432 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2433 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2434 }
2435 } else
2436 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2437
2438 for (unsigned i = 0; i < 4; ++i) {
2439 if (!(args->enabled_channels & (1 << i)))
2440 continue;
2441
2442 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2443 }
2444 }
2445
2446 static void
2447 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2448 LLVMValueRef *values, unsigned enabled_channels)
2449 {
2450 struct ac_export_args args;
2451
2452 si_llvm_init_export_args(ctx, values, enabled_channels,
2453 V_008DFC_SQ_EXP_PARAM + index, &args);
2454 ac_build_export(&ctx->ac, &args);
2455 }
2456
2457 static LLVMValueRef
2458 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2459 {
2460 LLVMValueRef output =
2461 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2462
2463 return LLVMBuildLoad(ctx->ac.builder, output, "");
2464 }
2465
2466 static void
2467 radv_emit_stream_output(struct radv_shader_context *ctx,
2468 LLVMValueRef const *so_buffers,
2469 LLVMValueRef const *so_write_offsets,
2470 const struct radv_stream_output *output)
2471 {
2472 unsigned num_comps = util_bitcount(output->component_mask);
2473 unsigned loc = output->location;
2474 unsigned buf = output->buffer;
2475 unsigned offset = output->offset;
2476 unsigned start;
2477 LLVMValueRef out[4];
2478
2479 assert(num_comps && num_comps <= 4);
2480 if (!num_comps || num_comps > 4)
2481 return;
2482
2483 /* Get the first component. */
2484 start = ffs(output->component_mask) - 1;
2485
2486 /* Load the output as int. */
2487 for (int i = 0; i < num_comps; i++) {
2488 out[i] = ac_to_integer(&ctx->ac,
2489 radv_load_output(ctx, loc, start + i));
2490 }
2491
2492 /* Pack the output. */
2493 LLVMValueRef vdata = NULL;
2494
2495 switch (num_comps) {
2496 case 1: /* as i32 */
2497 vdata = out[0];
2498 break;
2499 case 2: /* as v2i32 */
2500 case 3: /* as v4i32 (aligned to 4) */
2501 out[3] = LLVMGetUndef(ctx->ac.i32);
2502 /* fall through */
2503 case 4: /* as v4i32 */
2504 vdata = ac_build_gather_values(&ctx->ac, out,
2505 util_next_power_of_two(num_comps));
2506 break;
2507 }
2508
2509 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2510 vdata, num_comps, so_write_offsets[buf],
2511 ctx->ac.i32_0, offset,
2512 1, 1, true, false);
2513 }
2514
2515 static void
2516 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2517 {
2518 struct ac_build_if_state if_ctx;
2519 int i;
2520
2521 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2522 assert(ctx->streamout_config);
2523 LLVMValueRef so_vtx_count =
2524 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2525 LLVMConstInt(ctx->ac.i32, 16, false),
2526 LLVMConstInt(ctx->ac.i32, 7, false), false);
2527
2528 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2529
2530 /* can_emit = tid < so_vtx_count; */
2531 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2532 tid, so_vtx_count, "");
2533
2534 /* Emit the streamout code conditionally. This actually avoids
2535 * out-of-bounds buffer access. The hw tells us via the SGPR
2536 * (so_vtx_count) which threads are allowed to emit streamout data.
2537 */
2538 ac_nir_build_if(&if_ctx, ctx, can_emit);
2539 {
2540 /* The buffer offset is computed as follows:
2541 * ByteOffset = streamout_offset[buffer_id]*4 +
2542 * (streamout_write_index + thread_id)*stride[buffer_id] +
2543 * attrib_offset
2544 */
2545 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2546
2547 /* Compute (streamout_write_index + thread_id). */
2548 so_write_index =
2549 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2550
2551 /* Load the descriptor and compute the write offset for each
2552 * enabled buffer.
2553 */
2554 LLVMValueRef so_write_offset[4] = {};
2555 LLVMValueRef so_buffers[4] = {};
2556 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2557
2558 for (i = 0; i < 4; i++) {
2559 uint16_t stride = ctx->shader_info->info.so.strides[i];
2560
2561 if (!stride)
2562 continue;
2563
2564 LLVMValueRef offset =
2565 LLVMConstInt(ctx->ac.i32, i, false);
2566
2567 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2568 buf_ptr, offset);
2569
2570 LLVMValueRef so_offset = ctx->streamout_offset[i];
2571
2572 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2573 LLVMConstInt(ctx->ac.i32, 4, false), "");
2574
2575 so_write_offset[i] =
2576 ac_build_imad(&ctx->ac, so_write_index,
2577 LLVMConstInt(ctx->ac.i32,
2578 stride * 4, false),
2579 so_offset);
2580 }
2581
2582 /* Write streamout data. */
2583 for (i = 0; i < ctx->shader_info->info.so.num_outputs; i++) {
2584 struct radv_stream_output *output =
2585 &ctx->shader_info->info.so.outputs[i];
2586
2587 if (stream != output->stream)
2588 continue;
2589
2590 radv_emit_stream_output(ctx, so_buffers,
2591 so_write_offset, output);
2592 }
2593 }
2594 ac_nir_build_endif(&if_ctx);
2595 }
2596
2597 static void
2598 handle_vs_outputs_post(struct radv_shader_context *ctx,
2599 bool export_prim_id, bool export_layer_id,
2600 struct radv_vs_output_info *outinfo)
2601 {
2602 uint32_t param_count = 0;
2603 unsigned target;
2604 unsigned pos_idx, num_pos_exports = 0;
2605 struct ac_export_args args, pos_args[4] = {};
2606 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2607 int i;
2608
2609 if (ctx->options->key.has_multiview_view_index) {
2610 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2611 if(!*tmp_out) {
2612 for(unsigned i = 0; i < 4; ++i)
2613 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2614 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2615 }
2616
2617 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2618 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2619 }
2620
2621 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2622 sizeof(outinfo->vs_output_param_offset));
2623
2624 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2625 unsigned output_usage_mask, length;
2626 LLVMValueRef slots[8];
2627 unsigned j;
2628
2629 if (ctx->stage == MESA_SHADER_VERTEX &&
2630 !ctx->is_gs_copy_shader) {
2631 output_usage_mask =
2632 ctx->shader_info->info.vs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2633 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2634 output_usage_mask =
2635 ctx->shader_info->info.tes.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2636 } else {
2637 assert(ctx->is_gs_copy_shader);
2638 output_usage_mask =
2639 ctx->shader_info->info.gs.output_usage_mask[VARYING_SLOT_CLIP_DIST0];
2640 }
2641
2642 length = util_last_bit(output_usage_mask);
2643
2644 i = VARYING_SLOT_CLIP_DIST0;
2645 for (j = 0; j < length; j++)
2646 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2647
2648 for (i = length; i < 8; i++)
2649 slots[i] = LLVMGetUndef(ctx->ac.f32);
2650
2651 if (length > 4) {
2652 target = V_008DFC_SQ_EXP_POS + 3;
2653 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2654 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2655 &args, sizeof(args));
2656 }
2657
2658 target = V_008DFC_SQ_EXP_POS + 2;
2659 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2660 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2661 &args, sizeof(args));
2662
2663 /* Export the clip/cull distances values to the next stage. */
2664 radv_export_param(ctx, param_count, &slots[0], 0xf);
2665 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
2666 if (length > 4) {
2667 radv_export_param(ctx, param_count, &slots[4], 0xf);
2668 outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
2669 }
2670 }
2671
2672 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2673 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2674 for (unsigned j = 0; j < 4; j++)
2675 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2676 }
2677 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2678
2679 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2680 outinfo->writes_pointsize = true;
2681 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2682 }
2683
2684 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2685 outinfo->writes_layer = true;
2686 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2687 }
2688
2689 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2690 outinfo->writes_viewport_index = true;
2691 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2692 }
2693
2694 if (ctx->shader_info->info.so.num_outputs &&
2695 !ctx->is_gs_copy_shader) {
2696 /* The GS copy shader emission already emits streamout. */
2697 radv_emit_streamout(ctx, 0);
2698 }
2699
2700 if (outinfo->writes_pointsize ||
2701 outinfo->writes_layer ||
2702 outinfo->writes_viewport_index) {
2703 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2704 (outinfo->writes_layer == true ? 4 : 0));
2705 pos_args[1].valid_mask = 0;
2706 pos_args[1].done = 0;
2707 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2708 pos_args[1].compr = 0;
2709 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2710 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2711 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2712 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2713
2714 if (outinfo->writes_pointsize == true)
2715 pos_args[1].out[0] = psize_value;
2716 if (outinfo->writes_layer == true)
2717 pos_args[1].out[2] = layer_value;
2718 if (outinfo->writes_viewport_index == true) {
2719 if (ctx->options->chip_class >= GFX9) {
2720 /* GFX9 has the layer in out.z[10:0] and the viewport
2721 * index in out.z[19:16].
2722 */
2723 LLVMValueRef v = viewport_index_value;
2724 v = ac_to_integer(&ctx->ac, v);
2725 v = LLVMBuildShl(ctx->ac.builder, v,
2726 LLVMConstInt(ctx->ac.i32, 16, false),
2727 "");
2728 v = LLVMBuildOr(ctx->ac.builder, v,
2729 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2730
2731 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2732 pos_args[1].enabled_channels |= 1 << 2;
2733 } else {
2734 pos_args[1].out[3] = viewport_index_value;
2735 pos_args[1].enabled_channels |= 1 << 3;
2736 }
2737 }
2738 }
2739 for (i = 0; i < 4; i++) {
2740 if (pos_args[i].out[0])
2741 num_pos_exports++;
2742 }
2743
2744 pos_idx = 0;
2745 for (i = 0; i < 4; i++) {
2746 if (!pos_args[i].out[0])
2747 continue;
2748
2749 /* Specify the target we are exporting */
2750 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2751 if (pos_idx == num_pos_exports)
2752 pos_args[i].done = 1;
2753 ac_build_export(&ctx->ac, &pos_args[i]);
2754 }
2755
2756 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2757 LLVMValueRef values[4];
2758 if (!(ctx->output_mask & (1ull << i)))
2759 continue;
2760
2761 if (i != VARYING_SLOT_LAYER &&
2762 i != VARYING_SLOT_PRIMITIVE_ID &&
2763 i < VARYING_SLOT_VAR0)
2764 continue;
2765
2766 for (unsigned j = 0; j < 4; j++)
2767 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2768
2769 unsigned output_usage_mask;
2770
2771 if (ctx->stage == MESA_SHADER_VERTEX &&
2772 !ctx->is_gs_copy_shader) {
2773 output_usage_mask =
2774 ctx->shader_info->info.vs.output_usage_mask[i];
2775 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2776 output_usage_mask =
2777 ctx->shader_info->info.tes.output_usage_mask[i];
2778 } else {
2779 assert(ctx->is_gs_copy_shader);
2780 output_usage_mask =
2781 ctx->shader_info->info.gs.output_usage_mask[i];
2782 }
2783
2784 radv_export_param(ctx, param_count, values, output_usage_mask);
2785
2786 outinfo->vs_output_param_offset[i] = param_count++;
2787 }
2788
2789 if (export_prim_id) {
2790 LLVMValueRef values[4];
2791
2792 values[0] = ctx->vs_prim_id;
2793 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2794 ctx->shader_info->vs.vgpr_comp_cnt);
2795 for (unsigned j = 1; j < 4; j++)
2796 values[j] = ctx->ac.f32_0;
2797
2798 radv_export_param(ctx, param_count, values, 0x1);
2799
2800 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2801 outinfo->export_prim_id = true;
2802 }
2803
2804 if (export_layer_id && layer_value) {
2805 LLVMValueRef values[4];
2806
2807 values[0] = layer_value;
2808 for (unsigned j = 1; j < 4; j++)
2809 values[j] = ctx->ac.f32_0;
2810
2811 radv_export_param(ctx, param_count, values, 0x1);
2812
2813 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2814 }
2815
2816 outinfo->pos_exports = num_pos_exports;
2817 outinfo->param_exports = param_count;
2818 }
2819
2820 static void
2821 handle_es_outputs_post(struct radv_shader_context *ctx,
2822 struct radv_es_output_info *outinfo)
2823 {
2824 int j;
2825 uint64_t max_output_written = 0;
2826 LLVMValueRef lds_base = NULL;
2827
2828 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2829 unsigned output_usage_mask;
2830 int param_index;
2831 int length = 4;
2832
2833 if (!(ctx->output_mask & (1ull << i)))
2834 continue;
2835
2836 if (ctx->stage == MESA_SHADER_VERTEX) {
2837 output_usage_mask =
2838 ctx->shader_info->info.vs.output_usage_mask[i];
2839 } else {
2840 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2841 output_usage_mask =
2842 ctx->shader_info->info.tes.output_usage_mask[i];
2843 }
2844
2845 if (i == VARYING_SLOT_CLIP_DIST0)
2846 length = util_last_bit(output_usage_mask);
2847
2848 param_index = shader_io_get_unique_index(i);
2849
2850 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2851 }
2852
2853 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2854
2855 if (ctx->ac.chip_class >= GFX9) {
2856 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2857 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2858 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2859 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2860 LLVMBuildMul(ctx->ac.builder, wave_idx,
2861 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2862 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2863 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2864 }
2865
2866 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2867 LLVMValueRef dw_addr = NULL;
2868 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2869 unsigned output_usage_mask;
2870 int param_index;
2871 int length = 4;
2872
2873 if (!(ctx->output_mask & (1ull << i)))
2874 continue;
2875
2876 if (ctx->stage == MESA_SHADER_VERTEX) {
2877 output_usage_mask =
2878 ctx->shader_info->info.vs.output_usage_mask[i];
2879 } else {
2880 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2881 output_usage_mask =
2882 ctx->shader_info->info.tes.output_usage_mask[i];
2883 }
2884
2885 if (i == VARYING_SLOT_CLIP_DIST0)
2886 length = util_last_bit(output_usage_mask);
2887
2888 param_index = shader_io_get_unique_index(i);
2889
2890 if (lds_base) {
2891 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2892 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2893 "");
2894 }
2895
2896 for (j = 0; j < length; j++) {
2897 if (!(output_usage_mask & (1 << j)))
2898 continue;
2899
2900 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2901 out_val = ac_to_integer(&ctx->ac, out_val);
2902 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2903
2904 if (ctx->ac.chip_class >= GFX9) {
2905 LLVMValueRef dw_addr_offset =
2906 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2907 LLVMConstInt(ctx->ac.i32,
2908 j, false), "");
2909
2910 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2911 } else {
2912 ac_build_buffer_store_dword(&ctx->ac,
2913 ctx->esgs_ring,
2914 out_val, 1,
2915 NULL, ctx->es2gs_offset,
2916 (4 * param_index + j) * 4,
2917 1, 1, true, true);
2918 }
2919 }
2920 }
2921 }
2922
2923 static void
2924 handle_ls_outputs_post(struct radv_shader_context *ctx)
2925 {
2926 LLVMValueRef vertex_id = ctx->rel_auto_id;
2927 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2928 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2929 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2930 vertex_dw_stride, "");
2931
2932 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2933 unsigned output_usage_mask =
2934 ctx->shader_info->info.vs.output_usage_mask[i];
2935 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2936 int length = 4;
2937
2938 if (!(ctx->output_mask & (1ull << i)))
2939 continue;
2940
2941 if (i == VARYING_SLOT_CLIP_DIST0)
2942 length = util_last_bit(output_usage_mask);
2943
2944 int param = shader_io_get_unique_index(i);
2945 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2946 LLVMConstInt(ctx->ac.i32, param * 4, false),
2947 "");
2948 for (unsigned j = 0; j < length; j++) {
2949 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2950 value = ac_to_integer(&ctx->ac, value);
2951 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2952 ac_lds_store(&ctx->ac, dw_addr, value);
2953 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2954 }
2955 }
2956 }
2957
2958 static void
2959 write_tess_factors(struct radv_shader_context *ctx)
2960 {
2961 unsigned stride, outer_comps, inner_comps;
2962 struct ac_build_if_state if_ctx, inner_if_ctx;
2963 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2964 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2965 unsigned tess_inner_index = 0, tess_outer_index;
2966 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2967 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2968 int i;
2969 ac_emit_barrier(&ctx->ac, ctx->stage);
2970
2971 switch (ctx->options->key.tcs.primitive_mode) {
2972 case GL_ISOLINES:
2973 stride = 2;
2974 outer_comps = 2;
2975 inner_comps = 0;
2976 break;
2977 case GL_TRIANGLES:
2978 stride = 4;
2979 outer_comps = 3;
2980 inner_comps = 1;
2981 break;
2982 case GL_QUADS:
2983 stride = 6;
2984 outer_comps = 4;
2985 inner_comps = 2;
2986 break;
2987 default:
2988 return;
2989 }
2990
2991 ac_nir_build_if(&if_ctx, ctx,
2992 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2993 invocation_id, ctx->ac.i32_0, ""));
2994
2995 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2996
2997 if (inner_comps) {
2998 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2999 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3000 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3001 }
3002
3003 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3004 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3005 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3006
3007 for (i = 0; i < 4; i++) {
3008 inner[i] = LLVMGetUndef(ctx->ac.i32);
3009 outer[i] = LLVMGetUndef(ctx->ac.i32);
3010 }
3011
3012 // LINES reversal
3013 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
3014 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3015 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3016 ctx->ac.i32_1, "");
3017 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3018 } else {
3019 for (i = 0; i < outer_comps; i++) {
3020 outer[i] = out[i] =
3021 ac_lds_load(&ctx->ac, lds_outer);
3022 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3023 ctx->ac.i32_1, "");
3024 }
3025 for (i = 0; i < inner_comps; i++) {
3026 inner[i] = out[outer_comps+i] =
3027 ac_lds_load(&ctx->ac, lds_inner);
3028 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3029 ctx->ac.i32_1, "");
3030 }
3031 }
3032
3033 /* Convert the outputs to vectors for stores. */
3034 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3035 vec1 = NULL;
3036
3037 if (stride > 4)
3038 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3039
3040
3041 buffer = ctx->hs_ring_tess_factor;
3042 tf_base = ctx->tess_factor_offset;
3043 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3044 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3045 unsigned tf_offset = 0;
3046
3047 if (ctx->options->chip_class <= VI) {
3048 ac_nir_build_if(&inner_if_ctx, ctx,
3049 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3050 rel_patch_id, ctx->ac.i32_0, ""));
3051
3052 /* Store the dynamic HS control word. */
3053 ac_build_buffer_store_dword(&ctx->ac, buffer,
3054 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3055 1, ctx->ac.i32_0, tf_base,
3056 0, 1, 0, true, false);
3057 tf_offset += 4;
3058
3059 ac_nir_build_endif(&inner_if_ctx);
3060 }
3061
3062 /* Store the tessellation factors. */
3063 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3064 MIN2(stride, 4), byteoffset, tf_base,
3065 tf_offset, 1, 0, true, false);
3066 if (vec1)
3067 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3068 stride - 4, byteoffset, tf_base,
3069 16 + tf_offset, 1, 0, true, false);
3070
3071 //store to offchip for TES to read - only if TES reads them
3072 if (ctx->options->key.tcs.tes_reads_tess_factors) {
3073 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3074 LLVMValueRef tf_inner_offset;
3075 unsigned param_outer, param_inner;
3076
3077 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3078 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3079 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3080
3081 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3082 util_next_power_of_two(outer_comps));
3083
3084 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3085 outer_comps, tf_outer_offset,
3086 ctx->oc_lds, 0, 1, 0, true, false);
3087 if (inner_comps) {
3088 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3089 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3090 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3091
3092 inner_vec = inner_comps == 1 ? inner[0] :
3093 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3094 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3095 inner_comps, tf_inner_offset,
3096 ctx->oc_lds, 0, 1, 0, true, false);
3097 }
3098 }
3099 ac_nir_build_endif(&if_ctx);
3100 }
3101
3102 static void
3103 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3104 {
3105 write_tess_factors(ctx);
3106 }
3107
3108 static bool
3109 si_export_mrt_color(struct radv_shader_context *ctx,
3110 LLVMValueRef *color, unsigned index,
3111 struct ac_export_args *args)
3112 {
3113 /* Export */
3114 si_llvm_init_export_args(ctx, color, 0xf,
3115 V_008DFC_SQ_EXP_MRT + index, args);
3116 if (!args->enabled_channels)
3117 return false; /* unnecessary NULL export */
3118
3119 return true;
3120 }
3121
3122 static void
3123 radv_export_mrt_z(struct radv_shader_context *ctx,
3124 LLVMValueRef depth, LLVMValueRef stencil,
3125 LLVMValueRef samplemask)
3126 {
3127 struct ac_export_args args;
3128
3129 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3130
3131 ac_build_export(&ctx->ac, &args);
3132 }
3133
3134 static void
3135 handle_fs_outputs_post(struct radv_shader_context *ctx)
3136 {
3137 unsigned index = 0;
3138 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3139 struct ac_export_args color_args[8];
3140
3141 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3142 LLVMValueRef values[4];
3143
3144 if (!(ctx->output_mask & (1ull << i)))
3145 continue;
3146
3147 if (i < FRAG_RESULT_DATA0)
3148 continue;
3149
3150 for (unsigned j = 0; j < 4; j++)
3151 values[j] = ac_to_float(&ctx->ac,
3152 radv_load_output(ctx, i, j));
3153
3154 bool ret = si_export_mrt_color(ctx, values,
3155 i - FRAG_RESULT_DATA0,
3156 &color_args[index]);
3157 if (ret)
3158 index++;
3159 }
3160
3161 /* Process depth, stencil, samplemask. */
3162 if (ctx->shader_info->info.ps.writes_z) {
3163 depth = ac_to_float(&ctx->ac,
3164 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3165 }
3166 if (ctx->shader_info->info.ps.writes_stencil) {
3167 stencil = ac_to_float(&ctx->ac,
3168 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3169 }
3170 if (ctx->shader_info->info.ps.writes_sample_mask) {
3171 samplemask = ac_to_float(&ctx->ac,
3172 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3173 }
3174
3175 /* Set the DONE bit on last non-null color export only if Z isn't
3176 * exported.
3177 */
3178 if (index > 0 &&
3179 !ctx->shader_info->info.ps.writes_z &&
3180 !ctx->shader_info->info.ps.writes_stencil &&
3181 !ctx->shader_info->info.ps.writes_sample_mask) {
3182 unsigned last = index - 1;
3183
3184 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3185 color_args[last].done = 1; /* DONE bit */
3186 }
3187
3188 /* Export PS outputs. */
3189 for (unsigned i = 0; i < index; i++)
3190 ac_build_export(&ctx->ac, &color_args[i]);
3191
3192 if (depth || stencil || samplemask)
3193 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3194 else if (!index)
3195 ac_build_export_null(&ctx->ac);
3196 }
3197
3198 static void
3199 emit_gs_epilogue(struct radv_shader_context *ctx)
3200 {
3201 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3202 }
3203
3204 static void
3205 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3206 LLVMValueRef *addrs)
3207 {
3208 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3209
3210 switch (ctx->stage) {
3211 case MESA_SHADER_VERTEX:
3212 if (ctx->options->key.vs.as_ls)
3213 handle_ls_outputs_post(ctx);
3214 else if (ctx->options->key.vs.as_es)
3215 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3216 else
3217 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
3218 ctx->options->key.vs.export_layer_id,
3219 &ctx->shader_info->vs.outinfo);
3220 break;
3221 case MESA_SHADER_FRAGMENT:
3222 handle_fs_outputs_post(ctx);
3223 break;
3224 case MESA_SHADER_GEOMETRY:
3225 emit_gs_epilogue(ctx);
3226 break;
3227 case MESA_SHADER_TESS_CTRL:
3228 handle_tcs_outputs_post(ctx);
3229 break;
3230 case MESA_SHADER_TESS_EVAL:
3231 if (ctx->options->key.tes.as_es)
3232 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3233 else
3234 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
3235 ctx->options->key.tes.export_layer_id,
3236 &ctx->shader_info->tes.outinfo);
3237 break;
3238 default:
3239 break;
3240 }
3241 }
3242
3243 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3244 LLVMPassManagerRef passmgr,
3245 const struct radv_nir_compiler_options *options)
3246 {
3247 LLVMRunPassManager(passmgr, ctx->ac.module);
3248 LLVMDisposeBuilder(ctx->ac.builder);
3249
3250 ac_llvm_context_dispose(&ctx->ac);
3251 }
3252
3253 static void
3254 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3255 {
3256 struct radv_vs_output_info *outinfo;
3257
3258 switch (ctx->stage) {
3259 case MESA_SHADER_FRAGMENT:
3260 case MESA_SHADER_COMPUTE:
3261 case MESA_SHADER_TESS_CTRL:
3262 case MESA_SHADER_GEOMETRY:
3263 return;
3264 case MESA_SHADER_VERTEX:
3265 if (ctx->options->key.vs.as_ls ||
3266 ctx->options->key.vs.as_es)
3267 return;
3268 outinfo = &ctx->shader_info->vs.outinfo;
3269 break;
3270 case MESA_SHADER_TESS_EVAL:
3271 if (ctx->options->key.vs.as_es)
3272 return;
3273 outinfo = &ctx->shader_info->tes.outinfo;
3274 break;
3275 default:
3276 unreachable("Unhandled shader type");
3277 }
3278
3279 ac_optimize_vs_outputs(&ctx->ac,
3280 ctx->main_function,
3281 outinfo->vs_output_param_offset,
3282 VARYING_SLOT_MAX,
3283 &outinfo->param_exports);
3284 }
3285
3286 static void
3287 ac_setup_rings(struct radv_shader_context *ctx)
3288 {
3289 if (ctx->options->chip_class <= VI &&
3290 (ctx->stage == MESA_SHADER_GEOMETRY ||
3291 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3292 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3293 : RING_ESGS_VS;
3294 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3295
3296 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3297 ctx->ring_offsets,
3298 offset);
3299 }
3300
3301 if (ctx->is_gs_copy_shader) {
3302 ctx->gsvs_ring[0] =
3303 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3304 LLVMConstInt(ctx->ac.i32,
3305 RING_GSVS_VS, false));
3306 }
3307
3308 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3309 /* The conceptual layout of the GSVS ring is
3310 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3311 * but the real memory layout is swizzled across
3312 * threads:
3313 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3314 * t16v0c0 ..
3315 * Override the buffer descriptor accordingly.
3316 */
3317 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3318 uint64_t stream_offset = 0;
3319 unsigned num_records = 64;
3320 LLVMValueRef base_ring;
3321
3322 base_ring =
3323 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3324 LLVMConstInt(ctx->ac.i32,
3325 RING_GSVS_GS, false));
3326
3327 for (unsigned stream = 0; stream < 4; stream++) {
3328 unsigned num_components, stride;
3329 LLVMValueRef ring, tmp;
3330
3331 num_components =
3332 ctx->shader_info->info.gs.num_stream_output_components[stream];
3333
3334 if (!num_components)
3335 continue;
3336
3337 stride = 4 * num_components * ctx->gs_max_out_vertices;
3338
3339 /* Limit on the stride field for <= CIK. */
3340 assert(stride < (1 << 14));
3341
3342 ring = LLVMBuildBitCast(ctx->ac.builder,
3343 base_ring, v2i64, "");
3344 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3345 ring, ctx->ac.i32_0, "");
3346 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3347 LLVMConstInt(ctx->ac.i64,
3348 stream_offset, 0), "");
3349 ring = LLVMBuildInsertElement(ctx->ac.builder,
3350 ring, tmp, ctx->ac.i32_0, "");
3351
3352 stream_offset += stride * 64;
3353
3354 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3355 ctx->ac.v4i32, "");
3356
3357 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3358 ctx->ac.i32_1, "");
3359 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3360 LLVMConstInt(ctx->ac.i32,
3361 S_008F04_STRIDE(stride), false), "");
3362 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3363 ctx->ac.i32_1, "");
3364
3365 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3366 LLVMConstInt(ctx->ac.i32,
3367 num_records, false),
3368 LLVMConstInt(ctx->ac.i32, 2, false), "");
3369
3370 ctx->gsvs_ring[stream] = ring;
3371 }
3372 }
3373
3374 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3375 ctx->stage == MESA_SHADER_TESS_EVAL) {
3376 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3377 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3378 }
3379 }
3380
3381 static unsigned
3382 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3383 const struct nir_shader *nir)
3384 {
3385 switch (nir->info.stage) {
3386 case MESA_SHADER_TESS_CTRL:
3387 return chip_class >= CIK ? 128 : 64;
3388 case MESA_SHADER_GEOMETRY:
3389 return chip_class >= GFX9 ? 128 : 64;
3390 case MESA_SHADER_COMPUTE:
3391 break;
3392 default:
3393 return 0;
3394 }
3395
3396 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3397 nir->info.cs.local_size[1] *
3398 nir->info.cs.local_size[2];
3399 return max_workgroup_size;
3400 }
3401
3402 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3403 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3404 {
3405 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3406 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3407 ctx->ac.i32_0, "");
3408 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3409 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3410 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3411 }
3412
3413 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3414 {
3415 for(int i = 5; i >= 0; --i) {
3416 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3417 (i & 1) * 16, 16);
3418 }
3419
3420 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
3421 }
3422
3423
3424 static
3425 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3426 struct nir_shader *const *shaders,
3427 int shader_count,
3428 struct radv_shader_variant_info *shader_info,
3429 const struct radv_nir_compiler_options *options)
3430 {
3431 struct radv_shader_context ctx = {0};
3432 unsigned i;
3433 ctx.options = options;
3434 ctx.shader_info = shader_info;
3435
3436 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3437 ctx.context = ctx.ac.context;
3438 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3439
3440 enum ac_float_mode float_mode =
3441 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3442 AC_FLOAT_MODE_DEFAULT;
3443
3444 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3445
3446 memset(shader_info, 0, sizeof(*shader_info));
3447
3448 for(int i = 0; i < shader_count; ++i)
3449 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3450
3451 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3452 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3453 for (i = 0; i < AC_UD_MAX_UD; i++)
3454 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3455
3456 ctx.max_workgroup_size = 0;
3457 for (int i = 0; i < shader_count; ++i) {
3458 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3459 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3460 shaders[i]));
3461 }
3462
3463 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3464 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3465
3466 ctx.abi.inputs = &ctx.inputs[0];
3467 ctx.abi.emit_outputs = handle_shader_outputs_post;
3468 ctx.abi.emit_vertex = visit_emit_vertex;
3469 ctx.abi.load_ubo = radv_load_ubo;
3470 ctx.abi.load_ssbo = radv_load_ssbo;
3471 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3472 ctx.abi.load_resource = radv_load_resource;
3473 ctx.abi.clamp_shadow_reference = false;
3474 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;
3475
3476 if (shader_count >= 2)
3477 ac_init_exec_full_mask(&ctx.ac);
3478
3479 if (ctx.ac.chip_class == GFX9 &&
3480 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3481 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3482
3483 for(int i = 0; i < shader_count; ++i) {
3484 ctx.stage = shaders[i]->info.stage;
3485 ctx.output_mask = 0;
3486
3487 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3488 for (int i = 0; i < 4; i++) {
3489 ctx.gs_next_vertex[i] =
3490 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3491 }
3492 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3493 ctx.abi.load_inputs = load_gs_input;
3494 ctx.abi.emit_primitive = visit_end_primitive;
3495 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3496 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3497 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3498 ctx.abi.load_tess_varyings = load_tcs_varyings;
3499 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3500 ctx.abi.store_tcs_outputs = store_tcs_output;
3501 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3502 if (shader_count == 1)
3503 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3504 else
3505 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3506 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3507 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3508 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3509 ctx.abi.load_tess_varyings = load_tes_input;
3510 ctx.abi.load_tess_coord = load_tess_coord;
3511 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3512 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3513 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3514 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3515 if (shader_info->info.vs.needs_instance_id) {
3516 if (ctx.options->key.vs.as_ls) {
3517 ctx.shader_info->vs.vgpr_comp_cnt =
3518 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3519 } else {
3520 ctx.shader_info->vs.vgpr_comp_cnt =
3521 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3522 }
3523 }
3524 ctx.abi.load_base_vertex = radv_load_base_vertex;
3525 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3526 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3527 ctx.abi.lookup_interp_param = lookup_interp_param;
3528 ctx.abi.load_sample_position = load_sample_position;
3529 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3530 ctx.abi.emit_kill = radv_emit_kill;
3531 }
3532
3533 if (i)
3534 ac_emit_barrier(&ctx.ac, ctx.stage);
3535
3536 nir_foreach_variable(variable, &shaders[i]->outputs)
3537 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3538
3539 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3540 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3541 shaders[i]->info.cull_distance_array_size > 4;
3542 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3543 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3544 shaders[i]->info.gs.vertices_out;
3545 }
3546
3547 ac_setup_rings(&ctx);
3548
3549 LLVMBasicBlockRef merge_block;
3550 if (shader_count >= 2) {
3551 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3552 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3553 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3554
3555 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
3556 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3557 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3558 thread_id, count, "");
3559 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3560
3561 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3562 }
3563
3564 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3565 handle_fs_inputs(&ctx, shaders[i]);
3566 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3567 handle_vs_inputs(&ctx, shaders[i]);
3568 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3569 prepare_gs_input_vgprs(&ctx);
3570
3571 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3572
3573 if (shader_count >= 2) {
3574 LLVMBuildBr(ctx.ac.builder, merge_block);
3575 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3576 }
3577
3578 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3579 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3580 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3581 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3582 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3583 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3584 }
3585 }
3586
3587 LLVMBuildRetVoid(ctx.ac.builder);
3588
3589 if (options->dump_preoptir)
3590 ac_dump_module(ctx.ac.module);
3591
3592 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3593
3594 if (shader_count == 1)
3595 ac_nir_eliminate_const_vs_outputs(&ctx);
3596
3597 if (options->dump_shader) {
3598 ctx.shader_info->private_mem_vgprs =
3599 ac_count_scratch_private_memory(ctx.main_function);
3600 }
3601
3602 return ctx.ac.module;
3603 }
3604
3605 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3606 {
3607 unsigned *retval = (unsigned *)context;
3608 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3609 char *description = LLVMGetDiagInfoDescription(di);
3610
3611 if (severity == LLVMDSError) {
3612 *retval = 1;
3613 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3614 description);
3615 }
3616
3617 LLVMDisposeMessage(description);
3618 }
3619
3620 static unsigned ac_llvm_compile(LLVMModuleRef M,
3621 struct ac_shader_binary *binary,
3622 struct ac_llvm_compiler *ac_llvm)
3623 {
3624 unsigned retval = 0;
3625 LLVMContextRef llvm_ctx;
3626
3627 /* Setup Diagnostic Handler*/
3628 llvm_ctx = LLVMGetModuleContext(M);
3629
3630 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3631 &retval);
3632
3633 /* Compile IR*/
3634 if (!radv_compile_to_binary(ac_llvm, M, binary))
3635 retval = 1;
3636 return retval;
3637 }
3638
3639 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
3640 LLVMModuleRef llvm_module,
3641 struct ac_shader_binary *binary,
3642 struct ac_shader_config *config,
3643 struct radv_shader_variant_info *shader_info,
3644 gl_shader_stage stage,
3645 const struct radv_nir_compiler_options *options)
3646 {
3647 if (options->dump_shader)
3648 ac_dump_module(llvm_module);
3649
3650 memset(binary, 0, sizeof(*binary));
3651
3652 if (options->record_llvm_ir) {
3653 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3654 binary->llvm_ir_string = strdup(llvm_ir);
3655 LLVMDisposeMessage(llvm_ir);
3656 }
3657
3658 int v = ac_llvm_compile(llvm_module, binary, ac_llvm);
3659 if (v) {
3660 fprintf(stderr, "compile failed\n");
3661 }
3662
3663 if (options->dump_shader)
3664 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3665
3666 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3667
3668 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3669 LLVMDisposeModule(llvm_module);
3670 LLVMContextDispose(ctx);
3671
3672 if (stage == MESA_SHADER_FRAGMENT) {
3673 shader_info->num_input_vgprs = 0;
3674 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3675 shader_info->num_input_vgprs += 2;
3676 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3677 shader_info->num_input_vgprs += 2;
3678 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3679 shader_info->num_input_vgprs += 2;
3680 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3681 shader_info->num_input_vgprs += 3;
3682 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3683 shader_info->num_input_vgprs += 2;
3684 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3685 shader_info->num_input_vgprs += 2;
3686 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3687 shader_info->num_input_vgprs += 2;
3688 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3689 shader_info->num_input_vgprs += 1;
3690 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3691 shader_info->num_input_vgprs += 1;
3692 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3693 shader_info->num_input_vgprs += 1;
3694 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3695 shader_info->num_input_vgprs += 1;
3696 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3697 shader_info->num_input_vgprs += 1;
3698 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3699 shader_info->num_input_vgprs += 1;
3700 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3701 shader_info->num_input_vgprs += 1;
3702 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3703 shader_info->num_input_vgprs += 1;
3704 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3705 shader_info->num_input_vgprs += 1;
3706 }
3707 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3708
3709 /* +3 for scratch wave offset and VCC */
3710 config->num_sgprs = MAX2(config->num_sgprs,
3711 shader_info->num_input_sgprs + 3);
3712
3713 /* Enable 64-bit and 16-bit denormals, because there is no performance
3714 * cost.
3715 *
3716 * If denormals are enabled, all floating-point output modifiers are
3717 * ignored.
3718 *
3719 * Don't enable denormals for 32-bit floats, because:
3720 * - Floating-point output modifiers would be ignored by the hw.
3721 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3722 * have to stop using those.
3723 * - SI & CI would be very slow.
3724 */
3725 config->float_mode |= V_00B028_FP_64_DENORMS;
3726 }
3727
3728 static void
3729 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3730 {
3731 switch (nir->info.stage) {
3732 case MESA_SHADER_COMPUTE:
3733 for (int i = 0; i < 3; ++i)
3734 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3735 break;
3736 case MESA_SHADER_FRAGMENT:
3737 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3738 break;
3739 case MESA_SHADER_GEOMETRY:
3740 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3741 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3742 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3743 shader_info->gs.invocations = nir->info.gs.invocations;
3744 break;
3745 case MESA_SHADER_TESS_EVAL:
3746 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3747 shader_info->tes.spacing = nir->info.tess.spacing;
3748 shader_info->tes.ccw = nir->info.tess.ccw;
3749 shader_info->tes.point_mode = nir->info.tess.point_mode;
3750 shader_info->tes.as_es = options->key.tes.as_es;
3751 break;
3752 case MESA_SHADER_TESS_CTRL:
3753 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3754 break;
3755 case MESA_SHADER_VERTEX:
3756 shader_info->vs.as_es = options->key.vs.as_es;
3757 shader_info->vs.as_ls = options->key.vs.as_ls;
3758 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3759 if (options->key.vs.as_ls)
3760 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3761 break;
3762 default:
3763 break;
3764 }
3765 }
3766
3767 void
3768 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
3769 struct ac_shader_binary *binary,
3770 struct ac_shader_config *config,
3771 struct radv_shader_variant_info *shader_info,
3772 struct nir_shader *const *nir,
3773 int nir_count,
3774 const struct radv_nir_compiler_options *options)
3775 {
3776
3777 LLVMModuleRef llvm_module;
3778
3779 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
3780 options);
3781
3782 ac_compile_llvm_module(ac_llvm, llvm_module, binary, config, shader_info,
3783 nir[0]->info.stage, options);
3784
3785 for (int i = 0; i < nir_count; ++i)
3786 ac_fill_shader_info(shader_info, nir[i], options);
3787
3788 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3789 if (options->chip_class == GFX9) {
3790 if (nir_count == 2 &&
3791 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3792 shader_info->gs.es_type = nir[0]->info.stage;
3793 }
3794 }
3795 }
3796
3797 static void
3798 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3799 {
3800 LLVMValueRef vtx_offset =
3801 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3802 LLVMConstInt(ctx->ac.i32, 4, false), "");
3803 LLVMValueRef stream_id;
3804
3805 /* Fetch the vertex stream ID. */
3806 if (ctx->shader_info->info.so.num_outputs) {
3807 stream_id =
3808 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
3809 } else {
3810 stream_id = ctx->ac.i32_0;
3811 }
3812
3813 LLVMBasicBlockRef end_bb;
3814 LLVMValueRef switch_inst;
3815
3816 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
3817 ctx->main_function, "end");
3818 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
3819
3820 for (unsigned stream = 0; stream < 4; stream++) {
3821 unsigned num_components =
3822 ctx->shader_info->info.gs.num_stream_output_components[stream];
3823 LLVMBasicBlockRef bb;
3824 unsigned offset;
3825
3826 if (!num_components)
3827 continue;
3828
3829 if (stream > 0 && !ctx->shader_info->info.so.num_outputs)
3830 continue;
3831
3832 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
3833 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
3834 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
3835
3836 offset = 0;
3837 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3838 unsigned output_usage_mask =
3839 ctx->shader_info->info.gs.output_usage_mask[i];
3840 unsigned output_stream =
3841 ctx->shader_info->info.gs.output_streams[i];
3842 int length = util_last_bit(output_usage_mask);
3843
3844 if (!(ctx->output_mask & (1ull << i)) ||
3845 output_stream != stream)
3846 continue;
3847
3848 for (unsigned j = 0; j < length; j++) {
3849 LLVMValueRef value, soffset;
3850
3851 if (!(output_usage_mask & (1 << j)))
3852 continue;
3853
3854 soffset = LLVMConstInt(ctx->ac.i32,
3855 offset *
3856 ctx->gs_max_out_vertices * 16 * 4, false);
3857
3858 offset++;
3859
3860 value = ac_build_buffer_load(&ctx->ac,
3861 ctx->gsvs_ring[0],
3862 1, ctx->ac.i32_0,
3863 vtx_offset, soffset,
3864 0, 1, 1, true, false);
3865
3866 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3867 if (ac_get_type_size(type) == 2) {
3868 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
3869 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
3870 }
3871
3872 LLVMBuildStore(ctx->ac.builder,
3873 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3874 }
3875 }
3876
3877 if (ctx->shader_info->info.so.num_outputs)
3878 radv_emit_streamout(ctx, stream);
3879
3880 if (stream == 0) {
3881 handle_vs_outputs_post(ctx, false, false,
3882 &ctx->shader_info->vs.outinfo);
3883 }
3884
3885 LLVMBuildBr(ctx->ac.builder, end_bb);
3886 }
3887
3888 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
3889 }
3890
3891 void
3892 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
3893 struct nir_shader *geom_shader,
3894 struct ac_shader_binary *binary,
3895 struct ac_shader_config *config,
3896 struct radv_shader_variant_info *shader_info,
3897 const struct radv_nir_compiler_options *options)
3898 {
3899 struct radv_shader_context ctx = {0};
3900 ctx.options = options;
3901 ctx.shader_info = shader_info;
3902
3903 ac_llvm_context_init(&ctx.ac, options->chip_class, options->family);
3904 ctx.context = ctx.ac.context;
3905 ctx.ac.module = ac_create_module(ac_llvm->tm, ctx.context);
3906
3907 ctx.is_gs_copy_shader = true;
3908
3909 enum ac_float_mode float_mode =
3910 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3911 AC_FLOAT_MODE_DEFAULT;
3912
3913 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3914 ctx.stage = MESA_SHADER_VERTEX;
3915
3916 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3917
3918 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3919
3920 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3921 ac_setup_rings(&ctx);
3922
3923 nir_foreach_variable(variable, &geom_shader->outputs) {
3924 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3925 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3926 variable, MESA_SHADER_VERTEX);
3927 }
3928
3929 ac_gs_copy_shader_emit(&ctx);
3930
3931 LLVMBuildRetVoid(ctx.ac.builder);
3932
3933 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
3934
3935 ac_compile_llvm_module(ac_llvm, ctx.ac.module, binary, config, shader_info,
3936 MESA_SHADER_VERTEX, options);
3937 }