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[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "nir/nir.h"
31
32 #include <llvm-c/Core.h>
33 #include <llvm-c/TargetMachine.h>
34 #include <llvm-c/Transforms/Scalar.h>
35 #if HAVE_LLVM >= 0x0700
36 #include <llvm-c/Transforms/Utils.h>
37 #endif
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_llvm_build.h"
44 #include "ac_shader_abi.h"
45 #include "ac_shader_util.h"
46 #include "ac_exp_param.h"
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct radv_shader_context {
51 struct ac_llvm_context ac;
52 const struct radv_nir_compiler_options *options;
53 struct radv_shader_variant_info *shader_info;
54 struct ac_shader_abi abi;
55
56 unsigned max_workgroup_size;
57 LLVMContextRef context;
58 LLVMValueRef main_function;
59
60 LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
61 LLVMValueRef ring_offsets;
62
63 LLVMValueRef vertex_buffers;
64 LLVMValueRef rel_auto_id;
65 LLVMValueRef vs_prim_id;
66 LLVMValueRef es2gs_offset;
67
68 LLVMValueRef oc_lds;
69 LLVMValueRef merged_wave_info;
70 LLVMValueRef tess_factor_offset;
71 LLVMValueRef tes_rel_patch_id;
72 LLVMValueRef tes_u;
73 LLVMValueRef tes_v;
74
75 LLVMValueRef gs2vs_offset;
76 LLVMValueRef gs_wave_id;
77 LLVMValueRef gs_vtx_offset[6];
78
79 LLVMValueRef esgs_ring;
80 LLVMValueRef gsvs_ring;
81 LLVMValueRef hs_ring_tess_offchip;
82 LLVMValueRef hs_ring_tess_factor;
83
84 LLVMValueRef sample_pos_offset;
85 LLVMValueRef persp_sample, persp_center, persp_centroid;
86 LLVMValueRef linear_sample, linear_center, linear_centroid;
87
88 gl_shader_stage stage;
89
90 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
91
92 uint64_t input_mask;
93 uint64_t output_mask;
94 uint8_t num_output_clips;
95 uint8_t num_output_culls;
96
97 bool is_gs_copy_shader;
98 LLVMValueRef gs_next_vertex;
99 unsigned gs_max_out_vertices;
100
101 unsigned tes_primitive_mode;
102
103 uint32_t tcs_patch_outputs_read;
104 uint64_t tcs_outputs_read;
105 uint32_t tcs_vertices_per_patch;
106 uint32_t tcs_num_inputs;
107 uint32_t tcs_num_patches;
108 uint32_t max_gsvs_emit_size;
109 uint32_t gsvs_vertex_size;
110 };
111
112 enum radeon_llvm_calling_convention {
113 RADEON_LLVM_AMDGPU_VS = 87,
114 RADEON_LLVM_AMDGPU_GS = 88,
115 RADEON_LLVM_AMDGPU_PS = 89,
116 RADEON_LLVM_AMDGPU_CS = 90,
117 RADEON_LLVM_AMDGPU_HS = 93,
118 };
119
120 static inline struct radv_shader_context *
121 radv_shader_context_from_abi(struct ac_shader_abi *abi)
122 {
123 struct radv_shader_context *ctx = NULL;
124 return container_of(abi, ctx, abi);
125 }
126
127 struct ac_build_if_state
128 {
129 struct radv_shader_context *ctx;
130 LLVMValueRef condition;
131 LLVMBasicBlockRef entry_block;
132 LLVMBasicBlockRef true_block;
133 LLVMBasicBlockRef false_block;
134 LLVMBasicBlockRef merge_block;
135 };
136
137 static LLVMBasicBlockRef
138 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
139 {
140 LLVMBasicBlockRef current_block;
141 LLVMBasicBlockRef next_block;
142 LLVMBasicBlockRef new_block;
143
144 /* get current basic block */
145 current_block = LLVMGetInsertBlock(ctx->ac.builder);
146
147 /* chqeck if there's another block after this one */
148 next_block = LLVMGetNextBasicBlock(current_block);
149 if (next_block) {
150 /* insert the new block before the next block */
151 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
152 }
153 else {
154 /* append new block after current block */
155 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
156 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
157 }
158 return new_block;
159 }
160
161 static void
162 ac_nir_build_if(struct ac_build_if_state *ifthen,
163 struct radv_shader_context *ctx,
164 LLVMValueRef condition)
165 {
166 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
167
168 memset(ifthen, 0, sizeof *ifthen);
169 ifthen->ctx = ctx;
170 ifthen->condition = condition;
171 ifthen->entry_block = block;
172
173 /* create endif/merge basic block for the phi functions */
174 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
175
176 /* create/insert true_block before merge_block */
177 ifthen->true_block =
178 LLVMInsertBasicBlockInContext(ctx->context,
179 ifthen->merge_block,
180 "if-true-block");
181
182 /* successive code goes into the true block */
183 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
184 }
185
186 /**
187 * End a conditional.
188 */
189 static void
190 ac_nir_build_endif(struct ac_build_if_state *ifthen)
191 {
192 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
193
194 /* Insert branch to the merge block from current block */
195 LLVMBuildBr(builder, ifthen->merge_block);
196
197 /*
198 * Now patch in the various branch instructions.
199 */
200
201 /* Insert the conditional branch instruction at the end of entry_block */
202 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
203 if (ifthen->false_block) {
204 /* we have an else clause */
205 LLVMBuildCondBr(builder, ifthen->condition,
206 ifthen->true_block, ifthen->false_block);
207 }
208 else {
209 /* no else clause */
210 LLVMBuildCondBr(builder, ifthen->condition,
211 ifthen->true_block, ifthen->merge_block);
212 }
213
214 /* Resume building code at end of the ifthen->merge_block */
215 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
216 }
217
218
219 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
220 {
221 switch (ctx->stage) {
222 case MESA_SHADER_TESS_CTRL:
223 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
224 case MESA_SHADER_TESS_EVAL:
225 return ctx->tes_rel_patch_id;
226 break;
227 default:
228 unreachable("Illegal stage");
229 }
230 }
231
232 static unsigned
233 get_tcs_num_patches(struct radv_shader_context *ctx)
234 {
235 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
236 unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
237 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
238 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
239 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
240 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
241 uint32_t output_vertex_size = num_tcs_outputs * 16;
242 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
243 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
244 unsigned num_patches;
245 unsigned hardware_lds_size;
246
247 /* Ensure that we only need one wave per SIMD so we don't need to check
248 * resource usage. Also ensures that the number of tcs in and out
249 * vertices per threadgroup are at most 256.
250 */
251 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
252 /* Make sure that the data fits in LDS. This assumes the shaders only
253 * use LDS for the inputs and outputs.
254 */
255 hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
256 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
257 /* Make sure the output data fits in the offchip buffer */
258 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
259 /* Not necessary for correctness, but improves performance. The
260 * specific value is taken from the proprietary driver.
261 */
262 num_patches = MIN2(num_patches, 40);
263
264 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
265 if (ctx->options->chip_class == SI) {
266 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
267 num_patches = MIN2(num_patches, one_wave);
268 }
269 return num_patches;
270 }
271
272 static unsigned
273 calculate_tess_lds_size(struct radv_shader_context *ctx)
274 {
275 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
276 unsigned num_tcs_output_cp;
277 unsigned num_tcs_outputs, num_tcs_patch_outputs;
278 unsigned input_vertex_size, output_vertex_size;
279 unsigned input_patch_size, output_patch_size;
280 unsigned pervertex_output_patch_size;
281 unsigned output_patch0_offset;
282 unsigned num_patches;
283 unsigned lds_size;
284
285 num_tcs_output_cp = ctx->tcs_vertices_per_patch;
286 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
287 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
288
289 input_vertex_size = ctx->tcs_num_inputs * 16;
290 output_vertex_size = num_tcs_outputs * 16;
291
292 input_patch_size = num_tcs_input_cp * input_vertex_size;
293
294 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
295 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
296
297 num_patches = ctx->tcs_num_patches;
298 output_patch0_offset = input_patch_size * num_patches;
299
300 lds_size = output_patch0_offset + output_patch_size * num_patches;
301 return lds_size;
302 }
303
304 /* Tessellation shaders pass outputs to the next shader using LDS.
305 *
306 * LS outputs = TCS inputs
307 * TCS outputs = TES inputs
308 *
309 * The LDS layout is:
310 * - TCS inputs for patch 0
311 * - TCS inputs for patch 1
312 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
313 * - ...
314 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
315 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
316 * - TCS outputs for patch 1
317 * - Per-patch TCS outputs for patch 1
318 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
319 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
320 * - ...
321 *
322 * All three shaders VS(LS), TCS, TES share the same LDS space.
323 */
324 static LLVMValueRef
325 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
326 {
327 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
328 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
329 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
330
331 input_patch_size /= 4;
332 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
333 }
334
335 static LLVMValueRef
336 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
337 {
338 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
339 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
340 uint32_t output_vertex_size = num_tcs_outputs * 16;
341 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
342 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
343 output_patch_size /= 4;
344 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
345 }
346
347 static LLVMValueRef
348 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
349 {
350 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
351 uint32_t output_vertex_size = num_tcs_outputs * 16;
352 output_vertex_size /= 4;
353 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
354 }
355
356 static LLVMValueRef
357 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
358 {
359 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
360 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
361 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
362 uint32_t output_patch0_offset = input_patch_size;
363 unsigned num_patches = ctx->tcs_num_patches;
364
365 output_patch0_offset *= num_patches;
366 output_patch0_offset /= 4;
367 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
368 }
369
370 static LLVMValueRef
371 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
372 {
373 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
374 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
375 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
376 uint32_t output_patch0_offset = input_patch_size;
377
378 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
379 uint32_t output_vertex_size = num_tcs_outputs * 16;
380 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
381 unsigned num_patches = ctx->tcs_num_patches;
382
383 output_patch0_offset *= num_patches;
384 output_patch0_offset += pervertex_output_patch_size;
385 output_patch0_offset /= 4;
386 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
387 }
388
389 static LLVMValueRef
390 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
391 {
392 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
393 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
394
395 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
396 }
397
398 static LLVMValueRef
399 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
400 {
401 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
402 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
403 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
404
405 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
406 LLVMBuildMul(ctx->ac.builder, patch_stride,
407 rel_patch_id, ""),
408 "");
409 }
410
411 static LLVMValueRef
412 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
413 {
414 LLVMValueRef patch0_patch_data_offset =
415 get_tcs_out_patch0_patch_data_offset(ctx);
416 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
417 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
418
419 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
420 LLVMBuildMul(ctx->ac.builder, patch_stride,
421 rel_patch_id, ""),
422 "");
423 }
424
425 #define MAX_ARGS 23
426 struct arg_info {
427 LLVMTypeRef types[MAX_ARGS];
428 LLVMValueRef *assign[MAX_ARGS];
429 unsigned array_params_mask;
430 uint8_t count;
431 uint8_t sgpr_count;
432 uint8_t num_sgprs_used;
433 uint8_t num_vgprs_used;
434 };
435
436 enum ac_arg_regfile {
437 ARG_SGPR,
438 ARG_VGPR,
439 };
440
441 static void
442 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
443 LLVMValueRef *param_ptr)
444 {
445 assert(info->count < MAX_ARGS);
446
447 info->assign[info->count] = param_ptr;
448 info->types[info->count] = type;
449 info->count++;
450
451 if (regfile == ARG_SGPR) {
452 info->num_sgprs_used += ac_get_type_size(type) / 4;
453 info->sgpr_count++;
454 } else {
455 assert(regfile == ARG_VGPR);
456 info->num_vgprs_used += ac_get_type_size(type) / 4;
457 }
458 }
459
460 static inline void
461 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
462 {
463 info->array_params_mask |= (1 << info->count);
464 add_arg(info, ARG_SGPR, type, param_ptr);
465 }
466
467 static void assign_arguments(LLVMValueRef main_function,
468 struct arg_info *info)
469 {
470 unsigned i;
471 for (i = 0; i < info->count; i++) {
472 if (info->assign[i])
473 *info->assign[i] = LLVMGetParam(main_function, i);
474 }
475 }
476
477 static LLVMValueRef
478 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
479 LLVMBuilderRef builder, LLVMTypeRef *return_types,
480 unsigned num_return_elems,
481 struct arg_info *args,
482 unsigned max_workgroup_size,
483 const struct radv_nir_compiler_options *options)
484 {
485 LLVMTypeRef main_function_type, ret_type;
486 LLVMBasicBlockRef main_function_body;
487
488 if (num_return_elems)
489 ret_type = LLVMStructTypeInContext(ctx, return_types,
490 num_return_elems, true);
491 else
492 ret_type = LLVMVoidTypeInContext(ctx);
493
494 /* Setup the function */
495 main_function_type =
496 LLVMFunctionType(ret_type, args->types, args->count, 0);
497 LLVMValueRef main_function =
498 LLVMAddFunction(module, "main", main_function_type);
499 main_function_body =
500 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
501 LLVMPositionBuilderAtEnd(builder, main_function_body);
502
503 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
504 for (unsigned i = 0; i < args->sgpr_count; ++i) {
505 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
506
507 if (args->array_params_mask & (1 << i)) {
508 LLVMValueRef P = LLVMGetParam(main_function, i);
509 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
510 ac_add_attr_dereferenceable(P, UINT64_MAX);
511 }
512 }
513
514 if (options->address32_hi) {
515 ac_llvm_add_target_dep_function_attr(main_function,
516 "amdgpu-32bit-address-high-bits",
517 options->address32_hi);
518 }
519
520 if (max_workgroup_size) {
521 ac_llvm_add_target_dep_function_attr(main_function,
522 "amdgpu-max-work-group-size",
523 max_workgroup_size);
524 }
525 if (options->unsafe_math) {
526 /* These were copied from some LLVM test. */
527 LLVMAddTargetDependentFunctionAttr(main_function,
528 "less-precise-fpmad",
529 "true");
530 LLVMAddTargetDependentFunctionAttr(main_function,
531 "no-infs-fp-math",
532 "true");
533 LLVMAddTargetDependentFunctionAttr(main_function,
534 "no-nans-fp-math",
535 "true");
536 LLVMAddTargetDependentFunctionAttr(main_function,
537 "unsafe-fp-math",
538 "true");
539 LLVMAddTargetDependentFunctionAttr(main_function,
540 "no-signed-zeros-fp-math",
541 "true");
542 }
543 return main_function;
544 }
545
546
547 static void
548 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
549 uint32_t indirect_offset)
550 {
551 ud_info->sgpr_idx = *sgpr_idx;
552 ud_info->num_sgprs = num_sgprs;
553 ud_info->indirect = indirect_offset > 0;
554 ud_info->indirect_offset = indirect_offset;
555 *sgpr_idx += num_sgprs;
556 }
557
558 static void
559 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
560 uint8_t num_sgprs)
561 {
562 struct radv_userdata_info *ud_info =
563 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
564 assert(ud_info);
565
566 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
567 }
568
569 static void
570 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
571 {
572 set_loc_shader(ctx, idx, sgpr_idx, 2);
573 }
574
575 static void
576 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
577 uint32_t indirect_offset)
578 {
579 struct radv_userdata_info *ud_info =
580 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
581 assert(ud_info);
582
583 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
584 }
585
586 struct user_sgpr_info {
587 bool need_ring_offsets;
588 uint8_t sgpr_count;
589 bool indirect_all_descriptor_sets;
590 };
591
592 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
593 gl_shader_stage stage)
594 {
595 switch (stage) {
596 case MESA_SHADER_VERTEX:
597 if (ctx->shader_info->info.needs_multiview_view_index ||
598 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
599 return true;
600 break;
601 case MESA_SHADER_TESS_EVAL:
602 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
603 return true;
604 break;
605 case MESA_SHADER_GEOMETRY:
606 case MESA_SHADER_TESS_CTRL:
607 if (ctx->shader_info->info.needs_multiview_view_index)
608 return true;
609 break;
610 default:
611 break;
612 }
613 return false;
614 }
615
616 static uint8_t
617 count_vs_user_sgprs(struct radv_shader_context *ctx)
618 {
619 uint8_t count = 0;
620
621 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
622 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
623
624 return count;
625 }
626
627 static void allocate_user_sgprs(struct radv_shader_context *ctx,
628 gl_shader_stage stage,
629 bool has_previous_stage,
630 gl_shader_stage previous_stage,
631 bool needs_view_index,
632 struct user_sgpr_info *user_sgpr_info)
633 {
634 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
635
636 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
637 if (stage == MESA_SHADER_GEOMETRY ||
638 stage == MESA_SHADER_VERTEX ||
639 stage == MESA_SHADER_TESS_CTRL ||
640 stage == MESA_SHADER_TESS_EVAL ||
641 ctx->is_gs_copy_shader)
642 user_sgpr_info->need_ring_offsets = true;
643
644 if (stage == MESA_SHADER_FRAGMENT &&
645 ctx->shader_info->info.ps.needs_sample_positions)
646 user_sgpr_info->need_ring_offsets = true;
647
648 /* 2 user sgprs will nearly always be allocated for scratch/rings */
649 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
650 user_sgpr_info->sgpr_count += 2;
651 }
652
653 switch (stage) {
654 case MESA_SHADER_COMPUTE:
655 if (ctx->shader_info->info.cs.uses_grid_size)
656 user_sgpr_info->sgpr_count += 3;
657 break;
658 case MESA_SHADER_FRAGMENT:
659 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
660 break;
661 case MESA_SHADER_VERTEX:
662 if (!ctx->is_gs_copy_shader)
663 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
664 break;
665 case MESA_SHADER_TESS_CTRL:
666 if (has_previous_stage) {
667 if (previous_stage == MESA_SHADER_VERTEX)
668 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
669 }
670 break;
671 case MESA_SHADER_TESS_EVAL:
672 break;
673 case MESA_SHADER_GEOMETRY:
674 if (has_previous_stage) {
675 if (previous_stage == MESA_SHADER_VERTEX) {
676 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
677 }
678 }
679 break;
680 default:
681 break;
682 }
683
684 if (needs_view_index)
685 user_sgpr_info->sgpr_count++;
686
687 if (ctx->shader_info->info.loads_push_constants)
688 user_sgpr_info->sgpr_count += 2;
689
690 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
691 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
692
693 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
694 user_sgpr_info->sgpr_count += 2;
695 user_sgpr_info->indirect_all_descriptor_sets = true;
696 } else {
697 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
698 }
699 }
700
701 static void
702 declare_global_input_sgprs(struct radv_shader_context *ctx,
703 gl_shader_stage stage,
704 bool has_previous_stage,
705 gl_shader_stage previous_stage,
706 const struct user_sgpr_info *user_sgpr_info,
707 struct arg_info *args,
708 LLVMValueRef *desc_sets)
709 {
710 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
711 unsigned num_sets = ctx->options->layout ?
712 ctx->options->layout->num_sets : 0;
713 unsigned stage_mask = 1 << stage;
714
715 if (has_previous_stage)
716 stage_mask |= 1 << previous_stage;
717
718 /* 1 for each descriptor set */
719 if (!user_sgpr_info->indirect_all_descriptor_sets) {
720 for (unsigned i = 0; i < num_sets; ++i) {
721 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
722 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
723 add_array_arg(args, type,
724 &ctx->descriptor_sets[i]);
725 }
726 }
727 } else {
728 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
729 }
730
731 if (ctx->shader_info->info.loads_push_constants) {
732 /* 1 for push constants and dynamic descriptors */
733 add_array_arg(args, type, &ctx->abi.push_constants);
734 }
735 }
736
737 static void
738 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
739 gl_shader_stage stage,
740 bool has_previous_stage,
741 gl_shader_stage previous_stage,
742 struct arg_info *args)
743 {
744 if (!ctx->is_gs_copy_shader &&
745 (stage == MESA_SHADER_VERTEX ||
746 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
747 if (ctx->shader_info->info.vs.has_vertex_buffers) {
748 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
749 &ctx->vertex_buffers);
750 }
751 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
752 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
753 if (ctx->shader_info->info.vs.needs_draw_id) {
754 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
755 }
756 }
757 }
758
759 static void
760 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
761 {
762 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
763 if (!ctx->is_gs_copy_shader) {
764 if (ctx->options->key.vs.as_ls) {
765 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
766 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
767 } else {
768 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
769 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
770 }
771 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
772 }
773 }
774
775 static void
776 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
777 {
778 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
779 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
780 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
781 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
782 }
783
784 static void
785 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
786 bool has_previous_stage, gl_shader_stage previous_stage,
787 const struct user_sgpr_info *user_sgpr_info,
788 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
789 {
790 unsigned num_sets = ctx->options->layout ?
791 ctx->options->layout->num_sets : 0;
792 unsigned stage_mask = 1 << stage;
793
794 if (has_previous_stage)
795 stage_mask |= 1 << previous_stage;
796
797 if (!user_sgpr_info->indirect_all_descriptor_sets) {
798 for (unsigned i = 0; i < num_sets; ++i) {
799 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
800 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
801 set_loc_desc(ctx, i, user_sgpr_idx, 0);
802 } else
803 ctx->descriptor_sets[i] = NULL;
804 }
805 } else {
806 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
807 user_sgpr_idx);
808
809 for (unsigned i = 0; i < num_sets; ++i) {
810 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
811 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
812 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
813 ctx->descriptor_sets[i] =
814 ac_build_load_to_sgpr(&ctx->ac,
815 desc_sets,
816 LLVMConstInt(ctx->ac.i32, i, false));
817
818 } else
819 ctx->descriptor_sets[i] = NULL;
820 }
821 ctx->shader_info->need_indirect_descriptor_sets = true;
822 }
823
824 if (ctx->shader_info->info.loads_push_constants) {
825 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
826 }
827 }
828
829 static void
830 set_vs_specific_input_locs(struct radv_shader_context *ctx,
831 gl_shader_stage stage, bool has_previous_stage,
832 gl_shader_stage previous_stage,
833 uint8_t *user_sgpr_idx)
834 {
835 if (!ctx->is_gs_copy_shader &&
836 (stage == MESA_SHADER_VERTEX ||
837 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
838 if (ctx->shader_info->info.vs.has_vertex_buffers) {
839 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
840 user_sgpr_idx);
841 }
842
843 unsigned vs_num = 2;
844 if (ctx->shader_info->info.vs.needs_draw_id)
845 vs_num++;
846
847 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
848 user_sgpr_idx, vs_num);
849 }
850 }
851
852 static void set_llvm_calling_convention(LLVMValueRef func,
853 gl_shader_stage stage)
854 {
855 enum radeon_llvm_calling_convention calling_conv;
856
857 switch (stage) {
858 case MESA_SHADER_VERTEX:
859 case MESA_SHADER_TESS_EVAL:
860 calling_conv = RADEON_LLVM_AMDGPU_VS;
861 break;
862 case MESA_SHADER_GEOMETRY:
863 calling_conv = RADEON_LLVM_AMDGPU_GS;
864 break;
865 case MESA_SHADER_TESS_CTRL:
866 calling_conv = RADEON_LLVM_AMDGPU_HS;
867 break;
868 case MESA_SHADER_FRAGMENT:
869 calling_conv = RADEON_LLVM_AMDGPU_PS;
870 break;
871 case MESA_SHADER_COMPUTE:
872 calling_conv = RADEON_LLVM_AMDGPU_CS;
873 break;
874 default:
875 unreachable("Unhandle shader type");
876 }
877
878 LLVMSetFunctionCallConv(func, calling_conv);
879 }
880
881 static void create_function(struct radv_shader_context *ctx,
882 gl_shader_stage stage,
883 bool has_previous_stage,
884 gl_shader_stage previous_stage)
885 {
886 uint8_t user_sgpr_idx;
887 struct user_sgpr_info user_sgpr_info;
888 struct arg_info args = {};
889 LLVMValueRef desc_sets;
890 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
891 allocate_user_sgprs(ctx, stage, has_previous_stage,
892 previous_stage, needs_view_index, &user_sgpr_info);
893
894 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
895 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
896 &ctx->ring_offsets);
897 }
898
899 switch (stage) {
900 case MESA_SHADER_COMPUTE:
901 declare_global_input_sgprs(ctx, stage, has_previous_stage,
902 previous_stage, &user_sgpr_info,
903 &args, &desc_sets);
904
905 if (ctx->shader_info->info.cs.uses_grid_size) {
906 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
907 &ctx->abi.num_work_groups);
908 }
909
910 for (int i = 0; i < 3; i++) {
911 ctx->abi.workgroup_ids[i] = NULL;
912 if (ctx->shader_info->info.cs.uses_block_id[i]) {
913 add_arg(&args, ARG_SGPR, ctx->ac.i32,
914 &ctx->abi.workgroup_ids[i]);
915 }
916 }
917
918 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
919 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
920 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
921 &ctx->abi.local_invocation_ids);
922 break;
923 case MESA_SHADER_VERTEX:
924 declare_global_input_sgprs(ctx, stage, has_previous_stage,
925 previous_stage, &user_sgpr_info,
926 &args, &desc_sets);
927 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
928 previous_stage, &args);
929
930 if (needs_view_index)
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->abi.view_index);
933 if (ctx->options->key.vs.as_es)
934 add_arg(&args, ARG_SGPR, ctx->ac.i32,
935 &ctx->es2gs_offset);
936
937 declare_vs_input_vgprs(ctx, &args);
938 break;
939 case MESA_SHADER_TESS_CTRL:
940 if (has_previous_stage) {
941 // First 6 system regs
942 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
943 add_arg(&args, ARG_SGPR, ctx->ac.i32,
944 &ctx->merged_wave_info);
945 add_arg(&args, ARG_SGPR, ctx->ac.i32,
946 &ctx->tess_factor_offset);
947
948 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
949 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
950 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
951
952 declare_global_input_sgprs(ctx, stage,
953 has_previous_stage,
954 previous_stage,
955 &user_sgpr_info, &args,
956 &desc_sets);
957 declare_vs_specific_input_sgprs(ctx, stage,
958 has_previous_stage,
959 previous_stage, &args);
960
961 if (needs_view_index)
962 add_arg(&args, ARG_SGPR, ctx->ac.i32,
963 &ctx->abi.view_index);
964
965 add_arg(&args, ARG_VGPR, ctx->ac.i32,
966 &ctx->abi.tcs_patch_id);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->abi.tcs_rel_ids);
969
970 declare_vs_input_vgprs(ctx, &args);
971 } else {
972 declare_global_input_sgprs(ctx, stage,
973 has_previous_stage,
974 previous_stage,
975 &user_sgpr_info, &args,
976 &desc_sets);
977
978 if (needs_view_index)
979 add_arg(&args, ARG_SGPR, ctx->ac.i32,
980 &ctx->abi.view_index);
981
982 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
983 add_arg(&args, ARG_SGPR, ctx->ac.i32,
984 &ctx->tess_factor_offset);
985 add_arg(&args, ARG_VGPR, ctx->ac.i32,
986 &ctx->abi.tcs_patch_id);
987 add_arg(&args, ARG_VGPR, ctx->ac.i32,
988 &ctx->abi.tcs_rel_ids);
989 }
990 break;
991 case MESA_SHADER_TESS_EVAL:
992 declare_global_input_sgprs(ctx, stage, has_previous_stage,
993 previous_stage, &user_sgpr_info,
994 &args, &desc_sets);
995
996 if (needs_view_index)
997 add_arg(&args, ARG_SGPR, ctx->ac.i32,
998 &ctx->abi.view_index);
999
1000 if (ctx->options->key.tes.as_es) {
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1003 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1004 &ctx->es2gs_offset);
1005 } else {
1006 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1007 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1008 }
1009 declare_tes_input_vgprs(ctx, &args);
1010 break;
1011 case MESA_SHADER_GEOMETRY:
1012 if (has_previous_stage) {
1013 // First 6 system regs
1014 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1015 &ctx->gs2vs_offset);
1016 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1017 &ctx->merged_wave_info);
1018 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1019
1020 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1021 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1023
1024 declare_global_input_sgprs(ctx, stage,
1025 has_previous_stage,
1026 previous_stage,
1027 &user_sgpr_info, &args,
1028 &desc_sets);
1029
1030 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1031 declare_vs_specific_input_sgprs(ctx, stage,
1032 has_previous_stage,
1033 previous_stage,
1034 &args);
1035 }
1036
1037 if (needs_view_index)
1038 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1039 &ctx->abi.view_index);
1040
1041 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1042 &ctx->gs_vtx_offset[0]);
1043 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1044 &ctx->gs_vtx_offset[2]);
1045 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1046 &ctx->abi.gs_prim_id);
1047 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1048 &ctx->abi.gs_invocation_id);
1049 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1050 &ctx->gs_vtx_offset[4]);
1051
1052 if (previous_stage == MESA_SHADER_VERTEX) {
1053 declare_vs_input_vgprs(ctx, &args);
1054 } else {
1055 declare_tes_input_vgprs(ctx, &args);
1056 }
1057 } else {
1058 declare_global_input_sgprs(ctx, stage,
1059 has_previous_stage,
1060 previous_stage,
1061 &user_sgpr_info, &args,
1062 &desc_sets);
1063
1064 if (needs_view_index)
1065 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1066 &ctx->abi.view_index);
1067
1068 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1069 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1070 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1071 &ctx->gs_vtx_offset[0]);
1072 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1073 &ctx->gs_vtx_offset[1]);
1074 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1075 &ctx->abi.gs_prim_id);
1076 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1077 &ctx->gs_vtx_offset[2]);
1078 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1079 &ctx->gs_vtx_offset[3]);
1080 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1081 &ctx->gs_vtx_offset[4]);
1082 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1083 &ctx->gs_vtx_offset[5]);
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->abi.gs_invocation_id);
1086 }
1087 break;
1088 case MESA_SHADER_FRAGMENT:
1089 declare_global_input_sgprs(ctx, stage, has_previous_stage,
1090 previous_stage, &user_sgpr_info,
1091 &args, &desc_sets);
1092
1093 if (ctx->shader_info->info.ps.needs_sample_positions)
1094 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1095 &ctx->sample_pos_offset);
1096
1097 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1098 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1099 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1100 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1101 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1102 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1103 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1104 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1105 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1106 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1107 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1108 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1109 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1111 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1113 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1114 break;
1115 default:
1116 unreachable("Shader stage not implemented");
1117 }
1118
1119 ctx->main_function = create_llvm_function(
1120 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1121 ctx->max_workgroup_size, ctx->options);
1122 set_llvm_calling_convention(ctx->main_function, stage);
1123
1124
1125 ctx->shader_info->num_input_vgprs = 0;
1126 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1127
1128 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1129
1130 if (ctx->stage != MESA_SHADER_FRAGMENT)
1131 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1132
1133 assign_arguments(ctx->main_function, &args);
1134
1135 user_sgpr_idx = 0;
1136
1137 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1138 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1139 &user_sgpr_idx);
1140 if (ctx->options->supports_spill) {
1141 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1142 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1143 NULL, 0, AC_FUNC_ATTR_READNONE);
1144 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1145 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1146 }
1147 }
1148
1149 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1150 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1151 if (has_previous_stage)
1152 user_sgpr_idx = 0;
1153
1154 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1155 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1156
1157 switch (stage) {
1158 case MESA_SHADER_COMPUTE:
1159 if (ctx->shader_info->info.cs.uses_grid_size) {
1160 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1161 &user_sgpr_idx, 3);
1162 }
1163 break;
1164 case MESA_SHADER_VERTEX:
1165 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1166 previous_stage, &user_sgpr_idx);
1167 if (ctx->abi.view_index)
1168 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1169 break;
1170 case MESA_SHADER_TESS_CTRL:
1171 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1172 previous_stage, &user_sgpr_idx);
1173 if (ctx->abi.view_index)
1174 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1175 break;
1176 case MESA_SHADER_TESS_EVAL:
1177 if (ctx->abi.view_index)
1178 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1179 break;
1180 case MESA_SHADER_GEOMETRY:
1181 if (has_previous_stage) {
1182 if (previous_stage == MESA_SHADER_VERTEX)
1183 set_vs_specific_input_locs(ctx, stage,
1184 has_previous_stage,
1185 previous_stage,
1186 &user_sgpr_idx);
1187 }
1188 if (ctx->abi.view_index)
1189 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1190 break;
1191 case MESA_SHADER_FRAGMENT:
1192 if (ctx->shader_info->info.ps.needs_sample_positions) {
1193 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1194 &user_sgpr_idx, 1);
1195 }
1196 break;
1197 default:
1198 unreachable("Shader stage not implemented");
1199 }
1200
1201 if (stage == MESA_SHADER_TESS_CTRL ||
1202 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1203 /* GFX9 has the ESGS ring buffer in LDS. */
1204 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1205 ac_declare_lds_as_pointer(&ctx->ac);
1206 }
1207
1208 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1209 }
1210
1211
1212 static LLVMValueRef
1213 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1214 unsigned desc_set, unsigned binding)
1215 {
1216 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1217 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1218 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1219 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1220 unsigned base_offset = layout->binding[binding].offset;
1221 LLVMValueRef offset, stride;
1222
1223 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1224 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1225 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1226 layout->binding[binding].dynamic_offset_offset;
1227 desc_ptr = ctx->abi.push_constants;
1228 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1229 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1230 } else
1231 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1232
1233 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1234 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
1235 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
1236
1237 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1238 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1239 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1240
1241 return desc_ptr;
1242 }
1243
1244
1245 /* The offchip buffer layout for TCS->TES is
1246 *
1247 * - attribute 0 of patch 0 vertex 0
1248 * - attribute 0 of patch 0 vertex 1
1249 * - attribute 0 of patch 0 vertex 2
1250 * ...
1251 * - attribute 0 of patch 1 vertex 0
1252 * - attribute 0 of patch 1 vertex 1
1253 * ...
1254 * - attribute 1 of patch 0 vertex 0
1255 * - attribute 1 of patch 0 vertex 1
1256 * ...
1257 * - per patch attribute 0 of patch 0
1258 * - per patch attribute 0 of patch 1
1259 * ...
1260 *
1261 * Note that every attribute has 4 components.
1262 */
1263 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1264 {
1265 uint32_t num_patches = ctx->tcs_num_patches;
1266 uint32_t num_tcs_outputs;
1267 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1268 num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
1269 else
1270 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1271
1272 uint32_t output_vertex_size = num_tcs_outputs * 16;
1273 uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
1274
1275 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1276 }
1277
1278 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1279 LLVMValueRef vertex_index)
1280 {
1281 LLVMValueRef param_stride;
1282 if (vertex_index)
1283 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
1284 else
1285 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1286 return param_stride;
1287 }
1288
1289 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1290 LLVMValueRef vertex_index,
1291 LLVMValueRef param_index)
1292 {
1293 LLVMValueRef base_addr;
1294 LLVMValueRef param_stride, constant16;
1295 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1296 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
1297 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1298 param_stride = calc_param_stride(ctx, vertex_index);
1299 if (vertex_index) {
1300 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
1301 vertices_per_patch, "");
1302
1303 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1304 vertex_index, "");
1305 } else {
1306 base_addr = rel_patch_id;
1307 }
1308
1309 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1310 LLVMBuildMul(ctx->ac.builder, param_index,
1311 param_stride, ""), "");
1312
1313 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1314
1315 if (!vertex_index) {
1316 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1317
1318 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1319 patch_data_offset, "");
1320 }
1321 return base_addr;
1322 }
1323
1324 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1325 unsigned param,
1326 unsigned const_index,
1327 bool is_compact,
1328 LLVMValueRef vertex_index,
1329 LLVMValueRef indir_index)
1330 {
1331 LLVMValueRef param_index;
1332
1333 if (indir_index)
1334 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1335 indir_index, "");
1336 else {
1337 if (const_index && !is_compact)
1338 param += const_index;
1339 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1340 }
1341 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1342 }
1343
1344 static LLVMValueRef
1345 get_dw_address(struct radv_shader_context *ctx,
1346 LLVMValueRef dw_addr,
1347 unsigned param,
1348 unsigned const_index,
1349 bool compact_const_index,
1350 LLVMValueRef vertex_index,
1351 LLVMValueRef stride,
1352 LLVMValueRef indir_index)
1353
1354 {
1355
1356 if (vertex_index) {
1357 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1358 LLVMBuildMul(ctx->ac.builder,
1359 vertex_index,
1360 stride, ""), "");
1361 }
1362
1363 if (indir_index)
1364 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1365 LLVMBuildMul(ctx->ac.builder, indir_index,
1366 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1367 else if (const_index && !compact_const_index)
1368 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1369 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1370
1371 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1372 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1373
1374 if (const_index && compact_const_index)
1375 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1376 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1377 return dw_addr;
1378 }
1379
1380 static LLVMValueRef
1381 load_tcs_varyings(struct ac_shader_abi *abi,
1382 LLVMTypeRef type,
1383 LLVMValueRef vertex_index,
1384 LLVMValueRef indir_index,
1385 unsigned const_index,
1386 unsigned location,
1387 unsigned driver_location,
1388 unsigned component,
1389 unsigned num_components,
1390 bool is_patch,
1391 bool is_compact,
1392 bool load_input)
1393 {
1394 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1395 LLVMValueRef dw_addr, stride;
1396 LLVMValueRef value[4], result;
1397 unsigned param = shader_io_get_unique_index(location);
1398
1399 if (load_input) {
1400 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1401 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1402 dw_addr = get_tcs_in_current_patch_offset(ctx);
1403 } else {
1404 if (!is_patch) {
1405 stride = get_tcs_out_vertex_stride(ctx);
1406 dw_addr = get_tcs_out_current_patch_offset(ctx);
1407 } else {
1408 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1409 stride = NULL;
1410 }
1411 }
1412
1413 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1414 indir_index);
1415
1416 for (unsigned i = 0; i < num_components + component; i++) {
1417 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1418 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1419 ctx->ac.i32_1, "");
1420 }
1421 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1422 return result;
1423 }
1424
1425 static void
1426 store_tcs_output(struct ac_shader_abi *abi,
1427 const nir_variable *var,
1428 LLVMValueRef vertex_index,
1429 LLVMValueRef param_index,
1430 unsigned const_index,
1431 LLVMValueRef src,
1432 unsigned writemask)
1433 {
1434 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1435 const unsigned location = var->data.location;
1436 const unsigned component = var->data.location_frac;
1437 const bool is_patch = var->data.patch;
1438 const bool is_compact = var->data.compact;
1439 LLVMValueRef dw_addr;
1440 LLVMValueRef stride = NULL;
1441 LLVMValueRef buf_addr = NULL;
1442 unsigned param;
1443 bool store_lds = true;
1444
1445 if (is_patch) {
1446 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1447 store_lds = false;
1448 } else {
1449 if (!(ctx->tcs_outputs_read & (1ULL << location)))
1450 store_lds = false;
1451 }
1452
1453 param = shader_io_get_unique_index(location);
1454 if (location == VARYING_SLOT_CLIP_DIST0 &&
1455 is_compact && const_index > 3) {
1456 const_index -= 3;
1457 param++;
1458 }
1459
1460 if (!is_patch) {
1461 stride = get_tcs_out_vertex_stride(ctx);
1462 dw_addr = get_tcs_out_current_patch_offset(ctx);
1463 } else {
1464 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1465 }
1466
1467 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1468 param_index);
1469 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1470 vertex_index, param_index);
1471
1472 bool is_tess_factor = false;
1473 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1474 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1475 is_tess_factor = true;
1476
1477 unsigned base = is_compact ? const_index : 0;
1478 for (unsigned chan = 0; chan < 8; chan++) {
1479 if (!(writemask & (1 << chan)))
1480 continue;
1481 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1482
1483 if (store_lds || is_tess_factor) {
1484 LLVMValueRef dw_addr_chan =
1485 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1486 LLVMConstInt(ctx->ac.i32, chan, false), "");
1487 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1488 }
1489
1490 if (!is_tess_factor && writemask != 0xF)
1491 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1492 buf_addr, ctx->oc_lds,
1493 4 * (base + chan), 1, 0, true, false);
1494 }
1495
1496 if (writemask == 0xF) {
1497 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1498 buf_addr, ctx->oc_lds,
1499 (base * 4), 1, 0, true, false);
1500 }
1501 }
1502
1503 static LLVMValueRef
1504 load_tes_input(struct ac_shader_abi *abi,
1505 LLVMTypeRef type,
1506 LLVMValueRef vertex_index,
1507 LLVMValueRef param_index,
1508 unsigned const_index,
1509 unsigned location,
1510 unsigned driver_location,
1511 unsigned component,
1512 unsigned num_components,
1513 bool is_patch,
1514 bool is_compact,
1515 bool load_input)
1516 {
1517 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1518 LLVMValueRef buf_addr;
1519 LLVMValueRef result;
1520 unsigned param = shader_io_get_unique_index(location);
1521
1522 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
1523 const_index -= 3;
1524 param++;
1525 }
1526
1527 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1528 is_compact, vertex_index, param_index);
1529
1530 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1531 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1532
1533 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1534 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
1535 result = ac_trim_vector(&ctx->ac, result, num_components);
1536 return result;
1537 }
1538
1539 static LLVMValueRef
1540 load_gs_input(struct ac_shader_abi *abi,
1541 unsigned location,
1542 unsigned driver_location,
1543 unsigned component,
1544 unsigned num_components,
1545 unsigned vertex_index,
1546 unsigned const_index,
1547 LLVMTypeRef type)
1548 {
1549 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1550 LLVMValueRef vtx_offset;
1551 unsigned param, vtx_offset_param;
1552 LLVMValueRef value[4], result;
1553
1554 vtx_offset_param = vertex_index;
1555 assert(vtx_offset_param < 6);
1556 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1557 LLVMConstInt(ctx->ac.i32, 4, false), "");
1558
1559 param = shader_io_get_unique_index(location);
1560
1561 for (unsigned i = component; i < num_components + component; i++) {
1562 if (ctx->ac.chip_class >= GFX9) {
1563 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1564 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1565 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1566 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1567 } else {
1568 LLVMValueRef soffset =
1569 LLVMConstInt(ctx->ac.i32,
1570 (param * 4 + i + const_index) * 256,
1571 false);
1572
1573 value[i] = ac_build_buffer_load(&ctx->ac,
1574 ctx->esgs_ring, 1,
1575 ctx->ac.i32_0,
1576 vtx_offset, soffset,
1577 0, 1, 0, true, false);
1578
1579 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
1580 type, "");
1581 }
1582 }
1583 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1584 result = ac_to_integer(&ctx->ac, result);
1585 return result;
1586 }
1587
1588
1589 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1590 {
1591 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1592 ac_build_kill_if_false(&ctx->ac, visible);
1593 }
1594
1595 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
1596 enum glsl_interp_mode interp, unsigned location)
1597 {
1598 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1599
1600 switch (interp) {
1601 case INTERP_MODE_FLAT:
1602 default:
1603 return NULL;
1604 case INTERP_MODE_SMOOTH:
1605 case INTERP_MODE_NONE:
1606 if (location == INTERP_CENTER)
1607 return ctx->persp_center;
1608 else if (location == INTERP_CENTROID)
1609 return ctx->persp_centroid;
1610 else if (location == INTERP_SAMPLE)
1611 return ctx->persp_sample;
1612 break;
1613 case INTERP_MODE_NOPERSPECTIVE:
1614 if (location == INTERP_CENTER)
1615 return ctx->linear_center;
1616 else if (location == INTERP_CENTROID)
1617 return ctx->linear_centroid;
1618 else if (location == INTERP_SAMPLE)
1619 return ctx->linear_sample;
1620 break;
1621 }
1622 return NULL;
1623 }
1624
1625 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1626 LLVMValueRef sample_id)
1627 {
1628 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1629
1630 LLVMValueRef result;
1631 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
1632
1633 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1634 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1635
1636 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
1637 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1638
1639 return result;
1640 }
1641
1642
1643 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1644 {
1645 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1646 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
1647 ctx->options->key.fs.log2_num_samples :
1648 ctx->options->key.fs.log2_ps_iter_samples;
1649
1650 /* The bit pattern matches that used by fixed function fragment
1651 * processing. */
1652 static const uint16_t ps_iter_masks[] = {
1653 0xffff, /* not used */
1654 0x5555,
1655 0x1111,
1656 0x0101,
1657 0x0001,
1658 };
1659 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1660
1661 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1662
1663 LLVMValueRef result, sample_id;
1664 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1665 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1666 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1667 return result;
1668 }
1669
1670
1671 static void
1672 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1673 {
1674 LLVMValueRef gs_next_vertex;
1675 LLVMValueRef can_emit;
1676 int idx;
1677 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1678
1679 assert(stream == 0);
1680
1681 /* Write vertex attribute values to GSVS ring */
1682 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1683 ctx->gs_next_vertex,
1684 "");
1685
1686 /* If this thread has already emitted the declared maximum number of
1687 * vertices, kill it: excessive vertex emissions are not supposed to
1688 * have any effect, and GS threads have no externally observable
1689 * effects other than emitting vertices.
1690 */
1691 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1692 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
1693 ac_build_kill_if_false(&ctx->ac, can_emit);
1694
1695 /* loop num outputs */
1696 idx = 0;
1697 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1698 unsigned output_usage_mask =
1699 ctx->shader_info->info.gs.output_usage_mask[i];
1700 LLVMValueRef *out_ptr = &addrs[i * 4];
1701 int length = 4;
1702 int slot = idx;
1703 int slot_inc = 1;
1704
1705 if (!(ctx->output_mask & (1ull << i)))
1706 continue;
1707
1708 if (i == VARYING_SLOT_CLIP_DIST0) {
1709 /* pack clip and cull into a single set of slots */
1710 length = ctx->num_output_clips + ctx->num_output_culls;
1711 if (length > 4)
1712 slot_inc = 2;
1713 output_usage_mask = (1 << length) - 1;
1714 }
1715
1716 for (unsigned j = 0; j < length; j++) {
1717 if (!(output_usage_mask & (1 << j)))
1718 continue;
1719
1720 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1721 out_ptr[j], "");
1722 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
1723 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1724 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1725
1726 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1727
1728 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
1729 out_val, 1,
1730 voffset, ctx->gs2vs_offset, 0,
1731 1, 1, true, true);
1732 }
1733 idx += slot_inc;
1734 }
1735
1736 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1737 ctx->ac.i32_1, "");
1738 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
1739
1740 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
1741 }
1742
1743 static void
1744 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1745 {
1746 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1747 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1748 }
1749
1750 static LLVMValueRef
1751 load_tess_coord(struct ac_shader_abi *abi)
1752 {
1753 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1754
1755 LLVMValueRef coord[4] = {
1756 ctx->tes_u,
1757 ctx->tes_v,
1758 ctx->ac.f32_0,
1759 ctx->ac.f32_0,
1760 };
1761
1762 if (ctx->tes_primitive_mode == GL_TRIANGLES)
1763 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1764 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1765
1766 return ac_build_gather_values(&ctx->ac, coord, 3);
1767 }
1768
1769 static LLVMValueRef
1770 load_patch_vertices_in(struct ac_shader_abi *abi)
1771 {
1772 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1773 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1774 }
1775
1776
1777 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1778 {
1779 return abi->base_vertex;
1780 }
1781
1782 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1783 LLVMValueRef buffer_ptr, bool write)
1784 {
1785 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1786 LLVMValueRef result;
1787
1788 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1789
1790 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1791 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1792
1793 return result;
1794 }
1795
1796 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1797 {
1798 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1799 LLVMValueRef result;
1800
1801 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1802
1803 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1804 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1805
1806 return result;
1807 }
1808
1809 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1810 unsigned descriptor_set,
1811 unsigned base_index,
1812 unsigned constant_index,
1813 LLVMValueRef index,
1814 enum ac_descriptor_type desc_type,
1815 bool image, bool write,
1816 bool bindless)
1817 {
1818 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1819 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1820 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1821 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1822 unsigned offset = binding->offset;
1823 unsigned stride = binding->size;
1824 unsigned type_size;
1825 LLVMBuilderRef builder = ctx->ac.builder;
1826 LLVMTypeRef type;
1827
1828 assert(base_index < layout->binding_count);
1829
1830 switch (desc_type) {
1831 case AC_DESC_IMAGE:
1832 type = ctx->ac.v8i32;
1833 type_size = 32;
1834 break;
1835 case AC_DESC_FMASK:
1836 type = ctx->ac.v8i32;
1837 offset += 32;
1838 type_size = 32;
1839 break;
1840 case AC_DESC_SAMPLER:
1841 type = ctx->ac.v4i32;
1842 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
1843 offset += 64;
1844
1845 type_size = 16;
1846 break;
1847 case AC_DESC_BUFFER:
1848 type = ctx->ac.v4i32;
1849 type_size = 16;
1850 break;
1851 default:
1852 unreachable("invalid desc_type\n");
1853 }
1854
1855 offset += constant_index * stride;
1856
1857 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1858 (!index || binding->immutable_samplers_equal)) {
1859 if (binding->immutable_samplers_equal)
1860 constant_index = 0;
1861
1862 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1863
1864 LLVMValueRef constants[] = {
1865 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1866 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1867 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1868 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1869 };
1870 return ac_build_gather_values(&ctx->ac, constants, 4);
1871 }
1872
1873 assert(stride % type_size == 0);
1874
1875 if (!index)
1876 index = ctx->ac.i32_0;
1877
1878 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1879
1880 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
1881 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
1882
1883 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1884 }
1885
1886 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1887 * so we may need to fix it up. */
1888 static LLVMValueRef
1889 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1890 unsigned adjustment,
1891 LLVMValueRef alpha)
1892 {
1893 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1894 return alpha;
1895
1896 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1897
1898 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1899 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1900 else
1901 alpha = ac_to_integer(&ctx->ac, alpha);
1902
1903 /* For the integer-like cases, do a natural sign extension.
1904 *
1905 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1906 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1907 * exponent.
1908 */
1909 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1910 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1911 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1912 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1913
1914 /* Convert back to the right type. */
1915 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1916 LLVMValueRef clamp;
1917 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1918 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1919 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1920 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1921 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1922 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1923 }
1924
1925 return alpha;
1926 }
1927
1928 static void
1929 handle_vs_input_decl(struct radv_shader_context *ctx,
1930 struct nir_variable *variable)
1931 {
1932 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
1933 LLVMValueRef t_offset;
1934 LLVMValueRef t_list;
1935 LLVMValueRef input;
1936 LLVMValueRef buffer_index;
1937 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1938 uint8_t input_usage_mask =
1939 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
1940 unsigned num_channels = util_last_bit(input_usage_mask);
1941
1942 variable->data.driver_location = variable->data.location * 4;
1943
1944 for (unsigned i = 0; i < attrib_count; ++i) {
1945 LLVMValueRef output[4];
1946 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1947
1948 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1949 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
1950
1951 if (divisor) {
1952 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
1953 ctx->abi.start_instance, "");
1954
1955 if (divisor != 1) {
1956 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1957 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1958 }
1959
1960 if (ctx->options->key.vs.as_ls) {
1961 ctx->shader_info->vs.vgpr_comp_cnt =
1962 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
1963 } else {
1964 ctx->shader_info->vs.vgpr_comp_cnt =
1965 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
1966 }
1967 } else {
1968 buffer_index = ctx->ac.i32_0;
1969 }
1970 } else
1971 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
1972 ctx->abi.base_vertex, "");
1973 t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
1974
1975 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1976
1977 input = ac_build_buffer_load_format(&ctx->ac, t_list,
1978 buffer_index,
1979 ctx->ac.i32_0,
1980 num_channels, false, true);
1981
1982 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
1983
1984 for (unsigned chan = 0; chan < 4; chan++) {
1985 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1986 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1987 }
1988
1989 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1990 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1991
1992 for (unsigned chan = 0; chan < 4; chan++) {
1993 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
1994 ac_to_integer(&ctx->ac, output[chan]);
1995 }
1996 }
1997 }
1998
1999 static void interp_fs_input(struct radv_shader_context *ctx,
2000 unsigned attr,
2001 LLVMValueRef interp_param,
2002 LLVMValueRef prim_mask,
2003 LLVMValueRef result[4])
2004 {
2005 LLVMValueRef attr_number;
2006 unsigned chan;
2007 LLVMValueRef i, j;
2008 bool interp = interp_param != NULL;
2009
2010 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
2011
2012 /* fs.constant returns the param from the middle vertex, so it's not
2013 * really useful for flat shading. It's meant to be used for custom
2014 * interpolation (but the intrinsic can't fetch from the other two
2015 * vertices).
2016 *
2017 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
2018 * to do the right thing. The only reason we use fs.constant is that
2019 * fs.interp cannot be used on integers, because they can be equal
2020 * to NaN.
2021 */
2022 if (interp) {
2023 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
2024 ctx->ac.v2f32, "");
2025
2026 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2027 ctx->ac.i32_0, "");
2028 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
2029 ctx->ac.i32_1, "");
2030 }
2031
2032 for (chan = 0; chan < 4; chan++) {
2033 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2034
2035 if (interp) {
2036 result[chan] = ac_build_fs_interp(&ctx->ac,
2037 llvm_chan,
2038 attr_number,
2039 prim_mask, i, j);
2040 } else {
2041 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2042 LLVMConstInt(ctx->ac.i32, 2, false),
2043 llvm_chan,
2044 attr_number,
2045 prim_mask);
2046 }
2047 }
2048 }
2049
2050 static void
2051 handle_fs_input_decl(struct radv_shader_context *ctx,
2052 struct nir_variable *variable)
2053 {
2054 int idx = variable->data.location;
2055 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2056 LLVMValueRef interp;
2057
2058 variable->data.driver_location = idx * 4;
2059 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
2060
2061 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
2062 unsigned interp_type;
2063 if (variable->data.sample)
2064 interp_type = INTERP_SAMPLE;
2065 else if (variable->data.centroid)
2066 interp_type = INTERP_CENTROID;
2067 else
2068 interp_type = INTERP_CENTER;
2069
2070 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
2071 } else
2072 interp = NULL;
2073
2074 for (unsigned i = 0; i < attrib_count; ++i)
2075 ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
2076
2077 }
2078
2079 static void
2080 handle_vs_inputs(struct radv_shader_context *ctx,
2081 struct nir_shader *nir) {
2082 nir_foreach_variable(variable, &nir->inputs)
2083 handle_vs_input_decl(ctx, variable);
2084 }
2085
2086 static void
2087 prepare_interp_optimize(struct radv_shader_context *ctx,
2088 struct nir_shader *nir)
2089 {
2090 bool uses_center = false;
2091 bool uses_centroid = false;
2092 nir_foreach_variable(variable, &nir->inputs) {
2093 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2094 variable->data.sample)
2095 continue;
2096
2097 if (variable->data.centroid)
2098 uses_centroid = true;
2099 else
2100 uses_center = true;
2101 }
2102
2103 if (uses_center && uses_centroid) {
2104 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2105 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
2106 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
2107 }
2108 }
2109
2110 static void
2111 handle_fs_inputs(struct radv_shader_context *ctx,
2112 struct nir_shader *nir)
2113 {
2114 prepare_interp_optimize(ctx, nir);
2115
2116 nir_foreach_variable(variable, &nir->inputs)
2117 handle_fs_input_decl(ctx, variable);
2118
2119 unsigned index = 0;
2120
2121 if (ctx->shader_info->info.ps.uses_input_attachments ||
2122 ctx->shader_info->info.needs_multiview_view_index)
2123 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
2124
2125 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
2126 LLVMValueRef interp_param;
2127 LLVMValueRef *inputs = ctx->inputs +ac_llvm_reg_index_soa(i, 0);
2128
2129 if (!(ctx->input_mask & (1ull << i)))
2130 continue;
2131
2132 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
2133 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
2134 interp_param = *inputs;
2135 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
2136 inputs);
2137
2138 if (!interp_param)
2139 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
2140 ++index;
2141 } else if (i == VARYING_SLOT_POS) {
2142 for(int i = 0; i < 3; ++i)
2143 inputs[i] = ctx->abi.frag_pos[i];
2144
2145 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2146 ctx->abi.frag_pos[3]);
2147 }
2148 }
2149 ctx->shader_info->fs.num_interp = index;
2150 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
2151
2152 if (ctx->shader_info->info.needs_multiview_view_index)
2153 ctx->abi.view_index = ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2154 }
2155
2156 static void
2157 scan_shader_output_decl(struct radv_shader_context *ctx,
2158 struct nir_variable *variable,
2159 struct nir_shader *shader,
2160 gl_shader_stage stage)
2161 {
2162 int idx = variable->data.location + variable->data.index;
2163 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2164 uint64_t mask_attribs;
2165
2166 variable->data.driver_location = idx * 4;
2167
2168 /* tess ctrl has it's own load/store paths for outputs */
2169 if (stage == MESA_SHADER_TESS_CTRL)
2170 return;
2171
2172 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2173 if (stage == MESA_SHADER_VERTEX ||
2174 stage == MESA_SHADER_TESS_EVAL ||
2175 stage == MESA_SHADER_GEOMETRY) {
2176 if (idx == VARYING_SLOT_CLIP_DIST0) {
2177 int length = shader->info.clip_distance_array_size +
2178 shader->info.cull_distance_array_size;
2179 if (stage == MESA_SHADER_VERTEX) {
2180 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2181 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2182 }
2183 if (stage == MESA_SHADER_TESS_EVAL) {
2184 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2185 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2186 }
2187
2188 if (length > 4)
2189 attrib_count = 2;
2190 else
2191 attrib_count = 1;
2192 mask_attribs = 1ull << idx;
2193 }
2194 }
2195
2196 ctx->output_mask |= mask_attribs;
2197 }
2198
2199
2200 /* Initialize arguments for the shader export intrinsic */
2201 static void
2202 si_llvm_init_export_args(struct radv_shader_context *ctx,
2203 LLVMValueRef *values,
2204 unsigned enabled_channels,
2205 unsigned target,
2206 struct ac_export_args *args)
2207 {
2208 /* Specify the channels that are enabled. */
2209 args->enabled_channels = enabled_channels;
2210
2211 /* Specify whether the EXEC mask represents the valid mask */
2212 args->valid_mask = 0;
2213
2214 /* Specify whether this is the last export */
2215 args->done = 0;
2216
2217 /* Specify the target we are exporting */
2218 args->target = target;
2219
2220 args->compr = false;
2221 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2222 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2223 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2224 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2225
2226 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
2227 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2228 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2229 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2230 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2231 unsigned chan;
2232
2233 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2234 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2235 unsigned bits, bool hi) = NULL;
2236
2237 switch(col_format) {
2238 case V_028714_SPI_SHADER_ZERO:
2239 args->enabled_channels = 0; /* writemask */
2240 args->target = V_008DFC_SQ_EXP_NULL;
2241 break;
2242
2243 case V_028714_SPI_SHADER_32_R:
2244 args->enabled_channels = 1;
2245 args->out[0] = values[0];
2246 break;
2247
2248 case V_028714_SPI_SHADER_32_GR:
2249 args->enabled_channels = 0x3;
2250 args->out[0] = values[0];
2251 args->out[1] = values[1];
2252 break;
2253
2254 case V_028714_SPI_SHADER_32_AR:
2255 args->enabled_channels = 0x9;
2256 args->out[0] = values[0];
2257 args->out[3] = values[3];
2258 break;
2259
2260 case V_028714_SPI_SHADER_FP16_ABGR:
2261 args->enabled_channels = 0x5;
2262 packf = ac_build_cvt_pkrtz_f16;
2263 break;
2264
2265 case V_028714_SPI_SHADER_UNORM16_ABGR:
2266 args->enabled_channels = 0x5;
2267 packf = ac_build_cvt_pknorm_u16;
2268 break;
2269
2270 case V_028714_SPI_SHADER_SNORM16_ABGR:
2271 args->enabled_channels = 0x5;
2272 packf = ac_build_cvt_pknorm_i16;
2273 break;
2274
2275 case V_028714_SPI_SHADER_UINT16_ABGR:
2276 args->enabled_channels = 0x5;
2277 packi = ac_build_cvt_pk_u16;
2278 break;
2279
2280 case V_028714_SPI_SHADER_SINT16_ABGR:
2281 args->enabled_channels = 0x5;
2282 packi = ac_build_cvt_pk_i16;
2283 break;
2284
2285 default:
2286 case V_028714_SPI_SHADER_32_ABGR:
2287 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2288 break;
2289 }
2290
2291 /* Pack f16 or norm_i16/u16. */
2292 if (packf) {
2293 for (chan = 0; chan < 2; chan++) {
2294 LLVMValueRef pack_args[2] = {
2295 values[2 * chan],
2296 values[2 * chan + 1]
2297 };
2298 LLVMValueRef packed;
2299
2300 packed = packf(&ctx->ac, pack_args);
2301 args->out[chan] = ac_to_float(&ctx->ac, packed);
2302 }
2303 args->compr = 1; /* COMPR flag */
2304 }
2305
2306 /* Pack i16/u16. */
2307 if (packi) {
2308 for (chan = 0; chan < 2; chan++) {
2309 LLVMValueRef pack_args[2] = {
2310 ac_to_integer(&ctx->ac, values[2 * chan]),
2311 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2312 };
2313 LLVMValueRef packed;
2314
2315 packed = packi(&ctx->ac, pack_args,
2316 is_int8 ? 8 : is_int10 ? 10 : 16,
2317 chan == 1);
2318 args->out[chan] = ac_to_float(&ctx->ac, packed);
2319 }
2320 args->compr = 1; /* COMPR flag */
2321 }
2322 return;
2323 }
2324
2325 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2326
2327 for (unsigned i = 0; i < 4; ++i) {
2328 if (!(args->enabled_channels & (1 << i)))
2329 continue;
2330
2331 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2332 }
2333 }
2334
2335 static void
2336 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2337 LLVMValueRef *values, unsigned enabled_channels)
2338 {
2339 struct ac_export_args args;
2340
2341 si_llvm_init_export_args(ctx, values, enabled_channels,
2342 V_008DFC_SQ_EXP_PARAM + index, &args);
2343 ac_build_export(&ctx->ac, &args);
2344 }
2345
2346 static LLVMValueRef
2347 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2348 {
2349 LLVMValueRef output =
2350 ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2351
2352 return LLVMBuildLoad(ctx->ac.builder, output, "");
2353 }
2354
2355 static void
2356 handle_vs_outputs_post(struct radv_shader_context *ctx,
2357 bool export_prim_id, bool export_layer_id,
2358 struct radv_vs_output_info *outinfo)
2359 {
2360 uint32_t param_count = 0;
2361 unsigned target;
2362 unsigned pos_idx, num_pos_exports = 0;
2363 struct ac_export_args args, pos_args[4] = {};
2364 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2365 int i;
2366
2367 if (ctx->options->key.has_multiview_view_index) {
2368 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2369 if(!*tmp_out) {
2370 for(unsigned i = 0; i < 4; ++i)
2371 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2372 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2373 }
2374
2375 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2376 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2377 }
2378
2379 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2380 sizeof(outinfo->vs_output_param_offset));
2381
2382 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
2383 LLVMValueRef slots[8];
2384 unsigned j;
2385
2386 if (outinfo->cull_dist_mask)
2387 outinfo->cull_dist_mask <<= ctx->num_output_clips;
2388
2389 i = VARYING_SLOT_CLIP_DIST0;
2390 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
2391 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2392
2393 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
2394 slots[i] = LLVMGetUndef(ctx->ac.f32);
2395
2396 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
2397 target = V_008DFC_SQ_EXP_POS + 3;
2398 si_llvm_init_export_args(ctx, &slots[4], 0xf, target, &args);
2399 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2400 &args, sizeof(args));
2401 }
2402
2403 target = V_008DFC_SQ_EXP_POS + 2;
2404 si_llvm_init_export_args(ctx, &slots[0], 0xf, target, &args);
2405 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2406 &args, sizeof(args));
2407
2408 }
2409
2410 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
2411 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
2412 for (unsigned j = 0; j < 4; j++)
2413 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
2414 }
2415 si_llvm_init_export_args(ctx, pos_values, 0xf, V_008DFC_SQ_EXP_POS, &pos_args[0]);
2416
2417 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
2418 outinfo->writes_pointsize = true;
2419 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
2420 }
2421
2422 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
2423 outinfo->writes_layer = true;
2424 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
2425 }
2426
2427 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
2428 outinfo->writes_viewport_index = true;
2429 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
2430 }
2431
2432 if (outinfo->writes_pointsize ||
2433 outinfo->writes_layer ||
2434 outinfo->writes_viewport_index) {
2435 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2436 (outinfo->writes_layer == true ? 4 : 0));
2437 pos_args[1].valid_mask = 0;
2438 pos_args[1].done = 0;
2439 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2440 pos_args[1].compr = 0;
2441 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2442 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2443 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2444 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2445
2446 if (outinfo->writes_pointsize == true)
2447 pos_args[1].out[0] = psize_value;
2448 if (outinfo->writes_layer == true)
2449 pos_args[1].out[2] = layer_value;
2450 if (outinfo->writes_viewport_index == true) {
2451 if (ctx->options->chip_class >= GFX9) {
2452 /* GFX9 has the layer in out.z[10:0] and the viewport
2453 * index in out.z[19:16].
2454 */
2455 LLVMValueRef v = viewport_index_value;
2456 v = ac_to_integer(&ctx->ac, v);
2457 v = LLVMBuildShl(ctx->ac.builder, v,
2458 LLVMConstInt(ctx->ac.i32, 16, false),
2459 "");
2460 v = LLVMBuildOr(ctx->ac.builder, v,
2461 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2462
2463 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2464 pos_args[1].enabled_channels |= 1 << 2;
2465 } else {
2466 pos_args[1].out[3] = viewport_index_value;
2467 pos_args[1].enabled_channels |= 1 << 3;
2468 }
2469 }
2470 }
2471 for (i = 0; i < 4; i++) {
2472 if (pos_args[i].out[0])
2473 num_pos_exports++;
2474 }
2475
2476 pos_idx = 0;
2477 for (i = 0; i < 4; i++) {
2478 if (!pos_args[i].out[0])
2479 continue;
2480
2481 /* Specify the target we are exporting */
2482 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2483 if (pos_idx == num_pos_exports)
2484 pos_args[i].done = 1;
2485 ac_build_export(&ctx->ac, &pos_args[i]);
2486 }
2487
2488 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2489 LLVMValueRef values[4];
2490 if (!(ctx->output_mask & (1ull << i)))
2491 continue;
2492
2493 if (i != VARYING_SLOT_LAYER &&
2494 i != VARYING_SLOT_PRIMITIVE_ID &&
2495 i < VARYING_SLOT_VAR0)
2496 continue;
2497
2498 for (unsigned j = 0; j < 4; j++)
2499 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2500
2501 unsigned output_usage_mask;
2502
2503 if (ctx->stage == MESA_SHADER_VERTEX &&
2504 !ctx->is_gs_copy_shader) {
2505 output_usage_mask =
2506 ctx->shader_info->info.vs.output_usage_mask[i];
2507 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2508 output_usage_mask =
2509 ctx->shader_info->info.tes.output_usage_mask[i];
2510 } else {
2511 assert(ctx->is_gs_copy_shader);
2512 output_usage_mask =
2513 ctx->shader_info->info.gs.output_usage_mask[i];
2514 }
2515
2516 radv_export_param(ctx, param_count, values, output_usage_mask);
2517
2518 outinfo->vs_output_param_offset[i] = param_count++;
2519 }
2520
2521 if (export_prim_id) {
2522 LLVMValueRef values[4];
2523
2524 values[0] = ctx->vs_prim_id;
2525 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
2526 ctx->shader_info->vs.vgpr_comp_cnt);
2527 for (unsigned j = 1; j < 4; j++)
2528 values[j] = ctx->ac.f32_0;
2529
2530 radv_export_param(ctx, param_count, values, 0x1);
2531
2532 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2533 outinfo->export_prim_id = true;
2534 }
2535
2536 if (export_layer_id && layer_value) {
2537 LLVMValueRef values[4];
2538
2539 values[0] = layer_value;
2540 for (unsigned j = 1; j < 4; j++)
2541 values[j] = ctx->ac.f32_0;
2542
2543 radv_export_param(ctx, param_count, values, 0x1);
2544
2545 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count++;
2546 }
2547
2548 outinfo->pos_exports = num_pos_exports;
2549 outinfo->param_exports = param_count;
2550 }
2551
2552 static void
2553 handle_es_outputs_post(struct radv_shader_context *ctx,
2554 struct radv_es_output_info *outinfo)
2555 {
2556 int j;
2557 uint64_t max_output_written = 0;
2558 LLVMValueRef lds_base = NULL;
2559
2560 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2561 int param_index;
2562 int length = 4;
2563
2564 if (!(ctx->output_mask & (1ull << i)))
2565 continue;
2566
2567 if (i == VARYING_SLOT_CLIP_DIST0)
2568 length = ctx->num_output_clips + ctx->num_output_culls;
2569
2570 param_index = shader_io_get_unique_index(i);
2571
2572 max_output_written = MAX2(param_index + (length > 4), max_output_written);
2573 }
2574
2575 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
2576
2577 if (ctx->ac.chip_class >= GFX9) {
2578 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2579 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2580 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
2581 LLVMConstInt(ctx->ac.i32, 24, false),
2582 LLVMConstInt(ctx->ac.i32, 4, false), false);
2583 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2584 LLVMBuildMul(ctx->ac.builder, wave_idx,
2585 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
2586 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2587 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2588 }
2589
2590 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2591 LLVMValueRef dw_addr = NULL;
2592 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2593 unsigned output_usage_mask;
2594 int param_index;
2595 int length = 4;
2596
2597 if (!(ctx->output_mask & (1ull << i)))
2598 continue;
2599
2600 if (ctx->stage == MESA_SHADER_VERTEX) {
2601 output_usage_mask =
2602 ctx->shader_info->info.vs.output_usage_mask[i];
2603 } else {
2604 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2605 output_usage_mask =
2606 ctx->shader_info->info.tes.output_usage_mask[i];
2607 }
2608
2609 if (i == VARYING_SLOT_CLIP_DIST0) {
2610 length = ctx->num_output_clips + ctx->num_output_culls;
2611 output_usage_mask = (1 << length) - 1;
2612 }
2613
2614 param_index = shader_io_get_unique_index(i);
2615
2616 if (lds_base) {
2617 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2618 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2619 "");
2620 }
2621
2622 for (j = 0; j < length; j++) {
2623 if (!(output_usage_mask & (1 << j)))
2624 continue;
2625
2626 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2627 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2628
2629 if (ctx->ac.chip_class >= GFX9) {
2630 LLVMValueRef dw_addr_offset =
2631 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2632 LLVMConstInt(ctx->ac.i32,
2633 j, false), "");
2634
2635 ac_lds_store(&ctx->ac, dw_addr_offset,
2636 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2637 } else {
2638 ac_build_buffer_store_dword(&ctx->ac,
2639 ctx->esgs_ring,
2640 out_val, 1,
2641 NULL, ctx->es2gs_offset,
2642 (4 * param_index + j) * 4,
2643 1, 1, true, true);
2644 }
2645 }
2646 }
2647 }
2648
2649 static void
2650 handle_ls_outputs_post(struct radv_shader_context *ctx)
2651 {
2652 LLVMValueRef vertex_id = ctx->rel_auto_id;
2653 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
2654 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2655 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2656 vertex_dw_stride, "");
2657
2658 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2659 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2660 int length = 4;
2661
2662 if (!(ctx->output_mask & (1ull << i)))
2663 continue;
2664
2665 if (i == VARYING_SLOT_CLIP_DIST0)
2666 length = ctx->num_output_clips + ctx->num_output_culls;
2667 int param = shader_io_get_unique_index(i);
2668 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2669 LLVMConstInt(ctx->ac.i32, param * 4, false),
2670 "");
2671 for (unsigned j = 0; j < length; j++) {
2672 ac_lds_store(&ctx->ac, dw_addr,
2673 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
2674 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2675 }
2676 }
2677 }
2678
2679 static void
2680 write_tess_factors(struct radv_shader_context *ctx)
2681 {
2682 unsigned stride, outer_comps, inner_comps;
2683 struct ac_build_if_state if_ctx, inner_if_ctx;
2684 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
2685 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
2686 unsigned tess_inner_index = 0, tess_outer_index;
2687 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
2688 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2689 int i;
2690 ac_emit_barrier(&ctx->ac, ctx->stage);
2691
2692 switch (ctx->options->key.tcs.primitive_mode) {
2693 case GL_ISOLINES:
2694 stride = 2;
2695 outer_comps = 2;
2696 inner_comps = 0;
2697 break;
2698 case GL_TRIANGLES:
2699 stride = 4;
2700 outer_comps = 3;
2701 inner_comps = 1;
2702 break;
2703 case GL_QUADS:
2704 stride = 6;
2705 outer_comps = 4;
2706 inner_comps = 2;
2707 break;
2708 default:
2709 return;
2710 }
2711
2712 ac_nir_build_if(&if_ctx, ctx,
2713 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2714 invocation_id, ctx->ac.i32_0, ""));
2715
2716 lds_base = get_tcs_out_current_patch_data_offset(ctx);
2717
2718 if (inner_comps) {
2719 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2720 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2721 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
2722 }
2723
2724 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2725 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2726 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
2727
2728 for (i = 0; i < 4; i++) {
2729 inner[i] = LLVMGetUndef(ctx->ac.i32);
2730 outer[i] = LLVMGetUndef(ctx->ac.i32);
2731 }
2732
2733 // LINES reversal
2734 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
2735 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
2736 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2737 ctx->ac.i32_1, "");
2738 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
2739 } else {
2740 for (i = 0; i < outer_comps; i++) {
2741 outer[i] = out[i] =
2742 ac_lds_load(&ctx->ac, lds_outer);
2743 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
2744 ctx->ac.i32_1, "");
2745 }
2746 for (i = 0; i < inner_comps; i++) {
2747 inner[i] = out[outer_comps+i] =
2748 ac_lds_load(&ctx->ac, lds_inner);
2749 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
2750 ctx->ac.i32_1, "");
2751 }
2752 }
2753
2754 /* Convert the outputs to vectors for stores. */
2755 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
2756 vec1 = NULL;
2757
2758 if (stride > 4)
2759 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
2760
2761
2762 buffer = ctx->hs_ring_tess_factor;
2763 tf_base = ctx->tess_factor_offset;
2764 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2765 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
2766 unsigned tf_offset = 0;
2767
2768 if (ctx->options->chip_class <= VI) {
2769 ac_nir_build_if(&inner_if_ctx, ctx,
2770 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2771 rel_patch_id, ctx->ac.i32_0, ""));
2772
2773 /* Store the dynamic HS control word. */
2774 ac_build_buffer_store_dword(&ctx->ac, buffer,
2775 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
2776 1, ctx->ac.i32_0, tf_base,
2777 0, 1, 0, true, false);
2778 tf_offset += 4;
2779
2780 ac_nir_build_endif(&inner_if_ctx);
2781 }
2782
2783 /* Store the tessellation factors. */
2784 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2785 MIN2(stride, 4), byteoffset, tf_base,
2786 tf_offset, 1, 0, true, false);
2787 if (vec1)
2788 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2789 stride - 4, byteoffset, tf_base,
2790 16 + tf_offset, 1, 0, true, false);
2791
2792 //store to offchip for TES to read - only if TES reads them
2793 if (ctx->options->key.tcs.tes_reads_tess_factors) {
2794 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
2795 LLVMValueRef tf_inner_offset;
2796 unsigned param_outer, param_inner;
2797
2798 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
2799 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
2800 LLVMConstInt(ctx->ac.i32, param_outer, 0));
2801
2802 outer_vec = ac_build_gather_values(&ctx->ac, outer,
2803 util_next_power_of_two(outer_comps));
2804
2805 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
2806 outer_comps, tf_outer_offset,
2807 ctx->oc_lds, 0, 1, 0, true, false);
2808 if (inner_comps) {
2809 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
2810 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
2811 LLVMConstInt(ctx->ac.i32, param_inner, 0));
2812
2813 inner_vec = inner_comps == 1 ? inner[0] :
2814 ac_build_gather_values(&ctx->ac, inner, inner_comps);
2815 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
2816 inner_comps, tf_inner_offset,
2817 ctx->oc_lds, 0, 1, 0, true, false);
2818 }
2819 }
2820 ac_nir_build_endif(&if_ctx);
2821 }
2822
2823 static void
2824 handle_tcs_outputs_post(struct radv_shader_context *ctx)
2825 {
2826 write_tess_factors(ctx);
2827 }
2828
2829 static bool
2830 si_export_mrt_color(struct radv_shader_context *ctx,
2831 LLVMValueRef *color, unsigned index,
2832 struct ac_export_args *args)
2833 {
2834 /* Export */
2835 si_llvm_init_export_args(ctx, color, 0xf,
2836 V_008DFC_SQ_EXP_MRT + index, args);
2837 if (!args->enabled_channels)
2838 return false; /* unnecessary NULL export */
2839
2840 return true;
2841 }
2842
2843 static void
2844 radv_export_mrt_z(struct radv_shader_context *ctx,
2845 LLVMValueRef depth, LLVMValueRef stencil,
2846 LLVMValueRef samplemask)
2847 {
2848 struct ac_export_args args;
2849
2850 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
2851
2852 ac_build_export(&ctx->ac, &args);
2853 }
2854
2855 static void
2856 handle_fs_outputs_post(struct radv_shader_context *ctx)
2857 {
2858 unsigned index = 0;
2859 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2860 struct ac_export_args color_args[8];
2861
2862 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2863 LLVMValueRef values[4];
2864
2865 if (!(ctx->output_mask & (1ull << i)))
2866 continue;
2867
2868 if (i < FRAG_RESULT_DATA0)
2869 continue;
2870
2871 for (unsigned j = 0; j < 4; j++)
2872 values[j] = ac_to_float(&ctx->ac,
2873 radv_load_output(ctx, i, j));
2874
2875 bool ret = si_export_mrt_color(ctx, values,
2876 i - FRAG_RESULT_DATA0,
2877 &color_args[index]);
2878 if (ret)
2879 index++;
2880 }
2881
2882 /* Process depth, stencil, samplemask. */
2883 if (ctx->shader_info->info.ps.writes_z) {
2884 depth = ac_to_float(&ctx->ac,
2885 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
2886 }
2887 if (ctx->shader_info->info.ps.writes_stencil) {
2888 stencil = ac_to_float(&ctx->ac,
2889 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
2890 }
2891 if (ctx->shader_info->info.ps.writes_sample_mask) {
2892 samplemask = ac_to_float(&ctx->ac,
2893 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
2894 }
2895
2896 /* Set the DONE bit on last non-null color export only if Z isn't
2897 * exported.
2898 */
2899 if (index > 0 &&
2900 !ctx->shader_info->info.ps.writes_z &&
2901 !ctx->shader_info->info.ps.writes_stencil &&
2902 !ctx->shader_info->info.ps.writes_sample_mask) {
2903 unsigned last = index - 1;
2904
2905 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
2906 color_args[last].done = 1; /* DONE bit */
2907 }
2908
2909 /* Export PS outputs. */
2910 for (unsigned i = 0; i < index; i++)
2911 ac_build_export(&ctx->ac, &color_args[i]);
2912
2913 if (depth || stencil || samplemask)
2914 radv_export_mrt_z(ctx, depth, stencil, samplemask);
2915 else if (!index)
2916 ac_build_export_null(&ctx->ac);
2917 }
2918
2919 static void
2920 emit_gs_epilogue(struct radv_shader_context *ctx)
2921 {
2922 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
2923 }
2924
2925 static void
2926 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
2927 LLVMValueRef *addrs)
2928 {
2929 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2930
2931 switch (ctx->stage) {
2932 case MESA_SHADER_VERTEX:
2933 if (ctx->options->key.vs.as_ls)
2934 handle_ls_outputs_post(ctx);
2935 else if (ctx->options->key.vs.as_es)
2936 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
2937 else
2938 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
2939 ctx->options->key.vs.export_layer_id,
2940 &ctx->shader_info->vs.outinfo);
2941 break;
2942 case MESA_SHADER_FRAGMENT:
2943 handle_fs_outputs_post(ctx);
2944 break;
2945 case MESA_SHADER_GEOMETRY:
2946 emit_gs_epilogue(ctx);
2947 break;
2948 case MESA_SHADER_TESS_CTRL:
2949 handle_tcs_outputs_post(ctx);
2950 break;
2951 case MESA_SHADER_TESS_EVAL:
2952 if (ctx->options->key.tes.as_es)
2953 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
2954 else
2955 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
2956 ctx->options->key.tes.export_layer_id,
2957 &ctx->shader_info->tes.outinfo);
2958 break;
2959 default:
2960 break;
2961 }
2962 }
2963
2964 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
2965 {
2966 LLVMPassManagerRef passmgr;
2967 /* Create the pass manager */
2968 passmgr = LLVMCreateFunctionPassManagerForModule(
2969 ctx->ac.module);
2970
2971 /* This pass should eliminate all the load and store instructions */
2972 LLVMAddPromoteMemoryToRegisterPass(passmgr);
2973
2974 /* Add some optimization passes */
2975 LLVMAddScalarReplAggregatesPass(passmgr);
2976 LLVMAddLICMPass(passmgr);
2977 LLVMAddAggressiveDCEPass(passmgr);
2978 LLVMAddCFGSimplificationPass(passmgr);
2979 LLVMAddInstructionCombiningPass(passmgr);
2980
2981 /* Run the pass */
2982 LLVMInitializeFunctionPassManager(passmgr);
2983 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
2984 LLVMFinalizeFunctionPassManager(passmgr);
2985
2986 LLVMDisposeBuilder(ctx->ac.builder);
2987 LLVMDisposePassManager(passmgr);
2988
2989 ac_llvm_context_dispose(&ctx->ac);
2990 }
2991
2992 static void
2993 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
2994 {
2995 struct radv_vs_output_info *outinfo;
2996
2997 switch (ctx->stage) {
2998 case MESA_SHADER_FRAGMENT:
2999 case MESA_SHADER_COMPUTE:
3000 case MESA_SHADER_TESS_CTRL:
3001 case MESA_SHADER_GEOMETRY:
3002 return;
3003 case MESA_SHADER_VERTEX:
3004 if (ctx->options->key.vs.as_ls ||
3005 ctx->options->key.vs.as_es)
3006 return;
3007 outinfo = &ctx->shader_info->vs.outinfo;
3008 break;
3009 case MESA_SHADER_TESS_EVAL:
3010 if (ctx->options->key.vs.as_es)
3011 return;
3012 outinfo = &ctx->shader_info->tes.outinfo;
3013 break;
3014 default:
3015 unreachable("Unhandled shader type");
3016 }
3017
3018 ac_optimize_vs_outputs(&ctx->ac,
3019 ctx->main_function,
3020 outinfo->vs_output_param_offset,
3021 VARYING_SLOT_MAX,
3022 &outinfo->param_exports);
3023 }
3024
3025 static void
3026 ac_setup_rings(struct radv_shader_context *ctx)
3027 {
3028 if (ctx->options->chip_class <= VI &&
3029 (ctx->stage == MESA_SHADER_GEOMETRY ||
3030 ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
3031 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3032 : RING_ESGS_VS;
3033 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3034
3035 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3036 ctx->ring_offsets,
3037 offset);
3038 }
3039
3040 if (ctx->is_gs_copy_shader) {
3041 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
3042 }
3043 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3044 LLVMValueRef tmp;
3045 uint32_t num_entries = 64;
3046 LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size, false);
3047 LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, ctx->max_gsvs_emit_size << 16, false);
3048 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
3049
3050 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
3051
3052 tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
3053 if (ctx->options->chip_class >= VI)
3054 tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, tmp, "");
3055 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3056 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
3057 tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
3058 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
3059 }
3060
3061 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3062 ctx->stage == MESA_SHADER_TESS_EVAL) {
3063 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3064 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3065 }
3066 }
3067
3068 static unsigned
3069 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
3070 const struct nir_shader *nir)
3071 {
3072 switch (nir->info.stage) {
3073 case MESA_SHADER_TESS_CTRL:
3074 return chip_class >= CIK ? 128 : 64;
3075 case MESA_SHADER_GEOMETRY:
3076 return chip_class >= GFX9 ? 128 : 64;
3077 case MESA_SHADER_COMPUTE:
3078 break;
3079 default:
3080 return 0;
3081 }
3082
3083 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
3084 nir->info.cs.local_size[1] *
3085 nir->info.cs.local_size[2];
3086 return max_workgroup_size;
3087 }
3088
3089 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3090 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3091 {
3092 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3093 LLVMConstInt(ctx->ac.i32, 8, false),
3094 LLVMConstInt(ctx->ac.i32, 8, false), false);
3095 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3096 ctx->ac.i32_0, "");
3097 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
3098 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
3099 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
3100 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
3101 }
3102
3103 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
3104 {
3105 for(int i = 5; i >= 0; --i) {
3106 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
3107 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
3108 LLVMConstInt(ctx->ac.i32, 16, false), false);
3109 }
3110
3111 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
3112 LLVMConstInt(ctx->ac.i32, 16, false),
3113 LLVMConstInt(ctx->ac.i32, 8, false), false);
3114 }
3115
3116
3117 static
3118 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
3119 struct nir_shader *const *shaders,
3120 int shader_count,
3121 struct radv_shader_variant_info *shader_info,
3122 const struct radv_nir_compiler_options *options)
3123 {
3124 struct radv_shader_context ctx = {0};
3125 unsigned i;
3126 ctx.options = options;
3127 ctx.shader_info = shader_info;
3128 ctx.context = LLVMContextCreate();
3129
3130 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3131 options->family);
3132 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3133 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
3134
3135 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
3136 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
3137 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
3138 LLVMDisposeTargetData(data_layout);
3139 LLVMDisposeMessage(data_layout_str);
3140
3141 enum ac_float_mode float_mode =
3142 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3143 AC_FLOAT_MODE_DEFAULT;
3144
3145 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3146
3147 memset(shader_info, 0, sizeof(*shader_info));
3148
3149 for(int i = 0; i < shader_count; ++i)
3150 radv_nir_shader_info_pass(shaders[i], options, &shader_info->info);
3151
3152 for (i = 0; i < RADV_UD_MAX_SETS; i++)
3153 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
3154 for (i = 0; i < AC_UD_MAX_UD; i++)
3155 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
3156
3157 ctx.max_workgroup_size = 0;
3158 for (int i = 0; i < shader_count; ++i) {
3159 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3160 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
3161 shaders[i]));
3162 }
3163
3164 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3165 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3166
3167 ctx.abi.inputs = &ctx.inputs[0];
3168 ctx.abi.emit_outputs = handle_shader_outputs_post;
3169 ctx.abi.emit_vertex = visit_emit_vertex;
3170 ctx.abi.load_ubo = radv_load_ubo;
3171 ctx.abi.load_ssbo = radv_load_ssbo;
3172 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3173 ctx.abi.load_resource = radv_load_resource;
3174 ctx.abi.clamp_shadow_reference = false;
3175 ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9;
3176
3177 if (shader_count >= 2)
3178 ac_init_exec_full_mask(&ctx.ac);
3179
3180 if (ctx.ac.chip_class == GFX9 &&
3181 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3182 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3183
3184 for(int i = 0; i < shader_count; ++i) {
3185 ctx.stage = shaders[i]->info.stage;
3186 ctx.output_mask = 0;
3187 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
3188 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
3189
3190 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3191 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
3192 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
3193 ctx.abi.load_inputs = load_gs_input;
3194 ctx.abi.emit_primitive = visit_end_primitive;
3195 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3196 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
3197 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
3198 ctx.abi.load_tess_varyings = load_tcs_varyings;
3199 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3200 ctx.abi.store_tcs_outputs = store_tcs_output;
3201 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3202 if (shader_count == 1)
3203 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
3204 else
3205 ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
3206 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
3207 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
3208 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
3209 ctx.abi.load_tess_varyings = load_tes_input;
3210 ctx.abi.load_tess_coord = load_tess_coord;
3211 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
3212 ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
3213 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
3214 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
3215 if (shader_info->info.vs.needs_instance_id) {
3216 if (ctx.options->key.vs.as_ls) {
3217 ctx.shader_info->vs.vgpr_comp_cnt =
3218 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
3219 } else {
3220 ctx.shader_info->vs.vgpr_comp_cnt =
3221 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
3222 }
3223 }
3224 ctx.abi.load_base_vertex = radv_load_base_vertex;
3225 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
3226 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
3227 ctx.abi.lookup_interp_param = lookup_interp_param;
3228 ctx.abi.load_sample_position = load_sample_position;
3229 ctx.abi.load_sample_mask_in = load_sample_mask_in;
3230 ctx.abi.emit_kill = radv_emit_kill;
3231 }
3232
3233 if (i)
3234 ac_emit_barrier(&ctx.ac, ctx.stage);
3235
3236 nir_foreach_variable(variable, &shaders[i]->outputs)
3237 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
3238
3239 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3240 unsigned addclip = shaders[i]->info.clip_distance_array_size +
3241 shaders[i]->info.cull_distance_array_size > 4;
3242 ctx.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
3243 ctx.max_gsvs_emit_size = ctx.gsvs_vertex_size *
3244 shaders[i]->info.gs.vertices_out;
3245 }
3246
3247 ac_setup_rings(&ctx);
3248
3249 LLVMBasicBlockRef merge_block;
3250 if (shader_count >= 2) {
3251 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
3252 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3253 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
3254
3255 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
3256 LLVMConstInt(ctx.ac.i32, 8 * i, false),
3257 LLVMConstInt(ctx.ac.i32, 8, false), false);
3258 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
3259 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
3260 thread_id, count, "");
3261 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
3262
3263 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
3264 }
3265
3266 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
3267 handle_fs_inputs(&ctx, shaders[i]);
3268 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
3269 handle_vs_inputs(&ctx, shaders[i]);
3270 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
3271 prepare_gs_input_vgprs(&ctx);
3272
3273 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
3274
3275 if (shader_count >= 2) {
3276 LLVMBuildBr(ctx.ac.builder, merge_block);
3277 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
3278 }
3279
3280 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3281 shader_info->gs.gsvs_vertex_size = ctx.gsvs_vertex_size;
3282 shader_info->gs.max_gsvs_emit_size = ctx.max_gsvs_emit_size;
3283 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
3284 shader_info->tcs.num_patches = ctx.tcs_num_patches;
3285 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
3286 }
3287 }
3288
3289 LLVMBuildRetVoid(ctx.ac.builder);
3290
3291 if (options->dump_preoptir)
3292 ac_dump_module(ctx.ac.module);
3293
3294 ac_llvm_finalize_module(&ctx);
3295
3296 if (shader_count == 1)
3297 ac_nir_eliminate_const_vs_outputs(&ctx);
3298
3299 if (options->dump_shader) {
3300 ctx.shader_info->private_mem_vgprs =
3301 ac_count_scratch_private_memory(ctx.main_function);
3302 }
3303
3304 return ctx.ac.module;
3305 }
3306
3307 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
3308 {
3309 unsigned *retval = (unsigned *)context;
3310 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
3311 char *description = LLVMGetDiagInfoDescription(di);
3312
3313 if (severity == LLVMDSError) {
3314 *retval = 1;
3315 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
3316 description);
3317 }
3318
3319 LLVMDisposeMessage(description);
3320 }
3321
3322 static unsigned ac_llvm_compile(LLVMModuleRef M,
3323 struct ac_shader_binary *binary,
3324 LLVMTargetMachineRef tm)
3325 {
3326 unsigned retval = 0;
3327 char *err;
3328 LLVMContextRef llvm_ctx;
3329 LLVMMemoryBufferRef out_buffer;
3330 unsigned buffer_size;
3331 const char *buffer_data;
3332 LLVMBool mem_err;
3333
3334 /* Setup Diagnostic Handler*/
3335 llvm_ctx = LLVMGetModuleContext(M);
3336
3337 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
3338 &retval);
3339
3340 /* Compile IR*/
3341 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
3342 &err, &out_buffer);
3343
3344 /* Process Errors/Warnings */
3345 if (mem_err) {
3346 fprintf(stderr, "%s: %s", __FUNCTION__, err);
3347 free(err);
3348 retval = 1;
3349 goto out;
3350 }
3351
3352 /* Extract Shader Code*/
3353 buffer_size = LLVMGetBufferSize(out_buffer);
3354 buffer_data = LLVMGetBufferStart(out_buffer);
3355
3356 ac_elf_read(buffer_data, buffer_size, binary);
3357
3358 /* Clean up */
3359 LLVMDisposeMemoryBuffer(out_buffer);
3360
3361 out:
3362 return retval;
3363 }
3364
3365 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
3366 LLVMModuleRef llvm_module,
3367 struct ac_shader_binary *binary,
3368 struct ac_shader_config *config,
3369 struct radv_shader_variant_info *shader_info,
3370 gl_shader_stage stage,
3371 const struct radv_nir_compiler_options *options)
3372 {
3373 if (options->dump_shader)
3374 ac_dump_module(llvm_module);
3375
3376 memset(binary, 0, sizeof(*binary));
3377
3378 if (options->record_llvm_ir) {
3379 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
3380 binary->llvm_ir_string = strdup(llvm_ir);
3381 LLVMDisposeMessage(llvm_ir);
3382 }
3383
3384 int v = ac_llvm_compile(llvm_module, binary, tm);
3385 if (v) {
3386 fprintf(stderr, "compile failed\n");
3387 }
3388
3389 if (options->dump_shader)
3390 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
3391
3392 ac_shader_binary_read_config(binary, config, 0, options->supports_spill);
3393
3394 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
3395 LLVMDisposeModule(llvm_module);
3396 LLVMContextDispose(ctx);
3397
3398 if (stage == MESA_SHADER_FRAGMENT) {
3399 shader_info->num_input_vgprs = 0;
3400 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
3401 shader_info->num_input_vgprs += 2;
3402 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
3403 shader_info->num_input_vgprs += 2;
3404 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
3405 shader_info->num_input_vgprs += 2;
3406 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
3407 shader_info->num_input_vgprs += 3;
3408 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
3409 shader_info->num_input_vgprs += 2;
3410 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
3411 shader_info->num_input_vgprs += 2;
3412 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
3413 shader_info->num_input_vgprs += 2;
3414 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
3415 shader_info->num_input_vgprs += 1;
3416 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
3417 shader_info->num_input_vgprs += 1;
3418 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
3419 shader_info->num_input_vgprs += 1;
3420 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
3421 shader_info->num_input_vgprs += 1;
3422 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
3423 shader_info->num_input_vgprs += 1;
3424 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
3425 shader_info->num_input_vgprs += 1;
3426 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
3427 shader_info->num_input_vgprs += 1;
3428 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
3429 shader_info->num_input_vgprs += 1;
3430 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
3431 shader_info->num_input_vgprs += 1;
3432 }
3433 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
3434
3435 /* +3 for scratch wave offset and VCC */
3436 config->num_sgprs = MAX2(config->num_sgprs,
3437 shader_info->num_input_sgprs + 3);
3438
3439 /* Enable 64-bit and 16-bit denormals, because there is no performance
3440 * cost.
3441 *
3442 * If denormals are enabled, all floating-point output modifiers are
3443 * ignored.
3444 *
3445 * Don't enable denormals for 32-bit floats, because:
3446 * - Floating-point output modifiers would be ignored by the hw.
3447 * - Some opcodes don't support denormals, such as v_mad_f32. We would
3448 * have to stop using those.
3449 * - SI & CI would be very slow.
3450 */
3451 config->float_mode |= V_00B028_FP_64_DENORMS;
3452 }
3453
3454 static void
3455 ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct radv_nir_compiler_options *options)
3456 {
3457 switch (nir->info.stage) {
3458 case MESA_SHADER_COMPUTE:
3459 for (int i = 0; i < 3; ++i)
3460 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
3461 break;
3462 case MESA_SHADER_FRAGMENT:
3463 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
3464 break;
3465 case MESA_SHADER_GEOMETRY:
3466 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
3467 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
3468 shader_info->gs.output_prim = nir->info.gs.output_primitive;
3469 shader_info->gs.invocations = nir->info.gs.invocations;
3470 break;
3471 case MESA_SHADER_TESS_EVAL:
3472 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
3473 shader_info->tes.spacing = nir->info.tess.spacing;
3474 shader_info->tes.ccw = nir->info.tess.ccw;
3475 shader_info->tes.point_mode = nir->info.tess.point_mode;
3476 shader_info->tes.as_es = options->key.tes.as_es;
3477 break;
3478 case MESA_SHADER_TESS_CTRL:
3479 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
3480 break;
3481 case MESA_SHADER_VERTEX:
3482 shader_info->vs.as_es = options->key.vs.as_es;
3483 shader_info->vs.as_ls = options->key.vs.as_ls;
3484 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
3485 if (options->key.vs.as_ls)
3486 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
3487 break;
3488 default:
3489 break;
3490 }
3491 }
3492
3493 void
3494 radv_compile_nir_shader(LLVMTargetMachineRef tm,
3495 struct ac_shader_binary *binary,
3496 struct ac_shader_config *config,
3497 struct radv_shader_variant_info *shader_info,
3498 struct nir_shader *const *nir,
3499 int nir_count,
3500 const struct radv_nir_compiler_options *options)
3501 {
3502
3503 LLVMModuleRef llvm_module;
3504
3505 llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
3506 options);
3507
3508 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
3509 nir[0]->info.stage, options);
3510
3511 for (int i = 0; i < nir_count; ++i)
3512 ac_fill_shader_info(shader_info, nir[i], options);
3513
3514 /* Determine the ES type (VS or TES) for the GS on GFX9. */
3515 if (options->chip_class == GFX9) {
3516 if (nir_count == 2 &&
3517 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
3518 shader_info->gs.es_type = nir[0]->info.stage;
3519 }
3520 }
3521 }
3522
3523 static void
3524 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
3525 {
3526 LLVMValueRef vtx_offset =
3527 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
3528 LLVMConstInt(ctx->ac.i32, 4, false), "");
3529 int idx = 0;
3530
3531 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3532 int length = 4;
3533 int slot = idx;
3534 int slot_inc = 1;
3535 if (!(ctx->output_mask & (1ull << i)))
3536 continue;
3537
3538 if (i == VARYING_SLOT_CLIP_DIST0) {
3539 /* unpack clip and cull from a single set of slots */
3540 length = ctx->num_output_clips + ctx->num_output_culls;
3541 if (length > 4)
3542 slot_inc = 2;
3543 }
3544
3545 for (unsigned j = 0; j < length; j++) {
3546 LLVMValueRef value, soffset;
3547
3548 soffset = LLVMConstInt(ctx->ac.i32,
3549 (slot * 4 + j) *
3550 ctx->gs_max_out_vertices * 16 * 4, false);
3551
3552 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
3553 1, ctx->ac.i32_0,
3554 vtx_offset, soffset,
3555 0, 1, 1, true, false);
3556
3557 LLVMBuildStore(ctx->ac.builder,
3558 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3559 }
3560 idx += slot_inc;
3561 }
3562 handle_vs_outputs_post(ctx, false, false, &ctx->shader_info->vs.outinfo);
3563 }
3564
3565 void
3566 radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
3567 struct nir_shader *geom_shader,
3568 struct ac_shader_binary *binary,
3569 struct ac_shader_config *config,
3570 struct radv_shader_variant_info *shader_info,
3571 const struct radv_nir_compiler_options *options)
3572 {
3573 struct radv_shader_context ctx = {0};
3574 ctx.context = LLVMContextCreate();
3575 ctx.options = options;
3576 ctx.shader_info = shader_info;
3577
3578 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
3579 options->family);
3580 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
3581
3582 ctx.is_gs_copy_shader = true;
3583 LLVMSetTarget(ctx.ac.module, "amdgcn--");
3584
3585 enum ac_float_mode float_mode =
3586 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
3587 AC_FLOAT_MODE_DEFAULT;
3588
3589 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
3590 ctx.stage = MESA_SHADER_VERTEX;
3591
3592 radv_nir_shader_info_pass(geom_shader, options, &shader_info->info);
3593
3594 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
3595
3596 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
3597 ac_setup_rings(&ctx);
3598
3599 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
3600 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
3601
3602 nir_foreach_variable(variable, &geom_shader->outputs) {
3603 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
3604 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
3605 variable, MESA_SHADER_VERTEX);
3606 }
3607
3608 ac_gs_copy_shader_emit(&ctx);
3609
3610 LLVMBuildRetVoid(ctx.ac.builder);
3611
3612 ac_llvm_finalize_module(&ctx);
3613
3614 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
3615 MESA_SHADER_VERTEX, options);
3616 }