2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 struct radv_shader_context
{
50 struct ac_llvm_context ac
;
51 const struct nir_shader
*shader
;
52 struct ac_shader_abi abi
;
53 const struct radv_shader_args
*args
;
55 gl_shader_stage stage
;
57 unsigned max_workgroup_size
;
58 LLVMContextRef context
;
59 LLVMValueRef main_function
;
61 LLVMValueRef descriptor_sets
[MAX_SETS
];
63 LLVMValueRef ring_offsets
;
65 LLVMValueRef rel_auto_id
;
67 LLVMValueRef gs_wave_id
;
68 LLVMValueRef gs_vtx_offset
[6];
70 LLVMValueRef esgs_ring
;
71 LLVMValueRef gsvs_ring
[4];
72 LLVMValueRef hs_ring_tess_offchip
;
73 LLVMValueRef hs_ring_tess_factor
;
75 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
79 LLVMValueRef gs_next_vertex
[4];
80 LLVMValueRef gs_curprim_verts
[4];
81 LLVMValueRef gs_generated_prims
[4];
82 LLVMValueRef gs_ngg_emit
;
83 LLVMValueRef gs_ngg_scratch
;
85 uint32_t tcs_num_inputs
;
86 uint32_t tcs_num_patches
;
88 LLVMValueRef vertexptr
; /* GFX10 only */
91 struct radv_shader_output_values
{
92 LLVMValueRef values
[4];
98 static inline struct radv_shader_context
*
99 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
101 struct radv_shader_context
*ctx
= NULL
;
102 return container_of(abi
, ctx
, abi
);
105 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
107 switch (ctx
->stage
) {
108 case MESA_SHADER_TESS_CTRL
:
109 return ac_unpack_param(&ctx
->ac
,
110 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
112 case MESA_SHADER_TESS_EVAL
:
113 return ac_get_arg(&ctx
->ac
, ctx
->args
->tes_rel_patch_id
);
116 unreachable("Illegal stage");
121 get_tcs_num_patches(struct radv_shader_context
*ctx
)
123 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
124 unsigned num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
125 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
126 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
127 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
128 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
129 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
130 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
131 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
132 unsigned num_patches
;
133 unsigned hardware_lds_size
;
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
139 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
143 hardware_lds_size
= 32768;
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
150 if (ctx
->args
->options
->chip_class
>= GFX7
&& ctx
->args
->options
->family
!= CHIP_STONEY
)
151 hardware_lds_size
= 65536;
153 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches
= MIN2(num_patches
, (ctx
->args
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
159 num_patches
= MIN2(num_patches
, 40);
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx
->args
->options
->chip_class
== GFX6
) {
163 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
164 num_patches
= MIN2(num_patches
, one_wave
);
170 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
172 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
173 unsigned num_tcs_output_cp
;
174 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
175 unsigned input_vertex_size
, output_vertex_size
;
176 unsigned input_patch_size
, output_patch_size
;
177 unsigned pervertex_output_patch_size
;
178 unsigned output_patch0_offset
;
179 unsigned num_patches
;
182 num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
183 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
184 num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
186 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
187 output_vertex_size
= num_tcs_outputs
* 16;
189 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
191 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
192 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
194 num_patches
= ctx
->tcs_num_patches
;
195 output_patch0_offset
= input_patch_size
* num_patches
;
197 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
201 /* Tessellation shaders pass outputs to the next shader using LDS.
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
224 assert(ctx
->stage
== MESA_SHADER_TESS_CTRL
);
225 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
226 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
228 input_patch_size
/= 4;
229 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
233 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
235 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
236 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
237 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
238 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
239 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
240 output_patch_size
/= 4;
241 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
245 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
247 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
248 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
249 output_vertex_size
/= 4;
250 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
254 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
256 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
257 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
258 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
259 uint32_t output_patch0_offset
= input_patch_size
;
260 unsigned num_patches
= ctx
->tcs_num_patches
;
262 output_patch0_offset
*= num_patches
;
263 output_patch0_offset
/= 4;
264 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
270 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
271 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
272 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
273 uint32_t output_patch0_offset
= input_patch_size
;
275 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
276 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
277 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
278 unsigned num_patches
= ctx
->tcs_num_patches
;
280 output_patch0_offset
*= num_patches
;
281 output_patch0_offset
+= pervertex_output_patch_size
;
282 output_patch0_offset
/= 4;
283 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
287 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
289 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
290 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
292 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
296 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
298 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
299 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
300 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
302 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
309 LLVMValueRef patch0_patch_data_offset
=
310 get_tcs_out_patch0_patch_data_offset(ctx
);
311 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
312 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
314 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
315 patch0_patch_data_offset
);
319 create_llvm_function(struct ac_llvm_context
*ctx
, LLVMModuleRef module
,
320 LLVMBuilderRef builder
,
321 const struct ac_shader_args
*args
,
322 enum ac_llvm_calling_convention convention
,
323 unsigned max_workgroup_size
,
324 const struct radv_nir_compiler_options
*options
)
326 LLVMValueRef main_function
=
327 ac_build_main(args
, ctx
, convention
, "main", ctx
->voidt
, module
);
329 if (options
->address32_hi
) {
330 ac_llvm_add_target_dep_function_attr(main_function
,
331 "amdgpu-32bit-address-high-bits",
332 options
->address32_hi
);
335 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
337 return main_function
;
341 load_descriptor_sets(struct radv_shader_context
*ctx
)
343 uint32_t mask
= ctx
->args
->shader_info
->desc_set_used_mask
;
344 if (ctx
->args
->shader_info
->need_indirect_descriptor_sets
) {
345 LLVMValueRef desc_sets
=
346 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[0]);
348 int i
= u_bit_scan(&mask
);
350 ctx
->descriptor_sets
[i
] =
351 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
352 LLVMConstInt(ctx
->ac
.i32
, i
, false));
357 int i
= u_bit_scan(&mask
);
359 ctx
->descriptor_sets
[i
] =
360 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[i
]);
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func
, gl_shader_stage stage
)
369 case MESA_SHADER_VERTEX
:
370 case MESA_SHADER_TESS_EVAL
:
371 return AC_LLVM_AMDGPU_VS
;
373 case MESA_SHADER_GEOMETRY
:
374 return AC_LLVM_AMDGPU_GS
;
376 case MESA_SHADER_TESS_CTRL
:
377 return AC_LLVM_AMDGPU_HS
;
379 case MESA_SHADER_FRAGMENT
:
380 return AC_LLVM_AMDGPU_PS
;
382 case MESA_SHADER_COMPUTE
:
383 return AC_LLVM_AMDGPU_CS
;
386 unreachable("Unhandle shader type");
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage
)
393 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
396 static void create_function(struct radv_shader_context
*ctx
,
397 gl_shader_stage stage
,
398 bool has_previous_stage
)
400 if (ctx
->ac
.chip_class
>= GFX10
) {
401 if (is_pre_gs_stage(stage
) && ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage
= MESA_SHADER_GEOMETRY
;
404 has_previous_stage
= true;
408 ctx
->main_function
= create_llvm_function(
409 &ctx
->ac
, ctx
->ac
.module
, ctx
->ac
.builder
, &ctx
->args
->ac
,
410 get_llvm_calling_convention(ctx
->main_function
, stage
),
411 ctx
->max_workgroup_size
,
414 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
415 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
416 NULL
, 0, AC_FUNC_ATTR_READNONE
);
417 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
418 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
420 load_descriptor_sets(ctx
);
422 if (stage
== MESA_SHADER_TESS_CTRL
||
423 (stage
== MESA_SHADER_VERTEX
&& ctx
->args
->options
->key
.vs_common_out
.as_ls
) ||
424 /* GFX9 has the ESGS ring buffer in LDS. */
425 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
426 ac_declare_lds_as_pointer(&ctx
->ac
);
433 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
434 unsigned desc_set
, unsigned binding
)
436 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
437 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
438 struct radv_pipeline_layout
*pipeline_layout
= ctx
->args
->options
->layout
;
439 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
440 unsigned base_offset
= layout
->binding
[binding
].offset
;
441 LLVMValueRef offset
, stride
;
443 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
444 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
445 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
446 layout
->binding
[binding
].dynamic_offset_offset
;
447 desc_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.push_constants
);
448 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
449 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
451 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
453 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
455 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
456 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
459 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
460 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
461 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
463 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
464 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
469 if (ctx
->ac
.chip_class
>= GFX10
) {
470 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
471 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
472 S_008F0C_RESOURCE_LEVEL(1);
474 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
478 LLVMValueRef desc_components
[4] = {
479 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
480 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->args
->options
->address32_hi
), false),
481 /* High limit to support variable sizes. */
482 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
483 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
486 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
493 /* The offchip buffer layout for TCS->TES is
495 * - attribute 0 of patch 0 vertex 0
496 * - attribute 0 of patch 0 vertex 1
497 * - attribute 0 of patch 0 vertex 2
499 * - attribute 0 of patch 1 vertex 0
500 * - attribute 0 of patch 1 vertex 1
502 * - attribute 1 of patch 0 vertex 0
503 * - attribute 1 of patch 0 vertex 1
505 * - per patch attribute 0 of patch 0
506 * - per patch attribute 0 of patch 1
509 * Note that every attribute has 4 components.
511 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
513 uint32_t num_patches
= ctx
->tcs_num_patches
;
514 uint32_t num_tcs_outputs
;
515 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
516 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
518 num_tcs_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
520 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
521 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
523 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
526 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
527 LLVMValueRef vertex_index
)
529 LLVMValueRef param_stride
;
531 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
533 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
537 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
538 LLVMValueRef vertex_index
,
539 LLVMValueRef param_index
)
541 LLVMValueRef base_addr
;
542 LLVMValueRef param_stride
, constant16
;
543 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
544 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
545 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
546 param_stride
= calc_param_stride(ctx
, vertex_index
);
548 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
549 vertices_per_patch
, vertex_index
);
551 base_addr
= rel_patch_id
;
554 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
555 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
556 param_stride
, ""), "");
558 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
561 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
563 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
564 patch_data_offset
, "");
569 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
571 unsigned const_index
,
573 LLVMValueRef vertex_index
,
574 LLVMValueRef indir_index
)
576 LLVMValueRef param_index
;
579 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
582 if (const_index
&& !is_compact
)
583 param
+= const_index
;
584 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
586 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
590 get_dw_address(struct radv_shader_context
*ctx
,
591 LLVMValueRef dw_addr
,
593 unsigned const_index
,
594 bool compact_const_index
,
595 LLVMValueRef vertex_index
,
597 LLVMValueRef indir_index
)
602 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
603 LLVMBuildMul(ctx
->ac
.builder
,
609 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
610 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
611 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
612 else if (const_index
&& !compact_const_index
)
613 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
614 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
616 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
617 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
619 if (const_index
&& compact_const_index
)
620 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
621 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
626 load_tcs_varyings(struct ac_shader_abi
*abi
,
628 LLVMValueRef vertex_index
,
629 LLVMValueRef indir_index
,
630 unsigned const_index
,
632 unsigned driver_location
,
634 unsigned num_components
,
639 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
640 LLVMValueRef dw_addr
, stride
;
641 LLVMValueRef value
[4], result
;
642 unsigned param
= shader_io_get_unique_index(location
);
645 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
646 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
647 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
650 stride
= get_tcs_out_vertex_stride(ctx
);
651 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
653 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
658 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
661 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
662 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
663 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
666 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
671 store_tcs_output(struct ac_shader_abi
*abi
,
672 const nir_variable
*var
,
673 LLVMValueRef vertex_index
,
674 LLVMValueRef param_index
,
675 unsigned const_index
,
679 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
680 const unsigned location
= var
->data
.location
;
681 unsigned component
= var
->data
.location_frac
;
682 const bool is_patch
= var
->data
.patch
;
683 const bool is_compact
= var
->data
.compact
;
684 LLVMValueRef dw_addr
;
685 LLVMValueRef stride
= NULL
;
686 LLVMValueRef buf_addr
= NULL
;
687 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
689 bool store_lds
= true;
692 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
695 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
699 param
= shader_io_get_unique_index(location
);
700 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
701 const_index
+= component
;
704 if (const_index
>= 4) {
711 stride
= get_tcs_out_vertex_stride(ctx
);
712 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
714 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
717 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
719 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
720 vertex_index
, param_index
);
722 bool is_tess_factor
= false;
723 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
724 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
725 is_tess_factor
= true;
727 unsigned base
= is_compact
? const_index
: 0;
728 for (unsigned chan
= 0; chan
< 8; chan
++) {
729 if (!(writemask
& (1 << chan
)))
731 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
732 value
= ac_to_integer(&ctx
->ac
, value
);
733 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
735 if (store_lds
|| is_tess_factor
) {
736 LLVMValueRef dw_addr_chan
=
737 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
738 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
739 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
742 if (!is_tess_factor
&& writemask
!= 0xF)
743 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
745 4 * (base
+ chan
), ac_glc
);
748 if (writemask
== 0xF) {
749 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
756 load_tes_input(struct ac_shader_abi
*abi
,
758 LLVMValueRef vertex_index
,
759 LLVMValueRef param_index
,
760 unsigned const_index
,
762 unsigned driver_location
,
764 unsigned num_components
,
769 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
770 LLVMValueRef buf_addr
;
772 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
773 unsigned param
= shader_io_get_unique_index(location
);
775 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
776 const_index
+= component
;
778 if (const_index
>= 4) {
784 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
785 is_compact
, vertex_index
, param_index
);
787 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
788 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
790 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
791 buf_addr
, oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
792 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
797 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
798 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
800 LLVMValueRef values
[2] = {
801 ac_to_integer(&ctx
->ac
, a
),
802 ac_to_integer(&ctx
->ac
, b
),
804 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
805 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
809 load_gs_input(struct ac_shader_abi
*abi
,
811 unsigned driver_location
,
813 unsigned num_components
,
814 unsigned vertex_index
,
815 unsigned const_index
,
818 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
819 LLVMValueRef vtx_offset
;
820 unsigned param
, vtx_offset_param
;
821 LLVMValueRef value
[4], result
;
823 vtx_offset_param
= vertex_index
;
824 assert(vtx_offset_param
< 6);
825 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
826 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
828 param
= shader_io_get_unique_index(location
);
830 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
831 if (ctx
->ac
.chip_class
>= GFX9
) {
832 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
833 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
834 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
835 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
837 if (ac_get_type_size(type
) == 8) {
838 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
839 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
840 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
842 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
845 LLVMValueRef soffset
=
846 LLVMConstInt(ctx
->ac
.i32
,
847 (param
* 4 + i
+ const_index
) * 256,
850 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
854 0, ac_glc
, true, false);
856 if (ac_get_type_size(type
) == 8) {
857 soffset
= LLVMConstInt(ctx
->ac
.i32
,
858 (param
* 4 + i
+ const_index
+ 1) * 256,
862 ac_build_buffer_load(&ctx
->ac
,
866 0, ac_glc
, true, false);
868 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
872 if (ac_get_type_size(type
) == 2) {
873 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
874 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
876 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
878 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
879 result
= ac_to_integer(&ctx
->ac
, result
);
884 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
886 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
887 ac_build_kill_if_false(&ctx
->ac
, visible
);
891 radv_get_sample_pos_offset(uint32_t num_samples
)
893 uint32_t sample_pos_offset
= 0;
895 switch (num_samples
) {
897 sample_pos_offset
= 1;
900 sample_pos_offset
= 3;
903 sample_pos_offset
= 7;
908 return sample_pos_offset
;
911 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
912 LLVMValueRef sample_id
)
914 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
917 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
918 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
920 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
921 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
923 uint32_t sample_pos_offset
=
924 radv_get_sample_pos_offset(ctx
->args
->options
->key
.fs
.num_samples
);
927 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
928 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
929 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
935 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
937 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
938 uint8_t log2_ps_iter_samples
;
940 if (ctx
->args
->shader_info
->ps
.force_persample
) {
941 log2_ps_iter_samples
=
942 util_logbase2(ctx
->args
->options
->key
.fs
.num_samples
);
944 log2_ps_iter_samples
= ctx
->args
->options
->key
.fs
.log2_ps_iter_samples
;
947 /* The bit pattern matches that used by fixed function fragment
949 static const uint16_t ps_iter_masks
[] = {
950 0xffff, /* not used */
956 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
958 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
960 LLVMValueRef result
, sample_id
;
961 sample_id
= ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.ancillary
), 8, 4);
962 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
963 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
,
964 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.sample_coverage
), "");
969 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
971 LLVMValueRef
*addrs
);
974 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
976 LLVMValueRef gs_next_vertex
;
977 LLVMValueRef can_emit
;
979 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
981 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
982 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
986 /* Write vertex attribute values to GSVS ring */
987 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
988 ctx
->gs_next_vertex
[stream
],
991 /* If this thread has already emitted the declared maximum number of
992 * vertices, don't emit any more: excessive vertex emissions are not
993 * supposed to have any effect.
995 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
996 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
998 bool use_kill
= !ctx
->args
->shader_info
->gs
.writes_memory
;
1000 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1002 ac_build_ifcc(&ctx
->ac
, can_emit
, 6505);
1004 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1005 unsigned output_usage_mask
=
1006 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
1007 uint8_t output_stream
=
1008 ctx
->args
->shader_info
->gs
.output_streams
[i
];
1009 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1010 int length
= util_last_bit(output_usage_mask
);
1012 if (!(ctx
->output_mask
& (1ull << i
)) ||
1013 output_stream
!= stream
)
1016 for (unsigned j
= 0; j
< length
; j
++) {
1017 if (!(output_usage_mask
& (1 << j
)))
1020 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1022 LLVMValueRef voffset
=
1023 LLVMConstInt(ctx
->ac
.i32
, offset
*
1024 ctx
->shader
->info
.gs
.vertices_out
, false);
1028 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1029 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1031 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1032 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1034 ac_build_buffer_store_dword(&ctx
->ac
,
1035 ctx
->gsvs_ring
[stream
],
1038 ac_get_arg(&ctx
->ac
,
1039 ctx
->args
->gs2vs_offset
),
1040 0, ac_glc
| ac_slc
| ac_swizzled
);
1044 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1046 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1048 ac_build_sendmsg(&ctx
->ac
,
1049 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1053 ac_build_endif(&ctx
->ac
, 6505);
1057 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1059 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1061 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
1062 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1066 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1070 load_tess_coord(struct ac_shader_abi
*abi
)
1072 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1074 LLVMValueRef coord
[4] = {
1075 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_u
),
1076 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_v
),
1081 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
1082 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1083 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1085 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1089 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1091 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1092 return LLVMConstInt(ctx
->ac
.i32
, ctx
->args
->options
->key
.tcs
.input_vertices
, false);
1096 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1098 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1099 return ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.base_vertex
);
1102 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1103 LLVMValueRef buffer_ptr
, bool write
)
1105 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1106 LLVMValueRef result
;
1108 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1110 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1111 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1116 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1118 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1119 LLVMValueRef result
;
1121 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1122 /* Do not load the descriptor for inlined uniform blocks. */
1126 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1128 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1129 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1134 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1135 unsigned descriptor_set
,
1136 unsigned base_index
,
1137 unsigned constant_index
,
1139 enum ac_descriptor_type desc_type
,
1140 bool image
, bool write
,
1143 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1144 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1145 struct radv_descriptor_set_layout
*layout
= ctx
->args
->options
->layout
->set
[descriptor_set
].layout
;
1146 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1147 unsigned offset
= binding
->offset
;
1148 unsigned stride
= binding
->size
;
1150 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1153 assert(base_index
< layout
->binding_count
);
1155 switch (desc_type
) {
1157 type
= ctx
->ac
.v8i32
;
1161 type
= ctx
->ac
.v8i32
;
1165 case AC_DESC_SAMPLER
:
1166 type
= ctx
->ac
.v4i32
;
1167 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1168 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1173 case AC_DESC_BUFFER
:
1174 type
= ctx
->ac
.v4i32
;
1177 case AC_DESC_PLANE_0
:
1178 case AC_DESC_PLANE_1
:
1179 case AC_DESC_PLANE_2
:
1180 type
= ctx
->ac
.v8i32
;
1182 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1185 unreachable("invalid desc_type\n");
1188 offset
+= constant_index
* stride
;
1190 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1191 (!index
|| binding
->immutable_samplers_equal
)) {
1192 if (binding
->immutable_samplers_equal
)
1195 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1197 LLVMValueRef constants
[] = {
1198 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1199 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1200 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1201 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1203 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1206 assert(stride
% type_size
== 0);
1208 LLVMValueRef adjusted_index
= index
;
1209 if (!adjusted_index
)
1210 adjusted_index
= ctx
->ac
.i32_0
;
1212 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1214 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1215 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1216 list
= LLVMBuildPointerCast(builder
, list
,
1217 ac_array_in_const32_addr_space(type
), "");
1219 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1221 /* 3 plane formats always have same size and format for plane 1 & 2, so
1222 * use the tail from plane 1 so that we can store only the first 16 bytes
1223 * of the last plane. */
1224 if (desc_type
== AC_DESC_PLANE_2
) {
1225 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1227 LLVMValueRef components
[8];
1228 for (unsigned i
= 0; i
< 4; ++i
)
1229 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1231 for (unsigned i
= 4; i
< 8; ++i
)
1232 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1233 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1239 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1240 * so we may need to fix it up. */
1242 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1243 unsigned adjustment
,
1246 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1249 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1251 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1253 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1254 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1256 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1258 /* For the integer-like cases, do a natural sign extension.
1260 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1261 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1264 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1265 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1266 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1267 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1269 /* Convert back to the right type. */
1270 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1272 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1273 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1274 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1275 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1276 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1277 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1280 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1283 static const struct vertex_format_info
{
1284 uint8_t vertex_byte_size
;
1285 uint8_t num_channels
;
1286 uint8_t chan_byte_size
;
1287 uint8_t chan_format
;
1288 } vertex_format_table
[] = {
1289 { 0, 4, 0, V_008F0C_BUF_DATA_FORMAT_INVALID
}, /* BUF_DATA_FORMAT_INVALID */
1290 { 1, 1, 1, V_008F0C_BUF_DATA_FORMAT_8
}, /* BUF_DATA_FORMAT_8 */
1291 { 2, 1, 2, V_008F0C_BUF_DATA_FORMAT_16
}, /* BUF_DATA_FORMAT_16 */
1292 { 2, 2, 1, V_008F0C_BUF_DATA_FORMAT_8
}, /* BUF_DATA_FORMAT_8_8 */
1293 { 4, 1, 4, V_008F0C_BUF_DATA_FORMAT_32
}, /* BUF_DATA_FORMAT_32 */
1294 { 4, 2, 2, V_008F0C_BUF_DATA_FORMAT_16
}, /* BUF_DATA_FORMAT_16_16 */
1295 { 4, 3, 0, V_008F0C_BUF_DATA_FORMAT_10_11_11
}, /* BUF_DATA_FORMAT_10_11_11 */
1296 { 4, 3, 0, V_008F0C_BUF_DATA_FORMAT_11_11_10
}, /* BUF_DATA_FORMAT_11_11_10 */
1297 { 4, 4, 0, V_008F0C_BUF_DATA_FORMAT_10_10_10_2
}, /* BUF_DATA_FORMAT_10_10_10_2 */
1298 { 4, 4, 0, V_008F0C_BUF_DATA_FORMAT_2_10_10_10
}, /* BUF_DATA_FORMAT_2_10_10_10 */
1299 { 4, 4, 1, V_008F0C_BUF_DATA_FORMAT_8
}, /* BUF_DATA_FORMAT_8_8_8_8 */
1300 { 8, 2, 4, V_008F0C_BUF_DATA_FORMAT_32
}, /* BUF_DATA_FORMAT_32_32 */
1301 { 8, 4, 2, V_008F0C_BUF_DATA_FORMAT_16
}, /* BUF_DATA_FORMAT_16_16_16_16 */
1302 { 12, 3, 4, V_008F0C_BUF_DATA_FORMAT_32
}, /* BUF_DATA_FORMAT_32_32_32 */
1303 { 16, 4, 4, V_008F0C_BUF_DATA_FORMAT_32
}, /* BUF_DATA_FORMAT_32_32_32_32 */
1307 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
1309 unsigned num_channels
,
1312 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
1313 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
1314 LLVMValueRef chan
[4];
1316 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
1317 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
1319 if (num_channels
== 4 && num_channels
== vec_size
)
1322 num_channels
= MIN2(num_channels
, vec_size
);
1324 for (unsigned i
= 0; i
< num_channels
; i
++)
1325 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
1327 assert(num_channels
== 1);
1331 for (unsigned i
= num_channels
; i
< 4; i
++) {
1332 chan
[i
] = i
== 3 ? one
: zero
;
1333 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
1336 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
1340 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1341 struct nir_variable
*variable
)
1343 LLVMValueRef t_list_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->vertex_buffers
);
1344 LLVMValueRef t_offset
;
1345 LLVMValueRef t_list
;
1347 LLVMValueRef buffer_index
;
1348 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1349 uint8_t input_usage_mask
=
1350 ctx
->args
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
1351 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
1353 variable
->data
.driver_location
= variable
->data
.location
* 4;
1355 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
1356 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
1357 LLVMValueRef output
[4];
1358 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
1359 unsigned attrib_format
= ctx
->args
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
1360 unsigned data_format
= attrib_format
& 0x0f;
1361 unsigned num_format
= (attrib_format
>> 4) & 0x07;
1362 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
1363 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
1365 if (ctx
->args
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
1366 uint32_t divisor
= ctx
->args
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
1369 buffer_index
= ctx
->abi
.instance_id
;
1372 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
1373 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
1376 buffer_index
= ctx
->ac
.i32_0
;
1379 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1380 ac_get_arg(&ctx
->ac
,
1381 ctx
->args
->ac
.start_instance
),\
1384 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1386 ac_get_arg(&ctx
->ac
,
1387 ctx
->args
->ac
.base_vertex
), "");
1390 assert(data_format
< ARRAY_SIZE(vertex_format_table
));
1391 const struct vertex_format_info
*vtx_info
= &vertex_format_table
[data_format
];
1393 /* Adjust the number of channels to load based on the vertex
1396 unsigned num_channels
= MIN2(num_input_channels
, vtx_info
->num_channels
);
1397 unsigned attrib_binding
= ctx
->args
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
1398 unsigned attrib_offset
= ctx
->args
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
1399 unsigned attrib_stride
= ctx
->args
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
1401 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1402 /* Always load, at least, 3 channels for formats that
1403 * need to be shuffled because X<->Z.
1405 num_channels
= MAX2(num_channels
, 3);
1408 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
1409 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
1411 /* Perform per-channel vertex fetch operations if unaligned
1412 * access are detected. Only GFX6 and GFX10 are affected.
1414 bool unaligned_vertex_fetches
= false;
1415 if ((ctx
->ac
.chip_class
== GFX6
|| ctx
->ac
.chip_class
== GFX10
) &&
1416 vtx_info
->chan_format
!= data_format
&&
1417 ((attrib_offset
% vtx_info
->vertex_byte_size
) ||
1418 (attrib_stride
% vtx_info
->vertex_byte_size
)))
1419 unaligned_vertex_fetches
= true;
1421 if (unaligned_vertex_fetches
) {
1422 unsigned chan_format
= vtx_info
->chan_format
;
1423 LLVMValueRef values
[4];
1425 assert(ctx
->ac
.chip_class
== GFX6
||
1426 ctx
->ac
.chip_class
== GFX10
);
1428 for (unsigned chan
= 0; chan
< num_channels
; chan
++) {
1429 unsigned chan_offset
= attrib_offset
+ chan
* vtx_info
->chan_byte_size
;
1430 LLVMValueRef chan_index
= buffer_index
;
1432 if (attrib_stride
!= 0 && chan_offset
> attrib_stride
) {
1433 LLVMValueRef buffer_offset
=
1434 LLVMConstInt(ctx
->ac
.i32
,
1435 chan_offset
/ attrib_stride
, false);
1437 chan_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1441 chan_offset
= chan_offset
% attrib_stride
;
1444 values
[chan
] = ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1446 LLVMConstInt(ctx
->ac
.i32
, chan_offset
, false),
1447 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
, 1,
1448 chan_format
, num_format
, 0, true);
1451 input
= ac_build_gather_values(&ctx
->ac
, values
, num_channels
);
1453 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
1454 LLVMValueRef buffer_offset
=
1455 LLVMConstInt(ctx
->ac
.i32
,
1456 attrib_offset
/ attrib_stride
, false);
1458 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1462 attrib_offset
= attrib_offset
% attrib_stride
;
1465 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1467 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
1468 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
1470 data_format
, num_format
, 0, true);
1473 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1475 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
1476 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
1477 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
1478 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
1480 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
1483 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
1486 for (unsigned chan
= 0; chan
< 4; chan
++) {
1487 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1488 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
1489 if (type
== GLSL_TYPE_FLOAT16
) {
1490 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
1491 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
1495 unsigned alpha_adjust
= (ctx
->args
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
1496 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
1498 for (unsigned chan
= 0; chan
< 4; chan
++) {
1499 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
1500 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
1501 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
1503 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
1509 handle_vs_inputs(struct radv_shader_context
*ctx
,
1510 struct nir_shader
*nir
) {
1511 nir_foreach_variable(variable
, &nir
->inputs
)
1512 handle_vs_input_decl(ctx
, variable
);
1516 prepare_interp_optimize(struct radv_shader_context
*ctx
,
1517 struct nir_shader
*nir
)
1519 bool uses_center
= false;
1520 bool uses_centroid
= false;
1521 nir_foreach_variable(variable
, &nir
->inputs
) {
1522 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
1523 variable
->data
.sample
)
1526 if (variable
->data
.centroid
)
1527 uses_centroid
= true;
1532 ctx
->abi
.persp_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_centroid
);
1533 ctx
->abi
.linear_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_centroid
);
1535 if (uses_center
&& uses_centroid
) {
1536 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
,
1537 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.prim_mask
),
1539 ctx
->abi
.persp_centroid
=
1540 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1541 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_center
),
1542 ctx
->abi
.persp_centroid
, "");
1543 ctx
->abi
.linear_centroid
=
1544 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1545 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_center
),
1546 ctx
->abi
.linear_centroid
, "");
1551 scan_shader_output_decl(struct radv_shader_context
*ctx
,
1552 struct nir_variable
*variable
,
1553 struct nir_shader
*shader
,
1554 gl_shader_stage stage
)
1556 int idx
= variable
->data
.location
+ variable
->data
.index
;
1557 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1558 uint64_t mask_attribs
;
1560 variable
->data
.driver_location
= idx
* 4;
1562 /* tess ctrl has it's own load/store paths for outputs */
1563 if (stage
== MESA_SHADER_TESS_CTRL
)
1566 if (variable
->data
.compact
) {
1567 unsigned component_count
= variable
->data
.location_frac
+
1568 glsl_get_length(variable
->type
);
1569 attrib_count
= (component_count
+ 3) / 4;
1572 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
1574 ctx
->output_mask
|= mask_attribs
;
1578 /* Initialize arguments for the shader export intrinsic */
1580 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
1581 LLVMValueRef
*values
,
1582 unsigned enabled_channels
,
1584 struct ac_export_args
*args
)
1586 /* Specify the channels that are enabled. */
1587 args
->enabled_channels
= enabled_channels
;
1589 /* Specify whether the EXEC mask represents the valid mask */
1590 args
->valid_mask
= 0;
1592 /* Specify whether this is the last export */
1595 /* Specify the target we are exporting */
1596 args
->target
= target
;
1598 args
->compr
= false;
1599 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
1600 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
1601 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
1602 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
1607 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
1608 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1609 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
1610 unsigned col_format
= (ctx
->args
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
1611 bool is_int8
= (ctx
->args
->options
->key
.fs
.is_int8
>> index
) & 1;
1612 bool is_int10
= (ctx
->args
->options
->key
.fs
.is_int10
>> index
) & 1;
1615 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
1616 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
1617 unsigned bits
, bool hi
) = NULL
;
1619 switch(col_format
) {
1620 case V_028714_SPI_SHADER_ZERO
:
1621 args
->enabled_channels
= 0; /* writemask */
1622 args
->target
= V_008DFC_SQ_EXP_NULL
;
1625 case V_028714_SPI_SHADER_32_R
:
1626 args
->enabled_channels
= 1;
1627 args
->out
[0] = values
[0];
1630 case V_028714_SPI_SHADER_32_GR
:
1631 args
->enabled_channels
= 0x3;
1632 args
->out
[0] = values
[0];
1633 args
->out
[1] = values
[1];
1636 case V_028714_SPI_SHADER_32_AR
:
1637 if (ctx
->ac
.chip_class
>= GFX10
) {
1638 args
->enabled_channels
= 0x3;
1639 args
->out
[0] = values
[0];
1640 args
->out
[1] = values
[3];
1642 args
->enabled_channels
= 0x9;
1643 args
->out
[0] = values
[0];
1644 args
->out
[3] = values
[3];
1648 case V_028714_SPI_SHADER_FP16_ABGR
:
1649 args
->enabled_channels
= 0x5;
1650 packf
= ac_build_cvt_pkrtz_f16
;
1652 for (unsigned chan
= 0; chan
< 4; chan
++)
1653 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
1659 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1660 args
->enabled_channels
= 0x5;
1661 packf
= ac_build_cvt_pknorm_u16
;
1664 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1665 args
->enabled_channels
= 0x5;
1666 packf
= ac_build_cvt_pknorm_i16
;
1669 case V_028714_SPI_SHADER_UINT16_ABGR
:
1670 args
->enabled_channels
= 0x5;
1671 packi
= ac_build_cvt_pk_u16
;
1673 for (unsigned chan
= 0; chan
< 4; chan
++)
1674 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
1675 ac_to_integer(&ctx
->ac
, values
[chan
]),
1680 case V_028714_SPI_SHADER_SINT16_ABGR
:
1681 args
->enabled_channels
= 0x5;
1682 packi
= ac_build_cvt_pk_i16
;
1684 for (unsigned chan
= 0; chan
< 4; chan
++)
1685 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
1686 ac_to_integer(&ctx
->ac
, values
[chan
]),
1692 case V_028714_SPI_SHADER_32_ABGR
:
1693 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1697 /* Pack f16 or norm_i16/u16. */
1699 for (chan
= 0; chan
< 2; chan
++) {
1700 LLVMValueRef pack_args
[2] = {
1702 values
[2 * chan
+ 1]
1704 LLVMValueRef packed
;
1706 packed
= packf(&ctx
->ac
, pack_args
);
1707 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1709 args
->compr
= 1; /* COMPR flag */
1714 for (chan
= 0; chan
< 2; chan
++) {
1715 LLVMValueRef pack_args
[2] = {
1716 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
1717 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
1719 LLVMValueRef packed
;
1721 packed
= packi(&ctx
->ac
, pack_args
,
1722 is_int8
? 8 : is_int10
? 10 : 16,
1724 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1726 args
->compr
= 1; /* COMPR flag */
1732 for (unsigned chan
= 0; chan
< 4; chan
++) {
1733 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
1734 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
1737 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1739 for (unsigned i
= 0; i
< 4; ++i
)
1740 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
1744 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
1745 LLVMValueRef
*values
, unsigned enabled_channels
)
1747 struct ac_export_args args
;
1749 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
1750 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
1751 ac_build_export(&ctx
->ac
, &args
);
1755 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
1757 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
1758 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
1762 radv_emit_stream_output(struct radv_shader_context
*ctx
,
1763 LLVMValueRef
const *so_buffers
,
1764 LLVMValueRef
const *so_write_offsets
,
1765 const struct radv_stream_output
*output
,
1766 struct radv_shader_output_values
*shader_out
)
1768 unsigned num_comps
= util_bitcount(output
->component_mask
);
1769 unsigned buf
= output
->buffer
;
1770 unsigned offset
= output
->offset
;
1772 LLVMValueRef out
[4];
1774 assert(num_comps
&& num_comps
<= 4);
1775 if (!num_comps
|| num_comps
> 4)
1778 /* Get the first component. */
1779 start
= ffs(output
->component_mask
) - 1;
1781 /* Load the output as int. */
1782 for (int i
= 0; i
< num_comps
; i
++) {
1783 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
1786 /* Pack the output. */
1787 LLVMValueRef vdata
= NULL
;
1789 switch (num_comps
) {
1790 case 1: /* as i32 */
1793 case 2: /* as v2i32 */
1794 case 3: /* as v4i32 (aligned to 4) */
1795 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
1797 case 4: /* as v4i32 */
1798 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
1799 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
1800 util_next_power_of_two(num_comps
) :
1805 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
1806 vdata
, num_comps
, so_write_offsets
[buf
],
1807 ctx
->ac
.i32_0
, offset
,
1812 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
1816 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1817 assert(ctx
->args
->streamout_config
.used
);
1818 LLVMValueRef so_vtx_count
=
1819 ac_build_bfe(&ctx
->ac
,
1820 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_config
),
1821 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1822 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
1824 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
1826 /* can_emit = tid < so_vtx_count; */
1827 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
1828 tid
, so_vtx_count
, "");
1830 /* Emit the streamout code conditionally. This actually avoids
1831 * out-of-bounds buffer access. The hw tells us via the SGPR
1832 * (so_vtx_count) which threads are allowed to emit streamout data.
1834 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
1836 /* The buffer offset is computed as follows:
1837 * ByteOffset = streamout_offset[buffer_id]*4 +
1838 * (streamout_write_index + thread_id)*stride[buffer_id] +
1841 LLVMValueRef so_write_index
=
1842 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_write_idx
);
1844 /* Compute (streamout_write_index + thread_id). */
1846 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
1848 /* Load the descriptor and compute the write offset for each
1851 LLVMValueRef so_write_offset
[4] = {};
1852 LLVMValueRef so_buffers
[4] = {};
1853 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
1855 for (i
= 0; i
< 4; i
++) {
1856 uint16_t stride
= ctx
->args
->shader_info
->so
.strides
[i
];
1861 LLVMValueRef offset
=
1862 LLVMConstInt(ctx
->ac
.i32
, i
, false);
1864 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
1867 LLVMValueRef so_offset
=
1868 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_offset
[i
]);
1870 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
1871 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1873 so_write_offset
[i
] =
1874 ac_build_imad(&ctx
->ac
, so_write_index
,
1875 LLVMConstInt(ctx
->ac
.i32
,
1880 /* Write streamout data. */
1881 for (i
= 0; i
< ctx
->args
->shader_info
->so
.num_outputs
; i
++) {
1882 struct radv_shader_output_values shader_out
= {};
1883 struct radv_stream_output
*output
=
1884 &ctx
->args
->shader_info
->so
.outputs
[i
];
1886 if (stream
!= output
->stream
)
1889 for (int j
= 0; j
< 4; j
++) {
1890 shader_out
.values
[j
] =
1891 radv_load_output(ctx
, output
->location
, j
);
1894 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
1895 output
, &shader_out
);
1898 ac_build_endif(&ctx
->ac
, 6501);
1902 radv_build_param_exports(struct radv_shader_context
*ctx
,
1903 struct radv_shader_output_values
*outputs
,
1905 struct radv_vs_output_info
*outinfo
,
1906 bool export_clip_dists
)
1908 unsigned param_count
= 0;
1910 for (unsigned i
= 0; i
< noutput
; i
++) {
1911 unsigned slot_name
= outputs
[i
].slot_name
;
1912 unsigned usage_mask
= outputs
[i
].usage_mask
;
1914 if (slot_name
!= VARYING_SLOT_LAYER
&&
1915 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
1916 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
1917 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
1918 slot_name
< VARYING_SLOT_VAR0
)
1921 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
1922 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
1925 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
1927 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
1928 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
1931 outinfo
->param_exports
= param_count
;
1934 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1935 * (position and parameter data only).
1938 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
1939 struct radv_shader_output_values
*outputs
,
1941 struct radv_vs_output_info
*outinfo
,
1942 bool export_clip_dists
)
1944 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
1945 struct ac_export_args pos_args
[4] = {};
1946 unsigned pos_idx
, index
;
1949 /* Build position exports */
1950 for (i
= 0; i
< noutput
; i
++) {
1951 switch (outputs
[i
].slot_name
) {
1952 case VARYING_SLOT_POS
:
1953 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1954 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
1956 case VARYING_SLOT_PSIZ
:
1957 psize_value
= outputs
[i
].values
[0];
1959 case VARYING_SLOT_LAYER
:
1960 layer_value
= outputs
[i
].values
[0];
1962 case VARYING_SLOT_VIEWPORT
:
1963 viewport_value
= outputs
[i
].values
[0];
1965 case VARYING_SLOT_CLIP_DIST0
:
1966 case VARYING_SLOT_CLIP_DIST1
:
1967 index
= 2 + outputs
[i
].slot_index
;
1968 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1969 V_008DFC_SQ_EXP_POS
+ index
,
1977 /* We need to add the position output manually if it's missing. */
1978 if (!pos_args
[0].out
[0]) {
1979 pos_args
[0].enabled_channels
= 0xf; /* writemask */
1980 pos_args
[0].valid_mask
= 0; /* EXEC mask */
1981 pos_args
[0].done
= 0; /* last export? */
1982 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
1983 pos_args
[0].compr
= 0; /* COMPR flag */
1984 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
1985 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
1986 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
1987 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
1990 if (outinfo
->writes_pointsize
||
1991 outinfo
->writes_layer
||
1992 outinfo
->writes_viewport_index
) {
1993 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
1994 (outinfo
->writes_layer
== true ? 4 : 0));
1995 pos_args
[1].valid_mask
= 0;
1996 pos_args
[1].done
= 0;
1997 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
1998 pos_args
[1].compr
= 0;
1999 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2000 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2001 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2002 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2004 if (outinfo
->writes_pointsize
== true)
2005 pos_args
[1].out
[0] = psize_value
;
2006 if (outinfo
->writes_layer
== true)
2007 pos_args
[1].out
[2] = layer_value
;
2008 if (outinfo
->writes_viewport_index
== true) {
2009 if (ctx
->args
->options
->chip_class
>= GFX9
) {
2010 /* GFX9 has the layer in out.z[10:0] and the viewport
2011 * index in out.z[19:16].
2013 LLVMValueRef v
= viewport_value
;
2014 v
= ac_to_integer(&ctx
->ac
, v
);
2015 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2016 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2018 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2019 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2021 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2022 pos_args
[1].enabled_channels
|= 1 << 2;
2024 pos_args
[1].out
[3] = viewport_value
;
2025 pos_args
[1].enabled_channels
|= 1 << 3;
2030 for (i
= 0; i
< 4; i
++) {
2031 if (pos_args
[i
].out
[0])
2032 outinfo
->pos_exports
++;
2035 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2036 * Setting valid_mask=1 prevents it and has no other effect.
2038 if (ctx
->ac
.family
== CHIP_NAVI10
||
2039 ctx
->ac
.family
== CHIP_NAVI12
||
2040 ctx
->ac
.family
== CHIP_NAVI14
)
2041 pos_args
[0].valid_mask
= 1;
2044 for (i
= 0; i
< 4; i
++) {
2045 if (!pos_args
[i
].out
[0])
2048 /* Specify the target we are exporting */
2049 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2051 if (pos_idx
== outinfo
->pos_exports
)
2052 /* Specify that this is the last export */
2053 pos_args
[i
].done
= 1;
2055 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2058 /* Build parameter exports */
2059 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2063 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2064 bool export_prim_id
,
2065 bool export_clip_dists
,
2066 struct radv_vs_output_info
*outinfo
)
2068 struct radv_shader_output_values
*outputs
;
2069 unsigned noutput
= 0;
2071 if (ctx
->args
->options
->key
.has_multiview_view_index
) {
2072 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2074 for(unsigned i
= 0; i
< 4; ++i
)
2075 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2076 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2079 LLVMValueRef view_index
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
);
2080 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, view_index
), *tmp_out
);
2081 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2084 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2085 sizeof(outinfo
->vs_output_param_offset
));
2086 outinfo
->pos_exports
= 0;
2088 if (!ctx
->args
->options
->use_ngg_streamout
&&
2089 ctx
->args
->shader_info
->so
.num_outputs
&&
2090 !ctx
->args
->is_gs_copy_shader
) {
2091 /* The GS copy shader emission already emits streamout. */
2092 radv_emit_streamout(ctx
, 0);
2095 /* Allocate a temporary array for the output values. */
2096 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2097 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2099 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2100 if (!(ctx
->output_mask
& (1ull << i
)))
2103 outputs
[noutput
].slot_name
= i
;
2104 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2106 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2107 !ctx
->args
->is_gs_copy_shader
) {
2108 outputs
[noutput
].usage_mask
=
2109 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2110 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2111 outputs
[noutput
].usage_mask
=
2112 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2114 assert(ctx
->args
->is_gs_copy_shader
);
2115 outputs
[noutput
].usage_mask
=
2116 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2119 for (unsigned j
= 0; j
< 4; j
++) {
2120 outputs
[noutput
].values
[j
] =
2121 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2127 /* Export PrimitiveID. */
2128 if (export_prim_id
) {
2129 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2130 outputs
[noutput
].slot_index
= 0;
2131 outputs
[noutput
].usage_mask
= 0x1;
2132 outputs
[noutput
].values
[0] =
2133 ac_get_arg(&ctx
->ac
, ctx
->args
->vs_prim_id
);
2134 for (unsigned j
= 1; j
< 4; j
++)
2135 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2139 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2145 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2146 struct radv_es_output_info
*outinfo
)
2149 LLVMValueRef lds_base
= NULL
;
2151 if (ctx
->ac
.chip_class
>= GFX9
) {
2152 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2153 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2154 LLVMValueRef wave_idx
=
2155 ac_unpack_param(&ctx
->ac
,
2156 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2157 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2158 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2159 LLVMConstInt(ctx
->ac
.i32
,
2160 ctx
->ac
.wave_size
, false), ""), "");
2161 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2162 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2165 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2166 LLVMValueRef dw_addr
= NULL
;
2167 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2168 unsigned output_usage_mask
;
2171 if (!(ctx
->output_mask
& (1ull << i
)))
2174 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2176 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2178 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2180 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2183 param_index
= shader_io_get_unique_index(i
);
2186 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2187 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2191 for (j
= 0; j
< 4; j
++) {
2192 if (!(output_usage_mask
& (1 << j
)))
2195 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2196 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2197 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2199 if (ctx
->ac
.chip_class
>= GFX9
) {
2200 LLVMValueRef dw_addr_offset
=
2201 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2202 LLVMConstInt(ctx
->ac
.i32
,
2205 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2207 ac_build_buffer_store_dword(&ctx
->ac
,
2211 ac_get_arg(&ctx
->ac
, ctx
->args
->es2gs_offset
),
2212 (4 * param_index
+ j
) * 4,
2213 ac_glc
| ac_slc
| ac_swizzled
);
2220 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2222 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2223 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
2224 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2225 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2226 vertex_dw_stride
, "");
2228 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2229 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2231 if (!(ctx
->output_mask
& (1ull << i
)))
2234 int param
= shader_io_get_unique_index(i
);
2235 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2236 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2238 for (unsigned j
= 0; j
< 4; j
++) {
2239 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2240 value
= ac_to_integer(&ctx
->ac
, value
);
2241 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2242 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2243 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2248 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2250 return ac_unpack_param(&ctx
->ac
,
2251 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2254 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2256 return ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 28, 4);
2259 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2261 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2263 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2264 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2265 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2268 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2270 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2271 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2272 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2276 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2278 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2279 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2280 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2284 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
2286 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2288 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2293 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2295 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2297 if (ctx
->args
->options
->key
.has_multiview_view_index
)
2300 LLVMTypeRef elements
[2] = {
2301 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
2302 LLVMArrayType(ctx
->ac
.i8
, 4),
2304 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
2305 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
2306 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
2310 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2311 * is in emit order; that is:
2312 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2313 * - during vertex emit, i.e. while the API GS shader invocation is running,
2314 * N = threadidx * gs_max_out_vertices + emitidx
2316 * Goals of the LDS memory layout:
2317 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2318 * in uniform control flow
2319 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2321 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2322 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2323 * 5. Avoid wasting memory.
2325 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2326 * layout, elimination of bank conflicts requires that each vertex occupy an
2327 * odd number of dwords. We use the additional dword to store the output stream
2328 * index as well as a flag to indicate whether this vertex ends a primitive
2329 * for rasterization.
2331 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2333 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2334 * Indices are swizzled in groups of 32, which ensures point 1 without
2335 * disturbing point 2.
2337 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2340 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
2342 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2343 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
2345 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2346 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
2347 if (write_stride_2exp
) {
2349 LLVMBuildLShr(builder
, vertexidx
,
2350 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
2351 LLVMValueRef swizzle
=
2352 LLVMBuildAnd(builder
, row
,
2353 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
2355 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
2358 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
2362 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
2363 LLVMValueRef emitidx
)
2365 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2368 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
2369 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
2370 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
2371 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
2375 unsigned num_vertices
;
2376 LLVMValueRef isnull
;
2377 LLVMValueRef index
[3];
2378 LLVMValueRef edgeflag
[3];
2381 static void build_export_prim(struct radv_shader_context
*ctx
,
2382 const struct ngg_prim
*prim
)
2384 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2385 struct ac_export_args args
;
2388 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
2389 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
2391 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
2392 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
2393 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
2394 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2395 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
2396 tmp
= LLVMBuildShl(builder
, tmp
,
2397 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
2398 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2401 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
2402 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2403 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2404 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2406 args
.target
= V_008DFC_SQ_EXP_PRIM
;
2407 args
.enabled_channels
= 1;
2409 args
.valid_mask
= false;
2412 ac_build_export(&ctx
->ac
, &args
);
2415 static struct radv_stream_output
*
2416 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
2418 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2419 if (so
->outputs
[i
].location
== location
)
2420 return &so
->outputs
[i
];
2426 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
2427 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
2428 unsigned stream
, LLVMValueRef offset_vtx
,
2429 LLVMValueRef vertexptr
)
2431 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2432 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2433 LLVMValueRef offset
[4] = {};
2436 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2437 if (!wg_offset_dw
[buffer
])
2440 tmp
= LLVMBuildMul(builder
, offset_vtx
,
2441 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
2442 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
2443 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2446 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2447 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
2448 unsigned noutput
= 0;
2449 unsigned out_idx
= 0;
2451 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2452 unsigned output_usage_mask
=
2453 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2454 uint8_t output_stream
=
2455 output_stream
= ctx
->args
->shader_info
->gs
.output_streams
[i
];
2457 if (!(ctx
->output_mask
& (1ull << i
)) ||
2458 output_stream
!= stream
)
2461 outputs
[noutput
].slot_name
= i
;
2462 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2463 outputs
[noutput
].usage_mask
= output_usage_mask
;
2465 int length
= util_last_bit(output_usage_mask
);
2467 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
2468 if (!(output_usage_mask
& (1 << j
)))
2471 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2472 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
2473 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
2476 for (unsigned j
= length
; j
< 4; j
++)
2477 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
2482 for (unsigned i
= 0; i
< noutput
; i
++) {
2483 struct radv_stream_output
*output
=
2484 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
2487 output
->stream
!= stream
)
2490 struct radv_shader_output_values out
= {};
2492 for (unsigned j
= 0; j
< 4; j
++) {
2493 out
.values
[j
] = outputs
[i
].values
[j
];
2496 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2499 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2500 struct radv_stream_output
*output
=
2501 &ctx
->args
->shader_info
->so
.outputs
[i
];
2503 if (stream
!= output
->stream
)
2506 struct radv_shader_output_values out
= {};
2508 for (unsigned comp
= 0; comp
< 4; comp
++) {
2509 if (!(output
->component_mask
& (1 << comp
)))
2512 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2513 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2514 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
2517 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2522 struct ngg_streamout
{
2523 LLVMValueRef num_vertices
;
2525 /* per-thread data */
2526 LLVMValueRef prim_enable
[4]; /* i1 per stream */
2527 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
2530 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
2534 * Build streamout logic.
2536 * Implies a barrier.
2538 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2540 * Clobbers gs_ngg_scratch[8:].
2542 static void build_streamout(struct radv_shader_context
*ctx
,
2543 struct ngg_streamout
*nggso
)
2545 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2546 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2547 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
2548 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2549 LLVMValueRef cond
, tmp
, tmp2
;
2550 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
2551 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
2552 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
2553 LLVMValueRef so_buffer
[4] = {};
2554 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
2555 (nggso
->vertices
[2] ? 1 : 0);
2556 LLVMValueRef prim_stride_dw
[4] = {};
2557 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
2558 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
2559 unsigned bufmask_for_stream
[4] = {};
2560 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
2561 unsigned scratch_emit_base
= isgs
? 4 : 0;
2562 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
2563 unsigned scratch_offset_base
= isgs
? 8 : 4;
2564 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
2566 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
2567 "amdgpu-gds-size", 256);
2569 /* Determine the mapping of streamout buffers to vertex streams. */
2570 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2571 unsigned buf
= so
->outputs
[i
].buffer
;
2572 unsigned stream
= so
->outputs
[i
].stream
;
2573 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
2574 stream_for_buffer
[buf
] = stream
;
2575 bufmask_for_stream
[stream
] |= 1 << buf
;
2578 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2579 if (stream_for_buffer
[buffer
] == -1)
2582 assert(so
->strides
[buffer
]);
2584 LLVMValueRef stride_for_buffer
=
2585 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
2586 prim_stride_dw
[buffer
] =
2587 LLVMBuildMul(builder
, stride_for_buffer
,
2588 nggso
->num_vertices
, "");
2589 prim_stride_dw_vgpr
= ac_build_writelane(
2590 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
2591 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2593 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
2594 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
2598 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2599 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
2601 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
2602 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
2604 /* Advance the streamout offsets in GDS. */
2605 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2606 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2608 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2609 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
2611 /* Fetch the number of generated primitives and store
2612 * it in GDS for later use.
2615 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
2616 tmp
= LLVMBuildLoad(builder
, tmp
, "");
2618 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
2619 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
2621 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
2623 unsigned swizzle
[4];
2624 int unused_stream
= -1;
2625 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2626 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2627 unused_stream
= stream
;
2631 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2632 if (stream_for_buffer
[buffer
] >= 0) {
2633 swizzle
[buffer
] = stream_for_buffer
[buffer
];
2635 assert(unused_stream
>= 0);
2636 swizzle
[buffer
] = unused_stream
;
2640 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
2641 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2642 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2644 LLVMValueRef args
[] = {
2645 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
2647 ctx
->ac
.i32_0
, // ordering
2648 ctx
->ac
.i32_0
, // scope
2649 ctx
->ac
.i1false
, // isVolatile
2650 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
2651 ctx
->ac
.i1true
, // wave release
2652 ctx
->ac
.i1true
, // wave done
2655 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
2656 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
2658 /* Keep offsets in a VGPR for quick retrieval via readlane by
2659 * the first wave for bounds checking, and also store in LDS
2660 * for retrieval by all waves later. */
2661 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
2663 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2664 scratch_offset_basev
, "");
2665 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
2666 LLVMBuildStore(builder
, tmp
, tmp2
);
2668 ac_build_endif(&ctx
->ac
, 5210);
2670 /* Determine the max emit per buffer. This is done via the SALU, in part
2671 * because LLVM can't generate divide-by-multiply if we try to do this
2672 * via VALU with one lane per buffer.
2674 LLVMValueRef max_emit
[4] = {};
2675 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2676 if (stream_for_buffer
[buffer
] == -1)
2679 /* Compute the streamout buffer size in DWORD. */
2680 LLVMValueRef bufsize_dw
=
2681 LLVMBuildLShr(builder
,
2682 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
2685 /* Load the streamout buffer offset from GDS. */
2686 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
2687 LLVMValueRef offset_dw
=
2688 ac_build_readlane(&ctx
->ac
, tmp
,
2689 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2691 /* Compute the remaining size to emit. */
2692 LLVMValueRef remaining_dw
=
2693 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
2694 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
2695 prim_stride_dw
[buffer
], "");
2697 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2698 bufsize_dw
, offset_dw
, "");
2699 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
2700 ctx
->ac
.i32_0
, tmp
, "");
2703 /* Determine the number of emitted primitives per stream and fixup the
2704 * GDS counter if necessary.
2706 * This is complicated by the fact that a single stream can emit to
2707 * multiple buffers (but luckily not vice versa).
2709 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
2711 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2712 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2715 /* Load the number of generated primitives from GDS and
2716 * determine that number for the given stream.
2718 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
2719 LLVMValueRef generated
=
2720 ac_build_readlane(&ctx
->ac
, tmp
,
2721 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2724 /* Compute the number of emitted primitives. */
2725 LLVMValueRef emit
= generated
;
2726 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2727 if (stream_for_buffer
[buffer
] == stream
)
2728 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
2731 /* Store the number of emitted primitives for that
2734 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
2735 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2737 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2738 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
2739 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
2740 tmp
= LLVMBuildLShr(builder
,
2741 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
2742 ac_get_thread_id(&ctx
->ac
), "");
2743 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2744 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
2746 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
2747 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2748 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
2749 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
2750 LLVMAtomicOrderingMonotonic
, false);
2752 ac_build_endif(&ctx
->ac
, 5222);
2753 ac_build_endif(&ctx
->ac
, 5221);
2756 /* Store the number of emitted primitives to LDS for later use. */
2757 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2758 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
2760 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2761 scratch_emit_basev
, "");
2762 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
2763 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
2765 ac_build_endif(&ctx
->ac
, 5225);
2767 ac_build_endif(&ctx
->ac
, 5200);
2769 /* Determine the workgroup-relative per-thread / primitive offset into
2770 * the streamout buffers */
2771 struct ac_wg_scan primemit_scan
[4] = {};
2774 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2775 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2778 primemit_scan
[stream
].enable_exclusive
= true;
2779 primemit_scan
[stream
].op
= nir_op_iadd
;
2780 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
2781 primemit_scan
[stream
].scratch
=
2782 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
2783 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
2784 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
2785 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
2786 primemit_scan
[stream
].maxwaves
= 8;
2787 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
2791 ac_build_s_barrier(&ctx
->ac
);
2793 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2794 LLVMValueRef wgoffset_dw
[4] = {};
2797 LLVMValueRef scratch_vgpr
;
2799 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
2800 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
2802 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2803 if (stream_for_buffer
[buffer
] >= 0) {
2804 wgoffset_dw
[buffer
] = ac_build_readlane(
2805 &ctx
->ac
, scratch_vgpr
,
2806 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
2810 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2811 if (ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2812 nggso
->emit
[stream
] = ac_build_readlane(
2813 &ctx
->ac
, scratch_vgpr
,
2814 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
2819 /* Write out primitive data */
2820 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2821 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2825 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
2827 primemit_scan
[stream
].result_exclusive
= tid
;
2830 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2831 primemit_scan
[stream
].result_exclusive
,
2832 nggso
->emit
[stream
], "");
2833 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
2834 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
2836 LLVMValueRef offset_vtx
=
2837 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
2838 nggso
->num_vertices
, "");
2840 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
2841 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2842 LLVMConstInt(ctx
->ac
.i32
, i
, false),
2843 nggso
->num_vertices
, "");
2844 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
2845 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
2846 stream
, offset_vtx
, nggso
->vertices
[i
]);
2847 ac_build_endif(&ctx
->ac
, 5241);
2848 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
2851 ac_build_endif(&ctx
->ac
, 5240);
2855 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
2857 unsigned lds_vertex_size
= 0;
2859 if (ctx
->args
->shader_info
->so
.num_outputs
)
2860 lds_vertex_size
= 4 * ctx
->args
->shader_info
->so
.num_outputs
+ 1;
2862 return lds_vertex_size
;
2866 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2867 * for the vertex outputs.
2869 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
2872 /* The extra dword is used to avoid LDS bank conflicts. */
2873 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
2874 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
2875 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
2876 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
2877 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
2881 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
2883 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2884 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2885 LLVMValueRef vertex_ptr
= NULL
;
2886 LLVMValueRef tmp
, tmp2
;
2888 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2889 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2891 if (!ctx
->args
->shader_info
->so
.num_outputs
)
2894 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
2896 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2897 struct radv_stream_output
*output
=
2898 &ctx
->args
->shader_info
->so
.outputs
[i
];
2900 unsigned loc
= output
->location
;
2902 for (unsigned comp
= 0; comp
< 4; comp
++) {
2903 if (!(output
->component_mask
& (1 << comp
)))
2906 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
2907 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2908 tmp2
= LLVMBuildLoad(builder
,
2909 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
2910 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
2911 LLVMBuildStore(builder
, tmp2
, tmp
);
2917 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
2919 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2922 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2923 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2925 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
,
2926 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
2927 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
,
2928 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 0, 8);
2929 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2930 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
2931 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2932 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
2933 LLVMValueRef vtxindex
[] = {
2934 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 0, 16),
2935 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 16, 16),
2936 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[2]), 0, 16),
2939 /* Determine the number of vertices per primitive. */
2940 unsigned num_vertices
;
2941 LLVMValueRef num_vertices_val
;
2943 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2944 LLVMValueRef outprim_val
=
2945 LLVMConstInt(ctx
->ac
.i32
,
2946 ctx
->args
->options
->key
.vs
.outprim
, false);
2947 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
2949 num_vertices
= 3; /* TODO: optimize for points & lines */
2951 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2953 if (ctx
->shader
->info
.tess
.point_mode
)
2955 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
2960 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
2964 if (ctx
->args
->shader_info
->so
.num_outputs
) {
2965 struct ngg_streamout nggso
= {};
2967 nggso
.num_vertices
= num_vertices_val
;
2968 nggso
.prim_enable
[0] = is_gs_thread
;
2970 for (unsigned i
= 0; i
< num_vertices
; ++i
)
2971 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
2973 build_streamout(ctx
, &nggso
);
2976 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2977 * to the ES thread of the provoking vertex.
2979 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2980 ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
2981 if (ctx
->args
->shader_info
->so
.num_outputs
)
2982 ac_build_s_barrier(&ctx
->ac
);
2984 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
2985 /* Extract the PROVOKING_VTX_INDEX field. */
2986 LLVMValueRef provoking_vtx_in_prim
=
2987 LLVMConstInt(ctx
->ac
.i32
, 0, false);
2989 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2990 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
2991 LLVMValueRef provoking_vtx_index
=
2992 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
2994 LLVMBuildStore(builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_prim_id
),
2995 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
2996 ac_build_endif(&ctx
->ac
, 5400);
2999 /* TODO: primitive culling */
3001 ac_build_sendmsg_gs_alloc_req(&ctx
->ac
, get_wave_id_in_tg(ctx
),
3002 ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3004 /* TODO: streamout queries */
3005 /* Export primitive data to the index buffer. Format is:
3006 * - bits 0..8: index 0
3007 * - bit 9: edge flag 0
3008 * - bits 10..18: index 1
3009 * - bit 19: edge flag 1
3010 * - bits 20..28: index 2
3011 * - bit 29: edge flag 2
3012 * - bit 31: null primitive (skip)
3014 * For the first version, we will always build up all three indices
3015 * independent of the primitive type. The additional garbage data
3018 * TODO: culling depends on the primitive type, so can have some
3021 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
3023 struct ngg_prim prim
= {};
3025 prim
.num_vertices
= num_vertices
;
3026 prim
.isnull
= ctx
->ac
.i1false
;
3027 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3029 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3030 tmp
= LLVMBuildLShr(builder
,
3031 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_invocation_id
),
3032 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3033 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3036 build_export_prim(ctx
, &prim
);
3038 ac_build_endif(&ctx
->ac
, 6001);
3040 /* Export per-vertex data (positions and parameters). */
3041 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
3043 struct radv_vs_output_info
*outinfo
=
3044 ctx
->stage
== MESA_SHADER_TESS_EVAL
?
3045 &ctx
->args
->shader_info
->tes
.outinfo
: &ctx
->args
->shader_info
->vs
.outinfo
;
3047 /* Exporting the primitive ID is handled below. */
3048 /* TODO: use the new VS export path */
3049 handle_vs_outputs_post(ctx
, false,
3050 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3053 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
3054 unsigned param_count
= outinfo
->param_exports
;
3055 LLVMValueRef values
[4];
3057 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3058 /* Wait for GS stores to finish. */
3059 ac_build_s_barrier(&ctx
->ac
);
3061 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3062 get_thread_id_in_tg(ctx
));
3063 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3065 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3066 values
[0] = ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tes_patch_id
);
3069 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3070 for (unsigned j
= 1; j
< 4; j
++)
3071 values
[j
] = ctx
->ac
.f32_0
;
3073 radv_export_param(ctx
, param_count
, values
, 0x1);
3075 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3076 outinfo
->param_exports
= param_count
;
3079 ac_build_endif(&ctx
->ac
, 6002);
3082 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3084 /* Zero out the part of LDS scratch that is used to accumulate the
3085 * per-stream generated primitive count.
3087 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3088 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3089 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3090 LLVMBasicBlockRef merge_block
;
3093 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3094 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3095 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3097 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3098 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3099 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3101 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3102 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3104 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3105 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3107 ac_build_s_barrier(&ctx
->ac
);
3110 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3112 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3113 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3116 /* Zero out remaining (non-emitted) primitive flags.
3118 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3119 * the emit threads via LDS. This is likely worse in the expected
3120 * typical case where each GS thread emits the full set of
3123 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3124 unsigned num_components
;
3127 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3128 if (!num_components
)
3131 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3133 ac_build_bgnloop(&ctx
->ac
, 5100);
3135 const LLVMValueRef vertexidx
=
3136 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3137 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3138 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3139 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3140 ac_build_break(&ctx
->ac
);
3141 ac_build_endif(&ctx
->ac
, 5101);
3143 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3144 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3146 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3147 LLVMValueRef gep_idx
[3] = {
3148 ctx
->ac
.i32_0
, /* implied C-style array */
3149 ctx
->ac
.i32_1
, /* second entry of struct */
3150 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3152 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3153 LLVMBuildStore(builder
, i8_0
, tmp
);
3155 ac_build_endloop(&ctx
->ac
, 5100);
3158 /* Accumulate generated primitives counts across the entire threadgroup. */
3159 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3160 unsigned num_components
;
3163 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3164 if (!num_components
)
3167 LLVMValueRef numprims
=
3168 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3169 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3171 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3172 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3174 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3175 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3176 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3177 numprims
, LLVMAtomicOrderingMonotonic
, false);
3179 ac_build_endif(&ctx
->ac
, 5105);
3183 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3185 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3186 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3187 LLVMValueRef tmp
, tmp2
;
3189 ac_build_s_barrier(&ctx
->ac
);
3191 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3192 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3195 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3196 struct ngg_streamout nggso
= {};
3198 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3200 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3201 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3202 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3205 LLVMValueRef gep_idx
[3] = {
3206 ctx
->ac
.i32_0
, /* implicit C-style array */
3207 ctx
->ac
.i32_1
, /* second value of struct */
3208 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3210 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3211 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3212 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3213 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3214 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
3217 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3218 tmp
= LLVMBuildSub(builder
, tid
,
3219 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3220 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
3221 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
3224 build_streamout(ctx
, &nggso
);
3229 /* Determine vertex liveness. */
3230 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3232 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3233 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3235 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3236 const LLVMValueRef primidx
=
3237 LLVMBuildAdd(builder
, tid
,
3238 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3241 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3242 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3245 /* Load primitive liveness */
3246 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3247 LLVMValueRef gep_idx
[3] = {
3248 ctx
->ac
.i32_0
, /* implicit C-style array */
3249 ctx
->ac
.i32_1
, /* second value of struct */
3250 ctx
->ac
.i32_0
, /* stream 0 */
3252 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3253 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3254 const LLVMValueRef primlive
=
3255 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3257 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3258 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3259 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3262 ac_build_endif(&ctx
->ac
, 5121 + i
);
3265 ac_build_endif(&ctx
->ac
, 5120);
3267 /* Inclusive scan addition across the current wave. */
3268 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3269 struct ac_wg_scan vertlive_scan
= {};
3270 vertlive_scan
.op
= nir_op_iadd
;
3271 vertlive_scan
.enable_reduce
= true;
3272 vertlive_scan
.enable_exclusive
= true;
3273 vertlive_scan
.src
= vertlive
;
3274 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3275 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3276 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3277 vertlive_scan
.maxwaves
= 8;
3279 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3281 /* Skip all exports (including index exports) when possible. At least on
3282 * early gfx10 revisions this is also to avoid hangs.
3284 LLVMValueRef have_exports
=
3285 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3287 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3289 /* Allocate export space. Send this message as early as possible, to
3290 * hide the latency of the SQ <-> SPI roundtrip.
3292 * Note: We could consider compacting primitives for export as well.
3293 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3294 * prim data per clock and skips null primitives at no additional
3295 * cost. So compacting primitives can only be beneficial when
3296 * there are 4 or more contiguous null primitives in the export
3297 * (in the common case of single-dword prim exports).
3299 ac_build_sendmsg_gs_alloc_req(&ctx
->ac
, get_wave_id_in_tg(ctx
),
3300 vertlive_scan
.result_reduce
, num_emit_threads
);
3302 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3303 * of the primitive liveness flags, relying on the fact that each
3304 * threadgroup can have at most 256 threads. */
3305 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3307 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3308 LLVMValueRef gep_idx
[3] = {
3309 ctx
->ac
.i32_0
, /* implicit C-style array */
3310 ctx
->ac
.i32_1
, /* second value of struct */
3311 ctx
->ac
.i32_1
, /* stream 1 */
3313 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3314 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3315 LLVMBuildStore(builder
, tmp2
, tmp
);
3317 ac_build_endif(&ctx
->ac
, 5130);
3319 ac_build_s_barrier(&ctx
->ac
);
3321 /* Export primitive data */
3322 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3323 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3326 struct ngg_prim prim
= {};
3327 prim
.num_vertices
= verts_per_prim
;
3329 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3330 LLVMValueRef gep_idx
[3] = {
3331 ctx
->ac
.i32_0
, /* implicit C-style array */
3332 ctx
->ac
.i32_1
, /* second value of struct */
3333 ctx
->ac
.i32_0
, /* primflag */
3335 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3336 flags
= LLVMBuildLoad(builder
, tmp
, "");
3337 prim
.isnull
= LLVMBuildNot(builder
, LLVMBuildTrunc(builder
, flags
, ctx
->ac
.i1
, ""), "");
3339 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3340 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3341 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3342 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3345 /* Geometry shaders output triangle strips, but NGG expects
3346 * triangles. We need to change the vertex order for odd
3347 * triangles to get correct front/back facing by swapping 2
3348 * vertex indices, but we also have to keep the provoking
3349 * vertex in the same place.
3351 if (verts_per_prim
== 3) {
3352 LLVMValueRef is_odd
= LLVMBuildLShr(builder
, flags
, ctx
->ac
.i8_1
, "");
3353 is_odd
= LLVMBuildTrunc(builder
, is_odd
, ctx
->ac
.i1
, "");
3355 struct ngg_prim in
= prim
;
3356 prim
.index
[0] = in
.index
[0];
3357 prim
.index
[1] = LLVMBuildSelect(builder
, is_odd
,
3358 in
.index
[2], in
.index
[1], "");
3359 prim
.index
[2] = LLVMBuildSelect(builder
, is_odd
,
3360 in
.index
[1], in
.index
[2], "");
3363 build_export_prim(ctx
, &prim
);
3365 ac_build_endif(&ctx
->ac
, 5140);
3367 /* Export position and parameter data */
3368 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3369 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3371 struct radv_vs_output_info
*outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3372 bool export_view_index
= ctx
->args
->options
->key
.has_multiview_view_index
;
3373 struct radv_shader_output_values
*outputs
;
3374 unsigned noutput
= 0;
3376 /* Allocate a temporary array for the output values. */
3377 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3378 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3380 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3381 sizeof(outinfo
->vs_output_param_offset
));
3382 outinfo
->pos_exports
= 0;
3384 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3385 LLVMValueRef gep_idx
[3] = {
3386 ctx
->ac
.i32_0
, /* implicit C-style array */
3387 ctx
->ac
.i32_1
, /* second value of struct */
3388 ctx
->ac
.i32_1
, /* stream 1: source data index */
3390 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3391 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3392 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3393 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3395 unsigned out_idx
= 0;
3396 gep_idx
[1] = ctx
->ac
.i32_0
;
3397 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3398 unsigned output_usage_mask
=
3399 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3400 int length
= util_last_bit(output_usage_mask
);
3402 if (!(ctx
->output_mask
& (1ull << i
)))
3405 outputs
[noutput
].slot_name
= i
;
3406 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3407 outputs
[noutput
].usage_mask
= output_usage_mask
;
3409 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3410 if (!(output_usage_mask
& (1 << j
)))
3413 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3414 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3415 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3417 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3418 if (ac_get_type_size(type
) == 2) {
3419 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3420 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3423 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3426 for (unsigned j
= length
; j
< 4; j
++)
3427 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3432 /* Export ViewIndex. */
3433 if (export_view_index
) {
3434 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3435 outputs
[noutput
].slot_index
= 0;
3436 outputs
[noutput
].usage_mask
= 0x1;
3437 outputs
[noutput
].values
[0] =
3438 ac_to_float(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
));
3439 for (unsigned j
= 1; j
< 4; j
++)
3440 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3444 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3445 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
);
3448 ac_build_endif(&ctx
->ac
, 5145);
3451 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3453 LLVMValueRef
*addrs
)
3455 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3457 const LLVMValueRef vertexidx
=
3458 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3460 /* If this thread has already emitted the declared maximum number of
3461 * vertices, skip the write: excessive vertex emissions are not
3462 * supposed to have any effect.
3464 const LLVMValueRef can_emit
=
3465 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3466 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3467 ac_build_ifcc(&ctx
->ac
, can_emit
, 9001);
3469 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3470 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3471 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3473 const LLVMValueRef vertexptr
=
3474 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3475 unsigned out_idx
= 0;
3476 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3477 unsigned output_usage_mask
=
3478 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3479 uint8_t output_stream
=
3480 ctx
->args
->shader_info
->gs
.output_streams
[i
];
3481 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3482 int length
= util_last_bit(output_usage_mask
);
3484 if (!(ctx
->output_mask
& (1ull << i
)) ||
3485 output_stream
!= stream
)
3488 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3489 if (!(output_usage_mask
& (1 << j
)))
3492 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3494 LLVMValueRef gep_idx
[3] = {
3495 ctx
->ac
.i32_0
, /* implied C-style array */
3496 ctx
->ac
.i32_0
, /* first entry of struct */
3497 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3499 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3501 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3502 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3504 LLVMBuildStore(builder
, out_val
, ptr
);
3507 assert(out_idx
* 4 <= ctx
->args
->shader_info
->gs
.gsvs_vertex_size
);
3509 /* Determine and store whether this vertex completed a primitive. */
3510 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3512 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
3513 const LLVMValueRef iscompleteprim
=
3514 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3516 /* Since the geometry shader emits triangle strips, we need to
3517 * track which primitive is odd and swap vertex indices to get
3518 * the correct vertex order.
3520 LLVMValueRef is_odd
= ctx
->ac
.i1false
;
3522 si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) == 3) {
3523 tmp
= LLVMBuildAnd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3524 is_odd
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
, ctx
->ac
.i32_1
, "");
3527 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3528 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3530 LLVMValueRef gep_idx
[3] = {
3531 ctx
->ac
.i32_0
, /* implied C-style array */
3532 ctx
->ac
.i32_1
, /* second struct entry */
3533 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3535 const LLVMValueRef primflagptr
=
3536 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3538 /* The per-vertex primitive flag encoding:
3539 * bit 0: whether this vertex finishes a primitive
3540 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3542 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3543 tmp
= LLVMBuildOr(builder
, tmp
,
3544 LLVMBuildShl(builder
,
3545 LLVMBuildZExt(builder
, is_odd
, ctx
->ac
.i8
, ""),
3546 ctx
->ac
.i8_1
, ""), "");
3547 LLVMBuildStore(builder
, tmp
, primflagptr
);
3549 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3550 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3551 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3553 ac_build_endif(&ctx
->ac
, 9001);
3557 write_tess_factors(struct radv_shader_context
*ctx
)
3559 unsigned stride
, outer_comps
, inner_comps
;
3560 LLVMValueRef tcs_rel_ids
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
);
3561 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 8, 5);
3562 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 0, 8);
3563 unsigned tess_inner_index
= 0, tess_outer_index
;
3564 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3565 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3567 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3569 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
3589 ac_build_ifcc(&ctx
->ac
,
3590 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3591 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
3593 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3596 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3597 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3598 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3601 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3602 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3603 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3605 for (i
= 0; i
< 4; i
++) {
3606 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3607 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3611 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3612 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3613 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3615 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3617 for (i
= 0; i
< outer_comps
; i
++) {
3619 ac_lds_load(&ctx
->ac
, lds_outer
);
3620 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3623 for (i
= 0; i
< inner_comps
; i
++) {
3624 inner
[i
] = out
[outer_comps
+i
] =
3625 ac_lds_load(&ctx
->ac
, lds_inner
);
3626 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3631 /* Convert the outputs to vectors for stores. */
3632 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3636 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3639 buffer
= ctx
->hs_ring_tess_factor
;
3640 tf_base
= ac_get_arg(&ctx
->ac
, ctx
->args
->tess_factor_offset
);
3641 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3642 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3643 unsigned tf_offset
= 0;
3645 if (ctx
->ac
.chip_class
<= GFX8
) {
3646 ac_build_ifcc(&ctx
->ac
,
3647 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3648 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
3650 /* Store the dynamic HS control word. */
3651 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3652 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3653 1, ctx
->ac
.i32_0
, tf_base
,
3657 ac_build_endif(&ctx
->ac
, 6504);
3660 /* Store the tessellation factors. */
3661 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3662 MIN2(stride
, 4), byteoffset
, tf_base
,
3665 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3666 stride
- 4, byteoffset
, tf_base
,
3667 16 + tf_offset
, ac_glc
);
3669 //store to offchip for TES to read - only if TES reads them
3670 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
3671 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3672 LLVMValueRef tf_inner_offset
;
3673 unsigned param_outer
, param_inner
;
3675 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3676 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3677 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3679 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3680 util_next_power_of_two(outer_comps
));
3682 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3683 outer_comps
, tf_outer_offset
,
3684 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3687 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3688 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3689 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3691 inner_vec
= inner_comps
== 1 ? inner
[0] :
3692 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3693 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3694 inner_comps
, tf_inner_offset
,
3695 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3700 ac_build_endif(&ctx
->ac
, 6503);
3704 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3706 write_tess_factors(ctx
);
3710 si_export_mrt_color(struct radv_shader_context
*ctx
,
3711 LLVMValueRef
*color
, unsigned index
,
3712 struct ac_export_args
*args
)
3715 si_llvm_init_export_args(ctx
, color
, 0xf,
3716 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3717 if (!args
->enabled_channels
)
3718 return false; /* unnecessary NULL export */
3724 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3725 LLVMValueRef depth
, LLVMValueRef stencil
,
3726 LLVMValueRef samplemask
)
3728 struct ac_export_args args
;
3730 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3732 ac_build_export(&ctx
->ac
, &args
);
3736 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3739 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3740 struct ac_export_args color_args
[8];
3742 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3743 LLVMValueRef values
[4];
3745 if (!(ctx
->output_mask
& (1ull << i
)))
3748 if (i
< FRAG_RESULT_DATA0
)
3751 for (unsigned j
= 0; j
< 4; j
++)
3752 values
[j
] = ac_to_float(&ctx
->ac
,
3753 radv_load_output(ctx
, i
, j
));
3755 bool ret
= si_export_mrt_color(ctx
, values
,
3756 i
- FRAG_RESULT_DATA0
,
3757 &color_args
[index
]);
3762 /* Process depth, stencil, samplemask. */
3763 if (ctx
->args
->shader_info
->ps
.writes_z
) {
3764 depth
= ac_to_float(&ctx
->ac
,
3765 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3767 if (ctx
->args
->shader_info
->ps
.writes_stencil
) {
3768 stencil
= ac_to_float(&ctx
->ac
,
3769 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3771 if (ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3772 samplemask
= ac_to_float(&ctx
->ac
,
3773 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3776 /* Set the DONE bit on last non-null color export only if Z isn't
3780 !ctx
->args
->shader_info
->ps
.writes_z
&&
3781 !ctx
->args
->shader_info
->ps
.writes_stencil
&&
3782 !ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3783 unsigned last
= index
- 1;
3785 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3786 color_args
[last
].done
= 1; /* DONE bit */
3789 /* Export PS outputs. */
3790 for (unsigned i
= 0; i
< index
; i
++)
3791 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3793 if (depth
|| stencil
|| samplemask
)
3794 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3796 ac_build_export_null(&ctx
->ac
);
3800 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3802 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
3803 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3807 if (ctx
->ac
.chip_class
>= GFX10
)
3808 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3810 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3814 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3815 LLVMValueRef
*addrs
)
3817 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3819 switch (ctx
->stage
) {
3820 case MESA_SHADER_VERTEX
:
3821 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
)
3822 handle_ls_outputs_post(ctx
);
3823 else if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3824 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->vs
.es_info
);
3825 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3826 handle_ngg_outputs_post_1(ctx
);
3828 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3829 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3830 &ctx
->args
->shader_info
->vs
.outinfo
);
3832 case MESA_SHADER_FRAGMENT
:
3833 handle_fs_outputs_post(ctx
);
3835 case MESA_SHADER_GEOMETRY
:
3836 emit_gs_epilogue(ctx
);
3838 case MESA_SHADER_TESS_CTRL
:
3839 handle_tcs_outputs_post(ctx
);
3841 case MESA_SHADER_TESS_EVAL
:
3842 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3843 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->tes
.es_info
);
3844 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3845 handle_ngg_outputs_post_1(ctx
);
3847 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3848 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3849 &ctx
->args
->shader_info
->tes
.outinfo
);
3856 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3857 LLVMPassManagerRef passmgr
,
3858 const struct radv_nir_compiler_options
*options
)
3860 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3861 LLVMDisposeBuilder(ctx
->ac
.builder
);
3863 ac_llvm_context_dispose(&ctx
->ac
);
3867 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3869 struct radv_vs_output_info
*outinfo
;
3871 switch (ctx
->stage
) {
3872 case MESA_SHADER_FRAGMENT
:
3873 case MESA_SHADER_COMPUTE
:
3874 case MESA_SHADER_TESS_CTRL
:
3875 case MESA_SHADER_GEOMETRY
:
3877 case MESA_SHADER_VERTEX
:
3878 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
||
3879 ctx
->args
->options
->key
.vs_common_out
.as_es
)
3881 outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3883 case MESA_SHADER_TESS_EVAL
:
3884 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3886 outinfo
= &ctx
->args
->shader_info
->tes
.outinfo
;
3889 unreachable("Unhandled shader type");
3892 ac_optimize_vs_outputs(&ctx
->ac
,
3894 outinfo
->vs_output_param_offset
,
3896 &outinfo
->param_exports
);
3900 ac_setup_rings(struct radv_shader_context
*ctx
)
3902 if (ctx
->args
->options
->chip_class
<= GFX8
&&
3903 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3904 ctx
->args
->options
->key
.vs_common_out
.as_es
|| ctx
->args
->options
->key
.vs_common_out
.as_es
)) {
3905 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3907 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3909 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3914 if (ctx
->args
->is_gs_copy_shader
) {
3916 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3917 LLVMConstInt(ctx
->ac
.i32
,
3918 RING_GSVS_VS
, false));
3921 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3922 /* The conceptual layout of the GSVS ring is
3923 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3924 * but the real memory layout is swizzled across
3926 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3928 * Override the buffer descriptor accordingly.
3930 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3931 uint64_t stream_offset
= 0;
3932 unsigned num_records
= ctx
->ac
.wave_size
;
3933 LLVMValueRef base_ring
;
3936 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3937 LLVMConstInt(ctx
->ac
.i32
,
3938 RING_GSVS_GS
, false));
3940 for (unsigned stream
= 0; stream
< 4; stream
++) {
3941 unsigned num_components
, stride
;
3942 LLVMValueRef ring
, tmp
;
3945 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3947 if (!num_components
)
3950 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
3952 /* Limit on the stride field for <= GFX7. */
3953 assert(stride
< (1 << 14));
3955 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3956 base_ring
, v2i64
, "");
3957 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3958 ring
, ctx
->ac
.i32_0
, "");
3959 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3960 LLVMConstInt(ctx
->ac
.i64
,
3961 stream_offset
, 0), "");
3962 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3963 ring
, tmp
, ctx
->ac
.i32_0
, "");
3965 stream_offset
+= stride
* ctx
->ac
.wave_size
;
3967 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3970 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3972 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3973 LLVMConstInt(ctx
->ac
.i32
,
3974 S_008F04_STRIDE(stride
), false), "");
3975 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3978 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3979 LLVMConstInt(ctx
->ac
.i32
,
3980 num_records
, false),
3981 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3983 ctx
->gsvs_ring
[stream
] = ring
;
3987 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3988 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3989 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3990 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3995 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3996 gl_shader_stage stage
,
3997 const struct nir_shader
*nir
)
3999 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
4001 for (unsigned i
= 0; i
< 3; i
++)
4002 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
4003 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
4006 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4007 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4009 LLVMValueRef count
=
4010 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
4011 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4013 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4014 ac_get_arg(&ctx
->ac
, ctx
->args
->rel_auto_id
),
4015 ctx
->abi
.instance_id
, "");
4016 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4017 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
4020 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4021 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_patch_id
),
4022 ctx
->abi
.vertex_id
, "");
4025 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
, bool merged
)
4028 for(int i
= 5; i
>= 0; --i
) {
4029 ctx
->gs_vtx_offset
[i
] =
4030 ac_unpack_param(&ctx
->ac
,
4031 ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
& ~1]),
4035 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
,
4036 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
),
4039 for (int i
= 0; i
< 6; i
++)
4040 ctx
->gs_vtx_offset
[i
] = ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
]);
4041 ctx
->gs_wave_id
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_wave_id
);
4045 /* Ensure that the esgs ring is declared.
4047 * We declare it with 64KB alignment as a hint that the
4048 * pointer value will always be 0.
4050 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4055 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4057 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4058 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4061 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4062 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4066 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4067 struct nir_shader
*const *shaders
,
4069 const struct radv_shader_args
*args
)
4071 struct radv_shader_context ctx
= {0};
4074 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
4076 if (args
->shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
4077 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
4080 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4081 args
->options
->family
, float_mode
,
4082 args
->shader_info
->wave_size
, 64);
4083 ctx
.context
= ctx
.ac
.context
;
4085 ctx
.max_workgroup_size
= 0;
4086 for (int i
= 0; i
< shader_count
; ++i
) {
4087 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4088 radv_nir_get_max_workgroup_size(args
->options
->chip_class
,
4089 shaders
[i
]->info
.stage
,
4093 if (ctx
.ac
.chip_class
>= GFX10
) {
4094 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4095 args
->options
->key
.vs_common_out
.as_ngg
) {
4096 ctx
.max_workgroup_size
= 128;
4100 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2);
4102 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4103 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4104 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4105 ctx
.abi
.load_ubo
= radv_load_ubo
;
4106 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4107 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4108 ctx
.abi
.load_resource
= radv_load_resource
;
4109 ctx
.abi
.clamp_shadow_reference
= false;
4110 ctx
.abi
.robust_buffer_access
= args
->options
->robust_buffer_access
;
4112 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && args
->options
->key
.vs_common_out
.as_ngg
;
4113 if (shader_count
>= 2 || is_ngg
)
4114 ac_init_exec_full_mask(&ctx
.ac
);
4116 if (args
->ac
.vertex_id
.used
)
4117 ctx
.abi
.vertex_id
= ac_get_arg(&ctx
.ac
, args
->ac
.vertex_id
);
4118 if (args
->rel_auto_id
.used
)
4119 ctx
.rel_auto_id
= ac_get_arg(&ctx
.ac
, args
->rel_auto_id
);
4120 if (args
->ac
.instance_id
.used
)
4121 ctx
.abi
.instance_id
= ac_get_arg(&ctx
.ac
, args
->ac
.instance_id
);
4123 if (args
->options
->has_ls_vgpr_init_bug
&&
4124 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4125 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4128 /* Declare scratch space base for streamout and vertex
4129 * compaction. Whether space is actually allocated is
4130 * determined during linking / PM4 creation.
4132 * Add an extra dword per vertex to ensure an odd stride, which
4133 * avoids bank conflicts for SoA accesses.
4135 declare_esgs_ring(&ctx
);
4137 /* This is really only needed when streamout and / or vertex
4138 * compaction is enabled.
4140 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4141 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4142 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4143 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
4144 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4147 for(int i
= 0; i
< shader_count
; ++i
) {
4148 ctx
.stage
= shaders
[i
]->info
.stage
;
4149 ctx
.shader
= shaders
[i
];
4150 ctx
.output_mask
= 0;
4152 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4153 for (int i
= 0; i
< 4; i
++) {
4154 ctx
.gs_next_vertex
[i
] =
4155 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4157 if (args
->options
->key
.vs_common_out
.as_ngg
) {
4158 for (unsigned i
= 0; i
< 4; ++i
) {
4159 ctx
.gs_curprim_verts
[i
] =
4160 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4161 ctx
.gs_generated_prims
[i
] =
4162 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4165 unsigned scratch_size
= 8;
4166 if (args
->shader_info
->so
.num_outputs
)
4169 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
4170 ctx
.gs_ngg_scratch
=
4171 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4172 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4173 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4174 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4176 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4177 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
4178 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
4179 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4182 ctx
.abi
.load_inputs
= load_gs_input
;
4183 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4184 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4185 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4186 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4187 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4188 if (shader_count
== 1)
4189 ctx
.tcs_num_inputs
= args
->options
->key
.tcs
.num_inputs
;
4191 ctx
.tcs_num_inputs
= util_last_bit64(args
->shader_info
->vs
.ls_outputs_written
);
4192 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4193 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4194 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4195 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4196 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4197 ctx
.tcs_num_patches
= args
->options
->key
.tes
.num_patches
;
4198 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4199 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4200 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4201 ctx
.abi
.load_sample_position
= load_sample_position
;
4202 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4203 ctx
.abi
.emit_kill
= radv_emit_kill
;
4206 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4207 args
->options
->key
.vs_common_out
.as_ngg
&&
4208 args
->options
->key
.vs_common_out
.export_prim_id
) {
4209 declare_esgs_ring(&ctx
);
4212 bool nested_barrier
= false;
4215 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4216 args
->options
->key
.vs_common_out
.as_ngg
) {
4217 gfx10_ngg_gs_emit_prologue(&ctx
);
4218 nested_barrier
= false;
4220 nested_barrier
= true;
4224 if (nested_barrier
) {
4225 /* Execute a barrier before the second shader in
4228 * Execute the barrier inside the conditional block,
4229 * so that empty waves can jump directly to s_endpgm,
4230 * which will also signal the barrier.
4232 * This is possible in gfx9, because an empty wave
4233 * for the second shader does not participate in
4234 * the epilogue. With NGG, empty waves may still
4235 * be required to export data (e.g. GS output vertices),
4236 * so we cannot let them exit early.
4238 * If the shader is TCS and the TCS epilog is present
4239 * and contains a barrier, it will wait there and then
4242 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4245 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4246 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4248 ac_setup_rings(&ctx
);
4250 LLVMBasicBlockRef merge_block
;
4251 if (shader_count
>= 2 || is_ngg
) {
4252 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4253 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4254 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4256 LLVMValueRef count
=
4257 ac_unpack_param(&ctx
.ac
,
4258 ac_get_arg(&ctx
.ac
, args
->merged_wave_info
),
4260 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4261 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4262 thread_id
, count
, "");
4263 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4265 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4268 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4269 prepare_interp_optimize(&ctx
, shaders
[i
]);
4270 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4271 handle_vs_inputs(&ctx
, shaders
[i
]);
4272 else if(shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4273 prepare_gs_input_vgprs(&ctx
, shader_count
>= 2);
4275 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, &args
->ac
, shaders
[i
]);
4277 if (shader_count
>= 2 || is_ngg
) {
4278 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4279 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4282 /* This needs to be outside the if wrapping the shader body, as sometimes
4283 * the HW generates waves with 0 es/vs threads. */
4284 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4285 args
->options
->key
.vs_common_out
.as_ngg
&&
4286 i
== shader_count
- 1) {
4287 handle_ngg_outputs_post_2(&ctx
);
4288 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4289 args
->options
->key
.vs_common_out
.as_ngg
) {
4290 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4293 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4294 args
->shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4295 args
->shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4299 LLVMBuildRetVoid(ctx
.ac
.builder
);
4301 if (args
->options
->dump_preoptir
) {
4302 fprintf(stderr
, "%s LLVM IR:\n\n",
4303 radv_get_shader_name(args
->shader_info
,
4304 shaders
[shader_count
- 1]->info
.stage
));
4305 ac_dump_module(ctx
.ac
.module
);
4306 fprintf(stderr
, "\n");
4309 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4311 if (shader_count
== 1)
4312 ac_nir_eliminate_const_vs_outputs(&ctx
);
4314 if (args
->options
->dump_shader
) {
4315 args
->shader_info
->private_mem_vgprs
=
4316 ac_count_scratch_private_memory(ctx
.main_function
);
4319 return ctx
.ac
.module
;
4322 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4324 unsigned *retval
= (unsigned *)context
;
4325 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4326 char *description
= LLVMGetDiagInfoDescription(di
);
4328 if (severity
== LLVMDSError
) {
4330 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4334 LLVMDisposeMessage(description
);
4337 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4338 char **pelf_buffer
, size_t *pelf_size
,
4339 struct ac_llvm_compiler
*ac_llvm
)
4341 unsigned retval
= 0;
4342 LLVMContextRef llvm_ctx
;
4344 /* Setup Diagnostic Handler*/
4345 llvm_ctx
= LLVMGetModuleContext(M
);
4347 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4351 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4356 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4357 LLVMModuleRef llvm_module
,
4358 struct radv_shader_binary
**rbinary
,
4359 gl_shader_stage stage
,
4361 const struct radv_nir_compiler_options
*options
)
4363 char *elf_buffer
= NULL
;
4364 size_t elf_size
= 0;
4365 char *llvm_ir_string
= NULL
;
4367 if (options
->dump_shader
) {
4368 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4369 ac_dump_module(llvm_module
);
4370 fprintf(stderr
, "\n");
4373 if (options
->record_ir
) {
4374 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4375 llvm_ir_string
= strdup(llvm_ir
);
4376 LLVMDisposeMessage(llvm_ir
);
4379 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4381 fprintf(stderr
, "compile failed\n");
4384 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4385 LLVMDisposeModule(llvm_module
);
4386 LLVMContextDispose(ctx
);
4388 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4389 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4390 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4391 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4393 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4395 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4396 rbin
->base
.stage
= stage
;
4397 rbin
->base
.total_size
= alloc_size
;
4398 rbin
->elf_size
= elf_size
;
4399 rbin
->llvm_ir_size
= llvm_ir_size
;
4400 *rbinary
= &rbin
->base
;
4402 free(llvm_ir_string
);
4407 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4408 struct radv_shader_binary
**rbinary
,
4409 const struct radv_shader_args
*args
,
4410 struct nir_shader
*const *nir
,
4414 LLVMModuleRef llvm_module
;
4416 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, args
);
4418 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
4419 nir
[nir_count
- 1]->info
.stage
,
4420 radv_get_shader_name(args
->shader_info
,
4421 nir
[nir_count
- 1]->info
.stage
),
4424 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4425 if (args
->options
->chip_class
>= GFX9
) {
4426 if (nir_count
== 2 &&
4427 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4428 args
->shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4434 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4436 LLVMValueRef vtx_offset
=
4437 LLVMBuildMul(ctx
->ac
.builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.vertex_id
),
4438 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4439 LLVMValueRef stream_id
;
4441 /* Fetch the vertex stream ID. */
4442 if (!ctx
->args
->options
->use_ngg_streamout
&&
4443 ctx
->args
->shader_info
->so
.num_outputs
) {
4445 ac_unpack_param(&ctx
->ac
,
4446 ac_get_arg(&ctx
->ac
,
4447 ctx
->args
->streamout_config
),
4450 stream_id
= ctx
->ac
.i32_0
;
4453 LLVMBasicBlockRef end_bb
;
4454 LLVMValueRef switch_inst
;
4456 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4457 ctx
->main_function
, "end");
4458 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4460 for (unsigned stream
= 0; stream
< 4; stream
++) {
4461 unsigned num_components
=
4462 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
4463 LLVMBasicBlockRef bb
;
4466 if (stream
> 0 && !num_components
)
4469 if (stream
> 0 && !ctx
->args
->shader_info
->so
.num_outputs
)
4472 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4473 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4474 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4477 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4478 unsigned output_usage_mask
=
4479 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4480 unsigned output_stream
=
4481 ctx
->args
->shader_info
->gs
.output_streams
[i
];
4482 int length
= util_last_bit(output_usage_mask
);
4484 if (!(ctx
->output_mask
& (1ull << i
)) ||
4485 output_stream
!= stream
)
4488 for (unsigned j
= 0; j
< length
; j
++) {
4489 LLVMValueRef value
, soffset
;
4491 if (!(output_usage_mask
& (1 << j
)))
4494 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4496 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
4500 value
= ac_build_buffer_load(&ctx
->ac
,
4503 vtx_offset
, soffset
,
4504 0, ac_glc
| ac_slc
, true, false);
4506 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4507 if (ac_get_type_size(type
) == 2) {
4508 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4509 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4512 LLVMBuildStore(ctx
->ac
.builder
,
4513 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4517 if (!ctx
->args
->options
->use_ngg_streamout
&&
4518 ctx
->args
->shader_info
->so
.num_outputs
)
4519 radv_emit_streamout(ctx
, stream
);
4522 handle_vs_outputs_post(ctx
, false, true,
4523 &ctx
->args
->shader_info
->vs
.outinfo
);
4526 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4529 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4533 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4534 struct nir_shader
*geom_shader
,
4535 struct radv_shader_binary
**rbinary
,
4536 const struct radv_shader_args
*args
)
4538 struct radv_shader_context ctx
= {0};
4541 assert(args
->is_gs_copy_shader
);
4543 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4544 args
->options
->family
, AC_FLOAT_MODE_DEFAULT
, 64, 64);
4545 ctx
.context
= ctx
.ac
.context
;
4547 ctx
.stage
= MESA_SHADER_VERTEX
;
4548 ctx
.shader
= geom_shader
;
4550 create_function(&ctx
, MESA_SHADER_VERTEX
, false);
4552 ac_setup_rings(&ctx
);
4554 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4555 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4556 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4557 variable
, MESA_SHADER_VERTEX
);
4560 ac_gs_copy_shader_emit(&ctx
);
4562 LLVMBuildRetVoid(ctx
.ac
.builder
);
4564 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4566 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
4567 MESA_SHADER_VERTEX
, "GS Copy Shader", args
->options
);
4568 (*rbinary
)->is_gs_copy_shader
= true;