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radv: Move argument declaration out of nir_to_llvm
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "nir/nir.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct radv_shader_context {
50 struct ac_llvm_context ac;
51 const struct nir_shader *shader;
52 struct ac_shader_abi abi;
53 const struct radv_shader_args *args;
54
55 gl_shader_stage stage;
56
57 unsigned max_workgroup_size;
58 LLVMContextRef context;
59 LLVMValueRef main_function;
60
61 LLVMValueRef descriptor_sets[MAX_SETS];
62
63 LLVMValueRef ring_offsets;
64
65 LLVMValueRef rel_auto_id;
66
67 LLVMValueRef gs_wave_id;
68 LLVMValueRef gs_vtx_offset[6];
69
70 LLVMValueRef esgs_ring;
71 LLVMValueRef gsvs_ring[4];
72 LLVMValueRef hs_ring_tess_offchip;
73 LLVMValueRef hs_ring_tess_factor;
74
75 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
76
77 uint64_t output_mask;
78
79 LLVMValueRef gs_next_vertex[4];
80 LLVMValueRef gs_curprim_verts[4];
81 LLVMValueRef gs_generated_prims[4];
82 LLVMValueRef gs_ngg_emit;
83 LLVMValueRef gs_ngg_scratch;
84
85 uint32_t tcs_num_inputs;
86 uint32_t tcs_num_patches;
87
88 LLVMValueRef vertexptr; /* GFX10 only */
89 };
90
91 struct radv_shader_output_values {
92 LLVMValueRef values[4];
93 unsigned slot_name;
94 unsigned slot_index;
95 unsigned usage_mask;
96 };
97
98 static inline struct radv_shader_context *
99 radv_shader_context_from_abi(struct ac_shader_abi *abi)
100 {
101 struct radv_shader_context *ctx = NULL;
102 return container_of(abi, ctx, abi);
103 }
104
105 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
106 {
107 switch (ctx->stage) {
108 case MESA_SHADER_TESS_CTRL:
109 return ac_unpack_param(&ctx->ac,
110 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
111 0, 8);
112 case MESA_SHADER_TESS_EVAL:
113 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
114 break;
115 default:
116 unreachable("Illegal stage");
117 }
118 }
119
120 static unsigned
121 get_tcs_num_patches(struct radv_shader_context *ctx)
122 {
123 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
124 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
125 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
126 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
127 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
128 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
129 uint32_t output_vertex_size = num_tcs_outputs * 16;
130 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
131 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
132 unsigned num_patches;
133 unsigned hardware_lds_size;
134
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
138 */
139 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
142 */
143 hardware_lds_size = 32768;
144
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
147 *
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
149 */
150 if (ctx->args->options->chip_class >= GFX7 && ctx->args->options->family != CHIP_STONEY)
151 hardware_lds_size = 65536;
152
153 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches = MIN2(num_patches, (ctx->args->options->tess_offchip_block_dw_size * 4) / output_patch_size);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
158 */
159 num_patches = MIN2(num_patches, 40);
160
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx->args->options->chip_class == GFX6) {
163 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
164 num_patches = MIN2(num_patches, one_wave);
165 }
166 return num_patches;
167 }
168
169 static unsigned
170 calculate_tess_lds_size(struct radv_shader_context *ctx)
171 {
172 unsigned num_tcs_input_cp = ctx->args->options->key.tcs.input_vertices;
173 unsigned num_tcs_output_cp;
174 unsigned num_tcs_outputs, num_tcs_patch_outputs;
175 unsigned input_vertex_size, output_vertex_size;
176 unsigned input_patch_size, output_patch_size;
177 unsigned pervertex_output_patch_size;
178 unsigned output_patch0_offset;
179 unsigned num_patches;
180 unsigned lds_size;
181
182 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
183 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
184 num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
185
186 input_vertex_size = ctx->tcs_num_inputs * 16;
187 output_vertex_size = num_tcs_outputs * 16;
188
189 input_patch_size = num_tcs_input_cp * input_vertex_size;
190
191 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
192 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
193
194 num_patches = ctx->tcs_num_patches;
195 output_patch0_offset = input_patch_size * num_patches;
196
197 lds_size = output_patch0_offset + output_patch_size * num_patches;
198 return lds_size;
199 }
200
201 /* Tessellation shaders pass outputs to the next shader using LDS.
202 *
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
205 *
206 * The LDS layout is:
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
210 * - ...
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
217 * - ...
218 *
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
220 */
221 static LLVMValueRef
222 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
223 {
224 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
225 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
226 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
227
228 input_patch_size /= 4;
229 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
230 }
231
232 static LLVMValueRef
233 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
234 {
235 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
236 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
237 uint32_t output_vertex_size = num_tcs_outputs * 16;
238 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
239 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
240 output_patch_size /= 4;
241 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
242 }
243
244 static LLVMValueRef
245 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
246 {
247 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
248 uint32_t output_vertex_size = num_tcs_outputs * 16;
249 output_vertex_size /= 4;
250 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
251 }
252
253 static LLVMValueRef
254 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
255 {
256 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
257 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
258 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
259 uint32_t output_patch0_offset = input_patch_size;
260 unsigned num_patches = ctx->tcs_num_patches;
261
262 output_patch0_offset *= num_patches;
263 output_patch0_offset /= 4;
264 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
265 }
266
267 static LLVMValueRef
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
269 {
270 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
271 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
272 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
273 uint32_t output_patch0_offset = input_patch_size;
274
275 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
276 uint32_t output_vertex_size = num_tcs_outputs * 16;
277 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
278 unsigned num_patches = ctx->tcs_num_patches;
279
280 output_patch0_offset *= num_patches;
281 output_patch0_offset += pervertex_output_patch_size;
282 output_patch0_offset /= 4;
283 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
284 }
285
286 static LLVMValueRef
287 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
288 {
289 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
290 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
291
292 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
293 }
294
295 static LLVMValueRef
296 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
297 {
298 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
299 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
300 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
301
302 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
303 patch0_offset);
304 }
305
306 static LLVMValueRef
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
308 {
309 LLVMValueRef patch0_patch_data_offset =
310 get_tcs_out_patch0_patch_data_offset(ctx);
311 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
312 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
313
314 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
315 patch0_patch_data_offset);
316 }
317
318 static LLVMValueRef
319 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
320 LLVMBuilderRef builder,
321 const struct ac_shader_args *args,
322 enum ac_llvm_calling_convention convention,
323 unsigned max_workgroup_size,
324 const struct radv_nir_compiler_options *options)
325 {
326 LLVMValueRef main_function =
327 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
328
329 if (options->address32_hi) {
330 ac_llvm_add_target_dep_function_attr(main_function,
331 "amdgpu-32bit-address-high-bits",
332 options->address32_hi);
333 }
334
335 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
336
337 return main_function;
338 }
339
340 static void
341 load_descriptor_sets(struct radv_shader_context *ctx)
342 {
343 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
344 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
345 LLVMValueRef desc_sets =
346 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
347 while (mask) {
348 int i = u_bit_scan(&mask);
349
350 ctx->descriptor_sets[i] =
351 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
352 LLVMConstInt(ctx->ac.i32, i, false));
353
354 }
355 } else {
356 while (mask) {
357 int i = u_bit_scan(&mask);
358
359 ctx->descriptor_sets[i] =
360 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
361 }
362 }
363 }
364
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
367 {
368 switch (stage) {
369 case MESA_SHADER_VERTEX:
370 case MESA_SHADER_TESS_EVAL:
371 return AC_LLVM_AMDGPU_VS;
372 break;
373 case MESA_SHADER_GEOMETRY:
374 return AC_LLVM_AMDGPU_GS;
375 break;
376 case MESA_SHADER_TESS_CTRL:
377 return AC_LLVM_AMDGPU_HS;
378 break;
379 case MESA_SHADER_FRAGMENT:
380 return AC_LLVM_AMDGPU_PS;
381 break;
382 case MESA_SHADER_COMPUTE:
383 return AC_LLVM_AMDGPU_CS;
384 break;
385 default:
386 unreachable("Unhandle shader type");
387 }
388 }
389
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage)
392 {
393 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
394 }
395
396 static void create_function(struct radv_shader_context *ctx,
397 gl_shader_stage stage,
398 bool has_previous_stage)
399 {
400 if (ctx->ac.chip_class >= GFX10) {
401 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage = MESA_SHADER_GEOMETRY;
404 has_previous_stage = true;
405 }
406 }
407
408 ctx->main_function = create_llvm_function(
409 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
410 get_llvm_calling_convention(ctx->main_function, stage),
411 ctx->max_workgroup_size,
412 ctx->args->options);
413
414 if (ctx->args->options->supports_spill) {
415 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
416 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
417 NULL, 0, AC_FUNC_ATTR_READNONE);
418 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
419 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
420 } else if (ctx->args->ring_offsets.used) {
421 ctx->ring_offsets = ac_get_arg(&ctx->ac, ctx->args->ring_offsets);
422 }
423
424 load_descriptor_sets(ctx);
425
426 if (stage == MESA_SHADER_TESS_CTRL ||
427 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
428 /* GFX9 has the ESGS ring buffer in LDS. */
429 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
430 ac_declare_lds_as_pointer(&ctx->ac);
431 }
432
433 }
434
435
436 static LLVMValueRef
437 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
438 unsigned desc_set, unsigned binding)
439 {
440 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
441 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
442 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
443 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
444 unsigned base_offset = layout->binding[binding].offset;
445 LLVMValueRef offset, stride;
446
447 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
448 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
449 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
450 layout->binding[binding].dynamic_offset_offset;
451 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
452 base_offset = pipeline_layout->push_constant_size + 16 * idx;
453 stride = LLVMConstInt(ctx->ac.i32, 16, false);
454 } else
455 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
456
457 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
458
459 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
460 offset = ac_build_imad(&ctx->ac, index, stride, offset);
461 }
462
463 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
464 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
465 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
466
467 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
468 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
469 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
470 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
471 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
472
473 if (ctx->ac.chip_class >= GFX10) {
474 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
475 S_008F0C_OOB_SELECT(3) |
476 S_008F0C_RESOURCE_LEVEL(1);
477 } else {
478 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
479 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
480 }
481
482 LLVMValueRef desc_components[4] = {
483 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
484 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
485 /* High limit to support variable sizes. */
486 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
487 LLVMConstInt(ctx->ac.i32, desc_type, false),
488 };
489
490 return ac_build_gather_values(&ctx->ac, desc_components, 4);
491 }
492
493 return desc_ptr;
494 }
495
496
497 /* The offchip buffer layout for TCS->TES is
498 *
499 * - attribute 0 of patch 0 vertex 0
500 * - attribute 0 of patch 0 vertex 1
501 * - attribute 0 of patch 0 vertex 2
502 * ...
503 * - attribute 0 of patch 1 vertex 0
504 * - attribute 0 of patch 1 vertex 1
505 * ...
506 * - attribute 1 of patch 0 vertex 0
507 * - attribute 1 of patch 0 vertex 1
508 * ...
509 * - per patch attribute 0 of patch 0
510 * - per patch attribute 0 of patch 1
511 * ...
512 *
513 * Note that every attribute has 4 components.
514 */
515 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
516 {
517 uint32_t num_patches = ctx->tcs_num_patches;
518 uint32_t num_tcs_outputs;
519 if (ctx->stage == MESA_SHADER_TESS_CTRL)
520 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
521 else
522 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
523
524 uint32_t output_vertex_size = num_tcs_outputs * 16;
525 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
526
527 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
528 }
529
530 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
531 LLVMValueRef vertex_index)
532 {
533 LLVMValueRef param_stride;
534 if (vertex_index)
535 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
536 else
537 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
538 return param_stride;
539 }
540
541 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
542 LLVMValueRef vertex_index,
543 LLVMValueRef param_index)
544 {
545 LLVMValueRef base_addr;
546 LLVMValueRef param_stride, constant16;
547 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
548 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
549 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
550 param_stride = calc_param_stride(ctx, vertex_index);
551 if (vertex_index) {
552 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
553 vertices_per_patch, vertex_index);
554 } else {
555 base_addr = rel_patch_id;
556 }
557
558 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
559 LLVMBuildMul(ctx->ac.builder, param_index,
560 param_stride, ""), "");
561
562 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
563
564 if (!vertex_index) {
565 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
566
567 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
568 patch_data_offset, "");
569 }
570 return base_addr;
571 }
572
573 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
574 unsigned param,
575 unsigned const_index,
576 bool is_compact,
577 LLVMValueRef vertex_index,
578 LLVMValueRef indir_index)
579 {
580 LLVMValueRef param_index;
581
582 if (indir_index)
583 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
584 indir_index, "");
585 else {
586 if (const_index && !is_compact)
587 param += const_index;
588 param_index = LLVMConstInt(ctx->ac.i32, param, false);
589 }
590 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
591 }
592
593 static LLVMValueRef
594 get_dw_address(struct radv_shader_context *ctx,
595 LLVMValueRef dw_addr,
596 unsigned param,
597 unsigned const_index,
598 bool compact_const_index,
599 LLVMValueRef vertex_index,
600 LLVMValueRef stride,
601 LLVMValueRef indir_index)
602
603 {
604
605 if (vertex_index) {
606 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
607 LLVMBuildMul(ctx->ac.builder,
608 vertex_index,
609 stride, ""), "");
610 }
611
612 if (indir_index)
613 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
614 LLVMBuildMul(ctx->ac.builder, indir_index,
615 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
616 else if (const_index && !compact_const_index)
617 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
618 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
619
620 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
621 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
622
623 if (const_index && compact_const_index)
624 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
625 LLVMConstInt(ctx->ac.i32, const_index, false), "");
626 return dw_addr;
627 }
628
629 static LLVMValueRef
630 load_tcs_varyings(struct ac_shader_abi *abi,
631 LLVMTypeRef type,
632 LLVMValueRef vertex_index,
633 LLVMValueRef indir_index,
634 unsigned const_index,
635 unsigned location,
636 unsigned driver_location,
637 unsigned component,
638 unsigned num_components,
639 bool is_patch,
640 bool is_compact,
641 bool load_input)
642 {
643 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
644 LLVMValueRef dw_addr, stride;
645 LLVMValueRef value[4], result;
646 unsigned param = shader_io_get_unique_index(location);
647
648 if (load_input) {
649 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
650 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
651 dw_addr = get_tcs_in_current_patch_offset(ctx);
652 } else {
653 if (!is_patch) {
654 stride = get_tcs_out_vertex_stride(ctx);
655 dw_addr = get_tcs_out_current_patch_offset(ctx);
656 } else {
657 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
658 stride = NULL;
659 }
660 }
661
662 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
663 indir_index);
664
665 for (unsigned i = 0; i < num_components + component; i++) {
666 value[i] = ac_lds_load(&ctx->ac, dw_addr);
667 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
668 ctx->ac.i32_1, "");
669 }
670 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
671 return result;
672 }
673
674 static void
675 store_tcs_output(struct ac_shader_abi *abi,
676 const nir_variable *var,
677 LLVMValueRef vertex_index,
678 LLVMValueRef param_index,
679 unsigned const_index,
680 LLVMValueRef src,
681 unsigned writemask)
682 {
683 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
684 const unsigned location = var->data.location;
685 unsigned component = var->data.location_frac;
686 const bool is_patch = var->data.patch;
687 const bool is_compact = var->data.compact;
688 LLVMValueRef dw_addr;
689 LLVMValueRef stride = NULL;
690 LLVMValueRef buf_addr = NULL;
691 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
692 unsigned param;
693 bool store_lds = true;
694
695 if (is_patch) {
696 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
697 store_lds = false;
698 } else {
699 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
700 store_lds = false;
701 }
702
703 param = shader_io_get_unique_index(location);
704 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
705 const_index += component;
706 component = 0;
707
708 if (const_index >= 4) {
709 const_index -= 4;
710 param++;
711 }
712 }
713
714 if (!is_patch) {
715 stride = get_tcs_out_vertex_stride(ctx);
716 dw_addr = get_tcs_out_current_patch_offset(ctx);
717 } else {
718 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
719 }
720
721 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
722 param_index);
723 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
724 vertex_index, param_index);
725
726 bool is_tess_factor = false;
727 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
728 location == VARYING_SLOT_TESS_LEVEL_OUTER)
729 is_tess_factor = true;
730
731 unsigned base = is_compact ? const_index : 0;
732 for (unsigned chan = 0; chan < 8; chan++) {
733 if (!(writemask & (1 << chan)))
734 continue;
735 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
736 value = ac_to_integer(&ctx->ac, value);
737 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
738
739 if (store_lds || is_tess_factor) {
740 LLVMValueRef dw_addr_chan =
741 LLVMBuildAdd(ctx->ac.builder, dw_addr,
742 LLVMConstInt(ctx->ac.i32, chan, false), "");
743 ac_lds_store(&ctx->ac, dw_addr_chan, value);
744 }
745
746 if (!is_tess_factor && writemask != 0xF)
747 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
748 buf_addr, oc_lds,
749 4 * (base + chan), ac_glc, false);
750 }
751
752 if (writemask == 0xF) {
753 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
754 buf_addr, oc_lds,
755 (base * 4), ac_glc, false);
756 }
757 }
758
759 static LLVMValueRef
760 load_tes_input(struct ac_shader_abi *abi,
761 LLVMTypeRef type,
762 LLVMValueRef vertex_index,
763 LLVMValueRef param_index,
764 unsigned const_index,
765 unsigned location,
766 unsigned driver_location,
767 unsigned component,
768 unsigned num_components,
769 bool is_patch,
770 bool is_compact,
771 bool load_input)
772 {
773 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
774 LLVMValueRef buf_addr;
775 LLVMValueRef result;
776 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
777 unsigned param = shader_io_get_unique_index(location);
778
779 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
780 const_index += component;
781 component = 0;
782 if (const_index >= 4) {
783 const_index -= 4;
784 param++;
785 }
786 }
787
788 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
789 is_compact, vertex_index, param_index);
790
791 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
792 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
793
794 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
795 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
796 result = ac_trim_vector(&ctx->ac, result, num_components);
797 return result;
798 }
799
800 static LLVMValueRef
801 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
802 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
803 {
804 LLVMValueRef values[2] = {
805 ac_to_integer(&ctx->ac, a),
806 ac_to_integer(&ctx->ac, b),
807 };
808 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
809 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
810 }
811
812 static LLVMValueRef
813 load_gs_input(struct ac_shader_abi *abi,
814 unsigned location,
815 unsigned driver_location,
816 unsigned component,
817 unsigned num_components,
818 unsigned vertex_index,
819 unsigned const_index,
820 LLVMTypeRef type)
821 {
822 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
823 LLVMValueRef vtx_offset;
824 unsigned param, vtx_offset_param;
825 LLVMValueRef value[4], result;
826
827 vtx_offset_param = vertex_index;
828 assert(vtx_offset_param < 6);
829 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
830 LLVMConstInt(ctx->ac.i32, 4, false), "");
831
832 param = shader_io_get_unique_index(location);
833
834 for (unsigned i = component; i < num_components + component; i++) {
835 if (ctx->ac.chip_class >= GFX9) {
836 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
837 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
838 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
839 value[i] = ac_lds_load(&ctx->ac, dw_addr);
840
841 if (ac_get_type_size(type) == 8) {
842 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
843 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
844 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
845
846 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
847 }
848 } else {
849 LLVMValueRef soffset =
850 LLVMConstInt(ctx->ac.i32,
851 (param * 4 + i + const_index) * 256,
852 false);
853
854 value[i] = ac_build_buffer_load(&ctx->ac,
855 ctx->esgs_ring, 1,
856 ctx->ac.i32_0,
857 vtx_offset, soffset,
858 0, ac_glc, true, false);
859
860 if (ac_get_type_size(type) == 8) {
861 soffset = LLVMConstInt(ctx->ac.i32,
862 (param * 4 + i + const_index + 1) * 256,
863 false);
864
865 LLVMValueRef tmp =
866 ac_build_buffer_load(&ctx->ac,
867 ctx->esgs_ring, 1,
868 ctx->ac.i32_0,
869 vtx_offset, soffset,
870 0, ac_glc, true, false);
871
872 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
873 }
874 }
875
876 if (ac_get_type_size(type) == 2) {
877 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
878 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
879 }
880 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
881 }
882 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
883 result = ac_to_integer(&ctx->ac, result);
884 return result;
885 }
886
887
888 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
889 {
890 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
891 ac_build_kill_if_false(&ctx->ac, visible);
892 }
893
894 static uint32_t
895 radv_get_sample_pos_offset(uint32_t num_samples)
896 {
897 uint32_t sample_pos_offset = 0;
898
899 switch (num_samples) {
900 case 2:
901 sample_pos_offset = 1;
902 break;
903 case 4:
904 sample_pos_offset = 3;
905 break;
906 case 8:
907 sample_pos_offset = 7;
908 break;
909 default:
910 break;
911 }
912 return sample_pos_offset;
913 }
914
915 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
916 LLVMValueRef sample_id)
917 {
918 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
919
920 LLVMValueRef result;
921 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
922 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
923
924 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
925 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
926
927 uint32_t sample_pos_offset =
928 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
929
930 sample_id =
931 LLVMBuildAdd(ctx->ac.builder, sample_id,
932 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
933 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
934
935 return result;
936 }
937
938
939 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
940 {
941 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
942 uint8_t log2_ps_iter_samples;
943
944 if (ctx->args->shader_info->ps.force_persample) {
945 log2_ps_iter_samples =
946 util_logbase2(ctx->args->options->key.fs.num_samples);
947 } else {
948 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
949 }
950
951 /* The bit pattern matches that used by fixed function fragment
952 * processing. */
953 static const uint16_t ps_iter_masks[] = {
954 0xffff, /* not used */
955 0x5555,
956 0x1111,
957 0x0101,
958 0x0001,
959 };
960 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
961
962 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
963
964 LLVMValueRef result, sample_id;
965 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
966 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
967 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
968 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
969 return result;
970 }
971
972
973 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
974 unsigned stream,
975 LLVMValueRef *addrs);
976
977 static void
978 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
979 {
980 LLVMValueRef gs_next_vertex;
981 LLVMValueRef can_emit;
982 unsigned offset = 0;
983 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
984
985 if (ctx->args->options->key.vs_common_out.as_ngg) {
986 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
987 return;
988 }
989
990 /* Write vertex attribute values to GSVS ring */
991 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
992 ctx->gs_next_vertex[stream],
993 "");
994
995 /* If this thread has already emitted the declared maximum number of
996 * vertices, don't emit any more: excessive vertex emissions are not
997 * supposed to have any effect.
998 */
999 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1000 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
1001
1002 bool use_kill = !ctx->args->shader_info->gs.writes_memory;
1003 if (use_kill)
1004 ac_build_kill_if_false(&ctx->ac, can_emit);
1005 else
1006 ac_build_ifcc(&ctx->ac, can_emit, 6505);
1007
1008 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1009 unsigned output_usage_mask =
1010 ctx->args->shader_info->gs.output_usage_mask[i];
1011 uint8_t output_stream =
1012 ctx->args->shader_info->gs.output_streams[i];
1013 LLVMValueRef *out_ptr = &addrs[i * 4];
1014 int length = util_last_bit(output_usage_mask);
1015
1016 if (!(ctx->output_mask & (1ull << i)) ||
1017 output_stream != stream)
1018 continue;
1019
1020 for (unsigned j = 0; j < length; j++) {
1021 if (!(output_usage_mask & (1 << j)))
1022 continue;
1023
1024 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1025 out_ptr[j], "");
1026 LLVMValueRef voffset =
1027 LLVMConstInt(ctx->ac.i32, offset *
1028 ctx->shader->info.gs.vertices_out, false);
1029
1030 offset++;
1031
1032 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1033 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1034
1035 out_val = ac_to_integer(&ctx->ac, out_val);
1036 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1037
1038 ac_build_buffer_store_dword(&ctx->ac,
1039 ctx->gsvs_ring[stream],
1040 out_val, 1,
1041 voffset,
1042 ac_get_arg(&ctx->ac,
1043 ctx->args->gs2vs_offset),
1044 0, ac_glc | ac_slc, true);
1045 }
1046 }
1047
1048 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1049 ctx->ac.i32_1, "");
1050 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1051
1052 ac_build_sendmsg(&ctx->ac,
1053 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1054 ctx->gs_wave_id);
1055
1056 if (!use_kill)
1057 ac_build_endif(&ctx->ac, 6505);
1058 }
1059
1060 static void
1061 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1062 {
1063 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1064
1065 if (ctx->args->options->key.vs_common_out.as_ngg) {
1066 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1067 return;
1068 }
1069
1070 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1071 }
1072
1073 static LLVMValueRef
1074 load_tess_coord(struct ac_shader_abi *abi)
1075 {
1076 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1077
1078 LLVMValueRef coord[4] = {
1079 ac_get_arg(&ctx->ac, ctx->args->tes_u),
1080 ac_get_arg(&ctx->ac, ctx->args->tes_v),
1081 ctx->ac.f32_0,
1082 ctx->ac.f32_0,
1083 };
1084
1085 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1086 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1087 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1088
1089 return ac_build_gather_values(&ctx->ac, coord, 3);
1090 }
1091
1092 static LLVMValueRef
1093 load_patch_vertices_in(struct ac_shader_abi *abi)
1094 {
1095 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1096 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
1097 }
1098
1099
1100 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1101 {
1102 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1103 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
1104 }
1105
1106 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1107 LLVMValueRef buffer_ptr, bool write)
1108 {
1109 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1110 LLVMValueRef result;
1111
1112 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1113
1114 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1115 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1116
1117 return result;
1118 }
1119
1120 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1121 {
1122 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1123 LLVMValueRef result;
1124
1125 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1126 /* Do not load the descriptor for inlined uniform blocks. */
1127 return buffer_ptr;
1128 }
1129
1130 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1131
1132 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1133 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1134
1135 return result;
1136 }
1137
1138 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1139 unsigned descriptor_set,
1140 unsigned base_index,
1141 unsigned constant_index,
1142 LLVMValueRef index,
1143 enum ac_descriptor_type desc_type,
1144 bool image, bool write,
1145 bool bindless)
1146 {
1147 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1148 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1149 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1150 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1151 unsigned offset = binding->offset;
1152 unsigned stride = binding->size;
1153 unsigned type_size;
1154 LLVMBuilderRef builder = ctx->ac.builder;
1155 LLVMTypeRef type;
1156
1157 assert(base_index < layout->binding_count);
1158
1159 switch (desc_type) {
1160 case AC_DESC_IMAGE:
1161 type = ctx->ac.v8i32;
1162 type_size = 32;
1163 break;
1164 case AC_DESC_FMASK:
1165 type = ctx->ac.v8i32;
1166 offset += 32;
1167 type_size = 32;
1168 break;
1169 case AC_DESC_SAMPLER:
1170 type = ctx->ac.v4i32;
1171 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1172 offset += radv_combined_image_descriptor_sampler_offset(binding);
1173 }
1174
1175 type_size = 16;
1176 break;
1177 case AC_DESC_BUFFER:
1178 type = ctx->ac.v4i32;
1179 type_size = 16;
1180 break;
1181 case AC_DESC_PLANE_0:
1182 case AC_DESC_PLANE_1:
1183 case AC_DESC_PLANE_2:
1184 type = ctx->ac.v8i32;
1185 type_size = 32;
1186 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1187 break;
1188 default:
1189 unreachable("invalid desc_type\n");
1190 }
1191
1192 offset += constant_index * stride;
1193
1194 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1195 (!index || binding->immutable_samplers_equal)) {
1196 if (binding->immutable_samplers_equal)
1197 constant_index = 0;
1198
1199 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1200
1201 LLVMValueRef constants[] = {
1202 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1203 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1204 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1205 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1206 };
1207 return ac_build_gather_values(&ctx->ac, constants, 4);
1208 }
1209
1210 assert(stride % type_size == 0);
1211
1212 LLVMValueRef adjusted_index = index;
1213 if (!adjusted_index)
1214 adjusted_index = ctx->ac.i32_0;
1215
1216 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1217
1218 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1219 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1220 list = LLVMBuildPointerCast(builder, list,
1221 ac_array_in_const32_addr_space(type), "");
1222
1223 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1224
1225 /* 3 plane formats always have same size and format for plane 1 & 2, so
1226 * use the tail from plane 1 so that we can store only the first 16 bytes
1227 * of the last plane. */
1228 if (desc_type == AC_DESC_PLANE_2) {
1229 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1230
1231 LLVMValueRef components[8];
1232 for (unsigned i = 0; i < 4; ++i)
1233 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1234
1235 for (unsigned i = 4; i < 8; ++i)
1236 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1237 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1238 }
1239
1240 return descriptor;
1241 }
1242
1243 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1244 * so we may need to fix it up. */
1245 static LLVMValueRef
1246 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1247 unsigned adjustment,
1248 LLVMValueRef alpha)
1249 {
1250 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1251 return alpha;
1252
1253 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1254
1255 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1256
1257 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1258 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1259 else
1260 alpha = ac_to_integer(&ctx->ac, alpha);
1261
1262 /* For the integer-like cases, do a natural sign extension.
1263 *
1264 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1265 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1266 * exponent.
1267 */
1268 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1269 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1270 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1271 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1272
1273 /* Convert back to the right type. */
1274 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1275 LLVMValueRef clamp;
1276 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1277 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1278 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1279 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1280 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1281 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1282 }
1283
1284 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1285 }
1286
1287 static unsigned
1288 get_num_channels_from_data_format(unsigned data_format)
1289 {
1290 switch (data_format) {
1291 case V_008F0C_BUF_DATA_FORMAT_8:
1292 case V_008F0C_BUF_DATA_FORMAT_16:
1293 case V_008F0C_BUF_DATA_FORMAT_32:
1294 return 1;
1295 case V_008F0C_BUF_DATA_FORMAT_8_8:
1296 case V_008F0C_BUF_DATA_FORMAT_16_16:
1297 case V_008F0C_BUF_DATA_FORMAT_32_32:
1298 return 2;
1299 case V_008F0C_BUF_DATA_FORMAT_10_11_11:
1300 case V_008F0C_BUF_DATA_FORMAT_11_11_10:
1301 case V_008F0C_BUF_DATA_FORMAT_32_32_32:
1302 return 3;
1303 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
1304 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
1305 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
1306 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
1307 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
1308 return 4;
1309 default:
1310 break;
1311 }
1312
1313 return 4;
1314 }
1315
1316 static LLVMValueRef
1317 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1318 LLVMValueRef value,
1319 unsigned num_channels,
1320 bool is_float)
1321 {
1322 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1323 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1324 LLVMValueRef chan[4];
1325
1326 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1327 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1328
1329 if (num_channels == 4 && num_channels == vec_size)
1330 return value;
1331
1332 num_channels = MIN2(num_channels, vec_size);
1333
1334 for (unsigned i = 0; i < num_channels; i++)
1335 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1336 } else {
1337 if (num_channels) {
1338 assert(num_channels == 1);
1339 chan[0] = value;
1340 }
1341 }
1342
1343 for (unsigned i = num_channels; i < 4; i++) {
1344 chan[i] = i == 3 ? one : zero;
1345 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1346 }
1347
1348 return ac_build_gather_values(&ctx->ac, chan, 4);
1349 }
1350
1351 static void
1352 handle_vs_input_decl(struct radv_shader_context *ctx,
1353 struct nir_variable *variable)
1354 {
1355 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1356 LLVMValueRef t_offset;
1357 LLVMValueRef t_list;
1358 LLVMValueRef input;
1359 LLVMValueRef buffer_index;
1360 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1361 uint8_t input_usage_mask =
1362 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1363 unsigned num_input_channels = util_last_bit(input_usage_mask);
1364
1365 variable->data.driver_location = variable->data.location * 4;
1366
1367 enum glsl_base_type type = glsl_get_base_type(variable->type);
1368 for (unsigned i = 0; i < attrib_count; ++i) {
1369 LLVMValueRef output[4];
1370 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1371 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1372 unsigned data_format = attrib_format & 0x0f;
1373 unsigned num_format = (attrib_format >> 4) & 0x07;
1374 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1375 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1376
1377 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1378 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1379
1380 if (divisor) {
1381 buffer_index = ctx->abi.instance_id;
1382
1383 if (divisor != 1) {
1384 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1385 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1386 }
1387 } else {
1388 buffer_index = ctx->ac.i32_0;
1389 }
1390
1391 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1392 ac_get_arg(&ctx->ac,
1393 ctx->args->ac.start_instance),\
1394 buffer_index, "");
1395 } else {
1396 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1397 ctx->abi.vertex_id,
1398 ac_get_arg(&ctx->ac,
1399 ctx->args->ac.base_vertex), "");
1400 }
1401
1402 /* Adjust the number of channels to load based on the vertex
1403 * attribute format.
1404 */
1405 unsigned num_format_channels = get_num_channels_from_data_format(data_format);
1406 unsigned num_channels = MIN2(num_input_channels, num_format_channels);
1407 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1408 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1409 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1410
1411 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1412 /* Always load, at least, 3 channels for formats that
1413 * need to be shuffled because X<->Z.
1414 */
1415 num_channels = MAX2(num_channels, 3);
1416 }
1417
1418 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1419 LLVMValueRef buffer_offset =
1420 LLVMConstInt(ctx->ac.i32,
1421 attrib_offset / attrib_stride, false);
1422
1423 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1424 buffer_index,
1425 buffer_offset, "");
1426
1427 attrib_offset = attrib_offset % attrib_stride;
1428 }
1429
1430 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1431 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1432
1433 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1434 buffer_index,
1435 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1436 ctx->ac.i32_0, ctx->ac.i32_0,
1437 num_channels,
1438 data_format, num_format, 0, true);
1439
1440 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1441 LLVMValueRef c[4];
1442 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1443 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1444 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1445 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1446
1447 input = ac_build_gather_values(&ctx->ac, c, 4);
1448 }
1449
1450 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1451 is_float);
1452
1453 for (unsigned chan = 0; chan < 4; chan++) {
1454 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1455 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1456 if (type == GLSL_TYPE_FLOAT16) {
1457 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1458 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1459 }
1460 }
1461
1462 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1463 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1464
1465 for (unsigned chan = 0; chan < 4; chan++) {
1466 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1467 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1468 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1469
1470 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1471 }
1472 }
1473 }
1474
1475 static void
1476 handle_vs_inputs(struct radv_shader_context *ctx,
1477 struct nir_shader *nir) {
1478 nir_foreach_variable(variable, &nir->inputs)
1479 handle_vs_input_decl(ctx, variable);
1480 }
1481
1482 static void
1483 prepare_interp_optimize(struct radv_shader_context *ctx,
1484 struct nir_shader *nir)
1485 {
1486 bool uses_center = false;
1487 bool uses_centroid = false;
1488 nir_foreach_variable(variable, &nir->inputs) {
1489 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1490 variable->data.sample)
1491 continue;
1492
1493 if (variable->data.centroid)
1494 uses_centroid = true;
1495 else
1496 uses_center = true;
1497 }
1498
1499 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1500 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1501
1502 if (uses_center && uses_centroid) {
1503 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1504 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1505 ctx->ac.i32_0, "");
1506 ctx->abi.persp_centroid =
1507 LLVMBuildSelect(ctx->ac.builder, sel,
1508 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1509 ctx->abi.persp_centroid, "");
1510 ctx->abi.linear_centroid =
1511 LLVMBuildSelect(ctx->ac.builder, sel,
1512 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1513 ctx->abi.linear_centroid, "");
1514 }
1515 }
1516
1517 static void
1518 scan_shader_output_decl(struct radv_shader_context *ctx,
1519 struct nir_variable *variable,
1520 struct nir_shader *shader,
1521 gl_shader_stage stage)
1522 {
1523 int idx = variable->data.location + variable->data.index;
1524 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1525 uint64_t mask_attribs;
1526
1527 variable->data.driver_location = idx * 4;
1528
1529 /* tess ctrl has it's own load/store paths for outputs */
1530 if (stage == MESA_SHADER_TESS_CTRL)
1531 return;
1532
1533 if (variable->data.compact) {
1534 unsigned component_count = variable->data.location_frac +
1535 glsl_get_length(variable->type);
1536 attrib_count = (component_count + 3) / 4;
1537 }
1538
1539 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1540
1541 ctx->output_mask |= mask_attribs;
1542 }
1543
1544
1545 /* Initialize arguments for the shader export intrinsic */
1546 static void
1547 si_llvm_init_export_args(struct radv_shader_context *ctx,
1548 LLVMValueRef *values,
1549 unsigned enabled_channels,
1550 unsigned target,
1551 struct ac_export_args *args)
1552 {
1553 /* Specify the channels that are enabled. */
1554 args->enabled_channels = enabled_channels;
1555
1556 /* Specify whether the EXEC mask represents the valid mask */
1557 args->valid_mask = 0;
1558
1559 /* Specify whether this is the last export */
1560 args->done = 0;
1561
1562 /* Specify the target we are exporting */
1563 args->target = target;
1564
1565 args->compr = false;
1566 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1567 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1568 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1569 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1570
1571 if (!values)
1572 return;
1573
1574 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1575 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1576 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1577 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1578 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1579 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1580 unsigned chan;
1581
1582 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1583 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1584 unsigned bits, bool hi) = NULL;
1585
1586 switch(col_format) {
1587 case V_028714_SPI_SHADER_ZERO:
1588 args->enabled_channels = 0; /* writemask */
1589 args->target = V_008DFC_SQ_EXP_NULL;
1590 break;
1591
1592 case V_028714_SPI_SHADER_32_R:
1593 args->enabled_channels = 1;
1594 args->out[0] = values[0];
1595 break;
1596
1597 case V_028714_SPI_SHADER_32_GR:
1598 args->enabled_channels = 0x3;
1599 args->out[0] = values[0];
1600 args->out[1] = values[1];
1601 break;
1602
1603 case V_028714_SPI_SHADER_32_AR:
1604 if (ctx->ac.chip_class >= GFX10) {
1605 args->enabled_channels = 0x3;
1606 args->out[0] = values[0];
1607 args->out[1] = values[3];
1608 } else {
1609 args->enabled_channels = 0x9;
1610 args->out[0] = values[0];
1611 args->out[3] = values[3];
1612 }
1613 break;
1614
1615 case V_028714_SPI_SHADER_FP16_ABGR:
1616 args->enabled_channels = 0x5;
1617 packf = ac_build_cvt_pkrtz_f16;
1618 if (is_16bit) {
1619 for (unsigned chan = 0; chan < 4; chan++)
1620 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1621 values[chan],
1622 ctx->ac.f32, "");
1623 }
1624 break;
1625
1626 case V_028714_SPI_SHADER_UNORM16_ABGR:
1627 args->enabled_channels = 0x5;
1628 packf = ac_build_cvt_pknorm_u16;
1629 break;
1630
1631 case V_028714_SPI_SHADER_SNORM16_ABGR:
1632 args->enabled_channels = 0x5;
1633 packf = ac_build_cvt_pknorm_i16;
1634 break;
1635
1636 case V_028714_SPI_SHADER_UINT16_ABGR:
1637 args->enabled_channels = 0x5;
1638 packi = ac_build_cvt_pk_u16;
1639 if (is_16bit) {
1640 for (unsigned chan = 0; chan < 4; chan++)
1641 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1642 ac_to_integer(&ctx->ac, values[chan]),
1643 ctx->ac.i32, "");
1644 }
1645 break;
1646
1647 case V_028714_SPI_SHADER_SINT16_ABGR:
1648 args->enabled_channels = 0x5;
1649 packi = ac_build_cvt_pk_i16;
1650 if (is_16bit) {
1651 for (unsigned chan = 0; chan < 4; chan++)
1652 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1653 ac_to_integer(&ctx->ac, values[chan]),
1654 ctx->ac.i32, "");
1655 }
1656 break;
1657
1658 default:
1659 case V_028714_SPI_SHADER_32_ABGR:
1660 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1661 break;
1662 }
1663
1664 /* Pack f16 or norm_i16/u16. */
1665 if (packf) {
1666 for (chan = 0; chan < 2; chan++) {
1667 LLVMValueRef pack_args[2] = {
1668 values[2 * chan],
1669 values[2 * chan + 1]
1670 };
1671 LLVMValueRef packed;
1672
1673 packed = packf(&ctx->ac, pack_args);
1674 args->out[chan] = ac_to_float(&ctx->ac, packed);
1675 }
1676 args->compr = 1; /* COMPR flag */
1677 }
1678
1679 /* Pack i16/u16. */
1680 if (packi) {
1681 for (chan = 0; chan < 2; chan++) {
1682 LLVMValueRef pack_args[2] = {
1683 ac_to_integer(&ctx->ac, values[2 * chan]),
1684 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1685 };
1686 LLVMValueRef packed;
1687
1688 packed = packi(&ctx->ac, pack_args,
1689 is_int8 ? 8 : is_int10 ? 10 : 16,
1690 chan == 1);
1691 args->out[chan] = ac_to_float(&ctx->ac, packed);
1692 }
1693 args->compr = 1; /* COMPR flag */
1694 }
1695 return;
1696 }
1697
1698 if (is_16bit) {
1699 for (unsigned chan = 0; chan < 4; chan++) {
1700 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1701 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1702 }
1703 } else
1704 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1705
1706 for (unsigned i = 0; i < 4; ++i)
1707 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1708 }
1709
1710 static void
1711 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1712 LLVMValueRef *values, unsigned enabled_channels)
1713 {
1714 struct ac_export_args args;
1715
1716 si_llvm_init_export_args(ctx, values, enabled_channels,
1717 V_008DFC_SQ_EXP_PARAM + index, &args);
1718 ac_build_export(&ctx->ac, &args);
1719 }
1720
1721 static LLVMValueRef
1722 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1723 {
1724 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1725 return LLVMBuildLoad(ctx->ac.builder, output, "");
1726 }
1727
1728 static void
1729 radv_emit_stream_output(struct radv_shader_context *ctx,
1730 LLVMValueRef const *so_buffers,
1731 LLVMValueRef const *so_write_offsets,
1732 const struct radv_stream_output *output,
1733 struct radv_shader_output_values *shader_out)
1734 {
1735 unsigned num_comps = util_bitcount(output->component_mask);
1736 unsigned buf = output->buffer;
1737 unsigned offset = output->offset;
1738 unsigned start;
1739 LLVMValueRef out[4];
1740
1741 assert(num_comps && num_comps <= 4);
1742 if (!num_comps || num_comps > 4)
1743 return;
1744
1745 /* Get the first component. */
1746 start = ffs(output->component_mask) - 1;
1747
1748 /* Load the output as int. */
1749 for (int i = 0; i < num_comps; i++) {
1750 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1751 }
1752
1753 /* Pack the output. */
1754 LLVMValueRef vdata = NULL;
1755
1756 switch (num_comps) {
1757 case 1: /* as i32 */
1758 vdata = out[0];
1759 break;
1760 case 2: /* as v2i32 */
1761 case 3: /* as v4i32 (aligned to 4) */
1762 out[3] = LLVMGetUndef(ctx->ac.i32);
1763 /* fall through */
1764 case 4: /* as v4i32 */
1765 vdata = ac_build_gather_values(&ctx->ac, out,
1766 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1767 util_next_power_of_two(num_comps) :
1768 num_comps);
1769 break;
1770 }
1771
1772 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1773 vdata, num_comps, so_write_offsets[buf],
1774 ctx->ac.i32_0, offset,
1775 ac_glc | ac_slc, false);
1776 }
1777
1778 static void
1779 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1780 {
1781 int i;
1782
1783 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1784 assert(ctx->args->streamout_config.used);
1785 LLVMValueRef so_vtx_count =
1786 ac_build_bfe(&ctx->ac,
1787 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1788 LLVMConstInt(ctx->ac.i32, 16, false),
1789 LLVMConstInt(ctx->ac.i32, 7, false), false);
1790
1791 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1792
1793 /* can_emit = tid < so_vtx_count; */
1794 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1795 tid, so_vtx_count, "");
1796
1797 /* Emit the streamout code conditionally. This actually avoids
1798 * out-of-bounds buffer access. The hw tells us via the SGPR
1799 * (so_vtx_count) which threads are allowed to emit streamout data.
1800 */
1801 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1802 {
1803 /* The buffer offset is computed as follows:
1804 * ByteOffset = streamout_offset[buffer_id]*4 +
1805 * (streamout_write_index + thread_id)*stride[buffer_id] +
1806 * attrib_offset
1807 */
1808 LLVMValueRef so_write_index =
1809 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1810
1811 /* Compute (streamout_write_index + thread_id). */
1812 so_write_index =
1813 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1814
1815 /* Load the descriptor and compute the write offset for each
1816 * enabled buffer.
1817 */
1818 LLVMValueRef so_write_offset[4] = {};
1819 LLVMValueRef so_buffers[4] = {};
1820 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1821
1822 for (i = 0; i < 4; i++) {
1823 uint16_t stride = ctx->args->shader_info->so.strides[i];
1824
1825 if (!stride)
1826 continue;
1827
1828 LLVMValueRef offset =
1829 LLVMConstInt(ctx->ac.i32, i, false);
1830
1831 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1832 buf_ptr, offset);
1833
1834 LLVMValueRef so_offset =
1835 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1836
1837 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1838 LLVMConstInt(ctx->ac.i32, 4, false), "");
1839
1840 so_write_offset[i] =
1841 ac_build_imad(&ctx->ac, so_write_index,
1842 LLVMConstInt(ctx->ac.i32,
1843 stride * 4, false),
1844 so_offset);
1845 }
1846
1847 /* Write streamout data. */
1848 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1849 struct radv_shader_output_values shader_out = {};
1850 struct radv_stream_output *output =
1851 &ctx->args->shader_info->so.outputs[i];
1852
1853 if (stream != output->stream)
1854 continue;
1855
1856 for (int j = 0; j < 4; j++) {
1857 shader_out.values[j] =
1858 radv_load_output(ctx, output->location, j);
1859 }
1860
1861 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1862 output, &shader_out);
1863 }
1864 }
1865 ac_build_endif(&ctx->ac, 6501);
1866 }
1867
1868 static void
1869 radv_build_param_exports(struct radv_shader_context *ctx,
1870 struct radv_shader_output_values *outputs,
1871 unsigned noutput,
1872 struct radv_vs_output_info *outinfo,
1873 bool export_clip_dists)
1874 {
1875 unsigned param_count = 0;
1876
1877 for (unsigned i = 0; i < noutput; i++) {
1878 unsigned slot_name = outputs[i].slot_name;
1879 unsigned usage_mask = outputs[i].usage_mask;
1880
1881 if (slot_name != VARYING_SLOT_LAYER &&
1882 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1883 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1884 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1885 slot_name < VARYING_SLOT_VAR0)
1886 continue;
1887
1888 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1889 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1890 continue;
1891
1892 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1893
1894 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1895 outinfo->vs_output_param_offset[slot_name] = param_count++;
1896 }
1897
1898 outinfo->param_exports = param_count;
1899 }
1900
1901 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1902 * (position and parameter data only).
1903 */
1904 static void
1905 radv_llvm_export_vs(struct radv_shader_context *ctx,
1906 struct radv_shader_output_values *outputs,
1907 unsigned noutput,
1908 struct radv_vs_output_info *outinfo,
1909 bool export_clip_dists)
1910 {
1911 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1912 struct ac_export_args pos_args[4] = {};
1913 unsigned pos_idx, index;
1914 int i;
1915
1916 /* Build position exports */
1917 for (i = 0; i < noutput; i++) {
1918 switch (outputs[i].slot_name) {
1919 case VARYING_SLOT_POS:
1920 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1921 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1922 break;
1923 case VARYING_SLOT_PSIZ:
1924 psize_value = outputs[i].values[0];
1925 break;
1926 case VARYING_SLOT_LAYER:
1927 layer_value = outputs[i].values[0];
1928 break;
1929 case VARYING_SLOT_VIEWPORT:
1930 viewport_value = outputs[i].values[0];
1931 break;
1932 case VARYING_SLOT_CLIP_DIST0:
1933 case VARYING_SLOT_CLIP_DIST1:
1934 index = 2 + outputs[i].slot_index;
1935 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1936 V_008DFC_SQ_EXP_POS + index,
1937 &pos_args[index]);
1938 break;
1939 default:
1940 break;
1941 }
1942 }
1943
1944 /* We need to add the position output manually if it's missing. */
1945 if (!pos_args[0].out[0]) {
1946 pos_args[0].enabled_channels = 0xf; /* writemask */
1947 pos_args[0].valid_mask = 0; /* EXEC mask */
1948 pos_args[0].done = 0; /* last export? */
1949 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1950 pos_args[0].compr = 0; /* COMPR flag */
1951 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1952 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1953 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1954 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1955 }
1956
1957 if (outinfo->writes_pointsize ||
1958 outinfo->writes_layer ||
1959 outinfo->writes_viewport_index) {
1960 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1961 (outinfo->writes_layer == true ? 4 : 0));
1962 pos_args[1].valid_mask = 0;
1963 pos_args[1].done = 0;
1964 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1965 pos_args[1].compr = 0;
1966 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1967 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1968 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1969 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1970
1971 if (outinfo->writes_pointsize == true)
1972 pos_args[1].out[0] = psize_value;
1973 if (outinfo->writes_layer == true)
1974 pos_args[1].out[2] = layer_value;
1975 if (outinfo->writes_viewport_index == true) {
1976 if (ctx->args->options->chip_class >= GFX9) {
1977 /* GFX9 has the layer in out.z[10:0] and the viewport
1978 * index in out.z[19:16].
1979 */
1980 LLVMValueRef v = viewport_value;
1981 v = ac_to_integer(&ctx->ac, v);
1982 v = LLVMBuildShl(ctx->ac.builder, v,
1983 LLVMConstInt(ctx->ac.i32, 16, false),
1984 "");
1985 v = LLVMBuildOr(ctx->ac.builder, v,
1986 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1987
1988 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1989 pos_args[1].enabled_channels |= 1 << 2;
1990 } else {
1991 pos_args[1].out[3] = viewport_value;
1992 pos_args[1].enabled_channels |= 1 << 3;
1993 }
1994 }
1995 }
1996
1997 for (i = 0; i < 4; i++) {
1998 if (pos_args[i].out[0])
1999 outinfo->pos_exports++;
2000 }
2001
2002 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2003 * Setting valid_mask=1 prevents it and has no other effect.
2004 */
2005 if (ctx->ac.family == CHIP_NAVI10 ||
2006 ctx->ac.family == CHIP_NAVI12 ||
2007 ctx->ac.family == CHIP_NAVI14)
2008 pos_args[0].valid_mask = 1;
2009
2010 pos_idx = 0;
2011 for (i = 0; i < 4; i++) {
2012 if (!pos_args[i].out[0])
2013 continue;
2014
2015 /* Specify the target we are exporting */
2016 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2017
2018 if (pos_idx == outinfo->pos_exports)
2019 /* Specify that this is the last export */
2020 pos_args[i].done = 1;
2021
2022 ac_build_export(&ctx->ac, &pos_args[i]);
2023 }
2024
2025 /* Build parameter exports */
2026 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2027 }
2028
2029 static void
2030 handle_vs_outputs_post(struct radv_shader_context *ctx,
2031 bool export_prim_id,
2032 bool export_clip_dists,
2033 struct radv_vs_output_info *outinfo)
2034 {
2035 struct radv_shader_output_values *outputs;
2036 unsigned noutput = 0;
2037
2038 if (ctx->args->options->key.has_multiview_view_index) {
2039 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2040 if(!*tmp_out) {
2041 for(unsigned i = 0; i < 4; ++i)
2042 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2043 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2044 }
2045
2046 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
2047 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
2048 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2049 }
2050
2051 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2052 sizeof(outinfo->vs_output_param_offset));
2053 outinfo->pos_exports = 0;
2054
2055 if (!ctx->args->options->use_ngg_streamout &&
2056 ctx->args->shader_info->so.num_outputs &&
2057 !ctx->args->is_gs_copy_shader) {
2058 /* The GS copy shader emission already emits streamout. */
2059 radv_emit_streamout(ctx, 0);
2060 }
2061
2062 /* Allocate a temporary array for the output values. */
2063 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2064 outputs = malloc(num_outputs * sizeof(outputs[0]));
2065
2066 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2067 if (!(ctx->output_mask & (1ull << i)))
2068 continue;
2069
2070 outputs[noutput].slot_name = i;
2071 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2072
2073 if (ctx->stage == MESA_SHADER_VERTEX &&
2074 !ctx->args->is_gs_copy_shader) {
2075 outputs[noutput].usage_mask =
2076 ctx->args->shader_info->vs.output_usage_mask[i];
2077 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2078 outputs[noutput].usage_mask =
2079 ctx->args->shader_info->tes.output_usage_mask[i];
2080 } else {
2081 assert(ctx->args->is_gs_copy_shader);
2082 outputs[noutput].usage_mask =
2083 ctx->args->shader_info->gs.output_usage_mask[i];
2084 }
2085
2086 for (unsigned j = 0; j < 4; j++) {
2087 outputs[noutput].values[j] =
2088 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2089 }
2090
2091 noutput++;
2092 }
2093
2094 /* Export PrimitiveID. */
2095 if (export_prim_id) {
2096 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2097 outputs[noutput].slot_index = 0;
2098 outputs[noutput].usage_mask = 0x1;
2099 outputs[noutput].values[0] =
2100 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2101 for (unsigned j = 1; j < 4; j++)
2102 outputs[noutput].values[j] = ctx->ac.f32_0;
2103 noutput++;
2104 }
2105
2106 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2107
2108 free(outputs);
2109 }
2110
2111 static void
2112 handle_es_outputs_post(struct radv_shader_context *ctx,
2113 struct radv_es_output_info *outinfo)
2114 {
2115 int j;
2116 LLVMValueRef lds_base = NULL;
2117
2118 if (ctx->ac.chip_class >= GFX9) {
2119 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2120 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2121 LLVMValueRef wave_idx =
2122 ac_unpack_param(&ctx->ac,
2123 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2124 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2125 LLVMBuildMul(ctx->ac.builder, wave_idx,
2126 LLVMConstInt(ctx->ac.i32,
2127 ctx->ac.wave_size, false), ""), "");
2128 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2129 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2130 }
2131
2132 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2133 LLVMValueRef dw_addr = NULL;
2134 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2135 unsigned output_usage_mask;
2136 int param_index;
2137
2138 if (!(ctx->output_mask & (1ull << i)))
2139 continue;
2140
2141 if (ctx->stage == MESA_SHADER_VERTEX) {
2142 output_usage_mask =
2143 ctx->args->shader_info->vs.output_usage_mask[i];
2144 } else {
2145 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2146 output_usage_mask =
2147 ctx->args->shader_info->tes.output_usage_mask[i];
2148 }
2149
2150 param_index = shader_io_get_unique_index(i);
2151
2152 if (lds_base) {
2153 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2154 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2155 "");
2156 }
2157
2158 for (j = 0; j < 4; j++) {
2159 if (!(output_usage_mask & (1 << j)))
2160 continue;
2161
2162 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2163 out_val = ac_to_integer(&ctx->ac, out_val);
2164 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2165
2166 if (ctx->ac.chip_class >= GFX9) {
2167 LLVMValueRef dw_addr_offset =
2168 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2169 LLVMConstInt(ctx->ac.i32,
2170 j, false), "");
2171
2172 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2173 } else {
2174 ac_build_buffer_store_dword(&ctx->ac,
2175 ctx->esgs_ring,
2176 out_val, 1,
2177 NULL,
2178 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2179 (4 * param_index + j) * 4,
2180 ac_glc | ac_slc, true);
2181 }
2182 }
2183 }
2184 }
2185
2186 static void
2187 handle_ls_outputs_post(struct radv_shader_context *ctx)
2188 {
2189 LLVMValueRef vertex_id = ctx->rel_auto_id;
2190 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2191 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2192 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2193 vertex_dw_stride, "");
2194
2195 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2196 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2197
2198 if (!(ctx->output_mask & (1ull << i)))
2199 continue;
2200
2201 int param = shader_io_get_unique_index(i);
2202 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2203 LLVMConstInt(ctx->ac.i32, param * 4, false),
2204 "");
2205 for (unsigned j = 0; j < 4; j++) {
2206 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2207 value = ac_to_integer(&ctx->ac, value);
2208 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2209 ac_lds_store(&ctx->ac, dw_addr, value);
2210 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2211 }
2212 }
2213 }
2214
2215 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2216 {
2217 return ac_unpack_param(&ctx->ac,
2218 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2219 }
2220
2221 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2222 {
2223 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2224 }
2225
2226 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2227 {
2228 LLVMBuilderRef builder = ctx->ac.builder;
2229 LLVMValueRef tmp;
2230 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2231 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2232 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2233 }
2234
2235 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2236 {
2237 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2238 LLVMConstInt(ctx->ac.i32, 12, false),
2239 LLVMConstInt(ctx->ac.i32, 9, false),
2240 false);
2241 }
2242
2243 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2244 {
2245 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2246 LLVMConstInt(ctx->ac.i32, 22, false),
2247 LLVMConstInt(ctx->ac.i32, 9, false),
2248 false);
2249 }
2250
2251 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2252 {
2253 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2254 ctx->ac.i32_0,
2255 LLVMConstInt(ctx->ac.i32, 11, false),
2256 false);
2257 }
2258
2259 static LLVMValueRef
2260 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2261 {
2262 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2263
2264 if (ctx->args->options->key.has_multiview_view_index)
2265 num_outputs++;
2266
2267 LLVMTypeRef elements[2] = {
2268 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2269 LLVMArrayType(ctx->ac.i8, 4),
2270 };
2271 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2272 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2273 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2274 }
2275
2276 /**
2277 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2278 * is in emit order; that is:
2279 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2280 * - during vertex emit, i.e. while the API GS shader invocation is running,
2281 * N = threadidx * gs_max_out_vertices + emitidx
2282 *
2283 * Goals of the LDS memory layout:
2284 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2285 * in uniform control flow
2286 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2287 * culling
2288 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2289 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2290 * 5. Avoid wasting memory.
2291 *
2292 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2293 * layout, elimination of bank conflicts requires that each vertex occupy an
2294 * odd number of dwords. We use the additional dword to store the output stream
2295 * index as well as a flag to indicate whether this vertex ends a primitive
2296 * for rasterization.
2297 *
2298 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2299 *
2300 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2301 * Indices are swizzled in groups of 32, which ensures point 1 without
2302 * disturbing point 2.
2303 *
2304 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2305 */
2306 static LLVMValueRef
2307 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2308 {
2309 LLVMBuilderRef builder = ctx->ac.builder;
2310 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2311
2312 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2313 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2314 if (write_stride_2exp) {
2315 LLVMValueRef row =
2316 LLVMBuildLShr(builder, vertexidx,
2317 LLVMConstInt(ctx->ac.i32, 5, false), "");
2318 LLVMValueRef swizzle =
2319 LLVMBuildAnd(builder, row,
2320 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2321 false), "");
2322 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2323 }
2324
2325 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2326 }
2327
2328 static LLVMValueRef
2329 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2330 LLVMValueRef emitidx)
2331 {
2332 LLVMBuilderRef builder = ctx->ac.builder;
2333 LLVMValueRef tmp;
2334
2335 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2336 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2337 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2338 return ngg_gs_vertex_ptr(ctx, vertexidx);
2339 }
2340
2341 /* Send GS Alloc Req message from the first wave of the group to SPI.
2342 * Message payload is:
2343 * - bits 0..10: vertices in group
2344 * - bits 12..22: primitives in group
2345 */
2346 static void build_sendmsg_gs_alloc_req(struct radv_shader_context *ctx,
2347 LLVMValueRef vtx_cnt,
2348 LLVMValueRef prim_cnt)
2349 {
2350 LLVMBuilderRef builder = ctx->ac.builder;
2351 LLVMValueRef tmp;
2352
2353 tmp = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2354 ac_build_ifcc(&ctx->ac, tmp, 5020);
2355
2356 tmp = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->ac.i32, 12, false),"");
2357 tmp = LLVMBuildOr(builder, tmp, vtx_cnt, "");
2358 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_ALLOC_REQ, tmp);
2359
2360 ac_build_endif(&ctx->ac, 5020);
2361 }
2362
2363 struct ngg_prim {
2364 unsigned num_vertices;
2365 LLVMValueRef isnull;
2366 LLVMValueRef swap;
2367 LLVMValueRef index[3];
2368 LLVMValueRef edgeflag[3];
2369 };
2370
2371 static void build_export_prim(struct radv_shader_context *ctx,
2372 const struct ngg_prim *prim)
2373 {
2374 LLVMBuilderRef builder = ctx->ac.builder;
2375 struct ac_export_args args;
2376 LLVMValueRef vertices[3];
2377 LLVMValueRef odd, even;
2378 LLVMValueRef tmp;
2379
2380 tmp = LLVMBuildZExt(builder, prim->isnull, ctx->ac.i32, "");
2381 args.out[0] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 31, false), "");
2382
2383 for (unsigned i = 0; i < prim->num_vertices; ++i) {
2384 tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
2385 tmp = LLVMBuildShl(builder, tmp,
2386 LLVMConstInt(ctx->ac.i32, 9, false), "");
2387 vertices[i] = LLVMBuildOr(builder, prim->index[i], tmp, "");
2388 }
2389
2390 switch (prim->num_vertices) {
2391 case 1:
2392 args.out[0] = LLVMBuildOr(builder, args.out[0], vertices[0], "");
2393 break;
2394 case 2:
2395 tmp = LLVMBuildShl(builder, vertices[1],
2396 LLVMConstInt(ctx->ac.i32, 10, false), "");
2397 tmp = LLVMBuildOr(builder, args.out[0], tmp, "");
2398 args.out[0] = LLVMBuildOr(builder, tmp, vertices[0], "");
2399 break;
2400 case 3:
2401 /* Swap vertices if needed to follow drawing order. */
2402 tmp = LLVMBuildShl(builder, vertices[2],
2403 LLVMConstInt(ctx->ac.i32, 20, false), "");
2404 even = LLVMBuildOr(builder, args.out[0], tmp, "");
2405 tmp = LLVMBuildShl(builder, vertices[1],
2406 LLVMConstInt(ctx->ac.i32, 10, false), "");
2407 even = LLVMBuildOr(builder, even, tmp, "");
2408 even = LLVMBuildOr(builder, even, vertices[0], "");
2409
2410 tmp = LLVMBuildShl(builder, vertices[1],
2411 LLVMConstInt(ctx->ac.i32, 20, false), "");
2412 odd = LLVMBuildOr(builder, args.out[0], tmp, "");
2413 tmp = LLVMBuildShl(builder, vertices[2],
2414 LLVMConstInt(ctx->ac.i32, 10, false), "");
2415 odd = LLVMBuildOr(builder, odd, tmp, "");
2416 odd = LLVMBuildOr(builder, odd, vertices[0], "");
2417
2418 args.out[0] = LLVMBuildSelect(builder, prim->swap, odd, even, "");
2419 break;
2420 default:
2421 unreachable("invalid number of vertices");
2422 }
2423
2424 args.out[0] = LLVMBuildBitCast(builder, args.out[0], ctx->ac.f32, "");
2425 args.out[1] = LLVMGetUndef(ctx->ac.f32);
2426 args.out[2] = LLVMGetUndef(ctx->ac.f32);
2427 args.out[3] = LLVMGetUndef(ctx->ac.f32);
2428
2429 args.target = V_008DFC_SQ_EXP_PRIM;
2430 args.enabled_channels = 1;
2431 args.done = true;
2432 args.valid_mask = false;
2433 args.compr = false;
2434
2435 ac_build_export(&ctx->ac, &args);
2436 }
2437
2438 static struct radv_stream_output *
2439 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2440 {
2441 for (unsigned i = 0; i < so->num_outputs; ++i) {
2442 if (so->outputs[i].location == location)
2443 return &so->outputs[i];
2444 }
2445
2446 return NULL;
2447 }
2448
2449 static void build_streamout_vertex(struct radv_shader_context *ctx,
2450 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2451 unsigned stream, LLVMValueRef offset_vtx,
2452 LLVMValueRef vertexptr)
2453 {
2454 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2455 LLVMBuilderRef builder = ctx->ac.builder;
2456 LLVMValueRef offset[4] = {};
2457 LLVMValueRef tmp;
2458
2459 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2460 if (!wg_offset_dw[buffer])
2461 continue;
2462
2463 tmp = LLVMBuildMul(builder, offset_vtx,
2464 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2465 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2466 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2467 }
2468
2469 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2470 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2471 unsigned noutput = 0;
2472 unsigned out_idx = 0;
2473
2474 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2475 unsigned output_usage_mask =
2476 ctx->args->shader_info->gs.output_usage_mask[i];
2477 uint8_t output_stream =
2478 output_stream = ctx->args->shader_info->gs.output_streams[i];
2479
2480 if (!(ctx->output_mask & (1ull << i)) ||
2481 output_stream != stream)
2482 continue;
2483
2484 outputs[noutput].slot_name = i;
2485 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2486 outputs[noutput].usage_mask = output_usage_mask;
2487
2488 int length = util_last_bit(output_usage_mask);
2489
2490 for (unsigned j = 0; j < length; j++, out_idx++) {
2491 if (!(output_usage_mask & (1 << j)))
2492 continue;
2493
2494 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2495 LLVMConstInt(ctx->ac.i32, out_idx, false));
2496 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2497 }
2498
2499 for (unsigned j = length; j < 4; j++)
2500 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2501
2502 noutput++;
2503 }
2504
2505 for (unsigned i = 0; i < noutput; i++) {
2506 struct radv_stream_output *output =
2507 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2508
2509 if (!output ||
2510 output->stream != stream)
2511 continue;
2512
2513 struct radv_shader_output_values out = {};
2514
2515 for (unsigned j = 0; j < 4; j++) {
2516 out.values[j] = outputs[i].values[j];
2517 }
2518
2519 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2520 }
2521 } else {
2522 for (unsigned i = 0; i < so->num_outputs; ++i) {
2523 struct radv_stream_output *output =
2524 &ctx->args->shader_info->so.outputs[i];
2525
2526 if (stream != output->stream)
2527 continue;
2528
2529 struct radv_shader_output_values out = {};
2530
2531 for (unsigned comp = 0; comp < 4; comp++) {
2532 if (!(output->component_mask & (1 << comp)))
2533 continue;
2534
2535 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2536 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2537 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2538 }
2539
2540 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2541 }
2542 }
2543 }
2544
2545 struct ngg_streamout {
2546 LLVMValueRef num_vertices;
2547
2548 /* per-thread data */
2549 LLVMValueRef prim_enable[4]; /* i1 per stream */
2550 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2551
2552 /* Output */
2553 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2554 };
2555
2556 /**
2557 * Build streamout logic.
2558 *
2559 * Implies a barrier.
2560 *
2561 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2562 *
2563 * Clobbers gs_ngg_scratch[8:].
2564 */
2565 static void build_streamout(struct radv_shader_context *ctx,
2566 struct ngg_streamout *nggso)
2567 {
2568 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2569 LLVMBuilderRef builder = ctx->ac.builder;
2570 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2571 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2572 LLVMValueRef cond, tmp, tmp2;
2573 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2574 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2575 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2576 LLVMValueRef so_buffer[4] = {};
2577 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2578 (nggso->vertices[2] ? 1 : 0);
2579 LLVMValueRef prim_stride_dw[4] = {};
2580 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2581 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2582 unsigned bufmask_for_stream[4] = {};
2583 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2584 unsigned scratch_emit_base = isgs ? 4 : 0;
2585 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2586 unsigned scratch_offset_base = isgs ? 8 : 4;
2587 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2588
2589 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2590 "amdgpu-gds-size", 256);
2591
2592 /* Determine the mapping of streamout buffers to vertex streams. */
2593 for (unsigned i = 0; i < so->num_outputs; ++i) {
2594 unsigned buf = so->outputs[i].buffer;
2595 unsigned stream = so->outputs[i].stream;
2596 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2597 stream_for_buffer[buf] = stream;
2598 bufmask_for_stream[stream] |= 1 << buf;
2599 }
2600
2601 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2602 if (stream_for_buffer[buffer] == -1)
2603 continue;
2604
2605 assert(so->strides[buffer]);
2606
2607 LLVMValueRef stride_for_buffer =
2608 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2609 prim_stride_dw[buffer] =
2610 LLVMBuildMul(builder, stride_for_buffer,
2611 nggso->num_vertices, "");
2612 prim_stride_dw_vgpr = ac_build_writelane(
2613 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2614 LLVMConstInt(ctx->ac.i32, buffer, false));
2615
2616 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2617 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2618 offset);
2619 }
2620
2621 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2622 ac_build_ifcc(&ctx->ac, cond, 5200);
2623 {
2624 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2625 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2626
2627 /* Advance the streamout offsets in GDS. */
2628 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2629 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2630
2631 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2632 ac_build_ifcc(&ctx->ac, cond, 5210);
2633 {
2634 /* Fetch the number of generated primitives and store
2635 * it in GDS for later use.
2636 */
2637 if (isgs) {
2638 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2639 tmp = LLVMBuildLoad(builder, tmp, "");
2640 } else {
2641 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2642 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2643 }
2644 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2645
2646 unsigned swizzle[4];
2647 int unused_stream = -1;
2648 for (unsigned stream = 0; stream < 4; ++stream) {
2649 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2650 unused_stream = stream;
2651 break;
2652 }
2653 }
2654 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2655 if (stream_for_buffer[buffer] >= 0) {
2656 swizzle[buffer] = stream_for_buffer[buffer];
2657 } else {
2658 assert(unused_stream >= 0);
2659 swizzle[buffer] = unused_stream;
2660 }
2661 }
2662
2663 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2664 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2665 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2666
2667 LLVMValueRef args[] = {
2668 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2669 tmp,
2670 ctx->ac.i32_0, // ordering
2671 ctx->ac.i32_0, // scope
2672 ctx->ac.i1false, // isVolatile
2673 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2674 ctx->ac.i1true, // wave release
2675 ctx->ac.i1true, // wave done
2676 };
2677
2678 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2679 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2680
2681 /* Keep offsets in a VGPR for quick retrieval via readlane by
2682 * the first wave for bounds checking, and also store in LDS
2683 * for retrieval by all waves later. */
2684 LLVMBuildStore(builder, tmp, offsets_vgpr);
2685
2686 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2687 scratch_offset_basev, "");
2688 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2689 LLVMBuildStore(builder, tmp, tmp2);
2690 }
2691 ac_build_endif(&ctx->ac, 5210);
2692
2693 /* Determine the max emit per buffer. This is done via the SALU, in part
2694 * because LLVM can't generate divide-by-multiply if we try to do this
2695 * via VALU with one lane per buffer.
2696 */
2697 LLVMValueRef max_emit[4] = {};
2698 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2699 if (stream_for_buffer[buffer] == -1)
2700 continue;
2701
2702 /* Compute the streamout buffer size in DWORD. */
2703 LLVMValueRef bufsize_dw =
2704 LLVMBuildLShr(builder,
2705 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2706 i32_2, "");
2707
2708 /* Load the streamout buffer offset from GDS. */
2709 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2710 LLVMValueRef offset_dw =
2711 ac_build_readlane(&ctx->ac, tmp,
2712 LLVMConstInt(ctx->ac.i32, buffer, false));
2713
2714 /* Compute the remaining size to emit. */
2715 LLVMValueRef remaining_dw =
2716 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2717 tmp = LLVMBuildUDiv(builder, remaining_dw,
2718 prim_stride_dw[buffer], "");
2719
2720 cond = LLVMBuildICmp(builder, LLVMIntULT,
2721 bufsize_dw, offset_dw, "");
2722 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2723 ctx->ac.i32_0, tmp, "");
2724 }
2725
2726 /* Determine the number of emitted primitives per stream and fixup the
2727 * GDS counter if necessary.
2728 *
2729 * This is complicated by the fact that a single stream can emit to
2730 * multiple buffers (but luckily not vice versa).
2731 */
2732 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2733
2734 for (unsigned stream = 0; stream < 4; ++stream) {
2735 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2736 continue;
2737
2738 /* Load the number of generated primitives from GDS and
2739 * determine that number for the given stream.
2740 */
2741 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2742 LLVMValueRef generated =
2743 ac_build_readlane(&ctx->ac, tmp,
2744 LLVMConstInt(ctx->ac.i32, stream, false));
2745
2746
2747 /* Compute the number of emitted primitives. */
2748 LLVMValueRef emit = generated;
2749 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2750 if (stream_for_buffer[buffer] == stream)
2751 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2752 }
2753
2754 /* Store the number of emitted primitives for that
2755 * stream.
2756 */
2757 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2758 LLVMConstInt(ctx->ac.i32, stream, false));
2759
2760 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2761 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2762 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2763 tmp = LLVMBuildLShr(builder,
2764 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2765 ac_get_thread_id(&ctx->ac), "");
2766 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2767 ac_build_ifcc(&ctx->ac, tmp, 5222);
2768 {
2769 tmp = LLVMBuildSub(builder, generated, emit, "");
2770 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2771 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2772 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2773 LLVMAtomicOrderingMonotonic, false);
2774 }
2775 ac_build_endif(&ctx->ac, 5222);
2776 ac_build_endif(&ctx->ac, 5221);
2777 }
2778
2779 /* Store the number of emitted primitives to LDS for later use. */
2780 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2781 ac_build_ifcc(&ctx->ac, cond, 5225);
2782 {
2783 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2784 scratch_emit_basev, "");
2785 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2786 LLVMBuildStore(builder, emit_vgpr, tmp);
2787 }
2788 ac_build_endif(&ctx->ac, 5225);
2789 }
2790 ac_build_endif(&ctx->ac, 5200);
2791
2792 /* Determine the workgroup-relative per-thread / primitive offset into
2793 * the streamout buffers */
2794 struct ac_wg_scan primemit_scan[4] = {};
2795
2796 if (isgs) {
2797 for (unsigned stream = 0; stream < 4; ++stream) {
2798 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2799 continue;
2800
2801 primemit_scan[stream].enable_exclusive = true;
2802 primemit_scan[stream].op = nir_op_iadd;
2803 primemit_scan[stream].src = nggso->prim_enable[stream];
2804 primemit_scan[stream].scratch =
2805 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2806 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2807 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2808 primemit_scan[stream].numwaves = get_tgsize(ctx);
2809 primemit_scan[stream].maxwaves = 8;
2810 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2811 }
2812 }
2813
2814 ac_build_s_barrier(&ctx->ac);
2815
2816 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2817 LLVMValueRef wgoffset_dw[4] = {};
2818
2819 {
2820 LLVMValueRef scratch_vgpr;
2821
2822 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2823 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2824
2825 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2826 if (stream_for_buffer[buffer] >= 0) {
2827 wgoffset_dw[buffer] = ac_build_readlane(
2828 &ctx->ac, scratch_vgpr,
2829 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2830 }
2831 }
2832
2833 for (unsigned stream = 0; stream < 4; ++stream) {
2834 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2835 nggso->emit[stream] = ac_build_readlane(
2836 &ctx->ac, scratch_vgpr,
2837 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2838 }
2839 }
2840 }
2841
2842 /* Write out primitive data */
2843 for (unsigned stream = 0; stream < 4; ++stream) {
2844 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2845 continue;
2846
2847 if (isgs) {
2848 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2849 } else {
2850 primemit_scan[stream].result_exclusive = tid;
2851 }
2852
2853 cond = LLVMBuildICmp(builder, LLVMIntULT,
2854 primemit_scan[stream].result_exclusive,
2855 nggso->emit[stream], "");
2856 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2857 ac_build_ifcc(&ctx->ac, cond, 5240);
2858 {
2859 LLVMValueRef offset_vtx =
2860 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2861 nggso->num_vertices, "");
2862
2863 for (unsigned i = 0; i < max_num_vertices; ++i) {
2864 cond = LLVMBuildICmp(builder, LLVMIntULT,
2865 LLVMConstInt(ctx->ac.i32, i, false),
2866 nggso->num_vertices, "");
2867 ac_build_ifcc(&ctx->ac, cond, 5241);
2868 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2869 stream, offset_vtx, nggso->vertices[i]);
2870 ac_build_endif(&ctx->ac, 5241);
2871 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2872 }
2873 }
2874 ac_build_endif(&ctx->ac, 5240);
2875 }
2876 }
2877
2878 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2879 {
2880 unsigned lds_vertex_size = 0;
2881
2882 if (ctx->args->shader_info->so.num_outputs)
2883 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2884
2885 return lds_vertex_size;
2886 }
2887
2888 /**
2889 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2890 * for the vertex outputs.
2891 */
2892 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2893 LLVMValueRef vtxid)
2894 {
2895 /* The extra dword is used to avoid LDS bank conflicts. */
2896 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2897 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2898 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2899 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2900 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2901 }
2902
2903 static void
2904 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2905 {
2906 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2907 LLVMBuilderRef builder = ctx->ac.builder;
2908 LLVMValueRef vertex_ptr = NULL;
2909 LLVMValueRef tmp, tmp2;
2910
2911 assert((ctx->stage == MESA_SHADER_VERTEX ||
2912 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2913
2914 if (!ctx->args->shader_info->so.num_outputs)
2915 return;
2916
2917 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2918
2919 for (unsigned i = 0; i < so->num_outputs; ++i) {
2920 struct radv_stream_output *output =
2921 &ctx->args->shader_info->so.outputs[i];
2922
2923 unsigned loc = output->location;
2924
2925 for (unsigned comp = 0; comp < 4; comp++) {
2926 if (!(output->component_mask & (1 << comp)))
2927 continue;
2928
2929 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2930 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2931 tmp2 = LLVMBuildLoad(builder,
2932 ctx->abi.outputs[4 * loc + comp], "");
2933 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2934 LLVMBuildStore(builder, tmp2, tmp);
2935 }
2936 }
2937 }
2938
2939 static void
2940 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2941 {
2942 LLVMBuilderRef builder = ctx->ac.builder;
2943 LLVMValueRef tmp;
2944
2945 assert((ctx->stage == MESA_SHADER_VERTEX ||
2946 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2947
2948 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2949 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2950 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2951 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2952 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2953 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2954 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2955 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2956 LLVMValueRef vtxindex[] = {
2957 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2958 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2959 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2960 };
2961
2962 /* Determine the number of vertices per primitive. */
2963 unsigned num_vertices;
2964 LLVMValueRef num_vertices_val;
2965
2966 if (ctx->stage == MESA_SHADER_VERTEX) {
2967 LLVMValueRef outprim_val =
2968 LLVMConstInt(ctx->ac.i32,
2969 ctx->args->options->key.vs.outprim, false);
2970 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2971 ctx->ac.i32_1, "");
2972 num_vertices = 3; /* TODO: optimize for points & lines */
2973 } else {
2974 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2975
2976 if (ctx->shader->info.tess.point_mode)
2977 num_vertices = 1;
2978 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2979 num_vertices = 2;
2980 else
2981 num_vertices = 3;
2982
2983 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2984 }
2985
2986 /* Streamout */
2987 if (ctx->args->shader_info->so.num_outputs) {
2988 struct ngg_streamout nggso = {};
2989
2990 nggso.num_vertices = num_vertices_val;
2991 nggso.prim_enable[0] = is_gs_thread;
2992
2993 for (unsigned i = 0; i < num_vertices; ++i)
2994 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2995
2996 build_streamout(ctx, &nggso);
2997 }
2998
2999 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3000 * to the ES thread of the provoking vertex.
3001 */
3002 if (ctx->stage == MESA_SHADER_VERTEX &&
3003 ctx->args->options->key.vs_common_out.export_prim_id) {
3004 if (ctx->args->shader_info->so.num_outputs)
3005 ac_build_s_barrier(&ctx->ac);
3006
3007 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
3008 /* Extract the PROVOKING_VTX_INDEX field. */
3009 LLVMValueRef provoking_vtx_in_prim =
3010 LLVMConstInt(ctx->ac.i32, 0, false);
3011
3012 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3013 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
3014 LLVMValueRef provoking_vtx_index =
3015 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
3016
3017 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
3018 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
3019 ac_build_endif(&ctx->ac, 5400);
3020 }
3021
3022 /* TODO: primitive culling */
3023
3024 build_sendmsg_gs_alloc_req(ctx, ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
3025
3026 /* TODO: streamout queries */
3027 /* Export primitive data to the index buffer. Format is:
3028 * - bits 0..8: index 0
3029 * - bit 9: edge flag 0
3030 * - bits 10..18: index 1
3031 * - bit 19: edge flag 1
3032 * - bits 20..28: index 2
3033 * - bit 29: edge flag 2
3034 * - bit 31: null primitive (skip)
3035 *
3036 * For the first version, we will always build up all three indices
3037 * independent of the primitive type. The additional garbage data
3038 * shouldn't hurt.
3039 *
3040 * TODO: culling depends on the primitive type, so can have some
3041 * interaction here.
3042 */
3043 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
3044 {
3045 struct ngg_prim prim = {};
3046
3047 prim.num_vertices = num_vertices;
3048 prim.isnull = ctx->ac.i1false;
3049 prim.swap = ctx->ac.i1false;
3050 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
3051
3052 for (unsigned i = 0; i < num_vertices; ++i) {
3053 tmp = LLVMBuildLShr(builder,
3054 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
3055 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
3056 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3057 }
3058
3059 build_export_prim(ctx, &prim);
3060 }
3061 ac_build_endif(&ctx->ac, 6001);
3062
3063 /* Export per-vertex data (positions and parameters). */
3064 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
3065 {
3066 struct radv_vs_output_info *outinfo =
3067 ctx->stage == MESA_SHADER_TESS_EVAL ?
3068 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
3069
3070 /* Exporting the primitive ID is handled below. */
3071 /* TODO: use the new VS export path */
3072 handle_vs_outputs_post(ctx, false,
3073 ctx->args->options->key.vs_common_out.export_clip_dists,
3074 outinfo);
3075
3076 if (ctx->args->options->key.vs_common_out.export_prim_id) {
3077 unsigned param_count = outinfo->param_exports;
3078 LLVMValueRef values[4];
3079
3080 if (ctx->stage == MESA_SHADER_VERTEX) {
3081 /* Wait for GS stores to finish. */
3082 ac_build_s_barrier(&ctx->ac);
3083
3084 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3085 get_thread_id_in_tg(ctx));
3086 values[0] = LLVMBuildLoad(builder, tmp, "");
3087 } else {
3088 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3089 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
3090 }
3091
3092 values[0] = ac_to_float(&ctx->ac, values[0]);
3093 for (unsigned j = 1; j < 4; j++)
3094 values[j] = ctx->ac.f32_0;
3095
3096 radv_export_param(ctx, param_count, values, 0x1);
3097
3098 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3099 outinfo->param_exports = param_count;
3100 }
3101 }
3102 ac_build_endif(&ctx->ac, 6002);
3103 }
3104
3105 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3106 {
3107 /* Zero out the part of LDS scratch that is used to accumulate the
3108 * per-stream generated primitive count.
3109 */
3110 LLVMBuilderRef builder = ctx->ac.builder;
3111 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3112 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3113 LLVMBasicBlockRef merge_block;
3114 LLVMValueRef cond;
3115
3116 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3117 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3118 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3119
3120 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3121 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3122 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3123
3124 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3125 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3126
3127 LLVMBuildBr(ctx->ac.builder, merge_block);
3128 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3129
3130 ac_build_s_barrier(&ctx->ac);
3131 }
3132
3133 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3134 {
3135 LLVMBuilderRef builder = ctx->ac.builder;
3136 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3137 LLVMValueRef tmp;
3138
3139 /* Zero out remaining (non-emitted) primitive flags.
3140 *
3141 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3142 * the emit threads via LDS. This is likely worse in the expected
3143 * typical case where each GS thread emits the full set of
3144 * vertices.
3145 */
3146 for (unsigned stream = 0; stream < 4; ++stream) {
3147 unsigned num_components;
3148
3149 num_components =
3150 ctx->args->shader_info->gs.num_stream_output_components[stream];
3151 if (!num_components)
3152 continue;
3153
3154 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3155
3156 ac_build_bgnloop(&ctx->ac, 5100);
3157
3158 const LLVMValueRef vertexidx =
3159 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3160 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3161 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3162 ac_build_ifcc(&ctx->ac, tmp, 5101);
3163 ac_build_break(&ctx->ac);
3164 ac_build_endif(&ctx->ac, 5101);
3165
3166 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3167 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3168
3169 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3170 LLVMValueRef gep_idx[3] = {
3171 ctx->ac.i32_0, /* implied C-style array */
3172 ctx->ac.i32_1, /* second entry of struct */
3173 LLVMConstInt(ctx->ac.i32, stream, false),
3174 };
3175 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3176 LLVMBuildStore(builder, i8_0, tmp);
3177
3178 ac_build_endloop(&ctx->ac, 5100);
3179 }
3180
3181 /* Accumulate generated primitives counts across the entire threadgroup. */
3182 for (unsigned stream = 0; stream < 4; ++stream) {
3183 unsigned num_components;
3184
3185 num_components =
3186 ctx->args->shader_info->gs.num_stream_output_components[stream];
3187 if (!num_components)
3188 continue;
3189
3190 LLVMValueRef numprims =
3191 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3192 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3193
3194 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3195 ac_build_ifcc(&ctx->ac, tmp, 5105);
3196 {
3197 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3198 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3199 LLVMConstInt(ctx->ac.i32, stream, false)),
3200 numprims, LLVMAtomicOrderingMonotonic, false);
3201 }
3202 ac_build_endif(&ctx->ac, 5105);
3203 }
3204 }
3205
3206 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3207 {
3208 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3209 LLVMBuilderRef builder = ctx->ac.builder;
3210 LLVMValueRef tmp, tmp2;
3211
3212 ac_build_s_barrier(&ctx->ac);
3213
3214 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3215 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3216
3217 /* Streamout */
3218 if (ctx->args->shader_info->so.num_outputs) {
3219 struct ngg_streamout nggso = {};
3220
3221 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3222
3223 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3224 for (unsigned stream = 0; stream < 4; ++stream) {
3225 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3226 continue;
3227
3228 LLVMValueRef gep_idx[3] = {
3229 ctx->ac.i32_0, /* implicit C-style array */
3230 ctx->ac.i32_1, /* second value of struct */
3231 LLVMConstInt(ctx->ac.i32, stream, false),
3232 };
3233 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3234 tmp = LLVMBuildLoad(builder, tmp, "");
3235 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3236 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3237 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3238 }
3239
3240 for (unsigned i = 0; i < verts_per_prim; ++i) {
3241 tmp = LLVMBuildSub(builder, tid,
3242 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3243 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3244 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3245 }
3246
3247 build_streamout(ctx, &nggso);
3248 }
3249
3250 /* TODO: culling */
3251
3252 /* Determine vertex liveness. */
3253 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3254
3255 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3256 ac_build_ifcc(&ctx->ac, tmp, 5120);
3257 {
3258 for (unsigned i = 0; i < verts_per_prim; ++i) {
3259 const LLVMValueRef primidx =
3260 LLVMBuildAdd(builder, tid,
3261 LLVMConstInt(ctx->ac.i32, i, false), "");
3262
3263 if (i > 0) {
3264 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3265 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3266 }
3267
3268 /* Load primitive liveness */
3269 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3270 LLVMValueRef gep_idx[3] = {
3271 ctx->ac.i32_0, /* implicit C-style array */
3272 ctx->ac.i32_1, /* second value of struct */
3273 ctx->ac.i32_0, /* stream 0 */
3274 };
3275 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3276 tmp = LLVMBuildLoad(builder, tmp, "");
3277 const LLVMValueRef primlive =
3278 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3279
3280 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3281 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3282 LLVMBuildStore(builder, tmp, vertliveptr);
3283
3284 if (i > 0)
3285 ac_build_endif(&ctx->ac, 5121 + i);
3286 }
3287 }
3288 ac_build_endif(&ctx->ac, 5120);
3289
3290 /* Inclusive scan addition across the current wave. */
3291 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3292 struct ac_wg_scan vertlive_scan = {};
3293 vertlive_scan.op = nir_op_iadd;
3294 vertlive_scan.enable_reduce = true;
3295 vertlive_scan.enable_exclusive = true;
3296 vertlive_scan.src = vertlive;
3297 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3298 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3299 vertlive_scan.numwaves = get_tgsize(ctx);
3300 vertlive_scan.maxwaves = 8;
3301
3302 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3303
3304 /* Skip all exports (including index exports) when possible. At least on
3305 * early gfx10 revisions this is also to avoid hangs.
3306 */
3307 LLVMValueRef have_exports =
3308 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3309 num_emit_threads =
3310 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3311
3312 /* Allocate export space. Send this message as early as possible, to
3313 * hide the latency of the SQ <-> SPI roundtrip.
3314 *
3315 * Note: We could consider compacting primitives for export as well.
3316 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3317 * prim data per clock and skips null primitives at no additional
3318 * cost. So compacting primitives can only be beneficial when
3319 * there are 4 or more contiguous null primitives in the export
3320 * (in the common case of single-dword prim exports).
3321 */
3322 build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
3323
3324 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3325 * of the primitive liveness flags, relying on the fact that each
3326 * threadgroup can have at most 256 threads. */
3327 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3328 {
3329 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3330 LLVMValueRef gep_idx[3] = {
3331 ctx->ac.i32_0, /* implicit C-style array */
3332 ctx->ac.i32_1, /* second value of struct */
3333 ctx->ac.i32_1, /* stream 1 */
3334 };
3335 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3336 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3337 LLVMBuildStore(builder, tmp2, tmp);
3338 }
3339 ac_build_endif(&ctx->ac, 5130);
3340
3341 ac_build_s_barrier(&ctx->ac);
3342
3343 /* Export primitive data */
3344 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3345 ac_build_ifcc(&ctx->ac, tmp, 5140);
3346 {
3347 struct ngg_prim prim = {};
3348 prim.num_vertices = verts_per_prim;
3349
3350 tmp = ngg_gs_vertex_ptr(ctx, tid);
3351 LLVMValueRef gep_idx[3] = {
3352 ctx->ac.i32_0, /* implicit C-style array */
3353 ctx->ac.i32_1, /* second value of struct */
3354 ctx->ac.i32_0, /* primflag */
3355 };
3356 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3357 tmp = LLVMBuildLoad(builder, tmp, "");
3358 prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
3359 LLVMConstInt(ctx->ac.i8, 0, false), "");
3360 prim.swap = LLVMBuildICmp(builder, LLVMIntEQ,
3361 LLVMBuildAnd(builder, tid, LLVMConstInt(ctx->ac.i32, 1, false), ""),
3362 LLVMConstInt(ctx->ac.i32, 1, false), "");
3363
3364 for (unsigned i = 0; i < verts_per_prim; ++i) {
3365 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3366 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3367 prim.edgeflag[i] = ctx->ac.i1false;
3368 }
3369
3370 build_export_prim(ctx, &prim);
3371 }
3372 ac_build_endif(&ctx->ac, 5140);
3373
3374 /* Export position and parameter data */
3375 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3376 ac_build_ifcc(&ctx->ac, tmp, 5145);
3377 {
3378 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3379 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3380 struct radv_shader_output_values *outputs;
3381 unsigned noutput = 0;
3382
3383 /* Allocate a temporary array for the output values. */
3384 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3385 outputs = calloc(num_outputs, sizeof(outputs[0]));
3386
3387 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3388 sizeof(outinfo->vs_output_param_offset));
3389 outinfo->pos_exports = 0;
3390
3391 tmp = ngg_gs_vertex_ptr(ctx, tid);
3392 LLVMValueRef gep_idx[3] = {
3393 ctx->ac.i32_0, /* implicit C-style array */
3394 ctx->ac.i32_1, /* second value of struct */
3395 ctx->ac.i32_1, /* stream 1: source data index */
3396 };
3397 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3398 tmp = LLVMBuildLoad(builder, tmp, "");
3399 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3400 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3401
3402 unsigned out_idx = 0;
3403 gep_idx[1] = ctx->ac.i32_0;
3404 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3405 unsigned output_usage_mask =
3406 ctx->args->shader_info->gs.output_usage_mask[i];
3407 int length = util_last_bit(output_usage_mask);
3408
3409 if (!(ctx->output_mask & (1ull << i)))
3410 continue;
3411
3412 outputs[noutput].slot_name = i;
3413 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3414 outputs[noutput].usage_mask = output_usage_mask;
3415
3416 for (unsigned j = 0; j < length; j++, out_idx++) {
3417 if (!(output_usage_mask & (1 << j)))
3418 continue;
3419
3420 gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
3421 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3422 tmp = LLVMBuildLoad(builder, tmp, "");
3423
3424 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3425 if (ac_get_type_size(type) == 2) {
3426 tmp = ac_to_integer(&ctx->ac, tmp);
3427 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3428 }
3429
3430 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3431 }
3432
3433 for (unsigned j = length; j < 4; j++)
3434 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3435
3436 noutput++;
3437 }
3438
3439 /* Export ViewIndex. */
3440 if (export_view_index) {
3441 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3442 outputs[noutput].slot_index = 0;
3443 outputs[noutput].usage_mask = 0x1;
3444 outputs[noutput].values[0] =
3445 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3446 for (unsigned j = 1; j < 4; j++)
3447 outputs[noutput].values[j] = ctx->ac.f32_0;
3448 noutput++;
3449 }
3450
3451 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3452 ctx->args->options->key.vs_common_out.export_clip_dists);
3453 FREE(outputs);
3454 }
3455 ac_build_endif(&ctx->ac, 5145);
3456 }
3457
3458 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3459 unsigned stream,
3460 LLVMValueRef *addrs)
3461 {
3462 LLVMBuilderRef builder = ctx->ac.builder;
3463 LLVMValueRef tmp;
3464 const LLVMValueRef vertexidx =
3465 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3466
3467 /* If this thread has already emitted the declared maximum number of
3468 * vertices, skip the write: excessive vertex emissions are not
3469 * supposed to have any effect.
3470 */
3471 const LLVMValueRef can_emit =
3472 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3473 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3474 ac_build_ifcc(&ctx->ac, can_emit, 9001);
3475
3476 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3477 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3478 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3479
3480 const LLVMValueRef vertexptr =
3481 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3482 unsigned out_idx = 0;
3483 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3484 unsigned output_usage_mask =
3485 ctx->args->shader_info->gs.output_usage_mask[i];
3486 uint8_t output_stream =
3487 ctx->args->shader_info->gs.output_streams[i];
3488 LLVMValueRef *out_ptr = &addrs[i * 4];
3489 int length = util_last_bit(output_usage_mask);
3490
3491 if (!(ctx->output_mask & (1ull << i)) ||
3492 output_stream != stream)
3493 continue;
3494
3495 for (unsigned j = 0; j < length; j++, out_idx++) {
3496 if (!(output_usage_mask & (1 << j)))
3497 continue;
3498
3499 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3500 out_ptr[j], "");
3501 LLVMValueRef gep_idx[3] = {
3502 ctx->ac.i32_0, /* implied C-style array */
3503 ctx->ac.i32_0, /* first entry of struct */
3504 LLVMConstInt(ctx->ac.i32, out_idx, false),
3505 };
3506 LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3507
3508 out_val = ac_to_integer(&ctx->ac, out_val);
3509 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3510
3511 LLVMBuildStore(builder, out_val, ptr);
3512 }
3513 }
3514 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3515
3516 /* Determine and store whether this vertex completed a primitive. */
3517 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3518
3519 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3520 const LLVMValueRef iscompleteprim =
3521 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3522
3523 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3524 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3525
3526 LLVMValueRef gep_idx[3] = {
3527 ctx->ac.i32_0, /* implied C-style array */
3528 ctx->ac.i32_1, /* second struct entry */
3529 LLVMConstInt(ctx->ac.i32, stream, false),
3530 };
3531 const LLVMValueRef primflagptr =
3532 LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3533
3534 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3535 LLVMBuildStore(builder, tmp, primflagptr);
3536
3537 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3538 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3539 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3540
3541 ac_build_endif(&ctx->ac, 9001);
3542 }
3543
3544 static void
3545 write_tess_factors(struct radv_shader_context *ctx)
3546 {
3547 unsigned stride, outer_comps, inner_comps;
3548 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3549 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3550 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3551 unsigned tess_inner_index = 0, tess_outer_index;
3552 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3553 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3554 int i;
3555 ac_emit_barrier(&ctx->ac, ctx->stage);
3556
3557 switch (ctx->args->options->key.tcs.primitive_mode) {
3558 case GL_ISOLINES:
3559 stride = 2;
3560 outer_comps = 2;
3561 inner_comps = 0;
3562 break;
3563 case GL_TRIANGLES:
3564 stride = 4;
3565 outer_comps = 3;
3566 inner_comps = 1;
3567 break;
3568 case GL_QUADS:
3569 stride = 6;
3570 outer_comps = 4;
3571 inner_comps = 2;
3572 break;
3573 default:
3574 return;
3575 }
3576
3577 ac_build_ifcc(&ctx->ac,
3578 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3579 invocation_id, ctx->ac.i32_0, ""), 6503);
3580
3581 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3582
3583 if (inner_comps) {
3584 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3585 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3586 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3587 }
3588
3589 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3590 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3591 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3592
3593 for (i = 0; i < 4; i++) {
3594 inner[i] = LLVMGetUndef(ctx->ac.i32);
3595 outer[i] = LLVMGetUndef(ctx->ac.i32);
3596 }
3597
3598 // LINES reversal
3599 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3600 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3601 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3602 ctx->ac.i32_1, "");
3603 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3604 } else {
3605 for (i = 0; i < outer_comps; i++) {
3606 outer[i] = out[i] =
3607 ac_lds_load(&ctx->ac, lds_outer);
3608 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3609 ctx->ac.i32_1, "");
3610 }
3611 for (i = 0; i < inner_comps; i++) {
3612 inner[i] = out[outer_comps+i] =
3613 ac_lds_load(&ctx->ac, lds_inner);
3614 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3615 ctx->ac.i32_1, "");
3616 }
3617 }
3618
3619 /* Convert the outputs to vectors for stores. */
3620 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3621 vec1 = NULL;
3622
3623 if (stride > 4)
3624 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3625
3626
3627 buffer = ctx->hs_ring_tess_factor;
3628 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3629 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3630 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3631 unsigned tf_offset = 0;
3632
3633 if (ctx->ac.chip_class <= GFX8) {
3634 ac_build_ifcc(&ctx->ac,
3635 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3636 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3637
3638 /* Store the dynamic HS control word. */
3639 ac_build_buffer_store_dword(&ctx->ac, buffer,
3640 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3641 1, ctx->ac.i32_0, tf_base,
3642 0, ac_glc, false);
3643 tf_offset += 4;
3644
3645 ac_build_endif(&ctx->ac, 6504);
3646 }
3647
3648 /* Store the tessellation factors. */
3649 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3650 MIN2(stride, 4), byteoffset, tf_base,
3651 tf_offset, ac_glc, false);
3652 if (vec1)
3653 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3654 stride - 4, byteoffset, tf_base,
3655 16 + tf_offset, ac_glc, false);
3656
3657 //store to offchip for TES to read - only if TES reads them
3658 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3659 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3660 LLVMValueRef tf_inner_offset;
3661 unsigned param_outer, param_inner;
3662
3663 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3664 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3665 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3666
3667 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3668 util_next_power_of_two(outer_comps));
3669
3670 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3671 outer_comps, tf_outer_offset,
3672 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3673 0, ac_glc, false);
3674 if (inner_comps) {
3675 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3676 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3677 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3678
3679 inner_vec = inner_comps == 1 ? inner[0] :
3680 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3681 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3682 inner_comps, tf_inner_offset,
3683 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3684 0, ac_glc, false);
3685 }
3686 }
3687
3688 ac_build_endif(&ctx->ac, 6503);
3689 }
3690
3691 static void
3692 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3693 {
3694 write_tess_factors(ctx);
3695 }
3696
3697 static bool
3698 si_export_mrt_color(struct radv_shader_context *ctx,
3699 LLVMValueRef *color, unsigned index,
3700 struct ac_export_args *args)
3701 {
3702 /* Export */
3703 si_llvm_init_export_args(ctx, color, 0xf,
3704 V_008DFC_SQ_EXP_MRT + index, args);
3705 if (!args->enabled_channels)
3706 return false; /* unnecessary NULL export */
3707
3708 return true;
3709 }
3710
3711 static void
3712 radv_export_mrt_z(struct radv_shader_context *ctx,
3713 LLVMValueRef depth, LLVMValueRef stencil,
3714 LLVMValueRef samplemask)
3715 {
3716 struct ac_export_args args;
3717
3718 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3719
3720 ac_build_export(&ctx->ac, &args);
3721 }
3722
3723 static void
3724 handle_fs_outputs_post(struct radv_shader_context *ctx)
3725 {
3726 unsigned index = 0;
3727 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3728 struct ac_export_args color_args[8];
3729
3730 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3731 LLVMValueRef values[4];
3732
3733 if (!(ctx->output_mask & (1ull << i)))
3734 continue;
3735
3736 if (i < FRAG_RESULT_DATA0)
3737 continue;
3738
3739 for (unsigned j = 0; j < 4; j++)
3740 values[j] = ac_to_float(&ctx->ac,
3741 radv_load_output(ctx, i, j));
3742
3743 bool ret = si_export_mrt_color(ctx, values,
3744 i - FRAG_RESULT_DATA0,
3745 &color_args[index]);
3746 if (ret)
3747 index++;
3748 }
3749
3750 /* Process depth, stencil, samplemask. */
3751 if (ctx->args->shader_info->ps.writes_z) {
3752 depth = ac_to_float(&ctx->ac,
3753 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3754 }
3755 if (ctx->args->shader_info->ps.writes_stencil) {
3756 stencil = ac_to_float(&ctx->ac,
3757 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3758 }
3759 if (ctx->args->shader_info->ps.writes_sample_mask) {
3760 samplemask = ac_to_float(&ctx->ac,
3761 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3762 }
3763
3764 /* Set the DONE bit on last non-null color export only if Z isn't
3765 * exported.
3766 */
3767 if (index > 0 &&
3768 !ctx->args->shader_info->ps.writes_z &&
3769 !ctx->args->shader_info->ps.writes_stencil &&
3770 !ctx->args->shader_info->ps.writes_sample_mask) {
3771 unsigned last = index - 1;
3772
3773 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3774 color_args[last].done = 1; /* DONE bit */
3775 }
3776
3777 /* Export PS outputs. */
3778 for (unsigned i = 0; i < index; i++)
3779 ac_build_export(&ctx->ac, &color_args[i]);
3780
3781 if (depth || stencil || samplemask)
3782 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3783 else if (!index)
3784 ac_build_export_null(&ctx->ac);
3785 }
3786
3787 static void
3788 emit_gs_epilogue(struct radv_shader_context *ctx)
3789 {
3790 if (ctx->args->options->key.vs_common_out.as_ngg) {
3791 gfx10_ngg_gs_emit_epilogue_1(ctx);
3792 return;
3793 }
3794
3795 if (ctx->ac.chip_class >= GFX10)
3796 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3797
3798 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3799 }
3800
3801 static void
3802 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3803 LLVMValueRef *addrs)
3804 {
3805 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3806
3807 switch (ctx->stage) {
3808 case MESA_SHADER_VERTEX:
3809 if (ctx->args->options->key.vs_common_out.as_ls)
3810 handle_ls_outputs_post(ctx);
3811 else if (ctx->args->options->key.vs_common_out.as_es)
3812 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3813 else if (ctx->args->options->key.vs_common_out.as_ngg)
3814 handle_ngg_outputs_post_1(ctx);
3815 else
3816 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3817 ctx->args->options->key.vs_common_out.export_clip_dists,
3818 &ctx->args->shader_info->vs.outinfo);
3819 break;
3820 case MESA_SHADER_FRAGMENT:
3821 handle_fs_outputs_post(ctx);
3822 break;
3823 case MESA_SHADER_GEOMETRY:
3824 emit_gs_epilogue(ctx);
3825 break;
3826 case MESA_SHADER_TESS_CTRL:
3827 handle_tcs_outputs_post(ctx);
3828 break;
3829 case MESA_SHADER_TESS_EVAL:
3830 if (ctx->args->options->key.vs_common_out.as_es)
3831 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3832 else if (ctx->args->options->key.vs_common_out.as_ngg)
3833 handle_ngg_outputs_post_1(ctx);
3834 else
3835 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3836 ctx->args->options->key.vs_common_out.export_clip_dists,
3837 &ctx->args->shader_info->tes.outinfo);
3838 break;
3839 default:
3840 break;
3841 }
3842 }
3843
3844 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3845 LLVMPassManagerRef passmgr,
3846 const struct radv_nir_compiler_options *options)
3847 {
3848 LLVMRunPassManager(passmgr, ctx->ac.module);
3849 LLVMDisposeBuilder(ctx->ac.builder);
3850
3851 ac_llvm_context_dispose(&ctx->ac);
3852 }
3853
3854 static void
3855 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3856 {
3857 struct radv_vs_output_info *outinfo;
3858
3859 switch (ctx->stage) {
3860 case MESA_SHADER_FRAGMENT:
3861 case MESA_SHADER_COMPUTE:
3862 case MESA_SHADER_TESS_CTRL:
3863 case MESA_SHADER_GEOMETRY:
3864 return;
3865 case MESA_SHADER_VERTEX:
3866 if (ctx->args->options->key.vs_common_out.as_ls ||
3867 ctx->args->options->key.vs_common_out.as_es)
3868 return;
3869 outinfo = &ctx->args->shader_info->vs.outinfo;
3870 break;
3871 case MESA_SHADER_TESS_EVAL:
3872 if (ctx->args->options->key.vs_common_out.as_es)
3873 return;
3874 outinfo = &ctx->args->shader_info->tes.outinfo;
3875 break;
3876 default:
3877 unreachable("Unhandled shader type");
3878 }
3879
3880 ac_optimize_vs_outputs(&ctx->ac,
3881 ctx->main_function,
3882 outinfo->vs_output_param_offset,
3883 VARYING_SLOT_MAX,
3884 &outinfo->param_exports);
3885 }
3886
3887 static void
3888 ac_setup_rings(struct radv_shader_context *ctx)
3889 {
3890 if (ctx->args->options->chip_class <= GFX8 &&
3891 (ctx->stage == MESA_SHADER_GEOMETRY ||
3892 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3893 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3894 : RING_ESGS_VS;
3895 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3896
3897 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3898 ctx->ring_offsets,
3899 offset);
3900 }
3901
3902 if (ctx->args->is_gs_copy_shader) {
3903 ctx->gsvs_ring[0] =
3904 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3905 LLVMConstInt(ctx->ac.i32,
3906 RING_GSVS_VS, false));
3907 }
3908
3909 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3910 /* The conceptual layout of the GSVS ring is
3911 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3912 * but the real memory layout is swizzled across
3913 * threads:
3914 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3915 * t16v0c0 ..
3916 * Override the buffer descriptor accordingly.
3917 */
3918 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3919 uint64_t stream_offset = 0;
3920 unsigned num_records = ctx->ac.wave_size;
3921 LLVMValueRef base_ring;
3922
3923 base_ring =
3924 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3925 LLVMConstInt(ctx->ac.i32,
3926 RING_GSVS_GS, false));
3927
3928 for (unsigned stream = 0; stream < 4; stream++) {
3929 unsigned num_components, stride;
3930 LLVMValueRef ring, tmp;
3931
3932 num_components =
3933 ctx->args->shader_info->gs.num_stream_output_components[stream];
3934
3935 if (!num_components)
3936 continue;
3937
3938 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3939
3940 /* Limit on the stride field for <= GFX7. */
3941 assert(stride < (1 << 14));
3942
3943 ring = LLVMBuildBitCast(ctx->ac.builder,
3944 base_ring, v2i64, "");
3945 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3946 ring, ctx->ac.i32_0, "");
3947 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3948 LLVMConstInt(ctx->ac.i64,
3949 stream_offset, 0), "");
3950 ring = LLVMBuildInsertElement(ctx->ac.builder,
3951 ring, tmp, ctx->ac.i32_0, "");
3952
3953 stream_offset += stride * ctx->ac.wave_size;
3954
3955 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3956 ctx->ac.v4i32, "");
3957
3958 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3959 ctx->ac.i32_1, "");
3960 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3961 LLVMConstInt(ctx->ac.i32,
3962 S_008F04_STRIDE(stride), false), "");
3963 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3964 ctx->ac.i32_1, "");
3965
3966 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3967 LLVMConstInt(ctx->ac.i32,
3968 num_records, false),
3969 LLVMConstInt(ctx->ac.i32, 2, false), "");
3970
3971 ctx->gsvs_ring[stream] = ring;
3972 }
3973 }
3974
3975 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3976 ctx->stage == MESA_SHADER_TESS_EVAL) {
3977 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3978 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3979 }
3980 }
3981
3982 unsigned
3983 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3984 gl_shader_stage stage,
3985 const struct nir_shader *nir)
3986 {
3987 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3988 unsigned sizes[3];
3989 for (unsigned i = 0; i < 3; i++)
3990 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3991 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3992 }
3993
3994 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3995 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3996 {
3997 LLVMValueRef count =
3998 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3999 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
4000 ctx->ac.i32_0, "");
4001 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
4002 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
4003 ctx->abi.instance_id, "");
4004 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
4005 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
4006 ctx->rel_auto_id,
4007 "");
4008 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
4009 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
4010 ctx->abi.vertex_id, "");
4011 }
4012
4013 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
4014 {
4015 if (merged) {
4016 for(int i = 5; i >= 0; --i) {
4017 ctx->gs_vtx_offset[i] =
4018 ac_unpack_param(&ctx->ac,
4019 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
4020 (i & 1) * 16, 16);
4021 }
4022
4023 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
4024 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
4025 16, 8);
4026 } else {
4027 for (int i = 0; i < 6; i++)
4028 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
4029 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
4030 }
4031 }
4032
4033 /* Ensure that the esgs ring is declared.
4034 *
4035 * We declare it with 64KB alignment as a hint that the
4036 * pointer value will always be 0.
4037 */
4038 static void declare_esgs_ring(struct radv_shader_context *ctx)
4039 {
4040 if (ctx->esgs_ring)
4041 return;
4042
4043 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
4044
4045 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4046 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
4047 "esgs_ring",
4048 AC_ADDR_SPACE_LDS);
4049 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
4050 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4051 }
4052
4053 static
4054 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
4055 struct nir_shader *const *shaders,
4056 int shader_count,
4057 const struct radv_shader_args *args)
4058 {
4059 struct radv_shader_context ctx = {0};
4060 ctx.args = args;
4061
4062 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
4063
4064 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
4065 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
4066 }
4067
4068 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4069 args->options->family, float_mode,
4070 args->shader_info->wave_size, 64);
4071 ctx.context = ctx.ac.context;
4072
4073 ctx.max_workgroup_size = 0;
4074 for (int i = 0; i < shader_count; ++i) {
4075 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4076 radv_nir_get_max_workgroup_size(args->options->chip_class,
4077 shaders[i]->info.stage,
4078 shaders[i]));
4079 }
4080
4081 if (ctx.ac.chip_class >= GFX10) {
4082 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4083 args->options->key.vs_common_out.as_ngg) {
4084 ctx.max_workgroup_size = 128;
4085 }
4086 }
4087
4088 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
4089
4090 ctx.abi.inputs = &ctx.inputs[0];
4091 ctx.abi.emit_outputs = handle_shader_outputs_post;
4092 ctx.abi.emit_vertex = visit_emit_vertex;
4093 ctx.abi.load_ubo = radv_load_ubo;
4094 ctx.abi.load_ssbo = radv_load_ssbo;
4095 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4096 ctx.abi.load_resource = radv_load_resource;
4097 ctx.abi.clamp_shadow_reference = false;
4098 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
4099
4100 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
4101 if (shader_count >= 2 || is_ngg)
4102 ac_init_exec_full_mask(&ctx.ac);
4103
4104 if (args->ac.vertex_id.used)
4105 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
4106 if (args->rel_auto_id.used)
4107 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
4108 if (args->ac.instance_id.used)
4109 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
4110
4111 if (args->options->has_ls_vgpr_init_bug &&
4112 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4113 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4114
4115 if (is_ngg) {
4116 /* Declare scratch space base for streamout and vertex
4117 * compaction. Whether space is actually allocated is
4118 * determined during linking / PM4 creation.
4119 *
4120 * Add an extra dword per vertex to ensure an odd stride, which
4121 * avoids bank conflicts for SoA accesses.
4122 */
4123 declare_esgs_ring(&ctx);
4124
4125 /* This is really only needed when streamout and / or vertex
4126 * compaction is enabled.
4127 */
4128 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
4129 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4130 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4131 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
4132 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4133 }
4134
4135 for(int i = 0; i < shader_count; ++i) {
4136 ctx.stage = shaders[i]->info.stage;
4137 ctx.shader = shaders[i];
4138 ctx.output_mask = 0;
4139
4140 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4141 for (int i = 0; i < 4; i++) {
4142 ctx.gs_next_vertex[i] =
4143 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4144 }
4145 if (args->options->key.vs_common_out.as_ngg) {
4146 for (unsigned i = 0; i < 4; ++i) {
4147 ctx.gs_curprim_verts[i] =
4148 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4149 ctx.gs_generated_prims[i] =
4150 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4151 }
4152
4153 unsigned scratch_size = 8;
4154 if (args->shader_info->so.num_outputs)
4155 scratch_size = 44;
4156
4157 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4158 ctx.gs_ngg_scratch =
4159 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4160 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4161 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4162 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4163
4164 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4165 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4166 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4167 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4168 }
4169
4170 ctx.abi.load_inputs = load_gs_input;
4171 ctx.abi.emit_primitive = visit_end_primitive;
4172 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4173 ctx.abi.load_tess_varyings = load_tcs_varyings;
4174 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4175 ctx.abi.store_tcs_outputs = store_tcs_output;
4176 if (shader_count == 1)
4177 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4178 else
4179 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4180 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4181 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4182 ctx.abi.load_tess_varyings = load_tes_input;
4183 ctx.abi.load_tess_coord = load_tess_coord;
4184 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4185 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4186 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4187 ctx.abi.load_base_vertex = radv_load_base_vertex;
4188 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4189 ctx.abi.load_sample_position = load_sample_position;
4190 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4191 ctx.abi.emit_kill = radv_emit_kill;
4192 }
4193
4194 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4195 args->options->key.vs_common_out.as_ngg &&
4196 args->options->key.vs_common_out.export_prim_id) {
4197 declare_esgs_ring(&ctx);
4198 }
4199
4200 bool nested_barrier = false;
4201
4202 if (i) {
4203 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4204 args->options->key.vs_common_out.as_ngg) {
4205 gfx10_ngg_gs_emit_prologue(&ctx);
4206 nested_barrier = false;
4207 } else {
4208 nested_barrier = true;
4209 }
4210 }
4211
4212 if (nested_barrier) {
4213 /* Execute a barrier before the second shader in
4214 * a merged shader.
4215 *
4216 * Execute the barrier inside the conditional block,
4217 * so that empty waves can jump directly to s_endpgm,
4218 * which will also signal the barrier.
4219 *
4220 * This is possible in gfx9, because an empty wave
4221 * for the second shader does not participate in
4222 * the epilogue. With NGG, empty waves may still
4223 * be required to export data (e.g. GS output vertices),
4224 * so we cannot let them exit early.
4225 *
4226 * If the shader is TCS and the TCS epilog is present
4227 * and contains a barrier, it will wait there and then
4228 * reach s_endpgm.
4229 */
4230 ac_emit_barrier(&ctx.ac, ctx.stage);
4231 }
4232
4233 nir_foreach_variable(variable, &shaders[i]->outputs)
4234 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4235
4236 ac_setup_rings(&ctx);
4237
4238 LLVMBasicBlockRef merge_block;
4239 if (shader_count >= 2 || is_ngg) {
4240 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4241 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4242 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4243
4244 LLVMValueRef count =
4245 ac_unpack_param(&ctx.ac,
4246 ac_get_arg(&ctx.ac, args->merged_wave_info),
4247 8 * i, 8);
4248 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4249 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4250 thread_id, count, "");
4251 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4252
4253 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4254 }
4255
4256 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4257 prepare_interp_optimize(&ctx, shaders[i]);
4258 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4259 handle_vs_inputs(&ctx, shaders[i]);
4260 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4261 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4262
4263 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4264
4265 if (shader_count >= 2 || is_ngg) {
4266 LLVMBuildBr(ctx.ac.builder, merge_block);
4267 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4268 }
4269
4270 /* This needs to be outside the if wrapping the shader body, as sometimes
4271 * the HW generates waves with 0 es/vs threads. */
4272 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4273 args->options->key.vs_common_out.as_ngg &&
4274 i == shader_count - 1) {
4275 handle_ngg_outputs_post_2(&ctx);
4276 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4277 args->options->key.vs_common_out.as_ngg) {
4278 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4279 }
4280
4281 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4282 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4283 args->shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4284 }
4285 }
4286
4287 LLVMBuildRetVoid(ctx.ac.builder);
4288
4289 if (args->options->dump_preoptir) {
4290 fprintf(stderr, "%s LLVM IR:\n\n",
4291 radv_get_shader_name(args->shader_info,
4292 shaders[shader_count - 1]->info.stage));
4293 ac_dump_module(ctx.ac.module);
4294 fprintf(stderr, "\n");
4295 }
4296
4297 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4298
4299 if (shader_count == 1)
4300 ac_nir_eliminate_const_vs_outputs(&ctx);
4301
4302 if (args->options->dump_shader) {
4303 args->shader_info->private_mem_vgprs =
4304 ac_count_scratch_private_memory(ctx.main_function);
4305 }
4306
4307 return ctx.ac.module;
4308 }
4309
4310 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4311 {
4312 unsigned *retval = (unsigned *)context;
4313 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4314 char *description = LLVMGetDiagInfoDescription(di);
4315
4316 if (severity == LLVMDSError) {
4317 *retval = 1;
4318 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4319 description);
4320 }
4321
4322 LLVMDisposeMessage(description);
4323 }
4324
4325 static unsigned radv_llvm_compile(LLVMModuleRef M,
4326 char **pelf_buffer, size_t *pelf_size,
4327 struct ac_llvm_compiler *ac_llvm)
4328 {
4329 unsigned retval = 0;
4330 LLVMContextRef llvm_ctx;
4331
4332 /* Setup Diagnostic Handler*/
4333 llvm_ctx = LLVMGetModuleContext(M);
4334
4335 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4336 &retval);
4337
4338 /* Compile IR*/
4339 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4340 retval = 1;
4341 return retval;
4342 }
4343
4344 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4345 LLVMModuleRef llvm_module,
4346 struct radv_shader_binary **rbinary,
4347 gl_shader_stage stage,
4348 const char *name,
4349 const struct radv_nir_compiler_options *options)
4350 {
4351 char *elf_buffer = NULL;
4352 size_t elf_size = 0;
4353 char *llvm_ir_string = NULL;
4354
4355 if (options->dump_shader) {
4356 fprintf(stderr, "%s LLVM IR:\n\n", name);
4357 ac_dump_module(llvm_module);
4358 fprintf(stderr, "\n");
4359 }
4360
4361 if (options->record_ir) {
4362 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4363 llvm_ir_string = strdup(llvm_ir);
4364 LLVMDisposeMessage(llvm_ir);
4365 }
4366
4367 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4368 if (v) {
4369 fprintf(stderr, "compile failed\n");
4370 }
4371
4372 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4373 LLVMDisposeModule(llvm_module);
4374 LLVMContextDispose(ctx);
4375
4376 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4377 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4378 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4379 memcpy(rbin->data, elf_buffer, elf_size);
4380 if (llvm_ir_string)
4381 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4382
4383 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4384 rbin->base.stage = stage;
4385 rbin->base.total_size = alloc_size;
4386 rbin->elf_size = elf_size;
4387 rbin->llvm_ir_size = llvm_ir_size;
4388 *rbinary = &rbin->base;
4389
4390 free(llvm_ir_string);
4391 free(elf_buffer);
4392 }
4393
4394 void
4395 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4396 struct radv_shader_binary **rbinary,
4397 const struct radv_shader_args *args,
4398 struct nir_shader *const *nir,
4399 int nir_count)
4400 {
4401
4402 LLVMModuleRef llvm_module;
4403
4404 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4405
4406 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4407 nir[nir_count - 1]->info.stage,
4408 radv_get_shader_name(args->shader_info,
4409 nir[nir_count - 1]->info.stage),
4410 args->options);
4411
4412 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4413 if (args->options->chip_class >= GFX9) {
4414 if (nir_count == 2 &&
4415 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4416 args->shader_info->gs.es_type = nir[0]->info.stage;
4417 }
4418 }
4419 }
4420
4421 static void
4422 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4423 {
4424 LLVMValueRef vtx_offset =
4425 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4426 LLVMConstInt(ctx->ac.i32, 4, false), "");
4427 LLVMValueRef stream_id;
4428
4429 /* Fetch the vertex stream ID. */
4430 if (!ctx->args->options->use_ngg_streamout &&
4431 ctx->args->shader_info->so.num_outputs) {
4432 stream_id =
4433 ac_unpack_param(&ctx->ac,
4434 ac_get_arg(&ctx->ac,
4435 ctx->args->streamout_config),
4436 24, 2);
4437 } else {
4438 stream_id = ctx->ac.i32_0;
4439 }
4440
4441 LLVMBasicBlockRef end_bb;
4442 LLVMValueRef switch_inst;
4443
4444 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4445 ctx->main_function, "end");
4446 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4447
4448 for (unsigned stream = 0; stream < 4; stream++) {
4449 unsigned num_components =
4450 ctx->args->shader_info->gs.num_stream_output_components[stream];
4451 LLVMBasicBlockRef bb;
4452 unsigned offset;
4453
4454 if (stream > 0 && !num_components)
4455 continue;
4456
4457 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4458 continue;
4459
4460 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4461 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4462 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4463
4464 offset = 0;
4465 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4466 unsigned output_usage_mask =
4467 ctx->args->shader_info->gs.output_usage_mask[i];
4468 unsigned output_stream =
4469 ctx->args->shader_info->gs.output_streams[i];
4470 int length = util_last_bit(output_usage_mask);
4471
4472 if (!(ctx->output_mask & (1ull << i)) ||
4473 output_stream != stream)
4474 continue;
4475
4476 for (unsigned j = 0; j < length; j++) {
4477 LLVMValueRef value, soffset;
4478
4479 if (!(output_usage_mask & (1 << j)))
4480 continue;
4481
4482 soffset = LLVMConstInt(ctx->ac.i32,
4483 offset *
4484 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4485
4486 offset++;
4487
4488 value = ac_build_buffer_load(&ctx->ac,
4489 ctx->gsvs_ring[0],
4490 1, ctx->ac.i32_0,
4491 vtx_offset, soffset,
4492 0, ac_glc | ac_slc, true, false);
4493
4494 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4495 if (ac_get_type_size(type) == 2) {
4496 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4497 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4498 }
4499
4500 LLVMBuildStore(ctx->ac.builder,
4501 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4502 }
4503 }
4504
4505 if (!ctx->args->options->use_ngg_streamout &&
4506 ctx->args->shader_info->so.num_outputs)
4507 radv_emit_streamout(ctx, stream);
4508
4509 if (stream == 0) {
4510 handle_vs_outputs_post(ctx, false, true,
4511 &ctx->args->shader_info->vs.outinfo);
4512 }
4513
4514 LLVMBuildBr(ctx->ac.builder, end_bb);
4515 }
4516
4517 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4518 }
4519
4520 void
4521 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4522 struct nir_shader *geom_shader,
4523 struct radv_shader_binary **rbinary,
4524 const struct radv_shader_args *args)
4525 {
4526 struct radv_shader_context ctx = {0};
4527 ctx.args = args;
4528
4529 assert(args->is_gs_copy_shader);
4530
4531 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4532 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4533 ctx.context = ctx.ac.context;
4534
4535 ctx.stage = MESA_SHADER_VERTEX;
4536 ctx.shader = geom_shader;
4537
4538 create_function(&ctx, MESA_SHADER_VERTEX, false);
4539
4540 ac_setup_rings(&ctx);
4541
4542 nir_foreach_variable(variable, &geom_shader->outputs) {
4543 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4544 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4545 variable, MESA_SHADER_VERTEX);
4546 }
4547
4548 ac_gs_copy_shader_emit(&ctx);
4549
4550 LLVMBuildRetVoid(ctx.ac.builder);
4551
4552 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4553
4554 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4555 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4556 (*rbinary)->is_gs_copy_shader = true;
4557
4558 }