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radv: add radv_shader_dump_stats() helper
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "r600d_common.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49
50 static void
51 radv_pipeline_destroy(struct radv_device *device,
52 struct radv_pipeline *pipeline,
53 const VkAllocationCallbacks* allocator)
54 {
55 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
56 if (pipeline->shaders[i])
57 radv_shader_variant_destroy(device, pipeline->shaders[i]);
58
59 if (pipeline->gs_copy_shader)
60 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
61
62 vk_free2(&device->alloc, allocator, pipeline);
63 }
64
65 void radv_DestroyPipeline(
66 VkDevice _device,
67 VkPipeline _pipeline,
68 const VkAllocationCallbacks* pAllocator)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
72
73 if (!_pipeline)
74 return;
75
76 radv_pipeline_destroy(device, pipeline, pAllocator);
77 }
78
79 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
80 {
81 int i;
82
83 for (i = 0; i < MESA_SHADER_STAGES; i++) {
84 if (!pipeline->shaders[i])
85 continue;
86
87 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
88 }
89 }
90
91 static struct radv_shader_variant *
92 radv_pipeline_compile(struct radv_pipeline *pipeline,
93 struct radv_pipeline_cache *cache,
94 struct radv_shader_module *module,
95 const char *entrypoint,
96 gl_shader_stage stage,
97 const VkSpecializationInfo *spec_info,
98 struct radv_pipeline_layout *layout,
99 const struct ac_shader_variant_key *key)
100 {
101 unsigned char sha1[20];
102 unsigned char gs_copy_sha1[20];
103 struct radv_shader_variant *variant;
104 nir_shader *nir;
105 void *code = NULL;
106 unsigned code_size = 0;
107
108 if (module->nir)
109 _mesa_sha1_compute(module->nir->info.name,
110 strlen(module->nir->info.name),
111 module->sha1);
112
113 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
114 if (stage == MESA_SHADER_GEOMETRY)
115 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
116 layout, key, 1);
117
118 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
119 cache,
120 sha1);
121
122 if (stage == MESA_SHADER_GEOMETRY) {
123 pipeline->gs_copy_shader =
124 radv_create_shader_variant_from_pipeline_cache(
125 pipeline->device,
126 cache,
127 gs_copy_sha1);
128 }
129
130 if (variant &&
131 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
132 return variant;
133
134 nir = radv_shader_compile_to_nir(pipeline->device,
135 module, entrypoint, stage,
136 spec_info);
137 if (nir == NULL)
138 return NULL;
139
140 if (!variant) {
141 variant = radv_shader_variant_create(pipeline->device, nir,
142 layout, key, &code,
143 &code_size);
144 }
145
146 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
147 void *gs_copy_code = NULL;
148 unsigned gs_copy_code_size = 0;
149 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
150 pipeline->device, nir, &gs_copy_code,
151 &gs_copy_code_size, key->has_multiview_view_index);
152
153 if (pipeline->gs_copy_shader) {
154 pipeline->gs_copy_shader =
155 radv_pipeline_cache_insert_shader(cache,
156 gs_copy_sha1,
157 pipeline->gs_copy_shader,
158 gs_copy_code,
159 gs_copy_code_size);
160 }
161
162 free(gs_copy_code);
163 }
164 if (!module->nir)
165 ralloc_free(nir);
166
167 if (variant)
168 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
169 code, code_size);
170
171 if (code)
172 free(code);
173 return variant;
174 }
175
176 static struct ac_shader_variant_key
177 radv_compute_tes_key(bool as_es, bool export_prim_id)
178 {
179 struct ac_shader_variant_key key;
180 memset(&key, 0, sizeof(key));
181 key.tes.as_es = as_es;
182 /* export prim id only happens when no geom shader */
183 if (!as_es)
184 key.tes.export_prim_id = export_prim_id;
185 return key;
186 }
187
188 static struct ac_shader_variant_key
189 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
190 {
191 struct ac_shader_variant_key key;
192 memset(&key, 0, sizeof(key));
193 key.tcs.primitive_mode = primitive_mode;
194 key.tcs.input_vertices = input_vertices;
195 return key;
196 }
197
198 static void
199 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
200 struct radv_pipeline_cache *cache,
201 struct radv_shader_module *tcs_module,
202 struct radv_shader_module *tes_module,
203 const char *tcs_entrypoint,
204 const char *tes_entrypoint,
205 const VkSpecializationInfo *tcs_spec_info,
206 const VkSpecializationInfo *tes_spec_info,
207 struct radv_pipeline_layout *layout,
208 unsigned input_vertices,
209 bool has_view_index)
210 {
211 unsigned char tcs_sha1[20], tes_sha1[20];
212 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
213 nir_shader *tes_nir, *tcs_nir;
214 void *tes_code = NULL, *tcs_code = NULL;
215 unsigned tes_code_size = 0, tcs_code_size = 0;
216 struct ac_shader_variant_key tes_key;
217 struct ac_shader_variant_key tcs_key;
218
219 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
220 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
221 tes_key.has_multiview_view_index = has_view_index;
222 if (tes_module->nir)
223 _mesa_sha1_compute(tes_module->nir->info.name,
224 strlen(tes_module->nir->info.name),
225 tes_module->sha1);
226 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
227
228 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
229 cache,
230 tes_sha1);
231
232 if (tes_variant) {
233 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
234
235 if (tcs_module->nir)
236 _mesa_sha1_compute(tcs_module->nir->info.name,
237 strlen(tcs_module->nir->info.name),
238 tcs_module->sha1);
239
240 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
241
242 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
243 cache,
244 tcs_sha1);
245 }
246
247 if (tcs_variant && tes_variant) {
248 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
249 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
250 return;
251 }
252
253 tes_nir = radv_shader_compile_to_nir(pipeline->device,
254 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
255 tes_spec_info);
256 if (tes_nir == NULL)
257 return;
258
259 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
260 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
261 tcs_spec_info);
262 if (tcs_nir == NULL)
263 return;
264
265 nir_lower_tes_patch_vertices(tes_nir,
266 tcs_nir->info.tess.tcs_vertices_out);
267
268 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
269 layout, &tes_key, &tes_code,
270 &tes_code_size);
271
272 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
273 if (tcs_module->nir)
274 _mesa_sha1_compute(tcs_module->nir->info.name,
275 strlen(tcs_module->nir->info.name),
276 tcs_module->sha1);
277
278 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
279
280 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
281 layout, &tcs_key, &tcs_code,
282 &tcs_code_size);
283
284 if (!tes_module->nir)
285 ralloc_free(tes_nir);
286
287 if (!tcs_module->nir)
288 ralloc_free(tcs_nir);
289
290 if (tes_variant)
291 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
292 tes_code, tes_code_size);
293
294 if (tcs_variant)
295 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
296 tcs_code, tcs_code_size);
297
298 if (tes_code)
299 free(tes_code);
300 if (tcs_code)
301 free(tcs_code);
302 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
303 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
304 return;
305 }
306
307 static VkResult
308 radv_pipeline_scratch_init(struct radv_device *device,
309 struct radv_pipeline *pipeline)
310 {
311 unsigned scratch_bytes_per_wave = 0;
312 unsigned max_waves = 0;
313 unsigned min_waves = 1;
314
315 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
316 if (pipeline->shaders[i]) {
317 unsigned max_stage_waves = device->scratch_waves;
318
319 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
320 pipeline->shaders[i]->config.scratch_bytes_per_wave);
321
322 max_stage_waves = MIN2(max_stage_waves,
323 4 * device->physical_device->rad_info.num_good_compute_units *
324 (256 / pipeline->shaders[i]->config.num_vgprs));
325 max_waves = MAX2(max_waves, max_stage_waves);
326 }
327 }
328
329 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
330 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
331 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
332 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
333 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
334 }
335
336 if (scratch_bytes_per_wave)
337 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
338
339 if (scratch_bytes_per_wave && max_waves < min_waves) {
340 /* Not really true at this moment, but will be true on first
341 * execution. Avoid having hanging shaders. */
342 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
343 }
344 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
345 pipeline->max_waves = max_waves;
346 return VK_SUCCESS;
347 }
348
349 static uint32_t si_translate_blend_function(VkBlendOp op)
350 {
351 switch (op) {
352 case VK_BLEND_OP_ADD:
353 return V_028780_COMB_DST_PLUS_SRC;
354 case VK_BLEND_OP_SUBTRACT:
355 return V_028780_COMB_SRC_MINUS_DST;
356 case VK_BLEND_OP_REVERSE_SUBTRACT:
357 return V_028780_COMB_DST_MINUS_SRC;
358 case VK_BLEND_OP_MIN:
359 return V_028780_COMB_MIN_DST_SRC;
360 case VK_BLEND_OP_MAX:
361 return V_028780_COMB_MAX_DST_SRC;
362 default:
363 return 0;
364 }
365 }
366
367 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
368 {
369 switch (factor) {
370 case VK_BLEND_FACTOR_ZERO:
371 return V_028780_BLEND_ZERO;
372 case VK_BLEND_FACTOR_ONE:
373 return V_028780_BLEND_ONE;
374 case VK_BLEND_FACTOR_SRC_COLOR:
375 return V_028780_BLEND_SRC_COLOR;
376 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
377 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
378 case VK_BLEND_FACTOR_DST_COLOR:
379 return V_028780_BLEND_DST_COLOR;
380 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
381 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
382 case VK_BLEND_FACTOR_SRC_ALPHA:
383 return V_028780_BLEND_SRC_ALPHA;
384 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
385 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
386 case VK_BLEND_FACTOR_DST_ALPHA:
387 return V_028780_BLEND_DST_ALPHA;
388 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
389 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
390 case VK_BLEND_FACTOR_CONSTANT_COLOR:
391 return V_028780_BLEND_CONSTANT_COLOR;
392 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
393 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
394 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
395 return V_028780_BLEND_CONSTANT_ALPHA;
396 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
397 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
398 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
399 return V_028780_BLEND_SRC_ALPHA_SATURATE;
400 case VK_BLEND_FACTOR_SRC1_COLOR:
401 return V_028780_BLEND_SRC1_COLOR;
402 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
403 return V_028780_BLEND_INV_SRC1_COLOR;
404 case VK_BLEND_FACTOR_SRC1_ALPHA:
405 return V_028780_BLEND_SRC1_ALPHA;
406 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
407 return V_028780_BLEND_INV_SRC1_ALPHA;
408 default:
409 return 0;
410 }
411 }
412
413 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
414 {
415 switch (op) {
416 case VK_BLEND_OP_ADD:
417 return V_028760_OPT_COMB_ADD;
418 case VK_BLEND_OP_SUBTRACT:
419 return V_028760_OPT_COMB_SUBTRACT;
420 case VK_BLEND_OP_REVERSE_SUBTRACT:
421 return V_028760_OPT_COMB_REVSUBTRACT;
422 case VK_BLEND_OP_MIN:
423 return V_028760_OPT_COMB_MIN;
424 case VK_BLEND_OP_MAX:
425 return V_028760_OPT_COMB_MAX;
426 default:
427 return V_028760_OPT_COMB_BLEND_DISABLED;
428 }
429 }
430
431 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
432 {
433 switch (factor) {
434 case VK_BLEND_FACTOR_ZERO:
435 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
436 case VK_BLEND_FACTOR_ONE:
437 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
438 case VK_BLEND_FACTOR_SRC_COLOR:
439 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
440 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
441 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
442 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
443 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
444 case VK_BLEND_FACTOR_SRC_ALPHA:
445 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
446 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
447 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
448 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
449 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
450 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
451 default:
452 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
453 }
454 }
455
456 /**
457 * Get rid of DST in the blend factors by commuting the operands:
458 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
459 */
460 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
461 unsigned *dst_factor, unsigned expected_dst,
462 unsigned replacement_src)
463 {
464 if (*src_factor == expected_dst &&
465 *dst_factor == VK_BLEND_FACTOR_ZERO) {
466 *src_factor = VK_BLEND_FACTOR_ZERO;
467 *dst_factor = replacement_src;
468
469 /* Commuting the operands requires reversing subtractions. */
470 if (*func == VK_BLEND_OP_SUBTRACT)
471 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
472 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
473 *func = VK_BLEND_OP_SUBTRACT;
474 }
475 }
476
477 static bool si_blend_factor_uses_dst(unsigned factor)
478 {
479 return factor == VK_BLEND_FACTOR_DST_COLOR ||
480 factor == VK_BLEND_FACTOR_DST_ALPHA ||
481 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
482 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
483 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
484 }
485
486 static bool is_dual_src(VkBlendFactor factor)
487 {
488 switch (factor) {
489 case VK_BLEND_FACTOR_SRC1_COLOR:
490 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
491 case VK_BLEND_FACTOR_SRC1_ALPHA:
492 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
493 return true;
494 default:
495 return false;
496 }
497 }
498
499 static unsigned si_choose_spi_color_format(VkFormat vk_format,
500 bool blend_enable,
501 bool blend_need_alpha)
502 {
503 const struct vk_format_description *desc = vk_format_description(vk_format);
504 unsigned format, ntype, swap;
505
506 /* Alpha is needed for alpha-to-coverage.
507 * Blending may be with or without alpha.
508 */
509 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
510 unsigned alpha = 0; /* exports alpha, but may not support blending */
511 unsigned blend = 0; /* supports blending, but may not export alpha */
512 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
513
514 format = radv_translate_colorformat(vk_format);
515 ntype = radv_translate_color_numformat(vk_format, desc,
516 vk_format_get_first_non_void_channel(vk_format));
517 swap = radv_translate_colorswap(vk_format, false);
518
519 /* Choose the SPI color formats. These are required values for Stoney/RB+.
520 * Other chips have multiple choices, though they are not necessarily better.
521 */
522 switch (format) {
523 case V_028C70_COLOR_5_6_5:
524 case V_028C70_COLOR_1_5_5_5:
525 case V_028C70_COLOR_5_5_5_1:
526 case V_028C70_COLOR_4_4_4_4:
527 case V_028C70_COLOR_10_11_11:
528 case V_028C70_COLOR_11_11_10:
529 case V_028C70_COLOR_8:
530 case V_028C70_COLOR_8_8:
531 case V_028C70_COLOR_8_8_8_8:
532 case V_028C70_COLOR_10_10_10_2:
533 case V_028C70_COLOR_2_10_10_10:
534 if (ntype == V_028C70_NUMBER_UINT)
535 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
536 else if (ntype == V_028C70_NUMBER_SINT)
537 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
538 else
539 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
540 break;
541
542 case V_028C70_COLOR_16:
543 case V_028C70_COLOR_16_16:
544 case V_028C70_COLOR_16_16_16_16:
545 if (ntype == V_028C70_NUMBER_UNORM ||
546 ntype == V_028C70_NUMBER_SNORM) {
547 /* UNORM16 and SNORM16 don't support blending */
548 if (ntype == V_028C70_NUMBER_UNORM)
549 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
550 else
551 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
552
553 /* Use 32 bits per channel for blending. */
554 if (format == V_028C70_COLOR_16) {
555 if (swap == V_028C70_SWAP_STD) { /* R */
556 blend = V_028714_SPI_SHADER_32_R;
557 blend_alpha = V_028714_SPI_SHADER_32_AR;
558 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
559 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
560 else
561 assert(0);
562 } else if (format == V_028C70_COLOR_16_16) {
563 if (swap == V_028C70_SWAP_STD) { /* RG */
564 blend = V_028714_SPI_SHADER_32_GR;
565 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
566 } else if (swap == V_028C70_SWAP_ALT) /* RA */
567 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
568 else
569 assert(0);
570 } else /* 16_16_16_16 */
571 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
572 } else if (ntype == V_028C70_NUMBER_UINT)
573 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
574 else if (ntype == V_028C70_NUMBER_SINT)
575 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
576 else if (ntype == V_028C70_NUMBER_FLOAT)
577 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
578 else
579 assert(0);
580 break;
581
582 case V_028C70_COLOR_32:
583 if (swap == V_028C70_SWAP_STD) { /* R */
584 blend = normal = V_028714_SPI_SHADER_32_R;
585 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
586 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
587 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
588 else
589 assert(0);
590 break;
591
592 case V_028C70_COLOR_32_32:
593 if (swap == V_028C70_SWAP_STD) { /* RG */
594 blend = normal = V_028714_SPI_SHADER_32_GR;
595 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
596 } else if (swap == V_028C70_SWAP_ALT) /* RA */
597 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
598 else
599 assert(0);
600 break;
601
602 case V_028C70_COLOR_32_32_32_32:
603 case V_028C70_COLOR_8_24:
604 case V_028C70_COLOR_24_8:
605 case V_028C70_COLOR_X24_8_32_FLOAT:
606 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
607 break;
608
609 default:
610 unreachable("unhandled blend format");
611 }
612
613 if (blend_enable && blend_need_alpha)
614 return blend_alpha;
615 else if(blend_need_alpha)
616 return alpha;
617 else if(blend_enable)
618 return blend;
619 else
620 return normal;
621 }
622
623 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
624 {
625 unsigned i, cb_shader_mask = 0;
626
627 for (i = 0; i < 8; i++) {
628 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
629 case V_028714_SPI_SHADER_ZERO:
630 break;
631 case V_028714_SPI_SHADER_32_R:
632 cb_shader_mask |= 0x1 << (i * 4);
633 break;
634 case V_028714_SPI_SHADER_32_GR:
635 cb_shader_mask |= 0x3 << (i * 4);
636 break;
637 case V_028714_SPI_SHADER_32_AR:
638 cb_shader_mask |= 0x9 << (i * 4);
639 break;
640 case V_028714_SPI_SHADER_FP16_ABGR:
641 case V_028714_SPI_SHADER_UNORM16_ABGR:
642 case V_028714_SPI_SHADER_SNORM16_ABGR:
643 case V_028714_SPI_SHADER_UINT16_ABGR:
644 case V_028714_SPI_SHADER_SINT16_ABGR:
645 case V_028714_SPI_SHADER_32_ABGR:
646 cb_shader_mask |= 0xf << (i * 4);
647 break;
648 default:
649 assert(0);
650 }
651 }
652 return cb_shader_mask;
653 }
654
655 static void
656 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
657 const VkGraphicsPipelineCreateInfo *pCreateInfo,
658 uint32_t blend_enable,
659 uint32_t blend_need_alpha,
660 bool single_cb_enable,
661 bool blend_mrt0_is_dual_src)
662 {
663 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
664 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
665 struct radv_blend_state *blend = &pipeline->graphics.blend;
666 unsigned col_format = 0;
667
668 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
669 unsigned cf;
670
671 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
672 cf = V_028714_SPI_SHADER_ZERO;
673 } else {
674 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
675
676 cf = si_choose_spi_color_format(attachment->format,
677 blend_enable & (1 << i),
678 blend_need_alpha & (1 << i));
679 }
680
681 col_format |= cf << (4 * i);
682 }
683
684 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
685
686 if (blend_mrt0_is_dual_src)
687 col_format |= (col_format & 0xf) << 4;
688 blend->spi_shader_col_format = col_format;
689 }
690
691 static bool
692 format_is_int8(VkFormat format)
693 {
694 const struct vk_format_description *desc = vk_format_description(format);
695 int channel = vk_format_get_first_non_void_channel(format);
696
697 return channel >= 0 && desc->channel[channel].pure_integer &&
698 desc->channel[channel].size == 8;
699 }
700
701 static bool
702 format_is_int10(VkFormat format)
703 {
704 const struct vk_format_description *desc = vk_format_description(format);
705
706 if (desc->nr_channels != 4)
707 return false;
708 for (unsigned i = 0; i < 4; i++) {
709 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
710 return true;
711 }
712 return false;
713 }
714
715 unsigned radv_format_meta_fs_key(VkFormat format)
716 {
717 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
718 bool is_int8 = format_is_int8(format);
719 bool is_int10 = format_is_int10(format);
720
721 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
722 }
723
724 static void
725 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
726 unsigned *is_int8, unsigned *is_int10)
727 {
728 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
729 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
730 *is_int8 = 0;
731 *is_int10 = 0;
732
733 for (unsigned i = 0; i < subpass->color_count; ++i) {
734 struct radv_render_pass_attachment *attachment;
735
736 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
737 continue;
738
739 attachment = pass->attachments + subpass->color_attachments[i].attachment;
740
741 if (format_is_int8(attachment->format))
742 *is_int8 |= 1 << i;
743 if (format_is_int10(attachment->format))
744 *is_int10 |= 1 << i;
745 }
746 }
747
748 static void
749 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
750 const VkGraphicsPipelineCreateInfo *pCreateInfo,
751 const struct radv_graphics_pipeline_create_info *extra)
752 {
753 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
754 struct radv_blend_state *blend = &pipeline->graphics.blend;
755 unsigned mode = V_028808_CB_NORMAL;
756 uint32_t blend_enable = 0, blend_need_alpha = 0;
757 bool blend_mrt0_is_dual_src = false;
758 int i;
759 bool single_cb_enable = false;
760
761 if (!vkblend)
762 return;
763
764 if (extra && extra->custom_blend_mode) {
765 single_cb_enable = true;
766 mode = extra->custom_blend_mode;
767 }
768 blend->cb_color_control = 0;
769 if (vkblend->logicOpEnable)
770 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
771 else
772 blend->cb_color_control |= S_028808_ROP3(0xcc);
773
774 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
775 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
776 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
777 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
778
779 blend->cb_target_mask = 0;
780 for (i = 0; i < vkblend->attachmentCount; i++) {
781 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
782 unsigned blend_cntl = 0;
783 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
784 VkBlendOp eqRGB = att->colorBlendOp;
785 VkBlendFactor srcRGB = att->srcColorBlendFactor;
786 VkBlendFactor dstRGB = att->dstColorBlendFactor;
787 VkBlendOp eqA = att->alphaBlendOp;
788 VkBlendFactor srcA = att->srcAlphaBlendFactor;
789 VkBlendFactor dstA = att->dstAlphaBlendFactor;
790
791 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
792
793 if (!att->colorWriteMask)
794 continue;
795
796 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
797 if (!att->blendEnable) {
798 blend->cb_blend_control[i] = blend_cntl;
799 continue;
800 }
801
802 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
803 if (i == 0)
804 blend_mrt0_is_dual_src = true;
805
806 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
807 srcRGB = VK_BLEND_FACTOR_ONE;
808 dstRGB = VK_BLEND_FACTOR_ONE;
809 }
810 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
811 srcA = VK_BLEND_FACTOR_ONE;
812 dstA = VK_BLEND_FACTOR_ONE;
813 }
814
815 /* Blending optimizations for RB+.
816 * These transformations don't change the behavior.
817 *
818 * First, get rid of DST in the blend factors:
819 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
820 */
821 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
822 VK_BLEND_FACTOR_DST_COLOR,
823 VK_BLEND_FACTOR_SRC_COLOR);
824
825 si_blend_remove_dst(&eqA, &srcA, &dstA,
826 VK_BLEND_FACTOR_DST_COLOR,
827 VK_BLEND_FACTOR_SRC_COLOR);
828
829 si_blend_remove_dst(&eqA, &srcA, &dstA,
830 VK_BLEND_FACTOR_DST_ALPHA,
831 VK_BLEND_FACTOR_SRC_ALPHA);
832
833 /* Look up the ideal settings from tables. */
834 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
835 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
836 srcA_opt = si_translate_blend_opt_factor(srcA, true);
837 dstA_opt = si_translate_blend_opt_factor(dstA, true);
838
839 /* Handle interdependencies. */
840 if (si_blend_factor_uses_dst(srcRGB))
841 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
842 if (si_blend_factor_uses_dst(srcA))
843 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
844
845 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
846 (dstRGB == VK_BLEND_FACTOR_ZERO ||
847 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
848 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
849 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
850
851 /* Set the final value. */
852 blend->sx_mrt_blend_opt[i] =
853 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
854 S_028760_COLOR_DST_OPT(dstRGB_opt) |
855 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
856 S_028760_ALPHA_SRC_OPT(srcA_opt) |
857 S_028760_ALPHA_DST_OPT(dstA_opt) |
858 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
859 blend_cntl |= S_028780_ENABLE(1);
860
861 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
862 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
863 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
864 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
865 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
866 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
867 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
868 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
869 }
870 blend->cb_blend_control[i] = blend_cntl;
871
872 blend_enable |= 1 << i;
873
874 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
875 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
876 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
877 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
878 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
879 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
880 blend_need_alpha |= 1 << i;
881 }
882 for (i = vkblend->attachmentCount; i < 8; i++) {
883 blend->cb_blend_control[i] = 0;
884 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
885 }
886
887 /* disable RB+ for now */
888 if (pipeline->device->physical_device->has_rbplus)
889 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
890
891 if (blend->cb_target_mask)
892 blend->cb_color_control |= S_028808_MODE(mode);
893 else
894 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
895
896 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
897 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
898 }
899
900 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
901 {
902 switch (op) {
903 case VK_STENCIL_OP_KEEP:
904 return V_02842C_STENCIL_KEEP;
905 case VK_STENCIL_OP_ZERO:
906 return V_02842C_STENCIL_ZERO;
907 case VK_STENCIL_OP_REPLACE:
908 return V_02842C_STENCIL_REPLACE_TEST;
909 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
910 return V_02842C_STENCIL_ADD_CLAMP;
911 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
912 return V_02842C_STENCIL_SUB_CLAMP;
913 case VK_STENCIL_OP_INVERT:
914 return V_02842C_STENCIL_INVERT;
915 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
916 return V_02842C_STENCIL_ADD_WRAP;
917 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
918 return V_02842C_STENCIL_SUB_WRAP;
919 default:
920 return 0;
921 }
922 }
923 static void
924 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
925 const VkGraphicsPipelineCreateInfo *pCreateInfo,
926 const struct radv_graphics_pipeline_create_info *extra)
927 {
928 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
929 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
930
931 memset(ds, 0, sizeof(*ds));
932 if (!vkds)
933 return;
934
935 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
936 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
937 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
938 return;
939
940 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
941 bool has_depth_attachment = vk_format_is_depth(attachment->format);
942 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
943
944 if (has_depth_attachment) {
945 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
946 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
947 S_028800_ZFUNC(vkds->depthCompareOp) |
948 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
949 }
950
951 if (has_stencil_attachment && vkds->stencilTestEnable) {
952 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
953 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
954 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
955 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
956 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
957
958 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
959 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
960 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
961 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
962 }
963
964 if (extra) {
965
966 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
967 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
968
969 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
970 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
971 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
972 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
973 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
974 }
975 }
976
977 static uint32_t si_translate_fill(VkPolygonMode func)
978 {
979 switch(func) {
980 case VK_POLYGON_MODE_FILL:
981 return V_028814_X_DRAW_TRIANGLES;
982 case VK_POLYGON_MODE_LINE:
983 return V_028814_X_DRAW_LINES;
984 case VK_POLYGON_MODE_POINT:
985 return V_028814_X_DRAW_POINTS;
986 default:
987 assert(0);
988 return V_028814_X_DRAW_POINTS;
989 }
990 }
991 static void
992 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
993 const VkGraphicsPipelineCreateInfo *pCreateInfo)
994 {
995 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
996 struct radv_raster_state *raster = &pipeline->graphics.raster;
997
998 memset(raster, 0, sizeof(*raster));
999
1000 raster->spi_interp_control =
1001 S_0286D4_FLAT_SHADE_ENA(1) |
1002 S_0286D4_PNT_SPRITE_ENA(1) |
1003 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1004 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1005 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1006 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1007 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1008
1009
1010 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1011 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1012 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1013 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1014 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1015 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1016
1017 raster->pa_su_vtx_cntl =
1018 S_028BE4_PIX_CENTER(1) | // TODO verify
1019 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1020 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1021
1022 raster->pa_su_sc_mode_cntl =
1023 S_028814_FACE(vkraster->frontFace) |
1024 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1025 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1026 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1027 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1028 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1029 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1030 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1031 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1032
1033 }
1034
1035 static void
1036 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1037 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1038 {
1039 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1040 struct radv_blend_state *blend = &pipeline->graphics.blend;
1041 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1042 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1043 int ps_iter_samples = 1;
1044 uint32_t mask = 0xffff;
1045
1046 if (vkms)
1047 ms->num_samples = vkms->rasterizationSamples;
1048 else
1049 ms->num_samples = 1;
1050
1051 if (vkms && vkms->sampleShadingEnable) {
1052 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1053 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1054 ps_iter_samples = ms->num_samples;
1055 }
1056
1057 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1058 ms->pa_sc_aa_config = 0;
1059 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1060 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1061 ms->pa_sc_mode_cntl_1 =
1062 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1063 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1064 /* always 1: */
1065 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1066 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1067 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1068 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1069 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1070 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1071 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1072
1073 if (ms->num_samples > 1) {
1074 unsigned log_samples = util_logbase2(ms->num_samples);
1075 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1076 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1077 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1078 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1079 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1080 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1081 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1082 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1083 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1084 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1085 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1086 }
1087
1088 if (vkms) {
1089 if (vkms->alphaToCoverageEnable)
1090 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1091
1092 if (vkms->pSampleMask)
1093 mask = vkms->pSampleMask[0] & 0xffff;
1094 }
1095
1096 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1097 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1098 }
1099
1100 static bool
1101 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1102 {
1103 switch (topology) {
1104 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1105 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1106 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1107 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1108 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1109 return false;
1110 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1111 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1112 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1113 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1114 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1115 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1116 return true;
1117 default:
1118 unreachable("unhandled primitive type");
1119 }
1120 }
1121
1122 static uint32_t
1123 si_translate_prim(enum VkPrimitiveTopology topology)
1124 {
1125 switch (topology) {
1126 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1127 return V_008958_DI_PT_POINTLIST;
1128 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1129 return V_008958_DI_PT_LINELIST;
1130 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1131 return V_008958_DI_PT_LINESTRIP;
1132 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1133 return V_008958_DI_PT_TRILIST;
1134 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1135 return V_008958_DI_PT_TRISTRIP;
1136 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1137 return V_008958_DI_PT_TRIFAN;
1138 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1139 return V_008958_DI_PT_LINELIST_ADJ;
1140 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1141 return V_008958_DI_PT_LINESTRIP_ADJ;
1142 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1143 return V_008958_DI_PT_TRILIST_ADJ;
1144 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1145 return V_008958_DI_PT_TRISTRIP_ADJ;
1146 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1147 return V_008958_DI_PT_PATCH;
1148 default:
1149 assert(0);
1150 return 0;
1151 }
1152 }
1153
1154 static uint32_t
1155 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1156 {
1157 switch (gl_prim) {
1158 case 0: /* GL_POINTS */
1159 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1160 case 1: /* GL_LINES */
1161 case 3: /* GL_LINE_STRIP */
1162 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1163 case 0x8E7A: /* GL_ISOLINES */
1164 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1165
1166 case 4: /* GL_TRIANGLES */
1167 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1168 case 5: /* GL_TRIANGLE_STRIP */
1169 case 7: /* GL_QUADS */
1170 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1171 default:
1172 assert(0);
1173 return 0;
1174 }
1175 }
1176
1177 static uint32_t
1178 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1179 {
1180 switch (topology) {
1181 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1182 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1183 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1188 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1194 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1195 default:
1196 assert(0);
1197 return 0;
1198 }
1199 }
1200
1201 static unsigned si_map_swizzle(unsigned swizzle)
1202 {
1203 switch (swizzle) {
1204 case VK_SWIZZLE_Y:
1205 return V_008F0C_SQ_SEL_Y;
1206 case VK_SWIZZLE_Z:
1207 return V_008F0C_SQ_SEL_Z;
1208 case VK_SWIZZLE_W:
1209 return V_008F0C_SQ_SEL_W;
1210 case VK_SWIZZLE_0:
1211 return V_008F0C_SQ_SEL_0;
1212 case VK_SWIZZLE_1:
1213 return V_008F0C_SQ_SEL_1;
1214 default: /* VK_SWIZZLE_X */
1215 return V_008F0C_SQ_SEL_X;
1216 }
1217 }
1218
1219 static void
1220 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1221 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1222 {
1223 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1224 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1225 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1226
1227 pipeline->dynamic_state = default_dynamic_state;
1228
1229 if (pCreateInfo->pDynamicState) {
1230 /* Remove all of the states that are marked as dynamic */
1231 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1232 for (uint32_t s = 0; s < count; s++)
1233 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1234 }
1235
1236 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1237
1238 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1239 *
1240 * pViewportState is [...] NULL if the pipeline
1241 * has rasterization disabled.
1242 */
1243 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1244 assert(pCreateInfo->pViewportState);
1245
1246 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1247 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1248 typed_memcpy(dynamic->viewport.viewports,
1249 pCreateInfo->pViewportState->pViewports,
1250 pCreateInfo->pViewportState->viewportCount);
1251 }
1252
1253 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1254 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1255 typed_memcpy(dynamic->scissor.scissors,
1256 pCreateInfo->pViewportState->pScissors,
1257 pCreateInfo->pViewportState->scissorCount);
1258 }
1259 }
1260
1261 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1262 assert(pCreateInfo->pRasterizationState);
1263 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1264 }
1265
1266 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1267 assert(pCreateInfo->pRasterizationState);
1268 dynamic->depth_bias.bias =
1269 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1270 dynamic->depth_bias.clamp =
1271 pCreateInfo->pRasterizationState->depthBiasClamp;
1272 dynamic->depth_bias.slope =
1273 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1274 }
1275
1276 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1277 *
1278 * pColorBlendState is [...] NULL if the pipeline has rasterization
1279 * disabled or if the subpass of the render pass the pipeline is
1280 * created against does not use any color attachments.
1281 */
1282 bool uses_color_att = false;
1283 for (unsigned i = 0; i < subpass->color_count; ++i) {
1284 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1285 uses_color_att = true;
1286 break;
1287 }
1288 }
1289
1290 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1291 assert(pCreateInfo->pColorBlendState);
1292 typed_memcpy(dynamic->blend_constants,
1293 pCreateInfo->pColorBlendState->blendConstants, 4);
1294 }
1295
1296 /* If there is no depthstencil attachment, then don't read
1297 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1298 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1299 * no need to override the depthstencil defaults in
1300 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1301 *
1302 * Section 9.2 of the Vulkan 1.0.15 spec says:
1303 *
1304 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1305 * disabled or if the subpass of the render pass the pipeline is created
1306 * against does not use a depth/stencil attachment.
1307 */
1308 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1309 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1310 assert(pCreateInfo->pDepthStencilState);
1311
1312 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1313 dynamic->depth_bounds.min =
1314 pCreateInfo->pDepthStencilState->minDepthBounds;
1315 dynamic->depth_bounds.max =
1316 pCreateInfo->pDepthStencilState->maxDepthBounds;
1317 }
1318
1319 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1320 dynamic->stencil_compare_mask.front =
1321 pCreateInfo->pDepthStencilState->front.compareMask;
1322 dynamic->stencil_compare_mask.back =
1323 pCreateInfo->pDepthStencilState->back.compareMask;
1324 }
1325
1326 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1327 dynamic->stencil_write_mask.front =
1328 pCreateInfo->pDepthStencilState->front.writeMask;
1329 dynamic->stencil_write_mask.back =
1330 pCreateInfo->pDepthStencilState->back.writeMask;
1331 }
1332
1333 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1334 dynamic->stencil_reference.front =
1335 pCreateInfo->pDepthStencilState->front.reference;
1336 dynamic->stencil_reference.back =
1337 pCreateInfo->pDepthStencilState->back.reference;
1338 }
1339 }
1340
1341 pipeline->dynamic_state_mask = states;
1342 }
1343
1344 static struct ac_shader_variant_key
1345 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1346 {
1347 struct ac_shader_variant_key key;
1348 const VkPipelineVertexInputStateCreateInfo *input_state =
1349 pCreateInfo->pVertexInputState;
1350
1351 memset(&key, 0, sizeof(key));
1352 key.vs.instance_rate_inputs = 0;
1353 key.vs.as_es = as_es;
1354 key.vs.as_ls = as_ls;
1355 key.vs.export_prim_id = export_prim_id;
1356
1357 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1358 unsigned binding;
1359 binding = input_state->pVertexAttributeDescriptions[i].binding;
1360 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1361 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1362 }
1363 return key;
1364 }
1365
1366 static void
1367 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1368 {
1369 struct radv_device *device = pipeline->device;
1370 unsigned num_se = device->physical_device->rad_info.max_se;
1371 unsigned wave_size = 64;
1372 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1373 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1374 unsigned alignment = 256 * num_se;
1375 /* The maximum size is 63.999 MB per SE. */
1376 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1377 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1378 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1379 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1380 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1381
1382 /* Calculate the minimum size. */
1383 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1384 wave_size, alignment);
1385 /* These are recommended sizes, not minimum sizes. */
1386 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1387 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1388 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1389 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1390
1391 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1392 esgs_ring_size = align(esgs_ring_size, alignment);
1393 gsvs_ring_size = align(gsvs_ring_size, alignment);
1394
1395 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1396 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1397 }
1398
1399 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1400 unsigned *lds_size)
1401 {
1402 /* SPI barrier management bug:
1403 * Make sure we have at least 4k of LDS in use to avoid the bug.
1404 * It applies to workgroup sizes of more than one wavefront.
1405 */
1406 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1407 device->physical_device->rad_info.family == CHIP_KABINI ||
1408 device->physical_device->rad_info.family == CHIP_MULLINS)
1409 *lds_size = MAX2(*lds_size, 8);
1410 }
1411
1412 static void
1413 calculate_tess_state(struct radv_pipeline *pipeline,
1414 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1415 {
1416 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1417 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1418 unsigned num_tcs_patch_outputs;
1419 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1420 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1421 unsigned lds_size, hardware_lds_size;
1422 unsigned perpatch_output_offset;
1423 unsigned num_patches;
1424 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1425
1426 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1427 * are laid out in LDS. */
1428 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1429
1430 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1431 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1432 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1433
1434 /* Ensure that we only need one wave per SIMD so we don't need to check
1435 * resource usage. Also ensures that the number of tcs in and out
1436 * vertices per threadgroup are at most 256.
1437 */
1438 input_vertex_size = num_tcs_inputs * 16;
1439 output_vertex_size = num_tcs_outputs * 16;
1440
1441 input_patch_size = num_tcs_input_cp * input_vertex_size;
1442
1443 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1444 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1445 /* Ensure that we only need one wave per SIMD so we don't need to check
1446 * resource usage. Also ensures that the number of tcs in and out
1447 * vertices per threadgroup are at most 256.
1448 */
1449 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1450
1451 /* Make sure that the data fits in LDS. This assumes the shaders only
1452 * use LDS for the inputs and outputs.
1453 */
1454 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1455 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1456
1457 /* Make sure the output data fits in the offchip buffer */
1458 num_patches = MIN2(num_patches,
1459 (pipeline->device->tess_offchip_block_dw_size * 4) /
1460 output_patch_size);
1461
1462 /* Not necessary for correctness, but improves performance. The
1463 * specific value is taken from the proprietary driver.
1464 */
1465 num_patches = MIN2(num_patches, 40);
1466
1467 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1468 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1469 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1470 num_patches = MIN2(num_patches, one_wave);
1471 }
1472
1473 output_patch0_offset = input_patch_size * num_patches;
1474 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1475
1476 lds_size = output_patch0_offset + output_patch_size * num_patches;
1477
1478 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1479 assert(lds_size <= 65536);
1480 lds_size = align(lds_size, 512) / 512;
1481 } else {
1482 assert(lds_size <= 32768);
1483 lds_size = align(lds_size, 256) / 256;
1484 }
1485 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1486
1487 tess->lds_size = lds_size;
1488
1489 tess->tcs_in_layout = (input_patch_size / 4) |
1490 ((input_vertex_size / 4) << 13);
1491 tess->tcs_out_layout = (output_patch_size / 4) |
1492 ((output_vertex_size / 4) << 13);
1493 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1494 ((perpatch_output_offset / 16) << 16);
1495 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1496 (num_tcs_output_cp << 9) | num_patches;
1497
1498 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1499 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1500 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1501 tess->num_patches = num_patches;
1502 tess->num_tcs_input_cp = num_tcs_input_cp;
1503
1504 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1505 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1506
1507 switch (tes->info.tes.primitive_mode) {
1508 case GL_TRIANGLES:
1509 type = V_028B6C_TESS_TRIANGLE;
1510 break;
1511 case GL_QUADS:
1512 type = V_028B6C_TESS_QUAD;
1513 break;
1514 case GL_ISOLINES:
1515 type = V_028B6C_TESS_ISOLINE;
1516 break;
1517 }
1518
1519 switch (tes->info.tes.spacing) {
1520 case TESS_SPACING_EQUAL:
1521 partitioning = V_028B6C_PART_INTEGER;
1522 break;
1523 case TESS_SPACING_FRACTIONAL_ODD:
1524 partitioning = V_028B6C_PART_FRAC_ODD;
1525 break;
1526 case TESS_SPACING_FRACTIONAL_EVEN:
1527 partitioning = V_028B6C_PART_FRAC_EVEN;
1528 break;
1529 default:
1530 break;
1531 }
1532
1533 if (tes->info.tes.point_mode)
1534 topology = V_028B6C_OUTPUT_POINT;
1535 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1536 topology = V_028B6C_OUTPUT_LINE;
1537 else if (tes->info.tes.ccw)
1538 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1539 else
1540 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1541
1542 if (pipeline->device->has_distributed_tess) {
1543 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1544 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1545 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1546 else
1547 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1548 } else
1549 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1550
1551 tess->tf_param = S_028B6C_TYPE(type) |
1552 S_028B6C_PARTITIONING(partitioning) |
1553 S_028B6C_TOPOLOGY(topology) |
1554 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1555 }
1556
1557 static const struct radv_prim_vertex_count prim_size_table[] = {
1558 [V_008958_DI_PT_NONE] = {0, 0},
1559 [V_008958_DI_PT_POINTLIST] = {1, 1},
1560 [V_008958_DI_PT_LINELIST] = {2, 2},
1561 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1562 [V_008958_DI_PT_TRILIST] = {3, 3},
1563 [V_008958_DI_PT_TRIFAN] = {3, 1},
1564 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1565 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1566 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1567 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1568 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1569 [V_008958_DI_PT_RECTLIST] = {3, 3},
1570 [V_008958_DI_PT_LINELOOP] = {2, 1},
1571 [V_008958_DI_PT_POLYGON] = {3, 1},
1572 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1573 };
1574
1575 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1576 {
1577 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1578 unsigned cut_mode;
1579
1580 if (gs_max_vert_out <= 128) {
1581 cut_mode = V_028A40_GS_CUT_128;
1582 } else if (gs_max_vert_out <= 256) {
1583 cut_mode = V_028A40_GS_CUT_256;
1584 } else if (gs_max_vert_out <= 512) {
1585 cut_mode = V_028A40_GS_CUT_512;
1586 } else {
1587 assert(gs_max_vert_out <= 1024);
1588 cut_mode = V_028A40_GS_CUT_1024;
1589 }
1590
1591 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1592 S_028A40_CUT_MODE(cut_mode)|
1593 S_028A40_ES_WRITE_OPTIMIZE(1) |
1594 S_028A40_GS_WRITE_OPTIMIZE(1);
1595 }
1596
1597 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1598 {
1599 struct radv_shader_variant *vs;
1600 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1601
1602 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1603
1604 pipeline->graphics.vgt_primitiveid_en = false;
1605 pipeline->graphics.vgt_gs_mode = 0;
1606
1607 if (radv_pipeline_has_gs(pipeline)) {
1608 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1609 } else if (outinfo->export_prim_id) {
1610 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1611 pipeline->graphics.vgt_primitiveid_en = true;
1612 }
1613 }
1614
1615 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1616 {
1617 struct radv_shader_variant *vs;
1618 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1619
1620 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1621
1622 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1623 clip_dist_mask = outinfo->clip_dist_mask;
1624 cull_dist_mask = outinfo->cull_dist_mask;
1625 total_mask = clip_dist_mask | cull_dist_mask;
1626
1627 bool misc_vec_ena = outinfo->writes_pointsize ||
1628 outinfo->writes_layer ||
1629 outinfo->writes_viewport_index;
1630 pipeline->graphics.pa_cl_vs_out_cntl =
1631 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1632 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1633 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1634 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1635 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1636 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1637 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1638 cull_dist_mask << 8 |
1639 clip_dist_mask;
1640
1641 }
1642
1643 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1644 {
1645 uint32_t ps_input_cntl;
1646 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1647 ps_input_cntl = S_028644_OFFSET(offset);
1648 if (flat_shade)
1649 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1650 } else {
1651 /* The input is a DEFAULT_VAL constant. */
1652 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1653 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1654 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1655 ps_input_cntl = S_028644_OFFSET(0x20) |
1656 S_028644_DEFAULT_VAL(offset);
1657 }
1658 return ps_input_cntl;
1659 }
1660
1661 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1662 {
1663 struct radv_shader_variant *ps, *vs;
1664 struct ac_vs_output_info *outinfo;
1665
1666 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1667 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1668
1669 outinfo = &vs->info.vs.outinfo;
1670
1671 unsigned ps_offset = 0;
1672
1673 if (ps->info.fs.prim_id_input) {
1674 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1675 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1676 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1677 ++ps_offset;
1678 }
1679 }
1680
1681 if (ps->info.fs.layer_input) {
1682 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1683 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1684 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1685 else
1686 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1687 ++ps_offset;
1688 }
1689
1690 if (ps->info.fs.has_pcoord) {
1691 unsigned val;
1692 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1693 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1694 ps_offset++;
1695 }
1696
1697 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1698 unsigned vs_offset;
1699 bool flat_shade;
1700 if (!(ps->info.fs.input_mask & (1u << i)))
1701 continue;
1702
1703 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1704 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1705 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1706 ++ps_offset;
1707 continue;
1708 }
1709
1710 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1711
1712 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1713 ++ps_offset;
1714 }
1715
1716 pipeline->graphics.ps_input_cntl_num = ps_offset;
1717 }
1718
1719 VkResult
1720 radv_pipeline_init(struct radv_pipeline *pipeline,
1721 struct radv_device *device,
1722 struct radv_pipeline_cache *cache,
1723 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1724 const struct radv_graphics_pipeline_create_info *extra,
1725 const VkAllocationCallbacks *alloc)
1726 {
1727 struct radv_shader_module fs_m = {0};
1728 VkResult result;
1729 bool has_view_index = false;
1730
1731 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1732 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1733 if (subpass->view_mask)
1734 has_view_index = true;
1735 if (alloc == NULL)
1736 alloc = &device->alloc;
1737
1738 pipeline->device = device;
1739 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1740
1741 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1742 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1743 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1744 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1745 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1746 pStages[stage] = &pCreateInfo->pStages[i];
1747 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1748 }
1749
1750 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1751
1752 if (!modules[MESA_SHADER_FRAGMENT]) {
1753 nir_builder fs_b;
1754 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1755 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1756 fs_m.nir = fs_b.shader;
1757 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1758 }
1759
1760 if (modules[MESA_SHADER_FRAGMENT]) {
1761 struct ac_shader_variant_key key = {0};
1762 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1763 if (pCreateInfo->pMultisampleState &&
1764 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1765 key.fs.multisample = true;
1766
1767 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1768 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
1769
1770 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1771
1772 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1773 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1774 stage ? stage->pName : "main",
1775 MESA_SHADER_FRAGMENT,
1776 stage ? stage->pSpecializationInfo : NULL,
1777 pipeline->layout, &key);
1778 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1779 }
1780
1781 if (fs_m.nir)
1782 ralloc_free(fs_m.nir);
1783
1784 if (modules[MESA_SHADER_VERTEX]) {
1785 bool as_es = false;
1786 bool as_ls = false;
1787 bool export_prim_id = false;
1788 if (modules[MESA_SHADER_TESS_CTRL])
1789 as_ls = true;
1790 else if (modules[MESA_SHADER_GEOMETRY])
1791 as_es = true;
1792 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1793 export_prim_id = true;
1794 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
1795 key.has_multiview_view_index = has_view_index;
1796
1797 pipeline->shaders[MESA_SHADER_VERTEX] =
1798 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1799 pStages[MESA_SHADER_VERTEX]->pName,
1800 MESA_SHADER_VERTEX,
1801 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1802 pipeline->layout, &key);
1803
1804 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1805 }
1806
1807 if (modules[MESA_SHADER_GEOMETRY]) {
1808 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
1809 key.has_multiview_view_index = has_view_index;
1810
1811 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1812 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1813 pStages[MESA_SHADER_GEOMETRY]->pName,
1814 MESA_SHADER_GEOMETRY,
1815 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1816 pipeline->layout, &key);
1817
1818 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1819 }
1820
1821 if (modules[MESA_SHADER_TESS_EVAL]) {
1822 assert(modules[MESA_SHADER_TESS_CTRL]);
1823
1824 radv_tess_pipeline_compile(pipeline,
1825 cache,
1826 modules[MESA_SHADER_TESS_CTRL],
1827 modules[MESA_SHADER_TESS_EVAL],
1828 pStages[MESA_SHADER_TESS_CTRL]->pName,
1829 pStages[MESA_SHADER_TESS_EVAL]->pName,
1830 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
1831 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
1832 pipeline->layout,
1833 pCreateInfo->pTessellationState->patchControlPoints,
1834 has_view_index);
1835 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
1836 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
1837 }
1838
1839 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1840 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1841 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1842 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1843 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1844
1845 if (radv_pipeline_has_gs(pipeline)) {
1846 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1847 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1848 } else {
1849 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1850 }
1851 if (extra && extra->use_rectlist) {
1852 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1853 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1854 pipeline->graphics.can_use_guardband = true;
1855 }
1856 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1857 /* prim vertex count will need TESS changes */
1858 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1859
1860 /* Ensure that some export memory is always allocated, for two reasons:
1861 *
1862 * 1) Correctness: The hardware ignores the EXEC mask if no export
1863 * memory is allocated, so KILL and alpha test do not work correctly
1864 * without this.
1865 * 2) Performance: Every shader needs at least a NULL export, even when
1866 * it writes no color/depth output. The NULL export instruction
1867 * stalls without this setting.
1868 *
1869 * Don't add this to CB_SHADER_MASK.
1870 */
1871 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1872 if (!pipeline->graphics.blend.spi_shader_col_format) {
1873 if (!ps->info.fs.writes_z &&
1874 !ps->info.fs.writes_stencil &&
1875 !ps->info.fs.writes_sample_mask)
1876 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1877 }
1878
1879 unsigned z_order;
1880 pipeline->graphics.db_shader_control = 0;
1881 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1882 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1883 else
1884 z_order = V_02880C_LATE_Z;
1885
1886 pipeline->graphics.db_shader_control =
1887 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1888 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1889 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1890 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1891 S_02880C_Z_ORDER(z_order) |
1892 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1893 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1894 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1895
1896 if (pipeline->device->physical_device->has_rbplus)
1897 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1898
1899 pipeline->graphics.shader_z_format =
1900 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1901 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1902 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1903 V_028710_SPI_SHADER_ZERO;
1904
1905 calculate_vgt_gs_mode(pipeline);
1906 calculate_pa_cl_vs_out_cntl(pipeline);
1907 calculate_ps_inputs(pipeline);
1908
1909 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1910 if (pipeline->shaders[i]) {
1911 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
1912 }
1913 }
1914
1915 uint32_t stages = 0;
1916 if (radv_pipeline_has_tess(pipeline)) {
1917 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1918 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1919
1920 if (radv_pipeline_has_gs(pipeline))
1921 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1922 S_028B54_GS_EN(1) |
1923 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1924 else
1925 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1926
1927 } else if (radv_pipeline_has_gs(pipeline))
1928 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1929 S_028B54_GS_EN(1) |
1930 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1931
1932 if (device->physical_device->rad_info.chip_class >= GFX9)
1933 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1934
1935 pipeline->graphics.vgt_shader_stages_en = stages;
1936
1937 if (radv_pipeline_has_gs(pipeline))
1938 calculate_gs_ring_sizes(pipeline);
1939
1940 if (radv_pipeline_has_tess(pipeline)) {
1941 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
1942 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
1943 pipeline->graphics.prim_vertex_count.incr = 1;
1944 }
1945 calculate_tess_state(pipeline, pCreateInfo);
1946 }
1947
1948 if (radv_pipeline_has_tess(pipeline))
1949 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
1950 else if (radv_pipeline_has_gs(pipeline))
1951 pipeline->graphics.primgroup_size = 64;
1952 else
1953 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
1954
1955 pipeline->graphics.partial_es_wave = false;
1956 if (pipeline->device->has_distributed_tess) {
1957 if (radv_pipeline_has_gs(pipeline)) {
1958 if (device->physical_device->rad_info.chip_class <= VI)
1959 pipeline->graphics.partial_es_wave = true;
1960 }
1961 }
1962 /* GS requirement. */
1963 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
1964 pipeline->graphics.partial_es_wave = true;
1965
1966 pipeline->graphics.wd_switch_on_eop = false;
1967 if (device->physical_device->rad_info.chip_class >= CIK) {
1968 unsigned prim = pipeline->graphics.prim;
1969 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
1970 * 4 shader engines. Set 1 to pass the assertion below.
1971 * The other cases are hardware requirements. */
1972 if (device->physical_device->rad_info.max_se < 4 ||
1973 prim == V_008958_DI_PT_POLYGON ||
1974 prim == V_008958_DI_PT_LINELOOP ||
1975 prim == V_008958_DI_PT_TRIFAN ||
1976 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
1977 (pipeline->graphics.prim_restart_enable &&
1978 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
1979 (prim != V_008958_DI_PT_POINTLIST &&
1980 prim != V_008958_DI_PT_LINESTRIP &&
1981 prim != V_008958_DI_PT_TRISTRIP))))
1982 pipeline->graphics.wd_switch_on_eop = true;
1983 }
1984
1985 pipeline->graphics.ia_switch_on_eoi = false;
1986 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1987 pipeline->graphics.ia_switch_on_eoi = true;
1988 if (radv_pipeline_has_gs(pipeline) &&
1989 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
1990 pipeline->graphics.ia_switch_on_eoi = true;
1991 if (radv_pipeline_has_tess(pipeline)) {
1992 /* SWITCH_ON_EOI must be set if PrimID is used. */
1993 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
1994 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
1995 pipeline->graphics.ia_switch_on_eoi = true;
1996 }
1997
1998 pipeline->graphics.partial_vs_wave = false;
1999 if (radv_pipeline_has_tess(pipeline)) {
2000 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2001 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2002 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2003 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2004 radv_pipeline_has_gs(pipeline))
2005 pipeline->graphics.partial_vs_wave = true;
2006 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2007 if (device->has_distributed_tess) {
2008 if (radv_pipeline_has_gs(pipeline)) {
2009 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2010 device->physical_device->rad_info.family == CHIP_FIJI ||
2011 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2012 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2013 device->physical_device->rad_info.family == CHIP_POLARIS12)
2014 pipeline->graphics.partial_vs_wave = true;
2015 } else {
2016 pipeline->graphics.partial_vs_wave = true;
2017 }
2018 }
2019 }
2020
2021 pipeline->graphics.base_ia_multi_vgt_param =
2022 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
2023 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
2024 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
2025 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
2026 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
2027
2028 const VkPipelineVertexInputStateCreateInfo *vi_info =
2029 pCreateInfo->pVertexInputState;
2030 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2031
2032 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2033 const VkVertexInputAttributeDescription *desc =
2034 &vi_info->pVertexAttributeDescriptions[i];
2035 unsigned loc = desc->location;
2036 const struct vk_format_description *format_desc;
2037 int first_non_void;
2038 uint32_t num_format, data_format;
2039 format_desc = vk_format_description(desc->format);
2040 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2041
2042 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2043 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2044
2045 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2046 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2047 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2048 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2049 S_008F0C_NUM_FORMAT(num_format) |
2050 S_008F0C_DATA_FORMAT(data_format);
2051 velems->format_size[loc] = format_desc->block.bits / 8;
2052 velems->offset[loc] = desc->offset;
2053 velems->binding[loc] = desc->binding;
2054 velems->count = MAX2(velems->count, loc + 1);
2055 }
2056
2057 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2058 const VkVertexInputBindingDescription *desc =
2059 &vi_info->pVertexBindingDescriptions[i];
2060
2061 pipeline->binding_stride[desc->binding] = desc->stride;
2062 }
2063
2064 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2065 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2066 if (loc->sgpr_idx != -1) {
2067 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2068 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2069 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2070 pipeline->graphics.vtx_emit_num = 3;
2071 else
2072 pipeline->graphics.vtx_emit_num = 2;
2073 }
2074 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2075 radv_dump_pipeline_stats(device, pipeline);
2076 }
2077
2078 result = radv_pipeline_scratch_init(device, pipeline);
2079 return result;
2080 }
2081
2082 VkResult
2083 radv_graphics_pipeline_create(
2084 VkDevice _device,
2085 VkPipelineCache _cache,
2086 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2087 const struct radv_graphics_pipeline_create_info *extra,
2088 const VkAllocationCallbacks *pAllocator,
2089 VkPipeline *pPipeline)
2090 {
2091 RADV_FROM_HANDLE(radv_device, device, _device);
2092 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2093 struct radv_pipeline *pipeline;
2094 VkResult result;
2095
2096 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2097 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2098 if (pipeline == NULL)
2099 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2100
2101 memset(pipeline, 0, sizeof(*pipeline));
2102 result = radv_pipeline_init(pipeline, device, cache,
2103 pCreateInfo, extra, pAllocator);
2104 if (result != VK_SUCCESS) {
2105 radv_pipeline_destroy(device, pipeline, pAllocator);
2106 return result;
2107 }
2108
2109 *pPipeline = radv_pipeline_to_handle(pipeline);
2110
2111 return VK_SUCCESS;
2112 }
2113
2114 VkResult radv_CreateGraphicsPipelines(
2115 VkDevice _device,
2116 VkPipelineCache pipelineCache,
2117 uint32_t count,
2118 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2119 const VkAllocationCallbacks* pAllocator,
2120 VkPipeline* pPipelines)
2121 {
2122 VkResult result = VK_SUCCESS;
2123 unsigned i = 0;
2124
2125 for (; i < count; i++) {
2126 VkResult r;
2127 r = radv_graphics_pipeline_create(_device,
2128 pipelineCache,
2129 &pCreateInfos[i],
2130 NULL, pAllocator, &pPipelines[i]);
2131 if (r != VK_SUCCESS) {
2132 result = r;
2133 pPipelines[i] = VK_NULL_HANDLE;
2134 }
2135 }
2136
2137 return result;
2138 }
2139
2140 static VkResult radv_compute_pipeline_create(
2141 VkDevice _device,
2142 VkPipelineCache _cache,
2143 const VkComputePipelineCreateInfo* pCreateInfo,
2144 const VkAllocationCallbacks* pAllocator,
2145 VkPipeline* pPipeline)
2146 {
2147 RADV_FROM_HANDLE(radv_device, device, _device);
2148 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2149 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2150 struct radv_pipeline *pipeline;
2151 VkResult result;
2152
2153 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2154 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2155 if (pipeline == NULL)
2156 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2157
2158 memset(pipeline, 0, sizeof(*pipeline));
2159 pipeline->device = device;
2160 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2161
2162 pipeline->shaders[MESA_SHADER_COMPUTE] =
2163 radv_pipeline_compile(pipeline, cache, module,
2164 pCreateInfo->stage.pName,
2165 MESA_SHADER_COMPUTE,
2166 pCreateInfo->stage.pSpecializationInfo,
2167 pipeline->layout, NULL);
2168
2169
2170 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2171 result = radv_pipeline_scratch_init(device, pipeline);
2172 if (result != VK_SUCCESS) {
2173 radv_pipeline_destroy(device, pipeline, pAllocator);
2174 return result;
2175 }
2176
2177 *pPipeline = radv_pipeline_to_handle(pipeline);
2178
2179 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2180 radv_dump_pipeline_stats(device, pipeline);
2181 }
2182 return VK_SUCCESS;
2183 }
2184 VkResult radv_CreateComputePipelines(
2185 VkDevice _device,
2186 VkPipelineCache pipelineCache,
2187 uint32_t count,
2188 const VkComputePipelineCreateInfo* pCreateInfos,
2189 const VkAllocationCallbacks* pAllocator,
2190 VkPipeline* pPipelines)
2191 {
2192 VkResult result = VK_SUCCESS;
2193
2194 unsigned i = 0;
2195 for (; i < count; i++) {
2196 VkResult r;
2197 r = radv_compute_pipeline_create(_device, pipelineCache,
2198 &pCreateInfos[i],
2199 pAllocator, &pPipelines[i]);
2200 if (r != VK_SUCCESS) {
2201 result = r;
2202 pPipelines[i] = VK_NULL_HANDLE;
2203 }
2204 }
2205
2206 return result;
2207 }