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radv: Combine vs and tes output keys parts.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50 #include "main/menums.h"
51
52 struct radv_blend_state {
53 uint32_t blend_enable_4bit;
54 uint32_t need_src_alpha;
55
56 uint32_t cb_color_control;
57 uint32_t cb_target_mask;
58 uint32_t cb_target_enabled_4bit;
59 uint32_t sx_mrt_blend_opt[8];
60 uint32_t cb_blend_control[8];
61
62 uint32_t spi_shader_col_format;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 struct radv_gs_state {
93 uint32_t vgt_gs_onchip_cntl;
94 uint32_t vgt_gs_max_prims_per_subgroup;
95 uint32_t vgt_esgs_ring_itemsize;
96 uint32_t lds_size;
97 };
98
99 static void
100 radv_pipeline_destroy(struct radv_device *device,
101 struct radv_pipeline *pipeline,
102 const VkAllocationCallbacks* allocator)
103 {
104 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
105 if (pipeline->shaders[i])
106 radv_shader_variant_destroy(device, pipeline->shaders[i]);
107
108 if (pipeline->gs_copy_shader)
109 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
110
111 if(pipeline->cs.buf)
112 free(pipeline->cs.buf);
113 vk_free2(&device->alloc, allocator, pipeline);
114 }
115
116 void radv_DestroyPipeline(
117 VkDevice _device,
118 VkPipeline _pipeline,
119 const VkAllocationCallbacks* pAllocator)
120 {
121 RADV_FROM_HANDLE(radv_device, device, _device);
122 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
123
124 if (!_pipeline)
125 return;
126
127 radv_pipeline_destroy(device, pipeline, pAllocator);
128 }
129
130 static uint32_t get_hash_flags(struct radv_device *device)
131 {
132 uint32_t hash_flags = 0;
133
134 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
135 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
136 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
137 hash_flags |= RADV_HASH_SHADER_SISCHED;
138 return hash_flags;
139 }
140
141 static VkResult
142 radv_pipeline_scratch_init(struct radv_device *device,
143 struct radv_pipeline *pipeline)
144 {
145 unsigned scratch_bytes_per_wave = 0;
146 unsigned max_waves = 0;
147 unsigned min_waves = 1;
148
149 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
150 if (pipeline->shaders[i]) {
151 unsigned max_stage_waves = device->scratch_waves;
152
153 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
154 pipeline->shaders[i]->config.scratch_bytes_per_wave);
155
156 max_stage_waves = MIN2(max_stage_waves,
157 4 * device->physical_device->rad_info.num_good_compute_units *
158 (256 / pipeline->shaders[i]->config.num_vgprs));
159 max_waves = MAX2(max_waves, max_stage_waves);
160 }
161 }
162
163 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
164 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
165 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
167 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
168 }
169
170 if (scratch_bytes_per_wave)
171 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
172
173 if (scratch_bytes_per_wave && max_waves < min_waves) {
174 /* Not really true at this moment, but will be true on first
175 * execution. Avoid having hanging shaders. */
176 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
177 }
178 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
179 pipeline->max_waves = max_waves;
180 return VK_SUCCESS;
181 }
182
183 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
184 {
185 switch (op) {
186 case VK_LOGIC_OP_CLEAR:
187 return V_028808_ROP3_CLEAR;
188 case VK_LOGIC_OP_AND:
189 return V_028808_ROP3_AND;
190 case VK_LOGIC_OP_AND_REVERSE:
191 return V_028808_ROP3_AND_REVERSE;
192 case VK_LOGIC_OP_COPY:
193 return V_028808_ROP3_COPY;
194 case VK_LOGIC_OP_AND_INVERTED:
195 return V_028808_ROP3_AND_INVERTED;
196 case VK_LOGIC_OP_NO_OP:
197 return V_028808_ROP3_NO_OP;
198 case VK_LOGIC_OP_XOR:
199 return V_028808_ROP3_XOR;
200 case VK_LOGIC_OP_OR:
201 return V_028808_ROP3_OR;
202 case VK_LOGIC_OP_NOR:
203 return V_028808_ROP3_NOR;
204 case VK_LOGIC_OP_EQUIVALENT:
205 return V_028808_ROP3_EQUIVALENT;
206 case VK_LOGIC_OP_INVERT:
207 return V_028808_ROP3_INVERT;
208 case VK_LOGIC_OP_OR_REVERSE:
209 return V_028808_ROP3_OR_REVERSE;
210 case VK_LOGIC_OP_COPY_INVERTED:
211 return V_028808_ROP3_COPY_INVERTED;
212 case VK_LOGIC_OP_OR_INVERTED:
213 return V_028808_ROP3_OR_INVERTED;
214 case VK_LOGIC_OP_NAND:
215 return V_028808_ROP3_NAND;
216 case VK_LOGIC_OP_SET:
217 return V_028808_ROP3_SET;
218 default:
219 unreachable("Unhandled logic op");
220 }
221 }
222
223
224 static uint32_t si_translate_blend_function(VkBlendOp op)
225 {
226 switch (op) {
227 case VK_BLEND_OP_ADD:
228 return V_028780_COMB_DST_PLUS_SRC;
229 case VK_BLEND_OP_SUBTRACT:
230 return V_028780_COMB_SRC_MINUS_DST;
231 case VK_BLEND_OP_REVERSE_SUBTRACT:
232 return V_028780_COMB_DST_MINUS_SRC;
233 case VK_BLEND_OP_MIN:
234 return V_028780_COMB_MIN_DST_SRC;
235 case VK_BLEND_OP_MAX:
236 return V_028780_COMB_MAX_DST_SRC;
237 default:
238 return 0;
239 }
240 }
241
242 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
243 {
244 switch (factor) {
245 case VK_BLEND_FACTOR_ZERO:
246 return V_028780_BLEND_ZERO;
247 case VK_BLEND_FACTOR_ONE:
248 return V_028780_BLEND_ONE;
249 case VK_BLEND_FACTOR_SRC_COLOR:
250 return V_028780_BLEND_SRC_COLOR;
251 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
252 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
253 case VK_BLEND_FACTOR_DST_COLOR:
254 return V_028780_BLEND_DST_COLOR;
255 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
256 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
257 case VK_BLEND_FACTOR_SRC_ALPHA:
258 return V_028780_BLEND_SRC_ALPHA;
259 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
260 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
261 case VK_BLEND_FACTOR_DST_ALPHA:
262 return V_028780_BLEND_DST_ALPHA;
263 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
264 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
265 case VK_BLEND_FACTOR_CONSTANT_COLOR:
266 return V_028780_BLEND_CONSTANT_COLOR;
267 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
268 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
269 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
270 return V_028780_BLEND_CONSTANT_ALPHA;
271 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
272 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
273 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
274 return V_028780_BLEND_SRC_ALPHA_SATURATE;
275 case VK_BLEND_FACTOR_SRC1_COLOR:
276 return V_028780_BLEND_SRC1_COLOR;
277 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
278 return V_028780_BLEND_INV_SRC1_COLOR;
279 case VK_BLEND_FACTOR_SRC1_ALPHA:
280 return V_028780_BLEND_SRC1_ALPHA;
281 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
282 return V_028780_BLEND_INV_SRC1_ALPHA;
283 default:
284 return 0;
285 }
286 }
287
288 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
289 {
290 switch (op) {
291 case VK_BLEND_OP_ADD:
292 return V_028760_OPT_COMB_ADD;
293 case VK_BLEND_OP_SUBTRACT:
294 return V_028760_OPT_COMB_SUBTRACT;
295 case VK_BLEND_OP_REVERSE_SUBTRACT:
296 return V_028760_OPT_COMB_REVSUBTRACT;
297 case VK_BLEND_OP_MIN:
298 return V_028760_OPT_COMB_MIN;
299 case VK_BLEND_OP_MAX:
300 return V_028760_OPT_COMB_MAX;
301 default:
302 return V_028760_OPT_COMB_BLEND_DISABLED;
303 }
304 }
305
306 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
307 {
308 switch (factor) {
309 case VK_BLEND_FACTOR_ZERO:
310 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
311 case VK_BLEND_FACTOR_ONE:
312 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
313 case VK_BLEND_FACTOR_SRC_COLOR:
314 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
315 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
316 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
317 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
318 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
319 case VK_BLEND_FACTOR_SRC_ALPHA:
320 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
321 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
322 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
323 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
324 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
325 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
326 default:
327 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
328 }
329 }
330
331 /**
332 * Get rid of DST in the blend factors by commuting the operands:
333 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
334 */
335 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
336 unsigned *dst_factor, unsigned expected_dst,
337 unsigned replacement_src)
338 {
339 if (*src_factor == expected_dst &&
340 *dst_factor == VK_BLEND_FACTOR_ZERO) {
341 *src_factor = VK_BLEND_FACTOR_ZERO;
342 *dst_factor = replacement_src;
343
344 /* Commuting the operands requires reversing subtractions. */
345 if (*func == VK_BLEND_OP_SUBTRACT)
346 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
347 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
348 *func = VK_BLEND_OP_SUBTRACT;
349 }
350 }
351
352 static bool si_blend_factor_uses_dst(unsigned factor)
353 {
354 return factor == VK_BLEND_FACTOR_DST_COLOR ||
355 factor == VK_BLEND_FACTOR_DST_ALPHA ||
356 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
357 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
358 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
359 }
360
361 static bool is_dual_src(VkBlendFactor factor)
362 {
363 switch (factor) {
364 case VK_BLEND_FACTOR_SRC1_COLOR:
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
366 case VK_BLEND_FACTOR_SRC1_ALPHA:
367 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
368 return true;
369 default:
370 return false;
371 }
372 }
373
374 static unsigned si_choose_spi_color_format(VkFormat vk_format,
375 bool blend_enable,
376 bool blend_need_alpha)
377 {
378 const struct vk_format_description *desc = vk_format_description(vk_format);
379 unsigned format, ntype, swap;
380
381 /* Alpha is needed for alpha-to-coverage.
382 * Blending may be with or without alpha.
383 */
384 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
385 unsigned alpha = 0; /* exports alpha, but may not support blending */
386 unsigned blend = 0; /* supports blending, but may not export alpha */
387 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
388
389 format = radv_translate_colorformat(vk_format);
390 ntype = radv_translate_color_numformat(vk_format, desc,
391 vk_format_get_first_non_void_channel(vk_format));
392 swap = radv_translate_colorswap(vk_format, false);
393
394 /* Choose the SPI color formats. These are required values for Stoney/RB+.
395 * Other chips have multiple choices, though they are not necessarily better.
396 */
397 switch (format) {
398 case V_028C70_COLOR_5_6_5:
399 case V_028C70_COLOR_1_5_5_5:
400 case V_028C70_COLOR_5_5_5_1:
401 case V_028C70_COLOR_4_4_4_4:
402 case V_028C70_COLOR_10_11_11:
403 case V_028C70_COLOR_11_11_10:
404 case V_028C70_COLOR_8:
405 case V_028C70_COLOR_8_8:
406 case V_028C70_COLOR_8_8_8_8:
407 case V_028C70_COLOR_10_10_10_2:
408 case V_028C70_COLOR_2_10_10_10:
409 if (ntype == V_028C70_NUMBER_UINT)
410 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
411 else if (ntype == V_028C70_NUMBER_SINT)
412 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
413 else
414 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
415 break;
416
417 case V_028C70_COLOR_16:
418 case V_028C70_COLOR_16_16:
419 case V_028C70_COLOR_16_16_16_16:
420 if (ntype == V_028C70_NUMBER_UNORM ||
421 ntype == V_028C70_NUMBER_SNORM) {
422 /* UNORM16 and SNORM16 don't support blending */
423 if (ntype == V_028C70_NUMBER_UNORM)
424 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
425 else
426 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
427
428 /* Use 32 bits per channel for blending. */
429 if (format == V_028C70_COLOR_16) {
430 if (swap == V_028C70_SWAP_STD) { /* R */
431 blend = V_028714_SPI_SHADER_32_R;
432 blend_alpha = V_028714_SPI_SHADER_32_AR;
433 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
434 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
435 else
436 assert(0);
437 } else if (format == V_028C70_COLOR_16_16) {
438 if (swap == V_028C70_SWAP_STD) { /* RG */
439 blend = V_028714_SPI_SHADER_32_GR;
440 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
441 } else if (swap == V_028C70_SWAP_ALT) /* RA */
442 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
443 else
444 assert(0);
445 } else /* 16_16_16_16 */
446 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
447 } else if (ntype == V_028C70_NUMBER_UINT)
448 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
449 else if (ntype == V_028C70_NUMBER_SINT)
450 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
451 else if (ntype == V_028C70_NUMBER_FLOAT)
452 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
453 else
454 assert(0);
455 break;
456
457 case V_028C70_COLOR_32:
458 if (swap == V_028C70_SWAP_STD) { /* R */
459 blend = normal = V_028714_SPI_SHADER_32_R;
460 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
461 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
462 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
463 else
464 assert(0);
465 break;
466
467 case V_028C70_COLOR_32_32:
468 if (swap == V_028C70_SWAP_STD) { /* RG */
469 blend = normal = V_028714_SPI_SHADER_32_GR;
470 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
471 } else if (swap == V_028C70_SWAP_ALT) /* RA */
472 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
473 else
474 assert(0);
475 break;
476
477 case V_028C70_COLOR_32_32_32_32:
478 case V_028C70_COLOR_8_24:
479 case V_028C70_COLOR_24_8:
480 case V_028C70_COLOR_X24_8_32_FLOAT:
481 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
482 break;
483
484 default:
485 unreachable("unhandled blend format");
486 }
487
488 if (blend_enable && blend_need_alpha)
489 return blend_alpha;
490 else if(blend_need_alpha)
491 return alpha;
492 else if(blend_enable)
493 return blend;
494 else
495 return normal;
496 }
497
498 static void
499 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
500 const VkGraphicsPipelineCreateInfo *pCreateInfo,
501 struct radv_blend_state *blend)
502 {
503 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
504 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
505 unsigned col_format = 0;
506 unsigned num_targets;
507
508 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
509 unsigned cf;
510
511 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
512 cf = V_028714_SPI_SHADER_ZERO;
513 } else {
514 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
515 bool blend_enable =
516 blend->blend_enable_4bit & (0xfu << (i * 4));
517
518 cf = si_choose_spi_color_format(attachment->format,
519 blend_enable,
520 blend->need_src_alpha & (1 << i));
521 }
522
523 col_format |= cf << (4 * i);
524 }
525
526 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
527 /* When a subpass doesn't have any color attachments, write the
528 * alpha channel of MRT0 when alpha coverage is enabled because
529 * the depth attachment needs it.
530 */
531 col_format |= V_028714_SPI_SHADER_32_AR;
532 }
533
534 /* If the i-th target format is set, all previous target formats must
535 * be non-zero to avoid hangs.
536 */
537 num_targets = (util_last_bit(col_format) + 3) / 4;
538 for (unsigned i = 0; i < num_targets; i++) {
539 if (!(col_format & (0xf << (i * 4)))) {
540 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
541 }
542 }
543
544 /* The output for dual source blending should have the same format as
545 * the first output.
546 */
547 if (blend->mrt0_is_dual_src)
548 col_format |= (col_format & 0xf) << 4;
549
550 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
551 blend->spi_shader_col_format = col_format;
552 }
553
554 static bool
555 format_is_int8(VkFormat format)
556 {
557 const struct vk_format_description *desc = vk_format_description(format);
558 int channel = vk_format_get_first_non_void_channel(format);
559
560 return channel >= 0 && desc->channel[channel].pure_integer &&
561 desc->channel[channel].size == 8;
562 }
563
564 static bool
565 format_is_int10(VkFormat format)
566 {
567 const struct vk_format_description *desc = vk_format_description(format);
568
569 if (desc->nr_channels != 4)
570 return false;
571 for (unsigned i = 0; i < 4; i++) {
572 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
573 return true;
574 }
575 return false;
576 }
577
578 /*
579 * Ordered so that for each i,
580 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
581 */
582 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
583 VK_FORMAT_R32_SFLOAT,
584 VK_FORMAT_R32G32_SFLOAT,
585 VK_FORMAT_R8G8B8A8_UNORM,
586 VK_FORMAT_R16G16B16A16_UNORM,
587 VK_FORMAT_R16G16B16A16_SNORM,
588 VK_FORMAT_R16G16B16A16_UINT,
589 VK_FORMAT_R16G16B16A16_SINT,
590 VK_FORMAT_R32G32B32A32_SFLOAT,
591 VK_FORMAT_R8G8B8A8_UINT,
592 VK_FORMAT_R8G8B8A8_SINT,
593 VK_FORMAT_A2R10G10B10_UINT_PACK32,
594 VK_FORMAT_A2R10G10B10_SINT_PACK32,
595 };
596
597 unsigned radv_format_meta_fs_key(VkFormat format)
598 {
599 unsigned col_format = si_choose_spi_color_format(format, false, false);
600
601 assert(col_format != V_028714_SPI_SHADER_32_AR);
602 if (col_format >= V_028714_SPI_SHADER_32_AR)
603 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
604
605 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
606 bool is_int8 = format_is_int8(format);
607 bool is_int10 = format_is_int10(format);
608
609 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
610 }
611
612 static void
613 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
614 unsigned *is_int8, unsigned *is_int10)
615 {
616 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
617 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
618 *is_int8 = 0;
619 *is_int10 = 0;
620
621 for (unsigned i = 0; i < subpass->color_count; ++i) {
622 struct radv_render_pass_attachment *attachment;
623
624 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
625 continue;
626
627 attachment = pass->attachments + subpass->color_attachments[i].attachment;
628
629 if (format_is_int8(attachment->format))
630 *is_int8 |= 1 << i;
631 if (format_is_int10(attachment->format))
632 *is_int10 |= 1 << i;
633 }
634 }
635
636 static void
637 radv_blend_check_commutativity(struct radv_blend_state *blend,
638 VkBlendOp op, VkBlendFactor src,
639 VkBlendFactor dst, unsigned chanmask)
640 {
641 /* Src factor is allowed when it does not depend on Dst. */
642 static const uint32_t src_allowed =
643 (1u << VK_BLEND_FACTOR_ONE) |
644 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
645 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
646 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
647 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
648 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
649 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
650 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
651 (1u << VK_BLEND_FACTOR_ZERO) |
652 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
653 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
654 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
655 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
656 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
657 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
658
659 if (dst == VK_BLEND_FACTOR_ONE &&
660 (src_allowed & (1u << src))) {
661 /* Addition is commutative, but floating point addition isn't
662 * associative: subtle changes can be introduced via different
663 * rounding. Be conservative, only enable for min and max.
664 */
665 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
666 blend->commutative_4bit |= chanmask;
667 }
668 }
669
670 static struct radv_blend_state
671 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
672 const VkGraphicsPipelineCreateInfo *pCreateInfo,
673 const struct radv_graphics_pipeline_create_info *extra)
674 {
675 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
676 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
677 struct radv_blend_state blend = {0};
678 unsigned mode = V_028808_CB_NORMAL;
679 int i;
680
681 if (!vkblend)
682 return blend;
683
684 if (extra && extra->custom_blend_mode) {
685 blend.single_cb_enable = true;
686 mode = extra->custom_blend_mode;
687 }
688 blend.cb_color_control = 0;
689 if (vkblend->logicOpEnable)
690 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
691 else
692 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
693
694 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
695 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
696 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
697 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
698 S_028B70_OFFSET_ROUND(1);
699
700 if (vkms && vkms->alphaToCoverageEnable) {
701 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
702 blend.need_src_alpha |= 0x1;
703 }
704
705 blend.cb_target_mask = 0;
706 for (i = 0; i < vkblend->attachmentCount; i++) {
707 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
708 unsigned blend_cntl = 0;
709 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
710 VkBlendOp eqRGB = att->colorBlendOp;
711 VkBlendFactor srcRGB = att->srcColorBlendFactor;
712 VkBlendFactor dstRGB = att->dstColorBlendFactor;
713 VkBlendOp eqA = att->alphaBlendOp;
714 VkBlendFactor srcA = att->srcAlphaBlendFactor;
715 VkBlendFactor dstA = att->dstAlphaBlendFactor;
716
717 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
718
719 if (!att->colorWriteMask)
720 continue;
721
722 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
723 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
724 if (!att->blendEnable) {
725 blend.cb_blend_control[i] = blend_cntl;
726 continue;
727 }
728
729 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
730 if (i == 0)
731 blend.mrt0_is_dual_src = true;
732
733 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
734 srcRGB = VK_BLEND_FACTOR_ONE;
735 dstRGB = VK_BLEND_FACTOR_ONE;
736 }
737 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
738 srcA = VK_BLEND_FACTOR_ONE;
739 dstA = VK_BLEND_FACTOR_ONE;
740 }
741
742 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
743 0x7 << (4 * i));
744 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
745 0x8 << (4 * i));
746
747 /* Blending optimizations for RB+.
748 * These transformations don't change the behavior.
749 *
750 * First, get rid of DST in the blend factors:
751 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
752 */
753 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
754 VK_BLEND_FACTOR_DST_COLOR,
755 VK_BLEND_FACTOR_SRC_COLOR);
756
757 si_blend_remove_dst(&eqA, &srcA, &dstA,
758 VK_BLEND_FACTOR_DST_COLOR,
759 VK_BLEND_FACTOR_SRC_COLOR);
760
761 si_blend_remove_dst(&eqA, &srcA, &dstA,
762 VK_BLEND_FACTOR_DST_ALPHA,
763 VK_BLEND_FACTOR_SRC_ALPHA);
764
765 /* Look up the ideal settings from tables. */
766 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
767 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
768 srcA_opt = si_translate_blend_opt_factor(srcA, true);
769 dstA_opt = si_translate_blend_opt_factor(dstA, true);
770
771 /* Handle interdependencies. */
772 if (si_blend_factor_uses_dst(srcRGB))
773 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
774 if (si_blend_factor_uses_dst(srcA))
775 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
776
777 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
778 (dstRGB == VK_BLEND_FACTOR_ZERO ||
779 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
781 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
782
783 /* Set the final value. */
784 blend.sx_mrt_blend_opt[i] =
785 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
786 S_028760_COLOR_DST_OPT(dstRGB_opt) |
787 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
788 S_028760_ALPHA_SRC_OPT(srcA_opt) |
789 S_028760_ALPHA_DST_OPT(dstA_opt) |
790 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
791 blend_cntl |= S_028780_ENABLE(1);
792
793 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
794 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
795 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
796 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
797 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
798 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
799 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
800 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
801 }
802 blend.cb_blend_control[i] = blend_cntl;
803
804 blend.blend_enable_4bit |= 0xfu << (i * 4);
805
806 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
807 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
808 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
809 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
810 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
811 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
812 blend.need_src_alpha |= 1 << i;
813 }
814 for (i = vkblend->attachmentCount; i < 8; i++) {
815 blend.cb_blend_control[i] = 0;
816 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
817 }
818
819 if (pipeline->device->physical_device->has_rbplus) {
820 /* Disable RB+ blend optimizations for dual source blending. */
821 if (blend.mrt0_is_dual_src) {
822 for (i = 0; i < 8; i++) {
823 blend.sx_mrt_blend_opt[i] =
824 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
825 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
826 }
827 }
828
829 /* RB+ doesn't work with dual source blending, logic op and
830 * RESOLVE.
831 */
832 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
833 mode == V_028808_CB_RESOLVE)
834 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
835 }
836
837 if (blend.cb_target_mask)
838 blend.cb_color_control |= S_028808_MODE(mode);
839 else
840 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
841
842 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
843 return blend;
844 }
845
846 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
847 {
848 switch (op) {
849 case VK_STENCIL_OP_KEEP:
850 return V_02842C_STENCIL_KEEP;
851 case VK_STENCIL_OP_ZERO:
852 return V_02842C_STENCIL_ZERO;
853 case VK_STENCIL_OP_REPLACE:
854 return V_02842C_STENCIL_REPLACE_TEST;
855 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
856 return V_02842C_STENCIL_ADD_CLAMP;
857 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
858 return V_02842C_STENCIL_SUB_CLAMP;
859 case VK_STENCIL_OP_INVERT:
860 return V_02842C_STENCIL_INVERT;
861 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
862 return V_02842C_STENCIL_ADD_WRAP;
863 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
864 return V_02842C_STENCIL_SUB_WRAP;
865 default:
866 return 0;
867 }
868 }
869
870 static uint32_t si_translate_fill(VkPolygonMode func)
871 {
872 switch(func) {
873 case VK_POLYGON_MODE_FILL:
874 return V_028814_X_DRAW_TRIANGLES;
875 case VK_POLYGON_MODE_LINE:
876 return V_028814_X_DRAW_LINES;
877 case VK_POLYGON_MODE_POINT:
878 return V_028814_X_DRAW_POINTS;
879 default:
880 assert(0);
881 return V_028814_X_DRAW_POINTS;
882 }
883 }
884
885 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
886 {
887 uint32_t num_samples = vkms->rasterizationSamples;
888 uint32_t ps_iter_samples = 1;
889
890 if (vkms->sampleShadingEnable) {
891 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
892 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
893 }
894 return ps_iter_samples;
895 }
896
897 static bool
898 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
899 {
900 return pCreateInfo->depthTestEnable &&
901 pCreateInfo->depthWriteEnable &&
902 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
903 }
904
905 static bool
906 radv_writes_stencil(const VkStencilOpState *state)
907 {
908 return state->writeMask &&
909 (state->failOp != VK_STENCIL_OP_KEEP ||
910 state->passOp != VK_STENCIL_OP_KEEP ||
911 state->depthFailOp != VK_STENCIL_OP_KEEP);
912 }
913
914 static bool
915 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
916 {
917 return pCreateInfo->stencilTestEnable &&
918 (radv_writes_stencil(&pCreateInfo->front) ||
919 radv_writes_stencil(&pCreateInfo->back));
920 }
921
922 static bool
923 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
924 {
925 return radv_is_depth_write_enabled(pCreateInfo) ||
926 radv_is_stencil_write_enabled(pCreateInfo);
927 }
928
929 static bool
930 radv_order_invariant_stencil_op(VkStencilOp op)
931 {
932 /* REPLACE is normally order invariant, except when the stencil
933 * reference value is written by the fragment shader. Tracking this
934 * interaction does not seem worth the effort, so be conservative.
935 */
936 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
937 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
938 op != VK_STENCIL_OP_REPLACE;
939 }
940
941 static bool
942 radv_order_invariant_stencil_state(const VkStencilOpState *state)
943 {
944 /* Compute whether, assuming Z writes are disabled, this stencil state
945 * is order invariant in the sense that the set of passing fragments as
946 * well as the final stencil buffer result does not depend on the order
947 * of fragments.
948 */
949 return !state->writeMask ||
950 /* The following assumes that Z writes are disabled. */
951 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
952 radv_order_invariant_stencil_op(state->passOp) &&
953 radv_order_invariant_stencil_op(state->depthFailOp)) ||
954 (state->compareOp == VK_COMPARE_OP_NEVER &&
955 radv_order_invariant_stencil_op(state->failOp));
956 }
957
958 static bool
959 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
960 struct radv_blend_state *blend,
961 const VkGraphicsPipelineCreateInfo *pCreateInfo)
962 {
963 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
964 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
965 unsigned colormask = blend->cb_target_enabled_4bit;
966
967 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
968 return false;
969
970 /* Be conservative if a logic operation is enabled with color buffers. */
971 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
972 return false;
973
974 /* Default depth/stencil invariance when no attachment is bound. */
975 struct radv_dsa_order_invariance dsa_order_invariant = {
976 .zs = true, .pass_set = true
977 };
978
979 if (pCreateInfo->pDepthStencilState &&
980 subpass->depth_stencil_attachment) {
981 const VkPipelineDepthStencilStateCreateInfo *vkds =
982 pCreateInfo->pDepthStencilState;
983 struct radv_render_pass_attachment *attachment =
984 pass->attachments + subpass->depth_stencil_attachment->attachment;
985 bool has_stencil = vk_format_is_stencil(attachment->format);
986 struct radv_dsa_order_invariance order_invariance[2];
987 struct radv_shader_variant *ps =
988 pipeline->shaders[MESA_SHADER_FRAGMENT];
989
990 /* Compute depth/stencil order invariance in order to know if
991 * it's safe to enable out-of-order.
992 */
993 bool zfunc_is_ordered =
994 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
995 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
996 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
997 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
998 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
999
1000 bool nozwrite_and_order_invariant_stencil =
1001 !radv_is_ds_write_enabled(vkds) ||
1002 (!radv_is_depth_write_enabled(vkds) &&
1003 radv_order_invariant_stencil_state(&vkds->front) &&
1004 radv_order_invariant_stencil_state(&vkds->back));
1005
1006 order_invariance[1].zs =
1007 nozwrite_and_order_invariant_stencil ||
1008 (!radv_is_stencil_write_enabled(vkds) &&
1009 zfunc_is_ordered);
1010 order_invariance[0].zs =
1011 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1012
1013 order_invariance[1].pass_set =
1014 nozwrite_and_order_invariant_stencil ||
1015 (!radv_is_stencil_write_enabled(vkds) &&
1016 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1017 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1018 order_invariance[0].pass_set =
1019 !radv_is_depth_write_enabled(vkds) ||
1020 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1021 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1022
1023 dsa_order_invariant = order_invariance[has_stencil];
1024 if (!dsa_order_invariant.zs)
1025 return false;
1026
1027 /* The set of PS invocations is always order invariant,
1028 * except when early Z/S tests are requested.
1029 */
1030 if (ps &&
1031 ps->info.info.ps.writes_memory &&
1032 ps->info.fs.early_fragment_test &&
1033 !dsa_order_invariant.pass_set)
1034 return false;
1035
1036 /* Determine if out-of-order rasterization should be disabled
1037 * when occlusion queries are used.
1038 */
1039 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1040 !dsa_order_invariant.pass_set;
1041 }
1042
1043 /* No color buffers are enabled for writing. */
1044 if (!colormask)
1045 return true;
1046
1047 unsigned blendmask = colormask & blend->blend_enable_4bit;
1048
1049 if (blendmask) {
1050 /* Only commutative blending. */
1051 if (blendmask & ~blend->commutative_4bit)
1052 return false;
1053
1054 if (!dsa_order_invariant.pass_set)
1055 return false;
1056 }
1057
1058 if (colormask & ~blendmask)
1059 return false;
1060
1061 return true;
1062 }
1063
1064 static void
1065 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1066 struct radv_blend_state *blend,
1067 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1068 {
1069 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1070 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1071 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1072 bool out_of_order_rast = false;
1073 int ps_iter_samples = 1;
1074 uint32_t mask = 0xffff;
1075
1076 if (vkms)
1077 ms->num_samples = vkms->rasterizationSamples;
1078 else
1079 ms->num_samples = 1;
1080
1081 if (vkms)
1082 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1083 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1084 ps_iter_samples = ms->num_samples;
1085 }
1086
1087 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1088 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1089 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1090 /* Out-of-order rasterization is explicitly enabled by the
1091 * application.
1092 */
1093 out_of_order_rast = true;
1094 } else {
1095 /* Determine if the driver can enable out-of-order
1096 * rasterization internally.
1097 */
1098 out_of_order_rast =
1099 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1100 }
1101
1102 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1103 ms->pa_sc_aa_config = 0;
1104 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1105 S_028804_INCOHERENT_EQAA_READS(1) |
1106 S_028804_INTERPOLATE_COMP_Z(1) |
1107 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1108 ms->pa_sc_mode_cntl_1 =
1109 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1110 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1111 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1112 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1113 /* always 1: */
1114 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1115 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1116 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1117 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1118 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1119 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1120 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1121 S_028A48_VPORT_SCISSOR_ENABLE(1);
1122
1123 if (ms->num_samples > 1) {
1124 unsigned log_samples = util_logbase2(ms->num_samples);
1125 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1126 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1127 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1128 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1129 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1130 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1131 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1132 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1133 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1134 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1135 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1136 if (ps_iter_samples > 1)
1137 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1138 }
1139
1140 if (vkms && vkms->pSampleMask) {
1141 mask = vkms->pSampleMask[0] & 0xffff;
1142 }
1143
1144 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1145 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1146 }
1147
1148 static bool
1149 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1150 {
1151 switch (topology) {
1152 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1153 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1154 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1155 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1156 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1157 return false;
1158 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1159 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1160 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1161 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1162 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1163 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1164 return true;
1165 default:
1166 unreachable("unhandled primitive type");
1167 }
1168 }
1169
1170 static uint32_t
1171 si_translate_prim(enum VkPrimitiveTopology topology)
1172 {
1173 switch (topology) {
1174 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1175 return V_008958_DI_PT_POINTLIST;
1176 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1177 return V_008958_DI_PT_LINELIST;
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1179 return V_008958_DI_PT_LINESTRIP;
1180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1181 return V_008958_DI_PT_TRILIST;
1182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1183 return V_008958_DI_PT_TRISTRIP;
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1185 return V_008958_DI_PT_TRIFAN;
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1187 return V_008958_DI_PT_LINELIST_ADJ;
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1189 return V_008958_DI_PT_LINESTRIP_ADJ;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1191 return V_008958_DI_PT_TRILIST_ADJ;
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1193 return V_008958_DI_PT_TRISTRIP_ADJ;
1194 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1195 return V_008958_DI_PT_PATCH;
1196 default:
1197 assert(0);
1198 return 0;
1199 }
1200 }
1201
1202 static uint32_t
1203 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1204 {
1205 switch (gl_prim) {
1206 case 0: /* GL_POINTS */
1207 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1208 case 1: /* GL_LINES */
1209 case 3: /* GL_LINE_STRIP */
1210 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1211 case 0x8E7A: /* GL_ISOLINES */
1212 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1213
1214 case 4: /* GL_TRIANGLES */
1215 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1216 case 5: /* GL_TRIANGLE_STRIP */
1217 case 7: /* GL_QUADS */
1218 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1219 default:
1220 assert(0);
1221 return 0;
1222 }
1223 }
1224
1225 static uint32_t
1226 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1227 {
1228 switch (topology) {
1229 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1230 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1231 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1234 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1235 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1236 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1240 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1241 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1242 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1243 default:
1244 assert(0);
1245 return 0;
1246 }
1247 }
1248
1249 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1250 {
1251 switch(state) {
1252 case VK_DYNAMIC_STATE_VIEWPORT:
1253 return RADV_DYNAMIC_VIEWPORT;
1254 case VK_DYNAMIC_STATE_SCISSOR:
1255 return RADV_DYNAMIC_SCISSOR;
1256 case VK_DYNAMIC_STATE_LINE_WIDTH:
1257 return RADV_DYNAMIC_LINE_WIDTH;
1258 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1259 return RADV_DYNAMIC_DEPTH_BIAS;
1260 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1261 return RADV_DYNAMIC_BLEND_CONSTANTS;
1262 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1263 return RADV_DYNAMIC_DEPTH_BOUNDS;
1264 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1265 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1266 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1267 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1268 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1269 return RADV_DYNAMIC_STENCIL_REFERENCE;
1270 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1271 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1272 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1273 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1274 default:
1275 unreachable("Unhandled dynamic state");
1276 }
1277 }
1278
1279 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1280 {
1281 uint32_t states = RADV_DYNAMIC_ALL;
1282
1283 /* If rasterization is disabled we do not care about any of the dynamic states,
1284 * since they are all rasterization related only. */
1285 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1286 return 0;
1287
1288 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1289 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1290
1291 if (!pCreateInfo->pDepthStencilState ||
1292 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1293 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1294
1295 if (!pCreateInfo->pDepthStencilState ||
1296 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1297 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1298 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1299 RADV_DYNAMIC_STENCIL_REFERENCE);
1300
1301 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1302 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1303
1304 if (!pCreateInfo->pMultisampleState ||
1305 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1306 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1307 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1308
1309 /* TODO: blend constants & line width. */
1310
1311 return states;
1312 }
1313
1314
1315 static void
1316 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1317 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1318 {
1319 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1320 uint32_t states = needed_states;
1321 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1322 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1323
1324 pipeline->dynamic_state = default_dynamic_state;
1325 pipeline->graphics.needed_dynamic_state = needed_states;
1326
1327 if (pCreateInfo->pDynamicState) {
1328 /* Remove all of the states that are marked as dynamic */
1329 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1330 for (uint32_t s = 0; s < count; s++)
1331 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1332 }
1333
1334 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1335
1336 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1337 assert(pCreateInfo->pViewportState);
1338
1339 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1340 if (states & RADV_DYNAMIC_VIEWPORT) {
1341 typed_memcpy(dynamic->viewport.viewports,
1342 pCreateInfo->pViewportState->pViewports,
1343 pCreateInfo->pViewportState->viewportCount);
1344 }
1345 }
1346
1347 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1348 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1349 if (states & RADV_DYNAMIC_SCISSOR) {
1350 typed_memcpy(dynamic->scissor.scissors,
1351 pCreateInfo->pViewportState->pScissors,
1352 pCreateInfo->pViewportState->scissorCount);
1353 }
1354 }
1355
1356 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1357 assert(pCreateInfo->pRasterizationState);
1358 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1359 }
1360
1361 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1362 assert(pCreateInfo->pRasterizationState);
1363 dynamic->depth_bias.bias =
1364 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1365 dynamic->depth_bias.clamp =
1366 pCreateInfo->pRasterizationState->depthBiasClamp;
1367 dynamic->depth_bias.slope =
1368 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1369 }
1370
1371 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1372 *
1373 * pColorBlendState is [...] NULL if the pipeline has rasterization
1374 * disabled or if the subpass of the render pass the pipeline is
1375 * created against does not use any color attachments.
1376 */
1377 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1378 assert(pCreateInfo->pColorBlendState);
1379 typed_memcpy(dynamic->blend_constants,
1380 pCreateInfo->pColorBlendState->blendConstants, 4);
1381 }
1382
1383 /* If there is no depthstencil attachment, then don't read
1384 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1385 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1386 * no need to override the depthstencil defaults in
1387 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1388 *
1389 * Section 9.2 of the Vulkan 1.0.15 spec says:
1390 *
1391 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1392 * disabled or if the subpass of the render pass the pipeline is created
1393 * against does not use a depth/stencil attachment.
1394 */
1395 if (needed_states && subpass->depth_stencil_attachment) {
1396 assert(pCreateInfo->pDepthStencilState);
1397
1398 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1399 dynamic->depth_bounds.min =
1400 pCreateInfo->pDepthStencilState->minDepthBounds;
1401 dynamic->depth_bounds.max =
1402 pCreateInfo->pDepthStencilState->maxDepthBounds;
1403 }
1404
1405 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1406 dynamic->stencil_compare_mask.front =
1407 pCreateInfo->pDepthStencilState->front.compareMask;
1408 dynamic->stencil_compare_mask.back =
1409 pCreateInfo->pDepthStencilState->back.compareMask;
1410 }
1411
1412 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1413 dynamic->stencil_write_mask.front =
1414 pCreateInfo->pDepthStencilState->front.writeMask;
1415 dynamic->stencil_write_mask.back =
1416 pCreateInfo->pDepthStencilState->back.writeMask;
1417 }
1418
1419 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1420 dynamic->stencil_reference.front =
1421 pCreateInfo->pDepthStencilState->front.reference;
1422 dynamic->stencil_reference.back =
1423 pCreateInfo->pDepthStencilState->back.reference;
1424 }
1425 }
1426
1427 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1428 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1429 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1430 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1431 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1432 typed_memcpy(dynamic->discard_rectangle.rectangles,
1433 discard_rectangle_info->pDiscardRectangles,
1434 discard_rectangle_info->discardRectangleCount);
1435 }
1436 }
1437
1438 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1439 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1440 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1441 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1442 /* If sampleLocationsEnable is VK_FALSE, the default sample
1443 * locations are used and the values specified in
1444 * sampleLocationsInfo are ignored.
1445 */
1446 if (sample_location_info->sampleLocationsEnable) {
1447 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1448 &sample_location_info->sampleLocationsInfo;
1449
1450 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1451
1452 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1453 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1454 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1455 typed_memcpy(&dynamic->sample_location.locations[0],
1456 pSampleLocationsInfo->pSampleLocations,
1457 pSampleLocationsInfo->sampleLocationsCount);
1458 }
1459 }
1460
1461 pipeline->dynamic_state.mask = states;
1462 }
1463
1464 static struct radv_gs_state
1465 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1466 const struct radv_pipeline *pipeline)
1467 {
1468 struct radv_gs_state gs = {0};
1469 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1470 struct radv_es_output_info *es_info;
1471 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1472 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1473 else
1474 es_info = radv_pipeline_has_tess(pipeline) ?
1475 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1476 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1477
1478 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1479 bool uses_adjacency;
1480 switch(pCreateInfo->pInputAssemblyState->topology) {
1481 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1482 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1483 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1484 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1485 uses_adjacency = true;
1486 break;
1487 default:
1488 uses_adjacency = false;
1489 break;
1490 }
1491
1492 /* All these are in dwords: */
1493 /* We can't allow using the whole LDS, because GS waves compete with
1494 * other shader stages for LDS space. */
1495 const unsigned max_lds_size = 8 * 1024;
1496 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1497 unsigned esgs_lds_size;
1498
1499 /* All these are per subgroup: */
1500 const unsigned max_out_prims = 32 * 1024;
1501 const unsigned max_es_verts = 255;
1502 const unsigned ideal_gs_prims = 64;
1503 unsigned max_gs_prims, gs_prims;
1504 unsigned min_es_verts, es_verts, worst_case_es_verts;
1505
1506 if (uses_adjacency || gs_num_invocations > 1)
1507 max_gs_prims = 127 / gs_num_invocations;
1508 else
1509 max_gs_prims = 255;
1510
1511 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1512 * Make sure we don't go over the maximum value.
1513 */
1514 if (gs_info->gs.vertices_out > 0) {
1515 max_gs_prims = MIN2(max_gs_prims,
1516 max_out_prims /
1517 (gs_info->gs.vertices_out * gs_num_invocations));
1518 }
1519 assert(max_gs_prims > 0);
1520
1521 /* If the primitive has adjacency, halve the number of vertices
1522 * that will be reused in multiple primitives.
1523 */
1524 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1525
1526 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1527 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1528
1529 /* Compute ESGS LDS size based on the worst case number of ES vertices
1530 * needed to create the target number of GS prims per subgroup.
1531 */
1532 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1533
1534 /* If total LDS usage is too big, refactor partitions based on ratio
1535 * of ESGS item sizes.
1536 */
1537 if (esgs_lds_size > max_lds_size) {
1538 /* Our target GS Prims Per Subgroup was too large. Calculate
1539 * the maximum number of GS Prims Per Subgroup that will fit
1540 * into LDS, capped by the maximum that the hardware can support.
1541 */
1542 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1543 max_gs_prims);
1544 assert(gs_prims > 0);
1545 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1546 max_es_verts);
1547
1548 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1549 assert(esgs_lds_size <= max_lds_size);
1550 }
1551
1552 /* Now calculate remaining ESGS information. */
1553 if (esgs_lds_size)
1554 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1555 else
1556 es_verts = max_es_verts;
1557
1558 /* Vertices for adjacency primitives are not always reused, so restore
1559 * it for ES_VERTS_PER_SUBGRP.
1560 */
1561 min_es_verts = gs_info->gs.vertices_in;
1562
1563 /* For normal primitives, the VGT only checks if they are past the ES
1564 * verts per subgroup after allocating a full GS primitive and if they
1565 * are, kick off a new subgroup. But if those additional ES verts are
1566 * unique (e.g. not reused) we need to make sure there is enough LDS
1567 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1568 */
1569 es_verts -= min_es_verts - 1;
1570
1571 uint32_t es_verts_per_subgroup = es_verts;
1572 uint32_t gs_prims_per_subgroup = gs_prims;
1573 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1574 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1575 gs.lds_size = align(esgs_lds_size, 128) / 128;
1576 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1577 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1578 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1579 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1580 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1581 assert(max_prims_per_subgroup <= max_out_prims);
1582
1583 return gs;
1584 }
1585
1586 static void
1587 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1588 {
1589 struct radv_device *device = pipeline->device;
1590 unsigned num_se = device->physical_device->rad_info.max_se;
1591 unsigned wave_size = 64;
1592 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1593 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1594 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1595 */
1596 unsigned gs_vertex_reuse =
1597 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1598 unsigned alignment = 256 * num_se;
1599 /* The maximum size is 63.999 MB per SE. */
1600 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1601 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1602
1603 /* Calculate the minimum size. */
1604 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1605 wave_size, alignment);
1606 /* These are recommended sizes, not minimum sizes. */
1607 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1608 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1609 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1610 gs_info->gs.max_gsvs_emit_size;
1611
1612 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1613 esgs_ring_size = align(esgs_ring_size, alignment);
1614 gsvs_ring_size = align(gsvs_ring_size, alignment);
1615
1616 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1617 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1618
1619 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1620 }
1621
1622 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1623 unsigned *lds_size)
1624 {
1625 /* If tessellation is all offchip and on-chip GS isn't used, this
1626 * workaround is not needed.
1627 */
1628 return;
1629
1630 /* SPI barrier management bug:
1631 * Make sure we have at least 4k of LDS in use to avoid the bug.
1632 * It applies to workgroup sizes of more than one wavefront.
1633 */
1634 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1635 device->physical_device->rad_info.family == CHIP_KABINI)
1636 *lds_size = MAX2(*lds_size, 8);
1637 }
1638
1639 struct radv_shader_variant *
1640 radv_get_shader(struct radv_pipeline *pipeline,
1641 gl_shader_stage stage)
1642 {
1643 if (stage == MESA_SHADER_VERTEX) {
1644 if (pipeline->shaders[MESA_SHADER_VERTEX])
1645 return pipeline->shaders[MESA_SHADER_VERTEX];
1646 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1647 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1648 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1649 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1650 } else if (stage == MESA_SHADER_TESS_EVAL) {
1651 if (!radv_pipeline_has_tess(pipeline))
1652 return NULL;
1653 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1654 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1655 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1656 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1657 }
1658 return pipeline->shaders[stage];
1659 }
1660
1661 static struct radv_tessellation_state
1662 calculate_tess_state(struct radv_pipeline *pipeline,
1663 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1664 {
1665 unsigned num_tcs_input_cp;
1666 unsigned num_tcs_output_cp;
1667 unsigned lds_size;
1668 unsigned num_patches;
1669 struct radv_tessellation_state tess = {0};
1670
1671 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1672 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1673 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1674
1675 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1676
1677 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1678 assert(lds_size <= 65536);
1679 lds_size = align(lds_size, 512) / 512;
1680 } else {
1681 assert(lds_size <= 32768);
1682 lds_size = align(lds_size, 256) / 256;
1683 }
1684 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1685
1686 tess.lds_size = lds_size;
1687
1688 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1689 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1690 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1691 tess.num_patches = num_patches;
1692
1693 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1694 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1695
1696 switch (tes->info.tes.primitive_mode) {
1697 case GL_TRIANGLES:
1698 type = V_028B6C_TESS_TRIANGLE;
1699 break;
1700 case GL_QUADS:
1701 type = V_028B6C_TESS_QUAD;
1702 break;
1703 case GL_ISOLINES:
1704 type = V_028B6C_TESS_ISOLINE;
1705 break;
1706 }
1707
1708 switch (tes->info.tes.spacing) {
1709 case TESS_SPACING_EQUAL:
1710 partitioning = V_028B6C_PART_INTEGER;
1711 break;
1712 case TESS_SPACING_FRACTIONAL_ODD:
1713 partitioning = V_028B6C_PART_FRAC_ODD;
1714 break;
1715 case TESS_SPACING_FRACTIONAL_EVEN:
1716 partitioning = V_028B6C_PART_FRAC_EVEN;
1717 break;
1718 default:
1719 break;
1720 }
1721
1722 bool ccw = tes->info.tes.ccw;
1723 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1724 vk_find_struct_const(pCreateInfo->pTessellationState,
1725 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1726
1727 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1728 ccw = !ccw;
1729
1730 if (tes->info.tes.point_mode)
1731 topology = V_028B6C_OUTPUT_POINT;
1732 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1733 topology = V_028B6C_OUTPUT_LINE;
1734 else if (ccw)
1735 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1736 else
1737 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1738
1739 if (pipeline->device->has_distributed_tess) {
1740 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1741 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1742 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1743 else
1744 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1745 } else
1746 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1747
1748 tess.tf_param = S_028B6C_TYPE(type) |
1749 S_028B6C_PARTITIONING(partitioning) |
1750 S_028B6C_TOPOLOGY(topology) |
1751 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1752
1753 return tess;
1754 }
1755
1756 static const struct radv_prim_vertex_count prim_size_table[] = {
1757 [V_008958_DI_PT_NONE] = {0, 0},
1758 [V_008958_DI_PT_POINTLIST] = {1, 1},
1759 [V_008958_DI_PT_LINELIST] = {2, 2},
1760 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1761 [V_008958_DI_PT_TRILIST] = {3, 3},
1762 [V_008958_DI_PT_TRIFAN] = {3, 1},
1763 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1764 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1765 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1766 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1767 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1768 [V_008958_DI_PT_RECTLIST] = {3, 3},
1769 [V_008958_DI_PT_LINELOOP] = {2, 1},
1770 [V_008958_DI_PT_POLYGON] = {3, 1},
1771 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1772 };
1773
1774 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1775 {
1776 if (radv_pipeline_has_gs(pipeline))
1777 return &pipeline->gs_copy_shader->info.vs.outinfo;
1778 else if (radv_pipeline_has_tess(pipeline))
1779 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1780 else
1781 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1782 }
1783
1784 static void
1785 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1786 {
1787 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1788 int shader_count = 0;
1789
1790 if(shaders[MESA_SHADER_FRAGMENT]) {
1791 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1792 }
1793 if(shaders[MESA_SHADER_GEOMETRY]) {
1794 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1795 }
1796 if(shaders[MESA_SHADER_TESS_EVAL]) {
1797 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1798 }
1799 if(shaders[MESA_SHADER_TESS_CTRL]) {
1800 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1801 }
1802 if(shaders[MESA_SHADER_VERTEX]) {
1803 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1804 }
1805
1806 if (shader_count > 1) {
1807 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
1808 unsigned last = ordered_shaders[0]->info.stage;
1809
1810 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
1811 ordered_shaders[1]->info.has_transform_feedback_varyings)
1812 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
1813
1814 for (int i = 0; i < shader_count; ++i) {
1815 nir_variable_mode mask = 0;
1816
1817 if (ordered_shaders[i]->info.stage != first)
1818 mask = mask | nir_var_shader_in;
1819
1820 if (ordered_shaders[i]->info.stage != last)
1821 mask = mask | nir_var_shader_out;
1822
1823 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
1824 radv_optimize_nir(ordered_shaders[i], false, false);
1825 }
1826 }
1827
1828 for (int i = 1; i < shader_count; ++i) {
1829 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1830 ordered_shaders[i - 1]);
1831
1832 if (nir_link_opt_varyings(ordered_shaders[i],
1833 ordered_shaders[i - 1]))
1834 radv_optimize_nir(ordered_shaders[i - 1], false, false);
1835
1836 nir_remove_dead_variables(ordered_shaders[i],
1837 nir_var_shader_out);
1838 nir_remove_dead_variables(ordered_shaders[i - 1],
1839 nir_var_shader_in);
1840
1841 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1842 ordered_shaders[i - 1]);
1843
1844 nir_compact_varyings(ordered_shaders[i],
1845 ordered_shaders[i - 1], true);
1846
1847 if (progress) {
1848 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1849 ac_lower_indirect_derefs(ordered_shaders[i],
1850 pipeline->device->physical_device->rad_info.chip_class);
1851 }
1852 radv_optimize_nir(ordered_shaders[i], false, false);
1853
1854 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1855 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1856 pipeline->device->physical_device->rad_info.chip_class);
1857 }
1858 radv_optimize_nir(ordered_shaders[i - 1], false, false);
1859 }
1860 }
1861 }
1862
1863 static uint32_t
1864 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
1865 uint32_t attrib_binding)
1866 {
1867 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
1868 const VkVertexInputBindingDescription *input_binding =
1869 &input_state->pVertexBindingDescriptions[i];
1870
1871 if (input_binding->binding == attrib_binding)
1872 return input_binding->stride;
1873 }
1874
1875 return 0;
1876 }
1877
1878 static struct radv_pipeline_key
1879 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1880 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1881 const struct radv_blend_state *blend,
1882 bool has_view_index)
1883 {
1884 const VkPipelineVertexInputStateCreateInfo *input_state =
1885 pCreateInfo->pVertexInputState;
1886 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1887 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1888
1889 struct radv_pipeline_key key;
1890 memset(&key, 0, sizeof(key));
1891
1892 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
1893 key.optimisations_disabled = 1;
1894
1895 key.has_multiview_view_index = has_view_index;
1896
1897 uint32_t binding_input_rate = 0;
1898 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1899 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1900 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1901 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1902 binding_input_rate |= 1u << binding;
1903 instance_rate_divisors[binding] = 1;
1904 }
1905 }
1906 if (divisor_state) {
1907 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1908 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1909 divisor_state->pVertexBindingDivisors[i].divisor;
1910 }
1911 }
1912
1913 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1914 const VkVertexInputAttributeDescription *desc =
1915 &input_state->pVertexAttributeDescriptions[i];
1916 const struct vk_format_description *format_desc;
1917 unsigned location = desc->location;
1918 unsigned binding = desc->binding;
1919 unsigned num_format, data_format;
1920 int first_non_void;
1921
1922 if (binding_input_rate & (1u << binding)) {
1923 key.instance_rate_inputs |= 1u << location;
1924 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1925 }
1926
1927 format_desc = vk_format_description(desc->format);
1928 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1929
1930 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1931 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1932
1933 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
1934 key.vertex_attribute_bindings[location] = desc->binding;
1935 key.vertex_attribute_offsets[location] = desc->offset;
1936 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
1937
1938 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
1939 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
1940 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
1941 uint64_t adjust;
1942 switch(format) {
1943 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1944 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
1945 adjust = RADV_ALPHA_ADJUST_SNORM;
1946 break;
1947 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1948 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
1949 adjust = RADV_ALPHA_ADJUST_SSCALED;
1950 break;
1951 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1952 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
1953 adjust = RADV_ALPHA_ADJUST_SINT;
1954 break;
1955 default:
1956 adjust = 0;
1957 break;
1958 }
1959 key.vertex_alpha_adjust |= adjust << (2 * location);
1960 }
1961
1962 switch (desc->format) {
1963 case VK_FORMAT_B8G8R8A8_UNORM:
1964 case VK_FORMAT_B8G8R8A8_SNORM:
1965 case VK_FORMAT_B8G8R8A8_USCALED:
1966 case VK_FORMAT_B8G8R8A8_SSCALED:
1967 case VK_FORMAT_B8G8R8A8_UINT:
1968 case VK_FORMAT_B8G8R8A8_SINT:
1969 case VK_FORMAT_B8G8R8A8_SRGB:
1970 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
1971 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
1972 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
1973 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
1974 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
1975 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
1976 key.vertex_post_shuffle |= 1 << location;
1977 break;
1978 default:
1979 break;
1980 }
1981 }
1982
1983 if (pCreateInfo->pTessellationState)
1984 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1985
1986
1987 if (pCreateInfo->pMultisampleState &&
1988 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1989 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1990 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1991 key.num_samples = num_samples;
1992 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1993 }
1994
1995 key.col_format = blend->spi_shader_col_format;
1996 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
1997 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1998
1999 return key;
2000 }
2001
2002 static void
2003 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
2004 const struct radv_pipeline_key *key,
2005 nir_shader **nir)
2006 {
2007 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2008 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2009 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2010 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2011 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2012 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2013 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2014 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2015 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2016 }
2017
2018 if (nir[MESA_SHADER_TESS_CTRL]) {
2019 keys[MESA_SHADER_VERTEX].vs.out.as_ls = true;
2020 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2021 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2022 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2023
2024 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2025 }
2026
2027 if (nir[MESA_SHADER_GEOMETRY]) {
2028 if (nir[MESA_SHADER_TESS_CTRL])
2029 keys[MESA_SHADER_TESS_EVAL].tes.out.as_es = true;
2030 else
2031 keys[MESA_SHADER_VERTEX].vs.out.as_es = true;
2032 }
2033
2034 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2035 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2036
2037 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2038 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2039 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2040 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2041 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2042 }
2043
2044 static void
2045 merge_tess_info(struct shader_info *tes_info,
2046 const struct shader_info *tcs_info)
2047 {
2048 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2049 *
2050 * "PointMode. Controls generation of points rather than triangles
2051 * or lines. This functionality defaults to disabled, and is
2052 * enabled if either shader stage includes the execution mode.
2053 *
2054 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2055 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2056 * and OutputVertices, it says:
2057 *
2058 * "One mode must be set in at least one of the tessellation
2059 * shader stages."
2060 *
2061 * So, the fields can be set in either the TCS or TES, but they must
2062 * agree if set in both. Our backend looks at TES, so bitwise-or in
2063 * the values from the TCS.
2064 */
2065 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2066 tes_info->tess.tcs_vertices_out == 0 ||
2067 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2068 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2069
2070 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2071 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2072 tcs_info->tess.spacing == tes_info->tess.spacing);
2073 tes_info->tess.spacing |= tcs_info->tess.spacing;
2074
2075 assert(tcs_info->tess.primitive_mode == 0 ||
2076 tes_info->tess.primitive_mode == 0 ||
2077 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2078 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2079 tes_info->tess.ccw |= tcs_info->tess.ccw;
2080 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2081 }
2082
2083 static
2084 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2085 {
2086 if (!ext)
2087 return;
2088
2089 if (ext->pPipelineCreationFeedback) {
2090 ext->pPipelineCreationFeedback->flags = 0;
2091 ext->pPipelineCreationFeedback->duration = 0;
2092 }
2093
2094 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2095 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2096 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2097 }
2098 }
2099
2100 static
2101 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2102 {
2103 if (!feedback)
2104 return;
2105
2106 feedback->duration -= radv_get_current_time();
2107 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2108 }
2109
2110 static
2111 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2112 {
2113 if (!feedback)
2114 return;
2115
2116 feedback->duration += radv_get_current_time();
2117 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2118 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2119 }
2120
2121 static
2122 void radv_create_shaders(struct radv_pipeline *pipeline,
2123 struct radv_device *device,
2124 struct radv_pipeline_cache *cache,
2125 const struct radv_pipeline_key *key,
2126 const VkPipelineShaderStageCreateInfo **pStages,
2127 const VkPipelineCreateFlags flags,
2128 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2129 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2130 {
2131 struct radv_shader_module fs_m = {0};
2132 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2133 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2134 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2135 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2136 unsigned char hash[20], gs_copy_hash[20];
2137
2138 radv_start_feedback(pipeline_feedback);
2139
2140 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2141 if (pStages[i]) {
2142 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2143 if (modules[i]->nir)
2144 _mesa_sha1_compute(modules[i]->nir->info.name,
2145 strlen(modules[i]->nir->info.name),
2146 modules[i]->sha1);
2147
2148 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2149 }
2150 }
2151
2152 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2153 memcpy(gs_copy_hash, hash, 20);
2154 gs_copy_hash[0] ^= 1;
2155
2156 bool found_in_application_cache = true;
2157 if (modules[MESA_SHADER_GEOMETRY]) {
2158 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2159 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2160 &found_in_application_cache);
2161 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2162 }
2163
2164 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2165 &found_in_application_cache) &&
2166 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2167 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2168 return;
2169 }
2170
2171 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2172 nir_builder fs_b;
2173 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2174 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2175 fs_m.nir = fs_b.shader;
2176 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2177 }
2178
2179 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2180 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2181
2182 if (!modules[i])
2183 continue;
2184
2185 radv_start_feedback(stage_feedbacks[i]);
2186
2187 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2188 stage ? stage->pName : "main", i,
2189 stage ? stage->pSpecializationInfo : NULL,
2190 flags, pipeline->layout);
2191
2192 /* We don't want to alter meta shaders IR directly so clone it
2193 * first.
2194 */
2195 if (nir[i]->info.name) {
2196 nir[i] = nir_shader_clone(NULL, nir[i]);
2197 }
2198
2199 radv_stop_feedback(stage_feedbacks[i], false);
2200 }
2201
2202 if (nir[MESA_SHADER_TESS_CTRL]) {
2203 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2204 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2205 }
2206
2207 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2208 radv_link_shaders(pipeline, nir);
2209
2210 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2211 if (nir[i]) {
2212 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2213 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2214 nir_lower_non_uniform_ubo_access |
2215 nir_lower_non_uniform_ssbo_access |
2216 nir_lower_non_uniform_texture_access |
2217 nir_lower_non_uniform_image_access);
2218 }
2219
2220 if (radv_can_dump_shader(device, modules[i], false))
2221 nir_print_shader(nir[i], stderr);
2222 }
2223
2224 radv_fill_shader_keys(keys, key, nir);
2225
2226 if (nir[MESA_SHADER_FRAGMENT]) {
2227 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2228 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2229
2230 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2231 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2232 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2233 &binaries[MESA_SHADER_FRAGMENT]);
2234
2235 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2236 }
2237
2238 /* TODO: These are no longer used as keys we should refactor this */
2239 keys[MESA_SHADER_VERTEX].vs.out.export_prim_id =
2240 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2241 keys[MESA_SHADER_VERTEX].vs.out.export_layer_id =
2242 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2243 keys[MESA_SHADER_VERTEX].vs.out.export_clip_dists =
2244 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2245 keys[MESA_SHADER_TESS_EVAL].tes.out.export_prim_id =
2246 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2247 keys[MESA_SHADER_TESS_EVAL].tes.out.export_layer_id =
2248 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2249 keys[MESA_SHADER_TESS_EVAL].tes.out.export_clip_dists =
2250 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2251 }
2252
2253 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2254 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2255 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2256 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2257 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2258
2259 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2260
2261 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2262 pipeline->layout,
2263 &key, &binaries[MESA_SHADER_TESS_CTRL]);
2264
2265 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2266 }
2267 modules[MESA_SHADER_VERTEX] = NULL;
2268 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2269 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2270 }
2271
2272 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2273 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2274 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2275 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2276
2277 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2278
2279 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2280 pipeline->layout,
2281 &keys[pre_stage] , &binaries[MESA_SHADER_GEOMETRY]);
2282
2283 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2284 }
2285 modules[pre_stage] = NULL;
2286 }
2287
2288 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2289 if(modules[i] && !pipeline->shaders[i]) {
2290 if (i == MESA_SHADER_TESS_CTRL) {
2291 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2292 }
2293 if (i == MESA_SHADER_TESS_EVAL) {
2294 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2295 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2296 }
2297
2298 radv_start_feedback(stage_feedbacks[i]);
2299
2300 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2301 pipeline->layout,
2302 keys + i, &binaries[i]);
2303
2304 radv_stop_feedback(stage_feedbacks[i], false);
2305 }
2306 }
2307
2308 if(modules[MESA_SHADER_GEOMETRY]) {
2309 struct radv_shader_binary *gs_copy_binary = NULL;
2310 if (!pipeline->gs_copy_shader) {
2311 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2312 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
2313 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2314 }
2315
2316 if (pipeline->gs_copy_shader) {
2317 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2318 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2319
2320 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2321 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2322
2323 radv_pipeline_cache_insert_shaders(device, cache,
2324 gs_copy_hash,
2325 variants,
2326 binaries);
2327 }
2328 free(gs_copy_binary);
2329 }
2330
2331 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2332 binaries);
2333
2334 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2335 free(binaries[i]);
2336 if (nir[i]) {
2337 if (!pipeline->device->keep_shader_info)
2338 ralloc_free(nir[i]);
2339
2340 if (radv_can_dump_shader_stats(device, modules[i]))
2341 radv_shader_dump_stats(device,
2342 pipeline->shaders[i],
2343 i, stderr);
2344 }
2345 }
2346
2347 if (fs_m.nir)
2348 ralloc_free(fs_m.nir);
2349
2350 radv_stop_feedback(pipeline_feedback, false);
2351 }
2352
2353 static uint32_t
2354 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2355 gl_shader_stage stage, enum chip_class chip_class)
2356 {
2357 bool has_gs = radv_pipeline_has_gs(pipeline);
2358 bool has_tess = radv_pipeline_has_tess(pipeline);
2359 switch (stage) {
2360 case MESA_SHADER_FRAGMENT:
2361 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2362 case MESA_SHADER_VERTEX:
2363 if (has_tess) {
2364 if (chip_class >= GFX10) {
2365 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2366 } else if (chip_class == GFX9) {
2367 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2368 } else {
2369 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2370 }
2371
2372 }
2373
2374 if (has_gs) {
2375 if (chip_class >= GFX10) {
2376 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2377 } else {
2378 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2379 }
2380 }
2381
2382 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2383 case MESA_SHADER_GEOMETRY:
2384 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2385 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2386 case MESA_SHADER_COMPUTE:
2387 return R_00B900_COMPUTE_USER_DATA_0;
2388 case MESA_SHADER_TESS_CTRL:
2389 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2390 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2391 case MESA_SHADER_TESS_EVAL:
2392 if (has_gs) {
2393 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2394 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2395 } else {
2396 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2397 }
2398 default:
2399 unreachable("unknown shader");
2400 }
2401 }
2402
2403 struct radv_bin_size_entry {
2404 unsigned bpp;
2405 VkExtent2D extent;
2406 };
2407
2408 static VkExtent2D
2409 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2410 {
2411 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2412 {
2413 /* One RB / SE */
2414 {
2415 /* One shader engine */
2416 { 0, {128, 128}},
2417 { 1, { 64, 128}},
2418 { 2, { 32, 128}},
2419 { 3, { 16, 128}},
2420 { 17, { 0, 0}},
2421 { UINT_MAX, { 0, 0}},
2422 },
2423 {
2424 /* Two shader engines */
2425 { 0, {128, 128}},
2426 { 2, { 64, 128}},
2427 { 3, { 32, 128}},
2428 { 5, { 16, 128}},
2429 { 17, { 0, 0}},
2430 { UINT_MAX, { 0, 0}},
2431 },
2432 {
2433 /* Four shader engines */
2434 { 0, {128, 128}},
2435 { 3, { 64, 128}},
2436 { 5, { 16, 128}},
2437 { 17, { 0, 0}},
2438 { UINT_MAX, { 0, 0}},
2439 },
2440 },
2441 {
2442 /* Two RB / SE */
2443 {
2444 /* One shader engine */
2445 { 0, {128, 128}},
2446 { 2, { 64, 128}},
2447 { 3, { 32, 128}},
2448 { 5, { 16, 128}},
2449 { 33, { 0, 0}},
2450 { UINT_MAX, { 0, 0}},
2451 },
2452 {
2453 /* Two shader engines */
2454 { 0, {128, 128}},
2455 { 3, { 64, 128}},
2456 { 5, { 32, 128}},
2457 { 9, { 16, 128}},
2458 { 33, { 0, 0}},
2459 { UINT_MAX, { 0, 0}},
2460 },
2461 {
2462 /* Four shader engines */
2463 { 0, {256, 256}},
2464 { 2, {128, 256}},
2465 { 3, {128, 128}},
2466 { 5, { 64, 128}},
2467 { 9, { 16, 128}},
2468 { 33, { 0, 0}},
2469 { UINT_MAX, { 0, 0}},
2470 },
2471 },
2472 {
2473 /* Four RB / SE */
2474 {
2475 /* One shader engine */
2476 { 0, {128, 256}},
2477 { 2, {128, 128}},
2478 { 3, { 64, 128}},
2479 { 5, { 32, 128}},
2480 { 9, { 16, 128}},
2481 { 33, { 0, 0}},
2482 { UINT_MAX, { 0, 0}},
2483 },
2484 {
2485 /* Two shader engines */
2486 { 0, {256, 256}},
2487 { 2, {128, 256}},
2488 { 3, {128, 128}},
2489 { 5, { 64, 128}},
2490 { 9, { 32, 128}},
2491 { 17, { 16, 128}},
2492 { 33, { 0, 0}},
2493 { UINT_MAX, { 0, 0}},
2494 },
2495 {
2496 /* Four shader engines */
2497 { 0, {256, 512}},
2498 { 2, {256, 256}},
2499 { 3, {128, 256}},
2500 { 5, {128, 128}},
2501 { 9, { 64, 128}},
2502 { 17, { 16, 128}},
2503 { 33, { 0, 0}},
2504 { UINT_MAX, { 0, 0}},
2505 },
2506 },
2507 };
2508 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2509 {
2510 // One RB / SE
2511 {
2512 // One shader engine
2513 { 0, {128, 256}},
2514 { 2, {128, 128}},
2515 { 4, { 64, 128}},
2516 { 7, { 32, 128}},
2517 { 13, { 16, 128}},
2518 { 49, { 0, 0}},
2519 { UINT_MAX, { 0, 0}},
2520 },
2521 {
2522 // Two shader engines
2523 { 0, {256, 256}},
2524 { 2, {128, 256}},
2525 { 4, {128, 128}},
2526 { 7, { 64, 128}},
2527 { 13, { 32, 128}},
2528 { 25, { 16, 128}},
2529 { 49, { 0, 0}},
2530 { UINT_MAX, { 0, 0}},
2531 },
2532 {
2533 // Four shader engines
2534 { 0, {256, 512}},
2535 { 2, {256, 256}},
2536 { 4, {128, 256}},
2537 { 7, {128, 128}},
2538 { 13, { 64, 128}},
2539 { 25, { 16, 128}},
2540 { 49, { 0, 0}},
2541 { UINT_MAX, { 0, 0}},
2542 },
2543 },
2544 {
2545 // Two RB / SE
2546 {
2547 // One shader engine
2548 { 0, {256, 256}},
2549 { 2, {128, 256}},
2550 { 4, {128, 128}},
2551 { 7, { 64, 128}},
2552 { 13, { 32, 128}},
2553 { 25, { 16, 128}},
2554 { 97, { 0, 0}},
2555 { UINT_MAX, { 0, 0}},
2556 },
2557 {
2558 // Two shader engines
2559 { 0, {256, 512}},
2560 { 2, {256, 256}},
2561 { 4, {128, 256}},
2562 { 7, {128, 128}},
2563 { 13, { 64, 128}},
2564 { 25, { 32, 128}},
2565 { 49, { 16, 128}},
2566 { 97, { 0, 0}},
2567 { UINT_MAX, { 0, 0}},
2568 },
2569 {
2570 // Four shader engines
2571 { 0, {512, 512}},
2572 { 2, {256, 512}},
2573 { 4, {256, 256}},
2574 { 7, {128, 256}},
2575 { 13, {128, 128}},
2576 { 25, { 64, 128}},
2577 { 49, { 16, 128}},
2578 { 97, { 0, 0}},
2579 { UINT_MAX, { 0, 0}},
2580 },
2581 },
2582 {
2583 // Four RB / SE
2584 {
2585 // One shader engine
2586 { 0, {256, 512}},
2587 { 2, {256, 256}},
2588 { 4, {128, 256}},
2589 { 7, {128, 128}},
2590 { 13, { 64, 128}},
2591 { 25, { 32, 128}},
2592 { 49, { 16, 128}},
2593 { UINT_MAX, { 0, 0}},
2594 },
2595 {
2596 // Two shader engines
2597 { 0, {512, 512}},
2598 { 2, {256, 512}},
2599 { 4, {256, 256}},
2600 { 7, {128, 256}},
2601 { 13, {128, 128}},
2602 { 25, { 64, 128}},
2603 { 49, { 32, 128}},
2604 { 97, { 16, 128}},
2605 { UINT_MAX, { 0, 0}},
2606 },
2607 {
2608 // Four shader engines
2609 { 0, {512, 512}},
2610 { 4, {256, 512}},
2611 { 7, {256, 256}},
2612 { 13, {128, 256}},
2613 { 25, {128, 128}},
2614 { 49, { 64, 128}},
2615 { 97, { 16, 128}},
2616 { UINT_MAX, { 0, 0}},
2617 },
2618 },
2619 };
2620
2621 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2622 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2623 VkExtent2D extent = {512, 512};
2624
2625 unsigned log_num_rb_per_se =
2626 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2627 pipeline->device->physical_device->rad_info.max_se);
2628 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2629
2630 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
2631 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2632 unsigned effective_samples = total_samples;
2633 unsigned color_bytes_per_pixel = 0;
2634
2635 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2636 if (vkblend) {
2637 for (unsigned i = 0; i < subpass->color_count; i++) {
2638 if (!vkblend->pAttachments[i].colorWriteMask)
2639 continue;
2640
2641 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2642 continue;
2643
2644 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2645 color_bytes_per_pixel += vk_format_get_blocksize(format);
2646 }
2647
2648 /* MSAA images typically don't use all samples all the time. */
2649 if (effective_samples >= 2 && ps_iter_samples <= 1)
2650 effective_samples = 2;
2651 color_bytes_per_pixel *= effective_samples;
2652 }
2653
2654 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2655 while(color_entry[1].bpp <= color_bytes_per_pixel)
2656 ++color_entry;
2657
2658 extent = color_entry->extent;
2659
2660 if (subpass->depth_stencil_attachment) {
2661 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
2662
2663 /* Coefficients taken from AMDVLK */
2664 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2665 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2666 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2667
2668 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2669 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
2670 ++ds_entry;
2671
2672 extent.width = MIN2(extent.width, ds_entry->extent.width);
2673 extent.height = MIN2(extent.height, ds_entry->extent.height);
2674 }
2675
2676 return extent;
2677 }
2678
2679 static void
2680 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
2681 struct radv_pipeline *pipeline,
2682 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2683 {
2684 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2685 return;
2686
2687 uint32_t pa_sc_binner_cntl_0 =
2688 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2689 S_028C44_DISABLE_START_OF_PRIM(1);
2690 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2691
2692 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2693
2694 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2695 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2696 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2697 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2698
2699 switch (pipeline->device->physical_device->rad_info.family) {
2700 case CHIP_VEGA10:
2701 case CHIP_VEGA12:
2702 case CHIP_VEGA20:
2703 context_states_per_bin = 1;
2704 persistent_states_per_bin = 1;
2705 fpovs_per_batch = 63;
2706 break;
2707 case CHIP_RAVEN:
2708 case CHIP_RAVEN2:
2709 context_states_per_bin = 6;
2710 persistent_states_per_bin = 32;
2711 fpovs_per_batch = 63;
2712 break;
2713 default:
2714 unreachable("unhandled family while determining binning state.");
2715 }
2716
2717 pa_sc_binner_cntl_0 =
2718 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2719 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2720 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2721 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2722 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2723 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2724 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2725 S_028C44_DISABLE_START_OF_PRIM(1) |
2726 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2727 S_028C44_OPTIMAL_BIN_SELECTION(1);
2728 }
2729
2730 radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
2731 pa_sc_binner_cntl_0);
2732
2733 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
2734 radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL,
2735 db_dfsm_control);
2736 } else {
2737 radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
2738 db_dfsm_control);
2739 }
2740 }
2741
2742
2743 static void
2744 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
2745 struct radv_pipeline *pipeline,
2746 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2747 const struct radv_graphics_pipeline_create_info *extra)
2748 {
2749 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2750 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2751 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2752 struct radv_render_pass_attachment *attachment = NULL;
2753 uint32_t db_depth_control = 0, db_stencil_control = 0;
2754 uint32_t db_render_control = 0, db_render_override2 = 0;
2755 uint32_t db_render_override = 0;
2756
2757 if (subpass->depth_stencil_attachment)
2758 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
2759
2760 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2761 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2762
2763 if (vkds && has_depth_attachment) {
2764 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2765 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2766 S_028800_ZFUNC(vkds->depthCompareOp) |
2767 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2768
2769 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2770 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2771 }
2772
2773 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2774 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2775 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2776 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2777 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2778 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2779
2780 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2781 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2782 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2783 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2784 }
2785
2786 if (attachment && extra) {
2787 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2788 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2789
2790 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2791 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2792 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2793 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2794 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2795 }
2796
2797 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2798 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2799
2800 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
2801 /* From VK_EXT_depth_range_unrestricted spec:
2802 *
2803 * "The behavior described in Primitive Clipping still applies.
2804 * If depth clamping is disabled the depth values are still
2805 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2806 * depth clamping is enabled the above equation is ignored and
2807 * the depth values are instead clamped to the VkViewport
2808 * minDepth and maxDepth values, which in the case of this
2809 * extension can be outside of the 0.0 to 1.0 range."
2810 */
2811 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2812 }
2813
2814 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2815 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2816
2817 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2818 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2819 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2820 }
2821
2822 static void
2823 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
2824 struct radv_pipeline *pipeline,
2825 const struct radv_blend_state *blend)
2826 {
2827 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
2828 radeon_emit_array(ctx_cs, blend->cb_blend_control,
2829 8);
2830 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2831 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2832
2833 if (pipeline->device->physical_device->has_rbplus) {
2834
2835 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2836 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
2837 }
2838
2839 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2840
2841 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2842 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2843
2844 pipeline->graphics.col_format = blend->spi_shader_col_format;
2845 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2846 }
2847
2848 static const VkConservativeRasterizationModeEXT
2849 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
2850 {
2851 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
2852 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
2853
2854 if (!conservative_raster)
2855 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
2856 return conservative_raster->conservativeRasterizationMode;
2857 }
2858
2859 static void
2860 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
2861 struct radv_pipeline *pipeline,
2862 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2863 {
2864 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2865 const VkConservativeRasterizationModeEXT mode =
2866 radv_get_conservative_raster_mode(vkraster);
2867 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
2868 bool depth_clip_disable = vkraster->depthClampEnable;
2869
2870 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
2871 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
2872 if (depth_clip_state) {
2873 depth_clip_disable = !depth_clip_state->depthClipEnable;
2874 }
2875
2876 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
2877 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2878 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
2879 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
2880 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2881 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2882
2883 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
2884 S_0286D4_FLAT_SHADE_ENA(1) |
2885 S_0286D4_PNT_SPRITE_ENA(1) |
2886 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2887 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2888 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2889 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2890 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2891
2892 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
2893 S_028BE4_PIX_CENTER(1) | // TODO verify
2894 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2895 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2896
2897 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
2898 S_028814_FACE(vkraster->frontFace) |
2899 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2900 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2901 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2902 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2903 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2904 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2905 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2906 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2907
2908 /* Conservative rasterization. */
2909 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
2910 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2911
2912 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
2913 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
2914 S_028804_OVERRASTERIZATION_AMOUNT(4);
2915
2916 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
2917 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
2918 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
2919
2920 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
2921 pa_sc_conservative_rast |=
2922 S_028C4C_OVER_RAST_ENABLE(1) |
2923 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
2924 S_028C4C_UNDER_RAST_ENABLE(0) |
2925 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
2926 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
2927 } else {
2928 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
2929 pa_sc_conservative_rast |=
2930 S_028C4C_OVER_RAST_ENABLE(0) |
2931 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
2932 S_028C4C_UNDER_RAST_ENABLE(1) |
2933 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
2934 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
2935 }
2936 }
2937
2938 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
2939 pa_sc_conservative_rast);
2940 }
2941
2942
2943 static void
2944 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
2945 struct radv_pipeline *pipeline)
2946 {
2947 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2948
2949 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2950 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
2951 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
2952
2953 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
2954 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2955
2956 /* The exclusion bits can be set to improve rasterization efficiency
2957 * if no sample lies on the pixel boundary (-8 sample offset). It's
2958 * currently always TRUE because the driver doesn't support 16 samples.
2959 */
2960 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
2961 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
2962 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
2963 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
2964 }
2965
2966 static void
2967 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
2968 struct radv_pipeline *pipeline)
2969 {
2970 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2971
2972 uint32_t vgt_primitiveid_en = false;
2973 uint32_t vgt_gs_mode = 0;
2974
2975 if (radv_pipeline_has_gs(pipeline)) {
2976 const struct radv_shader_variant *gs =
2977 pipeline->shaders[MESA_SHADER_GEOMETRY];
2978
2979 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2980 pipeline->device->physical_device->rad_info.chip_class);
2981 } else if (outinfo->export_prim_id) {
2982 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2983 vgt_primitiveid_en = true;
2984 }
2985
2986 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2987 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2988 }
2989
2990 static void
2991 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
2992 struct radeon_cmdbuf *cs,
2993 struct radv_pipeline *pipeline,
2994 struct radv_shader_variant *shader)
2995 {
2996 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2997
2998 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2999 radeon_emit(cs, va >> 8);
3000 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3001 radeon_emit(cs, shader->config.rsrc1);
3002 radeon_emit(cs, shader->config.rsrc2);
3003
3004 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3005 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3006 clip_dist_mask = outinfo->clip_dist_mask;
3007 cull_dist_mask = outinfo->cull_dist_mask;
3008 total_mask = clip_dist_mask | cull_dist_mask;
3009 bool misc_vec_ena = outinfo->writes_pointsize ||
3010 outinfo->writes_layer ||
3011 outinfo->writes_viewport_index;
3012
3013 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3014 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
3015
3016 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3017 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3018 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3019 V_02870C_SPI_SHADER_4COMP :
3020 V_02870C_SPI_SHADER_NONE) |
3021 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3022 V_02870C_SPI_SHADER_4COMP :
3023 V_02870C_SPI_SHADER_NONE) |
3024 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3025 V_02870C_SPI_SHADER_4COMP :
3026 V_02870C_SPI_SHADER_NONE));
3027
3028 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3029 S_028818_VTX_W0_FMT(1) |
3030 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3031 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3032 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3033
3034 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3035 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3036 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3037 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3038 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3039 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3040 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3041 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3042 cull_dist_mask << 8 |
3043 clip_dist_mask);
3044
3045 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3046 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3047 outinfo->writes_viewport_index);
3048 }
3049
3050 static void
3051 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3052 struct radv_pipeline *pipeline,
3053 struct radv_shader_variant *shader)
3054 {
3055 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3056
3057 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3058 radeon_emit(cs, va >> 8);
3059 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3060 radeon_emit(cs, shader->config.rsrc1);
3061 radeon_emit(cs, shader->config.rsrc2);
3062 }
3063
3064 static void
3065 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3066 struct radv_pipeline *pipeline,
3067 struct radv_shader_variant *shader,
3068 const struct radv_tessellation_state *tess)
3069 {
3070 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3071 uint32_t rsrc2 = shader->config.rsrc2;
3072
3073 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3074 radeon_emit(cs, va >> 8);
3075 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3076
3077 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3078 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3079 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3080 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3081
3082 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3083 radeon_emit(cs, shader->config.rsrc1);
3084 radeon_emit(cs, rsrc2);
3085 }
3086
3087 static void
3088 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3089 struct radv_pipeline *pipeline,
3090 struct radv_shader_variant *shader,
3091 const struct radv_tessellation_state *tess)
3092 {
3093 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3094
3095 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3096 unsigned hs_rsrc2 = shader->config.rsrc2;
3097
3098 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3099 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3100 } else {
3101 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3102 }
3103
3104 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3105 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3106 radeon_emit(cs, va >> 8);
3107 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3108 } else {
3109 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3110 radeon_emit(cs, va >> 8);
3111 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3112 }
3113
3114 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3115 radeon_emit(cs, shader->config.rsrc1);
3116 radeon_emit(cs, hs_rsrc2);
3117 } else {
3118 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3119 radeon_emit(cs, va >> 8);
3120 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3121 radeon_emit(cs, shader->config.rsrc1);
3122 radeon_emit(cs, shader->config.rsrc2);
3123 }
3124 }
3125
3126 static void
3127 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3128 struct radeon_cmdbuf *cs,
3129 struct radv_pipeline *pipeline,
3130 const struct radv_tessellation_state *tess)
3131 {
3132 struct radv_shader_variant *vs;
3133
3134 /* Skip shaders merged into HS/GS */
3135 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3136 if (!vs)
3137 return;
3138
3139 if (vs->info.vs.as_ls)
3140 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3141 else if (vs->info.vs.as_es)
3142 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3143 else
3144 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3145 }
3146
3147 static void
3148 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3149 struct radeon_cmdbuf *cs,
3150 struct radv_pipeline *pipeline,
3151 const struct radv_tessellation_state *tess)
3152 {
3153 if (!radv_pipeline_has_tess(pipeline))
3154 return;
3155
3156 struct radv_shader_variant *tes, *tcs;
3157
3158 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3159 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3160
3161 if (tes) {
3162 if (tes->info.tes.as_es)
3163 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3164 else
3165 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3166 }
3167
3168 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3169
3170 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3171 tess->tf_param);
3172
3173 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3174 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3175 tess->ls_hs_config);
3176 else
3177 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3178 tess->ls_hs_config);
3179 }
3180
3181 static void
3182 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
3183 struct radeon_cmdbuf *cs,
3184 struct radv_pipeline *pipeline,
3185 const struct radv_gs_state *gs_state)
3186 {
3187 struct radv_shader_variant *gs;
3188 unsigned gs_max_out_vertices;
3189 uint8_t *num_components;
3190 uint8_t max_stream;
3191 unsigned offset;
3192 uint64_t va;
3193
3194 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3195 if (!gs)
3196 return;
3197
3198 gs_max_out_vertices = gs->info.gs.vertices_out;
3199 max_stream = gs->info.info.gs.max_stream;
3200 num_components = gs->info.info.gs.num_stream_output_components;
3201
3202 offset = num_components[0] * gs_max_out_vertices;
3203
3204 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3205 radeon_emit(ctx_cs, offset);
3206 if (max_stream >= 1)
3207 offset += num_components[1] * gs_max_out_vertices;
3208 radeon_emit(ctx_cs, offset);
3209 if (max_stream >= 2)
3210 offset += num_components[2] * gs_max_out_vertices;
3211 radeon_emit(ctx_cs, offset);
3212 if (max_stream >= 3)
3213 offset += num_components[3] * gs_max_out_vertices;
3214 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3215
3216 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
3217
3218 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3219 radeon_emit(ctx_cs, num_components[0]);
3220 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3221 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3222 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3223
3224 uint32_t gs_num_invocations = gs->info.gs.invocations;
3225 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3226 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3227 S_028B90_ENABLE(gs_num_invocations > 0));
3228
3229 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3230 gs_state->vgt_esgs_ring_itemsize);
3231
3232 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3233
3234 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3235 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3236 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3237 radeon_emit(cs, va >> 8);
3238 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3239 } else {
3240 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3241 radeon_emit(cs, va >> 8);
3242 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3243 }
3244
3245 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3246 radeon_emit(cs, gs->config.rsrc1);
3247 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3248
3249 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3250 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3251 } else {
3252 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3253 radeon_emit(cs, va >> 8);
3254 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3255 radeon_emit(cs, gs->config.rsrc1);
3256 radeon_emit(cs, gs->config.rsrc2);
3257 }
3258
3259 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
3260 }
3261
3262 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
3263 {
3264 uint32_t ps_input_cntl;
3265 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3266 ps_input_cntl = S_028644_OFFSET(offset);
3267 if (flat_shade)
3268 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3269 if (float16) {
3270 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
3271 S_028644_ATTR0_VALID(1);
3272 }
3273 } else {
3274 /* The input is a DEFAULT_VAL constant. */
3275 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3276 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3277 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3278 ps_input_cntl = S_028644_OFFSET(0x20) |
3279 S_028644_DEFAULT_VAL(offset);
3280 }
3281 return ps_input_cntl;
3282 }
3283
3284 static void
3285 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
3286 struct radv_pipeline *pipeline)
3287 {
3288 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3289 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3290 uint32_t ps_input_cntl[32];
3291
3292 unsigned ps_offset = 0;
3293
3294 if (ps->info.info.ps.prim_id_input) {
3295 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3296 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3297 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3298 ++ps_offset;
3299 }
3300 }
3301
3302 if (ps->info.info.ps.layer_input ||
3303 ps->info.info.ps.uses_input_attachments ||
3304 ps->info.info.needs_multiview_view_index) {
3305 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3306 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3307 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3308 else
3309 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
3310 ++ps_offset;
3311 }
3312
3313 if (ps->info.info.ps.has_pcoord) {
3314 unsigned val;
3315 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3316 ps_input_cntl[ps_offset] = val;
3317 ps_offset++;
3318 }
3319
3320 if (ps->info.info.ps.num_input_clips_culls) {
3321 unsigned vs_offset;
3322
3323 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3324 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3325 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3326 ++ps_offset;
3327 }
3328
3329 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3330 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
3331 ps->info.info.ps.num_input_clips_culls > 4) {
3332 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3333 ++ps_offset;
3334 }
3335 }
3336
3337 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3338 unsigned vs_offset;
3339 bool flat_shade;
3340 bool float16;
3341 if (!(ps->info.fs.input_mask & (1u << i)))
3342 continue;
3343
3344 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3345 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3346 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3347 ++ps_offset;
3348 continue;
3349 }
3350
3351 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3352 float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset));
3353
3354 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
3355 ++ps_offset;
3356 }
3357
3358 if (ps_offset) {
3359 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3360 for (unsigned i = 0; i < ps_offset; i++) {
3361 radeon_emit(ctx_cs, ps_input_cntl[i]);
3362 }
3363 }
3364 }
3365
3366 static uint32_t
3367 radv_compute_db_shader_control(const struct radv_device *device,
3368 const struct radv_pipeline *pipeline,
3369 const struct radv_shader_variant *ps)
3370 {
3371 unsigned z_order;
3372 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3373 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3374 else
3375 z_order = V_02880C_LATE_Z;
3376
3377 bool disable_rbplus = device->physical_device->has_rbplus &&
3378 !device->physical_device->rbplus_allowed;
3379
3380 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3381 * but this appears to break Project Cars (DXVK). See
3382 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
3383 */
3384 bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
3385
3386 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3387 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3388 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3389 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
3390 S_02880C_Z_ORDER(z_order) |
3391 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3392 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3393 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3394 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3395 }
3396
3397 static void
3398 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
3399 struct radeon_cmdbuf *cs,
3400 struct radv_pipeline *pipeline)
3401 {
3402 struct radv_shader_variant *ps;
3403 uint64_t va;
3404 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3405
3406 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3407 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3408
3409 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3410 radeon_emit(cs, va >> 8);
3411 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3412 radeon_emit(cs, ps->config.rsrc1);
3413 radeon_emit(cs, ps->config.rsrc2);
3414
3415 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
3416 radv_compute_db_shader_control(pipeline->device,
3417 pipeline, ps));
3418
3419 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
3420 ps->config.spi_ps_input_ena);
3421
3422 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
3423 ps->config.spi_ps_input_addr);
3424
3425 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
3426 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3427
3428 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3429
3430 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
3431 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3432 ps->info.info.ps.writes_stencil,
3433 ps->info.info.ps.writes_sample_mask));
3434
3435 if (pipeline->device->dfsm_allowed) {
3436 /* optimise this? */
3437 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3438 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3439 }
3440 }
3441
3442 static void
3443 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
3444 struct radv_pipeline *pipeline)
3445 {
3446 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3447 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
3448 return;
3449
3450 unsigned vtx_reuse_depth = 30;
3451 if (radv_pipeline_has_tess(pipeline) &&
3452 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3453 vtx_reuse_depth = 14;
3454 }
3455 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3456 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3457 }
3458
3459 static uint32_t
3460 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3461 {
3462 uint32_t stages = 0;
3463 if (radv_pipeline_has_tess(pipeline)) {
3464 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3465 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3466
3467 if (radv_pipeline_has_gs(pipeline))
3468 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3469 S_028B54_GS_EN(1) |
3470 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3471 else
3472 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3473
3474 } else if (radv_pipeline_has_gs(pipeline))
3475 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3476 S_028B54_GS_EN(1) |
3477 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3478
3479 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3480 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3481
3482 return stages;
3483 }
3484
3485 static uint32_t
3486 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3487 {
3488 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3489 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3490
3491 if (!discard_rectangle_info)
3492 return 0xffff;
3493
3494 unsigned mask = 0;
3495
3496 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3497 /* Interpret i as a bitmask, and then set the bit in the mask if
3498 * that combination of rectangles in which the pixel is contained
3499 * should pass the cliprect test. */
3500 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3501
3502 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3503 !relevant_subset)
3504 continue;
3505
3506 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3507 relevant_subset)
3508 continue;
3509
3510 mask |= 1u << i;
3511 }
3512
3513 return mask;
3514 }
3515
3516 static void
3517 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
3518 struct radv_pipeline *pipeline,
3519 const struct radv_tessellation_state *tess,
3520 const struct radv_gs_state *gs_state)
3521 {
3522 bool break_wave_at_eoi = false;
3523 unsigned primgroup_size;
3524 unsigned vertgroup_size;
3525
3526 if (radv_pipeline_has_tess(pipeline)) {
3527 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
3528 vertgroup_size = 0;
3529 } else if (radv_pipeline_has_gs(pipeline)) {
3530 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
3531 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
3532 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
3533 } else {
3534 primgroup_size = 128; /* recommended without a GS and tess */
3535 vertgroup_size = 0;
3536 }
3537
3538 if (radv_pipeline_has_tess(pipeline)) {
3539 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3540 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
3541 break_wave_at_eoi = true;
3542 }
3543
3544 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
3545 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
3546 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
3547 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
3548 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
3549 }
3550
3551 static void
3552 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3553 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3554 const struct radv_graphics_pipeline_create_info *extra,
3555 const struct radv_blend_state *blend,
3556 const struct radv_tessellation_state *tess,
3557 const struct radv_gs_state *gs,
3558 unsigned prim, unsigned gs_out)
3559 {
3560 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
3561 struct radeon_cmdbuf *cs = &pipeline->cs;
3562
3563 cs->max_dw = 64;
3564 ctx_cs->max_dw = 256;
3565 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
3566 ctx_cs->buf = cs->buf + cs->max_dw;
3567
3568 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
3569 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
3570 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
3571 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
3572 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
3573 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
3574 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
3575 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs);
3576 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
3577 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
3578 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
3579 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
3580
3581 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
3582 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
3583
3584 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
3585 S_0286E8_WAVES(pipeline->max_waves) |
3586 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3587
3588 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3589
3590 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
3591 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
3592 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3593 } else {
3594 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3595 }
3596 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3597
3598 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3599
3600 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
3601
3602 assert(ctx_cs->cdw <= ctx_cs->max_dw);
3603 assert(cs->cdw <= cs->max_dw);
3604 }
3605
3606 static struct radv_ia_multi_vgt_param_helpers
3607 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3608 const struct radv_tessellation_state *tess,
3609 uint32_t prim)
3610 {
3611 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3612 const struct radv_device *device = pipeline->device;
3613
3614 if (radv_pipeline_has_tess(pipeline))
3615 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3616 else if (radv_pipeline_has_gs(pipeline))
3617 ia_multi_vgt_param.primgroup_size = 64;
3618 else
3619 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3620
3621 /* GS requirement. */
3622 ia_multi_vgt_param.partial_es_wave = false;
3623 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
3624 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3625 ia_multi_vgt_param.partial_es_wave = true;
3626
3627 ia_multi_vgt_param.wd_switch_on_eop = false;
3628 if (device->physical_device->rad_info.chip_class >= GFX7) {
3629 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3630 * 4 shader engines. Set 1 to pass the assertion below.
3631 * The other cases are hardware requirements. */
3632 if (device->physical_device->rad_info.max_se < 4 ||
3633 prim == V_008958_DI_PT_POLYGON ||
3634 prim == V_008958_DI_PT_LINELOOP ||
3635 prim == V_008958_DI_PT_TRIFAN ||
3636 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3637 (pipeline->graphics.prim_restart_enable &&
3638 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3639 (prim != V_008958_DI_PT_POINTLIST &&
3640 prim != V_008958_DI_PT_LINESTRIP))))
3641 ia_multi_vgt_param.wd_switch_on_eop = true;
3642 }
3643
3644 ia_multi_vgt_param.ia_switch_on_eoi = false;
3645 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3646 ia_multi_vgt_param.ia_switch_on_eoi = true;
3647 if (radv_pipeline_has_gs(pipeline) &&
3648 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3649 ia_multi_vgt_param.ia_switch_on_eoi = true;
3650 if (radv_pipeline_has_tess(pipeline)) {
3651 /* SWITCH_ON_EOI must be set if PrimID is used. */
3652 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3653 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
3654 ia_multi_vgt_param.ia_switch_on_eoi = true;
3655 }
3656
3657 ia_multi_vgt_param.partial_vs_wave = false;
3658 if (radv_pipeline_has_tess(pipeline)) {
3659 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3660 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3661 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3662 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3663 radv_pipeline_has_gs(pipeline))
3664 ia_multi_vgt_param.partial_vs_wave = true;
3665 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3666 if (device->has_distributed_tess) {
3667 if (radv_pipeline_has_gs(pipeline)) {
3668 if (device->physical_device->rad_info.chip_class <= GFX8)
3669 ia_multi_vgt_param.partial_es_wave = true;
3670 } else {
3671 ia_multi_vgt_param.partial_vs_wave = true;
3672 }
3673 }
3674 }
3675
3676 /* Workaround for a VGT hang when strip primitive types are used with
3677 * primitive restart.
3678 */
3679 if (pipeline->graphics.prim_restart_enable &&
3680 (prim == V_008958_DI_PT_LINESTRIP ||
3681 prim == V_008958_DI_PT_TRISTRIP ||
3682 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
3683 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
3684 ia_multi_vgt_param.partial_vs_wave = true;
3685 }
3686
3687 if (radv_pipeline_has_gs(pipeline)) {
3688 /* On these chips there is the possibility of a hang if the
3689 * pipeline uses a GS and partial_vs_wave is not set.
3690 *
3691 * This mostly does not hit 4-SE chips, as those typically set
3692 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
3693 * with GS due to another workaround.
3694 *
3695 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
3696 */
3697 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3698 device->physical_device->rad_info.family == CHIP_FIJI ||
3699 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3700 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3701 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
3702 device->physical_device->rad_info.family == CHIP_VEGAM) {
3703 ia_multi_vgt_param.partial_vs_wave = true;
3704 }
3705 }
3706
3707 ia_multi_vgt_param.base =
3708 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3709 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3710 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
3711 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3712 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3713
3714 return ia_multi_vgt_param;
3715 }
3716
3717
3718 static void
3719 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3720 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3721 {
3722 const VkPipelineVertexInputStateCreateInfo *vi_info =
3723 pCreateInfo->pVertexInputState;
3724 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3725
3726 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3727 const VkVertexInputAttributeDescription *desc =
3728 &vi_info->pVertexAttributeDescriptions[i];
3729 unsigned loc = desc->location;
3730 const struct vk_format_description *format_desc;
3731
3732 format_desc = vk_format_description(desc->format);
3733
3734 velems->format_size[loc] = format_desc->block.bits / 8;
3735 }
3736
3737 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3738 const VkVertexInputBindingDescription *desc =
3739 &vi_info->pVertexBindingDescriptions[i];
3740
3741 pipeline->binding_stride[desc->binding] = desc->stride;
3742 pipeline->num_vertex_bindings =
3743 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
3744 }
3745 }
3746
3747 static struct radv_shader_variant *
3748 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
3749 {
3750 int i;
3751
3752 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
3753 struct radv_shader_variant *shader =
3754 radv_get_shader(pipeline, i);
3755
3756 if (shader && shader->info.info.so.num_outputs > 0)
3757 return shader;
3758 }
3759
3760 return NULL;
3761 }
3762
3763 static VkResult
3764 radv_pipeline_init(struct radv_pipeline *pipeline,
3765 struct radv_device *device,
3766 struct radv_pipeline_cache *cache,
3767 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3768 const struct radv_graphics_pipeline_create_info *extra)
3769 {
3770 VkResult result;
3771 bool has_view_index = false;
3772
3773 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3774 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3775 if (subpass->view_mask)
3776 has_view_index = true;
3777
3778 pipeline->device = device;
3779 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3780 assert(pipeline->layout);
3781
3782 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3783
3784 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
3785 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
3786 radv_init_feedback(creation_feedback);
3787
3788 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
3789
3790 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3791 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
3792 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3793 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3794 pStages[stage] = &pCreateInfo->pStages[i];
3795 if(creation_feedback)
3796 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
3797 }
3798
3799 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
3800 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
3801
3802 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3803 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3804 uint32_t gs_out;
3805 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3806
3807 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3808
3809 if (radv_pipeline_has_gs(pipeline)) {
3810 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3811 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3812 } else {
3813 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3814 }
3815 if (extra && extra->use_rectlist) {
3816 prim = V_008958_DI_PT_RECTLIST;
3817 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3818 pipeline->graphics.can_use_guardband = true;
3819 }
3820 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3821 /* prim vertex count will need TESS changes */
3822 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3823
3824 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3825
3826 /* Ensure that some export memory is always allocated, for two reasons:
3827 *
3828 * 1) Correctness: The hardware ignores the EXEC mask if no export
3829 * memory is allocated, so KILL and alpha test do not work correctly
3830 * without this.
3831 * 2) Performance: Every shader needs at least a NULL export, even when
3832 * it writes no color/depth output. The NULL export instruction
3833 * stalls without this setting.
3834 *
3835 * Don't add this to CB_SHADER_MASK.
3836 */
3837 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3838 if (!blend.spi_shader_col_format) {
3839 if (!ps->info.info.ps.writes_z &&
3840 !ps->info.info.ps.writes_stencil &&
3841 !ps->info.info.ps.writes_sample_mask)
3842 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3843 }
3844
3845 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3846 if (pipeline->shaders[i]) {
3847 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3848 }
3849 }
3850
3851 struct radv_gs_state gs = {0};
3852 if (radv_pipeline_has_gs(pipeline)) {
3853 gs = calculate_gs_info(pCreateInfo, pipeline);
3854 calculate_gs_ring_sizes(pipeline, &gs);
3855 }
3856
3857 struct radv_tessellation_state tess = {0};
3858 if (radv_pipeline_has_tess(pipeline)) {
3859 if (prim == V_008958_DI_PT_PATCH) {
3860 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3861 pipeline->graphics.prim_vertex_count.incr = 1;
3862 }
3863 tess = calculate_tess_state(pipeline, pCreateInfo);
3864 }
3865
3866 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3867
3868 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3869
3870 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3871 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3872
3873 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3874 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3875 if (loc->sgpr_idx != -1) {
3876 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3877 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3878 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
3879 pipeline->graphics.vtx_emit_num = 3;
3880 else
3881 pipeline->graphics.vtx_emit_num = 2;
3882 }
3883
3884 /* Find the last vertex shader stage that eventually uses streamout. */
3885 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
3886
3887 result = radv_pipeline_scratch_init(device, pipeline);
3888 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3889
3890 return result;
3891 }
3892
3893 VkResult
3894 radv_graphics_pipeline_create(
3895 VkDevice _device,
3896 VkPipelineCache _cache,
3897 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3898 const struct radv_graphics_pipeline_create_info *extra,
3899 const VkAllocationCallbacks *pAllocator,
3900 VkPipeline *pPipeline)
3901 {
3902 RADV_FROM_HANDLE(radv_device, device, _device);
3903 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3904 struct radv_pipeline *pipeline;
3905 VkResult result;
3906
3907 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3908 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3909 if (pipeline == NULL)
3910 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3911
3912 result = radv_pipeline_init(pipeline, device, cache,
3913 pCreateInfo, extra);
3914 if (result != VK_SUCCESS) {
3915 radv_pipeline_destroy(device, pipeline, pAllocator);
3916 return result;
3917 }
3918
3919 *pPipeline = radv_pipeline_to_handle(pipeline);
3920
3921 return VK_SUCCESS;
3922 }
3923
3924 VkResult radv_CreateGraphicsPipelines(
3925 VkDevice _device,
3926 VkPipelineCache pipelineCache,
3927 uint32_t count,
3928 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3929 const VkAllocationCallbacks* pAllocator,
3930 VkPipeline* pPipelines)
3931 {
3932 VkResult result = VK_SUCCESS;
3933 unsigned i = 0;
3934
3935 for (; i < count; i++) {
3936 VkResult r;
3937 r = radv_graphics_pipeline_create(_device,
3938 pipelineCache,
3939 &pCreateInfos[i],
3940 NULL, pAllocator, &pPipelines[i]);
3941 if (r != VK_SUCCESS) {
3942 result = r;
3943 pPipelines[i] = VK_NULL_HANDLE;
3944 }
3945 }
3946
3947 return result;
3948 }
3949
3950
3951 static void
3952 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3953 {
3954 struct radv_shader_variant *compute_shader;
3955 struct radv_device *device = pipeline->device;
3956 unsigned compute_resource_limits;
3957 unsigned waves_per_threadgroup;
3958 uint64_t va;
3959
3960 pipeline->cs.buf = malloc(20 * 4);
3961 pipeline->cs.max_dw = 20;
3962
3963 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3964 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3965
3966 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3967 radeon_emit(&pipeline->cs, va >> 8);
3968 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3969
3970 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3971 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
3972 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
3973
3974 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3975 S_00B860_WAVES(pipeline->max_waves) |
3976 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3977
3978 /* Calculate best compute resource limits. */
3979 waves_per_threadgroup =
3980 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3981 compute_shader->info.cs.block_size[1] *
3982 compute_shader->info.cs.block_size[2], 64);
3983 compute_resource_limits =
3984 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3985
3986 if (device->physical_device->rad_info.chip_class >= GFX7) {
3987 unsigned num_cu_per_se =
3988 device->physical_device->rad_info.num_good_compute_units /
3989 device->physical_device->rad_info.max_se;
3990
3991 /* Force even distribution on all SIMDs in CU if the workgroup
3992 * size is 64. This has shown some good improvements if # of
3993 * CUs per SE is not a multiple of 4.
3994 */
3995 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3996 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3997 }
3998
3999 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4000 compute_resource_limits);
4001
4002 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4003 radeon_emit(&pipeline->cs,
4004 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4005 radeon_emit(&pipeline->cs,
4006 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4007 radeon_emit(&pipeline->cs,
4008 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4009
4010 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4011 }
4012
4013 static VkResult radv_compute_pipeline_create(
4014 VkDevice _device,
4015 VkPipelineCache _cache,
4016 const VkComputePipelineCreateInfo* pCreateInfo,
4017 const VkAllocationCallbacks* pAllocator,
4018 VkPipeline* pPipeline)
4019 {
4020 RADV_FROM_HANDLE(radv_device, device, _device);
4021 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4022 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4023 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4024 struct radv_pipeline *pipeline;
4025 VkResult result;
4026
4027 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4028 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4029 if (pipeline == NULL)
4030 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4031
4032 pipeline->device = device;
4033 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4034 assert(pipeline->layout);
4035
4036 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4037 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4038 radv_init_feedback(creation_feedback);
4039
4040 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4041 if (creation_feedback)
4042 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4043
4044 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4045 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4046
4047 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4048 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4049 result = radv_pipeline_scratch_init(device, pipeline);
4050 if (result != VK_SUCCESS) {
4051 radv_pipeline_destroy(device, pipeline, pAllocator);
4052 return result;
4053 }
4054
4055 radv_compute_generate_pm4(pipeline);
4056
4057 *pPipeline = radv_pipeline_to_handle(pipeline);
4058
4059 return VK_SUCCESS;
4060 }
4061
4062 VkResult radv_CreateComputePipelines(
4063 VkDevice _device,
4064 VkPipelineCache pipelineCache,
4065 uint32_t count,
4066 const VkComputePipelineCreateInfo* pCreateInfos,
4067 const VkAllocationCallbacks* pAllocator,
4068 VkPipeline* pPipelines)
4069 {
4070 VkResult result = VK_SUCCESS;
4071
4072 unsigned i = 0;
4073 for (; i < count; i++) {
4074 VkResult r;
4075 r = radv_compute_pipeline_create(_device, pipelineCache,
4076 &pCreateInfos[i],
4077 pAllocator, &pPipelines[i]);
4078 if (r != VK_SUCCESS) {
4079 result = r;
4080 pPipelines[i] = VK_NULL_HANDLE;
4081 }
4082 }
4083
4084 return result;
4085 }