projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Fix promotion of floats to doubles
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t cb_shader_mask;
62 uint32_t db_alpha_to_mask;
63
64 uint32_t commutative_4bit;
65
66 bool single_cb_enable;
67 bool mrt0_is_dual_src;
68 };
69
70 struct radv_dsa_order_invariance {
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
73 */
74 bool zs;
75
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
78 * fragments arrive.
79 */
80 bool pass_set;
81 };
82
83 struct radv_tessellation_state {
84 uint32_t ls_hs_config;
85 unsigned num_patches;
86 unsigned lds_size;
87 uint32_t tf_param;
88 };
89
90 static const VkPipelineMultisampleStateCreateInfo *
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
92 {
93 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
94 return pCreateInfo->pMultisampleState;
95 return NULL;
96 }
97
98 static const VkPipelineTessellationStateCreateInfo *
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
100 {
101 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
102 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
103 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
104 return pCreateInfo->pTessellationState;
105 }
106 }
107 return NULL;
108 }
109
110 static const VkPipelineDepthStencilStateCreateInfo *
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
112 {
113 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
114 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
115
116 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
117 subpass->depth_stencil_attachment)
118 return pCreateInfo->pDepthStencilState;
119 return NULL;
120 }
121
122 static const VkPipelineColorBlendStateCreateInfo *
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
124 {
125 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
126 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
127
128 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
129 subpass->has_color_att)
130 return pCreateInfo->pColorBlendState;
131 return NULL;
132 }
133
134 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
135 {
136 struct radv_shader_variant *variant = NULL;
137 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
138 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
139 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
140 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
141 else if (pipeline->shaders[MESA_SHADER_VERTEX])
142 variant = pipeline->shaders[MESA_SHADER_VERTEX];
143 else
144 return false;
145 return variant->info.is_ngg;
146 }
147
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
149 {
150 assert(radv_pipeline_has_ngg(pipeline));
151
152 struct radv_shader_variant *variant = NULL;
153 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
154 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
155 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
156 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
157 else if (pipeline->shaders[MESA_SHADER_VERTEX])
158 variant = pipeline->shaders[MESA_SHADER_VERTEX];
159 else
160 return false;
161 return variant->info.is_ngg_passthrough;
162 }
163
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
165 {
166 if (!radv_pipeline_has_gs(pipeline))
167 return false;
168
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
171 * enable NGG.
172 */
173 if (radv_pipeline_has_ngg(pipeline))
174 return false;
175
176 assert(pipeline->gs_copy_shader);
177 return true;
178 }
179
180 static void
181 radv_pipeline_destroy(struct radv_device *device,
182 struct radv_pipeline *pipeline,
183 const VkAllocationCallbacks* allocator)
184 {
185 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
186 if (pipeline->shaders[i])
187 radv_shader_variant_destroy(device, pipeline->shaders[i]);
188
189 if (pipeline->gs_copy_shader)
190 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
191
192 if(pipeline->cs.buf)
193 free(pipeline->cs.buf);
194 vk_free2(&device->alloc, allocator, pipeline);
195 }
196
197 void radv_DestroyPipeline(
198 VkDevice _device,
199 VkPipeline _pipeline,
200 const VkAllocationCallbacks* pAllocator)
201 {
202 RADV_FROM_HANDLE(radv_device, device, _device);
203 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
204
205 if (!_pipeline)
206 return;
207
208 radv_pipeline_destroy(device, pipeline, pAllocator);
209 }
210
211 static uint32_t get_hash_flags(struct radv_device *device)
212 {
213 uint32_t hash_flags = 0;
214
215 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
216 hash_flags |= RADV_HASH_SHADER_NO_NGG;
217 if (device->physical_device->cs_wave_size == 32)
218 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
219 if (device->physical_device->ps_wave_size == 32)
220 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
221 if (device->physical_device->ge_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
223 if (device->physical_device->use_aco)
224 hash_flags |= RADV_HASH_SHADER_ACO;
225 return hash_flags;
226 }
227
228 static VkResult
229 radv_pipeline_scratch_init(struct radv_device *device,
230 struct radv_pipeline *pipeline)
231 {
232 unsigned scratch_bytes_per_wave = 0;
233 unsigned max_waves = 0;
234 unsigned min_waves = 1;
235
236 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
237 if (pipeline->shaders[i] &&
238 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
239 unsigned max_stage_waves = device->scratch_waves;
240
241 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
242 pipeline->shaders[i]->config.scratch_bytes_per_wave);
243
244 max_stage_waves = MIN2(max_stage_waves,
245 4 * device->physical_device->rad_info.num_good_compute_units *
246 (256 / pipeline->shaders[i]->config.num_vgprs));
247 max_waves = MAX2(max_waves, max_stage_waves);
248 }
249 }
250
251 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
252 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
253 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
254 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
255 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
256 }
257
258 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
259 pipeline->max_waves = max_waves;
260 return VK_SUCCESS;
261 }
262
263 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
264 {
265 switch (op) {
266 case VK_LOGIC_OP_CLEAR:
267 return V_028808_ROP3_CLEAR;
268 case VK_LOGIC_OP_AND:
269 return V_028808_ROP3_AND;
270 case VK_LOGIC_OP_AND_REVERSE:
271 return V_028808_ROP3_AND_REVERSE;
272 case VK_LOGIC_OP_COPY:
273 return V_028808_ROP3_COPY;
274 case VK_LOGIC_OP_AND_INVERTED:
275 return V_028808_ROP3_AND_INVERTED;
276 case VK_LOGIC_OP_NO_OP:
277 return V_028808_ROP3_NO_OP;
278 case VK_LOGIC_OP_XOR:
279 return V_028808_ROP3_XOR;
280 case VK_LOGIC_OP_OR:
281 return V_028808_ROP3_OR;
282 case VK_LOGIC_OP_NOR:
283 return V_028808_ROP3_NOR;
284 case VK_LOGIC_OP_EQUIVALENT:
285 return V_028808_ROP3_EQUIVALENT;
286 case VK_LOGIC_OP_INVERT:
287 return V_028808_ROP3_INVERT;
288 case VK_LOGIC_OP_OR_REVERSE:
289 return V_028808_ROP3_OR_REVERSE;
290 case VK_LOGIC_OP_COPY_INVERTED:
291 return V_028808_ROP3_COPY_INVERTED;
292 case VK_LOGIC_OP_OR_INVERTED:
293 return V_028808_ROP3_OR_INVERTED;
294 case VK_LOGIC_OP_NAND:
295 return V_028808_ROP3_NAND;
296 case VK_LOGIC_OP_SET:
297 return V_028808_ROP3_SET;
298 default:
299 unreachable("Unhandled logic op");
300 }
301 }
302
303
304 static uint32_t si_translate_blend_function(VkBlendOp op)
305 {
306 switch (op) {
307 case VK_BLEND_OP_ADD:
308 return V_028780_COMB_DST_PLUS_SRC;
309 case VK_BLEND_OP_SUBTRACT:
310 return V_028780_COMB_SRC_MINUS_DST;
311 case VK_BLEND_OP_REVERSE_SUBTRACT:
312 return V_028780_COMB_DST_MINUS_SRC;
313 case VK_BLEND_OP_MIN:
314 return V_028780_COMB_MIN_DST_SRC;
315 case VK_BLEND_OP_MAX:
316 return V_028780_COMB_MAX_DST_SRC;
317 default:
318 return 0;
319 }
320 }
321
322 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
323 {
324 switch (factor) {
325 case VK_BLEND_FACTOR_ZERO:
326 return V_028780_BLEND_ZERO;
327 case VK_BLEND_FACTOR_ONE:
328 return V_028780_BLEND_ONE;
329 case VK_BLEND_FACTOR_SRC_COLOR:
330 return V_028780_BLEND_SRC_COLOR;
331 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
332 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
333 case VK_BLEND_FACTOR_DST_COLOR:
334 return V_028780_BLEND_DST_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
336 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
337 case VK_BLEND_FACTOR_SRC_ALPHA:
338 return V_028780_BLEND_SRC_ALPHA;
339 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
340 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
341 case VK_BLEND_FACTOR_DST_ALPHA:
342 return V_028780_BLEND_DST_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
345 case VK_BLEND_FACTOR_CONSTANT_COLOR:
346 return V_028780_BLEND_CONSTANT_COLOR;
347 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
348 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
349 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
350 return V_028780_BLEND_CONSTANT_ALPHA;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
353 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
354 return V_028780_BLEND_SRC_ALPHA_SATURATE;
355 case VK_BLEND_FACTOR_SRC1_COLOR:
356 return V_028780_BLEND_SRC1_COLOR;
357 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
358 return V_028780_BLEND_INV_SRC1_COLOR;
359 case VK_BLEND_FACTOR_SRC1_ALPHA:
360 return V_028780_BLEND_SRC1_ALPHA;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
362 return V_028780_BLEND_INV_SRC1_ALPHA;
363 default:
364 return 0;
365 }
366 }
367
368 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
369 {
370 switch (op) {
371 case VK_BLEND_OP_ADD:
372 return V_028760_OPT_COMB_ADD;
373 case VK_BLEND_OP_SUBTRACT:
374 return V_028760_OPT_COMB_SUBTRACT;
375 case VK_BLEND_OP_REVERSE_SUBTRACT:
376 return V_028760_OPT_COMB_REVSUBTRACT;
377 case VK_BLEND_OP_MIN:
378 return V_028760_OPT_COMB_MIN;
379 case VK_BLEND_OP_MAX:
380 return V_028760_OPT_COMB_MAX;
381 default:
382 return V_028760_OPT_COMB_BLEND_DISABLED;
383 }
384 }
385
386 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
387 {
388 switch (factor) {
389 case VK_BLEND_FACTOR_ZERO:
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
391 case VK_BLEND_FACTOR_ONE:
392 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
393 case VK_BLEND_FACTOR_SRC_COLOR:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
395 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
396 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
397 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
398 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
399 case VK_BLEND_FACTOR_SRC_ALPHA:
400 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
401 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
402 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
403 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
404 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
405 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
406 default:
407 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
408 }
409 }
410
411 /**
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 */
415 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
416 unsigned *dst_factor, unsigned expected_dst,
417 unsigned replacement_src)
418 {
419 if (*src_factor == expected_dst &&
420 *dst_factor == VK_BLEND_FACTOR_ZERO) {
421 *src_factor = VK_BLEND_FACTOR_ZERO;
422 *dst_factor = replacement_src;
423
424 /* Commuting the operands requires reversing subtractions. */
425 if (*func == VK_BLEND_OP_SUBTRACT)
426 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
427 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
428 *func = VK_BLEND_OP_SUBTRACT;
429 }
430 }
431
432 static bool si_blend_factor_uses_dst(unsigned factor)
433 {
434 return factor == VK_BLEND_FACTOR_DST_COLOR ||
435 factor == VK_BLEND_FACTOR_DST_ALPHA ||
436 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
437 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
438 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
439 }
440
441 static bool is_dual_src(VkBlendFactor factor)
442 {
443 switch (factor) {
444 case VK_BLEND_FACTOR_SRC1_COLOR:
445 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
446 case VK_BLEND_FACTOR_SRC1_ALPHA:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
448 return true;
449 default:
450 return false;
451 }
452 }
453
454 static unsigned si_choose_spi_color_format(VkFormat vk_format,
455 bool blend_enable,
456 bool blend_need_alpha)
457 {
458 const struct vk_format_description *desc = vk_format_description(vk_format);
459 unsigned format, ntype, swap;
460
461 /* Alpha is needed for alpha-to-coverage.
462 * Blending may be with or without alpha.
463 */
464 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
465 unsigned alpha = 0; /* exports alpha, but may not support blending */
466 unsigned blend = 0; /* supports blending, but may not export alpha */
467 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
468
469 format = radv_translate_colorformat(vk_format);
470 ntype = radv_translate_color_numformat(vk_format, desc,
471 vk_format_get_first_non_void_channel(vk_format));
472 swap = radv_translate_colorswap(vk_format, false);
473
474 /* Choose the SPI color formats. These are required values for Stoney/RB+.
475 * Other chips have multiple choices, though they are not necessarily better.
476 */
477 switch (format) {
478 case V_028C70_COLOR_5_6_5:
479 case V_028C70_COLOR_1_5_5_5:
480 case V_028C70_COLOR_5_5_5_1:
481 case V_028C70_COLOR_4_4_4_4:
482 case V_028C70_COLOR_10_11_11:
483 case V_028C70_COLOR_11_11_10:
484 case V_028C70_COLOR_8:
485 case V_028C70_COLOR_8_8:
486 case V_028C70_COLOR_8_8_8_8:
487 case V_028C70_COLOR_10_10_10_2:
488 case V_028C70_COLOR_2_10_10_10:
489 if (ntype == V_028C70_NUMBER_UINT)
490 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
491 else if (ntype == V_028C70_NUMBER_SINT)
492 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
493 else
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
495 break;
496
497 case V_028C70_COLOR_16:
498 case V_028C70_COLOR_16_16:
499 case V_028C70_COLOR_16_16_16_16:
500 if (ntype == V_028C70_NUMBER_UNORM ||
501 ntype == V_028C70_NUMBER_SNORM) {
502 /* UNORM16 and SNORM16 don't support blending */
503 if (ntype == V_028C70_NUMBER_UNORM)
504 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
505 else
506 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
507
508 /* Use 32 bits per channel for blending. */
509 if (format == V_028C70_COLOR_16) {
510 if (swap == V_028C70_SWAP_STD) { /* R */
511 blend = V_028714_SPI_SHADER_32_R;
512 blend_alpha = V_028714_SPI_SHADER_32_AR;
513 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
514 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
515 else
516 assert(0);
517 } else if (format == V_028C70_COLOR_16_16) {
518 if (swap == V_028C70_SWAP_STD) { /* RG */
519 blend = V_028714_SPI_SHADER_32_GR;
520 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
521 } else if (swap == V_028C70_SWAP_ALT) /* RA */
522 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
523 else
524 assert(0);
525 } else /* 16_16_16_16 */
526 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
527 } else if (ntype == V_028C70_NUMBER_UINT)
528 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
529 else if (ntype == V_028C70_NUMBER_SINT)
530 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
531 else if (ntype == V_028C70_NUMBER_FLOAT)
532 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
533 else
534 assert(0);
535 break;
536
537 case V_028C70_COLOR_32:
538 if (swap == V_028C70_SWAP_STD) { /* R */
539 blend = normal = V_028714_SPI_SHADER_32_R;
540 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
541 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
542 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
543 else
544 assert(0);
545 break;
546
547 case V_028C70_COLOR_32_32:
548 if (swap == V_028C70_SWAP_STD) { /* RG */
549 blend = normal = V_028714_SPI_SHADER_32_GR;
550 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
551 } else if (swap == V_028C70_SWAP_ALT) /* RA */
552 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
553 else
554 assert(0);
555 break;
556
557 case V_028C70_COLOR_32_32_32_32:
558 case V_028C70_COLOR_8_24:
559 case V_028C70_COLOR_24_8:
560 case V_028C70_COLOR_X24_8_32_FLOAT:
561 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
562 break;
563
564 default:
565 unreachable("unhandled blend format");
566 }
567
568 if (blend_enable && blend_need_alpha)
569 return blend_alpha;
570 else if(blend_need_alpha)
571 return alpha;
572 else if(blend_enable)
573 return blend;
574 else
575 return normal;
576 }
577
578 static void
579 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
580 const VkGraphicsPipelineCreateInfo *pCreateInfo,
581 struct radv_blend_state *blend)
582 {
583 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
584 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
585 unsigned col_format = 0;
586 unsigned num_targets;
587
588 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
589 unsigned cf;
590
591 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
592 cf = V_028714_SPI_SHADER_ZERO;
593 } else {
594 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
595 bool blend_enable =
596 blend->blend_enable_4bit & (0xfu << (i * 4));
597
598 cf = si_choose_spi_color_format(attachment->format,
599 blend_enable,
600 blend->need_src_alpha & (1 << i));
601 }
602
603 col_format |= cf << (4 * i);
604 }
605
606 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
607 /* When a subpass doesn't have any color attachments, write the
608 * alpha channel of MRT0 when alpha coverage is enabled because
609 * the depth attachment needs it.
610 */
611 col_format |= V_028714_SPI_SHADER_32_AR;
612 }
613
614 /* If the i-th target format is set, all previous target formats must
615 * be non-zero to avoid hangs.
616 */
617 num_targets = (util_last_bit(col_format) + 3) / 4;
618 for (unsigned i = 0; i < num_targets; i++) {
619 if (!(col_format & (0xf << (i * 4)))) {
620 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
621 }
622 }
623
624 /* The output for dual source blending should have the same format as
625 * the first output.
626 */
627 if (blend->mrt0_is_dual_src)
628 col_format |= (col_format & 0xf) << 4;
629
630 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
631 blend->spi_shader_col_format = col_format;
632 }
633
634 static bool
635 format_is_int8(VkFormat format)
636 {
637 const struct vk_format_description *desc = vk_format_description(format);
638 int channel = vk_format_get_first_non_void_channel(format);
639
640 return channel >= 0 && desc->channel[channel].pure_integer &&
641 desc->channel[channel].size == 8;
642 }
643
644 static bool
645 format_is_int10(VkFormat format)
646 {
647 const struct vk_format_description *desc = vk_format_description(format);
648
649 if (desc->nr_channels != 4)
650 return false;
651 for (unsigned i = 0; i < 4; i++) {
652 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
653 return true;
654 }
655 return false;
656 }
657
658 /*
659 * Ordered so that for each i,
660 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
661 */
662 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
663 VK_FORMAT_R32_SFLOAT,
664 VK_FORMAT_R32G32_SFLOAT,
665 VK_FORMAT_R8G8B8A8_UNORM,
666 VK_FORMAT_R16G16B16A16_UNORM,
667 VK_FORMAT_R16G16B16A16_SNORM,
668 VK_FORMAT_R16G16B16A16_UINT,
669 VK_FORMAT_R16G16B16A16_SINT,
670 VK_FORMAT_R32G32B32A32_SFLOAT,
671 VK_FORMAT_R8G8B8A8_UINT,
672 VK_FORMAT_R8G8B8A8_SINT,
673 VK_FORMAT_A2R10G10B10_UINT_PACK32,
674 VK_FORMAT_A2R10G10B10_SINT_PACK32,
675 };
676
677 unsigned radv_format_meta_fs_key(VkFormat format)
678 {
679 unsigned col_format = si_choose_spi_color_format(format, false, false);
680
681 assert(col_format != V_028714_SPI_SHADER_32_AR);
682 if (col_format >= V_028714_SPI_SHADER_32_AR)
683 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
684
685 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
686 bool is_int8 = format_is_int8(format);
687 bool is_int10 = format_is_int10(format);
688
689 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
690 }
691
692 static void
693 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
694 unsigned *is_int8, unsigned *is_int10)
695 {
696 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
697 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
698 *is_int8 = 0;
699 *is_int10 = 0;
700
701 for (unsigned i = 0; i < subpass->color_count; ++i) {
702 struct radv_render_pass_attachment *attachment;
703
704 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
705 continue;
706
707 attachment = pass->attachments + subpass->color_attachments[i].attachment;
708
709 if (format_is_int8(attachment->format))
710 *is_int8 |= 1 << i;
711 if (format_is_int10(attachment->format))
712 *is_int10 |= 1 << i;
713 }
714 }
715
716 static void
717 radv_blend_check_commutativity(struct radv_blend_state *blend,
718 VkBlendOp op, VkBlendFactor src,
719 VkBlendFactor dst, unsigned chanmask)
720 {
721 /* Src factor is allowed when it does not depend on Dst. */
722 static const uint32_t src_allowed =
723 (1u << VK_BLEND_FACTOR_ONE) |
724 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
725 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
726 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
727 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
728 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
729 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
730 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
731 (1u << VK_BLEND_FACTOR_ZERO) |
732 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
733 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
734 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
735 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
736 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
737 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
738
739 if (dst == VK_BLEND_FACTOR_ONE &&
740 (src_allowed & (1u << src))) {
741 /* Addition is commutative, but floating point addition isn't
742 * associative: subtle changes can be introduced via different
743 * rounding. Be conservative, only enable for min and max.
744 */
745 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
746 blend->commutative_4bit |= chanmask;
747 }
748 }
749
750 static struct radv_blend_state
751 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
752 const VkGraphicsPipelineCreateInfo *pCreateInfo,
753 const struct radv_graphics_pipeline_create_info *extra)
754 {
755 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
756 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
757 struct radv_blend_state blend = {0};
758 unsigned mode = V_028808_CB_NORMAL;
759 int i;
760
761 if (extra && extra->custom_blend_mode) {
762 blend.single_cb_enable = true;
763 mode = extra->custom_blend_mode;
764 }
765
766 blend.cb_color_control = 0;
767 if (vkblend) {
768 if (vkblend->logicOpEnable)
769 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
770 else
771 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
772 }
773
774 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
775 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
776 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
777 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
778 S_028B70_OFFSET_ROUND(1);
779
780 if (vkms && vkms->alphaToCoverageEnable) {
781 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
782 blend.need_src_alpha |= 0x1;
783 }
784
785 blend.cb_target_mask = 0;
786 if (vkblend) {
787 for (i = 0; i < vkblend->attachmentCount; i++) {
788 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
789 unsigned blend_cntl = 0;
790 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
791 VkBlendOp eqRGB = att->colorBlendOp;
792 VkBlendFactor srcRGB = att->srcColorBlendFactor;
793 VkBlendFactor dstRGB = att->dstColorBlendFactor;
794 VkBlendOp eqA = att->alphaBlendOp;
795 VkBlendFactor srcA = att->srcAlphaBlendFactor;
796 VkBlendFactor dstA = att->dstAlphaBlendFactor;
797
798 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
799
800 if (!att->colorWriteMask)
801 continue;
802
803 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
804 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
805 if (!att->blendEnable) {
806 blend.cb_blend_control[i] = blend_cntl;
807 continue;
808 }
809
810 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
811 if (i == 0)
812 blend.mrt0_is_dual_src = true;
813
814 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
815 srcRGB = VK_BLEND_FACTOR_ONE;
816 dstRGB = VK_BLEND_FACTOR_ONE;
817 }
818 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
819 srcA = VK_BLEND_FACTOR_ONE;
820 dstA = VK_BLEND_FACTOR_ONE;
821 }
822
823 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
824 0x7 << (4 * i));
825 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
826 0x8 << (4 * i));
827
828 /* Blending optimizations for RB+.
829 * These transformations don't change the behavior.
830 *
831 * First, get rid of DST in the blend factors:
832 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
833 */
834 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
835 VK_BLEND_FACTOR_DST_COLOR,
836 VK_BLEND_FACTOR_SRC_COLOR);
837
838 si_blend_remove_dst(&eqA, &srcA, &dstA,
839 VK_BLEND_FACTOR_DST_COLOR,
840 VK_BLEND_FACTOR_SRC_COLOR);
841
842 si_blend_remove_dst(&eqA, &srcA, &dstA,
843 VK_BLEND_FACTOR_DST_ALPHA,
844 VK_BLEND_FACTOR_SRC_ALPHA);
845
846 /* Look up the ideal settings from tables. */
847 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
848 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
849 srcA_opt = si_translate_blend_opt_factor(srcA, true);
850 dstA_opt = si_translate_blend_opt_factor(dstA, true);
851
852 /* Handle interdependencies. */
853 if (si_blend_factor_uses_dst(srcRGB))
854 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
855 if (si_blend_factor_uses_dst(srcA))
856 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
857
858 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
859 (dstRGB == VK_BLEND_FACTOR_ZERO ||
860 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
861 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
862 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
863
864 /* Set the final value. */
865 blend.sx_mrt_blend_opt[i] =
866 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
867 S_028760_COLOR_DST_OPT(dstRGB_opt) |
868 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
869 S_028760_ALPHA_SRC_OPT(srcA_opt) |
870 S_028760_ALPHA_DST_OPT(dstA_opt) |
871 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
872 blend_cntl |= S_028780_ENABLE(1);
873
874 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
875 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
876 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
877 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
878 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
879 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
880 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
881 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
882 }
883 blend.cb_blend_control[i] = blend_cntl;
884
885 blend.blend_enable_4bit |= 0xfu << (i * 4);
886
887 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
888 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
889 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
890 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
891 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
892 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
893 blend.need_src_alpha |= 1 << i;
894 }
895 for (i = vkblend->attachmentCount; i < 8; i++) {
896 blend.cb_blend_control[i] = 0;
897 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
898 }
899 }
900
901 if (pipeline->device->physical_device->rad_info.has_rbplus) {
902 /* Disable RB+ blend optimizations for dual source blending. */
903 if (blend.mrt0_is_dual_src) {
904 for (i = 0; i < 8; i++) {
905 blend.sx_mrt_blend_opt[i] =
906 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
907 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
908 }
909 }
910
911 /* RB+ doesn't work with dual source blending, logic op and
912 * RESOLVE.
913 */
914 if (blend.mrt0_is_dual_src ||
915 (vkblend && vkblend->logicOpEnable) ||
916 mode == V_028808_CB_RESOLVE)
917 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
918 }
919
920 if (blend.cb_target_mask)
921 blend.cb_color_control |= S_028808_MODE(mode);
922 else
923 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
924
925 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
926 return blend;
927 }
928
929 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
930 {
931 switch (op) {
932 case VK_STENCIL_OP_KEEP:
933 return V_02842C_STENCIL_KEEP;
934 case VK_STENCIL_OP_ZERO:
935 return V_02842C_STENCIL_ZERO;
936 case VK_STENCIL_OP_REPLACE:
937 return V_02842C_STENCIL_REPLACE_TEST;
938 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
939 return V_02842C_STENCIL_ADD_CLAMP;
940 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
941 return V_02842C_STENCIL_SUB_CLAMP;
942 case VK_STENCIL_OP_INVERT:
943 return V_02842C_STENCIL_INVERT;
944 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
945 return V_02842C_STENCIL_ADD_WRAP;
946 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
947 return V_02842C_STENCIL_SUB_WRAP;
948 default:
949 return 0;
950 }
951 }
952
953 static uint32_t si_translate_fill(VkPolygonMode func)
954 {
955 switch(func) {
956 case VK_POLYGON_MODE_FILL:
957 return V_028814_X_DRAW_TRIANGLES;
958 case VK_POLYGON_MODE_LINE:
959 return V_028814_X_DRAW_LINES;
960 case VK_POLYGON_MODE_POINT:
961 return V_028814_X_DRAW_POINTS;
962 default:
963 assert(0);
964 return V_028814_X_DRAW_POINTS;
965 }
966 }
967
968 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
969 {
970 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
971 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
972 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
973 uint32_t ps_iter_samples = 1;
974 uint32_t num_samples;
975
976 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
977 *
978 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
979 * subpass uses color attachments, totalSamples is the number of
980 * samples of the color attachments. Otherwise, totalSamples is the
981 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
982 * specified at pipeline creation time."
983 */
984 if (subpass->has_color_att) {
985 num_samples = subpass->color_sample_count;
986 } else {
987 num_samples = vkms->rasterizationSamples;
988 }
989
990 if (vkms->sampleShadingEnable) {
991 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
992 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
993 }
994 return ps_iter_samples;
995 }
996
997 static bool
998 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
999 {
1000 return pCreateInfo->depthTestEnable &&
1001 pCreateInfo->depthWriteEnable &&
1002 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
1003 }
1004
1005 static bool
1006 radv_writes_stencil(const VkStencilOpState *state)
1007 {
1008 return state->writeMask &&
1009 (state->failOp != VK_STENCIL_OP_KEEP ||
1010 state->passOp != VK_STENCIL_OP_KEEP ||
1011 state->depthFailOp != VK_STENCIL_OP_KEEP);
1012 }
1013
1014 static bool
1015 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
1016 {
1017 return pCreateInfo->stencilTestEnable &&
1018 (radv_writes_stencil(&pCreateInfo->front) ||
1019 radv_writes_stencil(&pCreateInfo->back));
1020 }
1021
1022 static bool
1023 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
1024 {
1025 return radv_is_depth_write_enabled(pCreateInfo) ||
1026 radv_is_stencil_write_enabled(pCreateInfo);
1027 }
1028
1029 static bool
1030 radv_order_invariant_stencil_op(VkStencilOp op)
1031 {
1032 /* REPLACE is normally order invariant, except when the stencil
1033 * reference value is written by the fragment shader. Tracking this
1034 * interaction does not seem worth the effort, so be conservative.
1035 */
1036 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
1037 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
1038 op != VK_STENCIL_OP_REPLACE;
1039 }
1040
1041 static bool
1042 radv_order_invariant_stencil_state(const VkStencilOpState *state)
1043 {
1044 /* Compute whether, assuming Z writes are disabled, this stencil state
1045 * is order invariant in the sense that the set of passing fragments as
1046 * well as the final stencil buffer result does not depend on the order
1047 * of fragments.
1048 */
1049 return !state->writeMask ||
1050 /* The following assumes that Z writes are disabled. */
1051 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
1052 radv_order_invariant_stencil_op(state->passOp) &&
1053 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1054 (state->compareOp == VK_COMPARE_OP_NEVER &&
1055 radv_order_invariant_stencil_op(state->failOp));
1056 }
1057
1058 static bool
1059 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1060 struct radv_blend_state *blend,
1061 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1062 {
1063 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1064 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1065 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1066 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
1067 unsigned colormask = blend->cb_target_enabled_4bit;
1068
1069 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1070 return false;
1071
1072 /* Be conservative if a logic operation is enabled with color buffers. */
1073 if (colormask && vkblend && vkblend->logicOpEnable)
1074 return false;
1075
1076 /* Default depth/stencil invariance when no attachment is bound. */
1077 struct radv_dsa_order_invariance dsa_order_invariant = {
1078 .zs = true, .pass_set = true
1079 };
1080
1081 if (vkds) {
1082 struct radv_render_pass_attachment *attachment =
1083 pass->attachments + subpass->depth_stencil_attachment->attachment;
1084 bool has_stencil = vk_format_is_stencil(attachment->format);
1085 struct radv_dsa_order_invariance order_invariance[2];
1086 struct radv_shader_variant *ps =
1087 pipeline->shaders[MESA_SHADER_FRAGMENT];
1088
1089 /* Compute depth/stencil order invariance in order to know if
1090 * it's safe to enable out-of-order.
1091 */
1092 bool zfunc_is_ordered =
1093 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1094 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1095 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1096 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1097 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1098
1099 bool nozwrite_and_order_invariant_stencil =
1100 !radv_is_ds_write_enabled(vkds) ||
1101 (!radv_is_depth_write_enabled(vkds) &&
1102 radv_order_invariant_stencil_state(&vkds->front) &&
1103 radv_order_invariant_stencil_state(&vkds->back));
1104
1105 order_invariance[1].zs =
1106 nozwrite_and_order_invariant_stencil ||
1107 (!radv_is_stencil_write_enabled(vkds) &&
1108 zfunc_is_ordered);
1109 order_invariance[0].zs =
1110 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1111
1112 order_invariance[1].pass_set =
1113 nozwrite_and_order_invariant_stencil ||
1114 (!radv_is_stencil_write_enabled(vkds) &&
1115 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1116 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1117 order_invariance[0].pass_set =
1118 !radv_is_depth_write_enabled(vkds) ||
1119 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1120 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1121
1122 dsa_order_invariant = order_invariance[has_stencil];
1123 if (!dsa_order_invariant.zs)
1124 return false;
1125
1126 /* The set of PS invocations is always order invariant,
1127 * except when early Z/S tests are requested.
1128 */
1129 if (ps &&
1130 ps->info.ps.writes_memory &&
1131 ps->info.ps.early_fragment_test &&
1132 !dsa_order_invariant.pass_set)
1133 return false;
1134
1135 /* Determine if out-of-order rasterization should be disabled
1136 * when occlusion queries are used.
1137 */
1138 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1139 !dsa_order_invariant.pass_set;
1140 }
1141
1142 /* No color buffers are enabled for writing. */
1143 if (!colormask)
1144 return true;
1145
1146 unsigned blendmask = colormask & blend->blend_enable_4bit;
1147
1148 if (blendmask) {
1149 /* Only commutative blending. */
1150 if (blendmask & ~blend->commutative_4bit)
1151 return false;
1152
1153 if (!dsa_order_invariant.pass_set)
1154 return false;
1155 }
1156
1157 if (colormask & ~blendmask)
1158 return false;
1159
1160 return true;
1161 }
1162
1163 static void
1164 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1165 struct radv_blend_state *blend,
1166 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1167 {
1168 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1169 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1170 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1171 bool out_of_order_rast = false;
1172 int ps_iter_samples = 1;
1173 uint32_t mask = 0xffff;
1174
1175 if (vkms) {
1176 ms->num_samples = vkms->rasterizationSamples;
1177
1178 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1179 *
1180 * "Sample shading is enabled for a graphics pipeline:
1181 *
1182 * - If the interface of the fragment shader entry point of the
1183 * graphics pipeline includes an input variable decorated
1184 * with SampleId or SamplePosition. In this case
1185 * minSampleShadingFactor takes the value 1.0.
1186 * - Else if the sampleShadingEnable member of the
1187 * VkPipelineMultisampleStateCreateInfo structure specified
1188 * when creating the graphics pipeline is set to VK_TRUE. In
1189 * this case minSampleShadingFactor takes the value of
1190 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1191 *
1192 * Otherwise, sample shading is considered disabled."
1193 */
1194 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1195 ps_iter_samples = ms->num_samples;
1196 } else {
1197 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1198 }
1199 } else {
1200 ms->num_samples = 1;
1201 }
1202
1203 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1204 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1205 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1206 /* Out-of-order rasterization is explicitly enabled by the
1207 * application.
1208 */
1209 out_of_order_rast = true;
1210 } else {
1211 /* Determine if the driver can enable out-of-order
1212 * rasterization internally.
1213 */
1214 out_of_order_rast =
1215 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1216 }
1217
1218 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1219 ms->pa_sc_aa_config = 0;
1220 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1221 S_028804_INCOHERENT_EQAA_READS(1) |
1222 S_028804_INTERPOLATE_COMP_Z(1) |
1223 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1224 ms->pa_sc_mode_cntl_1 =
1225 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1226 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1227 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1228 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1229 /* always 1: */
1230 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1231 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1232 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1233 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1234 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1235 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1236 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1237 S_028A48_VPORT_SCISSOR_ENABLE(1);
1238
1239 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1240 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1241 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1242 if (rast_line) {
1243 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1244 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1245 /* From the Vulkan spec 1.1.129:
1246 *
1247 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1248 * are being rasterized, sample locations may all be
1249 * treated as being at the pixel center (this may
1250 * affect attribute and depth interpolation)."
1251 */
1252 ms->num_samples = 1;
1253 }
1254 }
1255
1256 if (ms->num_samples > 1) {
1257 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1258 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1259 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1260 unsigned log_samples = util_logbase2(ms->num_samples);
1261 unsigned log_z_samples = util_logbase2(z_samples);
1262 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1263 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1264 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1265 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1266 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1267 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1268 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1269 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1270 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1271 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1272 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1273 if (ps_iter_samples > 1)
1274 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1275 }
1276
1277 if (vkms && vkms->pSampleMask) {
1278 mask = vkms->pSampleMask[0] & 0xffff;
1279 }
1280
1281 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1282 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1283 }
1284
1285 static bool
1286 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1287 {
1288 switch (topology) {
1289 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1290 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1291 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1292 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1293 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1294 return false;
1295 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1296 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1297 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1298 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1299 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1300 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1301 return true;
1302 default:
1303 unreachable("unhandled primitive type");
1304 }
1305 }
1306
1307 static uint32_t
1308 si_translate_prim(enum VkPrimitiveTopology topology)
1309 {
1310 switch (topology) {
1311 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1312 return V_008958_DI_PT_POINTLIST;
1313 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1314 return V_008958_DI_PT_LINELIST;
1315 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1316 return V_008958_DI_PT_LINESTRIP;
1317 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1318 return V_008958_DI_PT_TRILIST;
1319 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1320 return V_008958_DI_PT_TRISTRIP;
1321 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1322 return V_008958_DI_PT_TRIFAN;
1323 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1324 return V_008958_DI_PT_LINELIST_ADJ;
1325 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1326 return V_008958_DI_PT_LINESTRIP_ADJ;
1327 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1328 return V_008958_DI_PT_TRILIST_ADJ;
1329 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1330 return V_008958_DI_PT_TRISTRIP_ADJ;
1331 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1332 return V_008958_DI_PT_PATCH;
1333 default:
1334 assert(0);
1335 return 0;
1336 }
1337 }
1338
1339 static uint32_t
1340 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1341 {
1342 switch (gl_prim) {
1343 case 0: /* GL_POINTS */
1344 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1345 case 1: /* GL_LINES */
1346 case 3: /* GL_LINE_STRIP */
1347 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1348 case 0x8E7A: /* GL_ISOLINES */
1349 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1350
1351 case 4: /* GL_TRIANGLES */
1352 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1353 case 5: /* GL_TRIANGLE_STRIP */
1354 case 7: /* GL_QUADS */
1355 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1356 default:
1357 assert(0);
1358 return 0;
1359 }
1360 }
1361
1362 static uint32_t
1363 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1364 {
1365 switch (topology) {
1366 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1367 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1368 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1369 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1370 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1371 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1372 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1373 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1374 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1375 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1376 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1377 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1378 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1379 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1380 default:
1381 assert(0);
1382 return 0;
1383 }
1384 }
1385
1386 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1387 {
1388 switch(state) {
1389 case VK_DYNAMIC_STATE_VIEWPORT:
1390 return RADV_DYNAMIC_VIEWPORT;
1391 case VK_DYNAMIC_STATE_SCISSOR:
1392 return RADV_DYNAMIC_SCISSOR;
1393 case VK_DYNAMIC_STATE_LINE_WIDTH:
1394 return RADV_DYNAMIC_LINE_WIDTH;
1395 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1396 return RADV_DYNAMIC_DEPTH_BIAS;
1397 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1398 return RADV_DYNAMIC_BLEND_CONSTANTS;
1399 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1400 return RADV_DYNAMIC_DEPTH_BOUNDS;
1401 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1402 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1403 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1404 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1405 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1406 return RADV_DYNAMIC_STENCIL_REFERENCE;
1407 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1408 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1409 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1410 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1411 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1412 return RADV_DYNAMIC_LINE_STIPPLE;
1413 default:
1414 unreachable("Unhandled dynamic state");
1415 }
1416 }
1417
1418 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1419 {
1420 uint32_t states = RADV_DYNAMIC_ALL;
1421
1422 /* If rasterization is disabled we do not care about any of the dynamic states,
1423 * since they are all rasterization related only. */
1424 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1425 return 0;
1426
1427 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1428 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1429
1430 if (!pCreateInfo->pDepthStencilState ||
1431 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1432 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1433
1434 if (!pCreateInfo->pDepthStencilState ||
1435 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1436 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1437 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1438 RADV_DYNAMIC_STENCIL_REFERENCE);
1439
1440 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1441 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1442
1443 if (!pCreateInfo->pMultisampleState ||
1444 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1445 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1446 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1447
1448 if (!pCreateInfo->pRasterizationState ||
1449 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1450 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1451 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1452
1453 /* TODO: blend constants & line width. */
1454
1455 return states;
1456 }
1457
1458
1459 static void
1460 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1461 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1462 {
1463 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1464 uint32_t states = needed_states;
1465 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1466 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1467
1468 pipeline->dynamic_state = default_dynamic_state;
1469 pipeline->graphics.needed_dynamic_state = needed_states;
1470
1471 if (pCreateInfo->pDynamicState) {
1472 /* Remove all of the states that are marked as dynamic */
1473 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1474 for (uint32_t s = 0; s < count; s++)
1475 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1476 }
1477
1478 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1479
1480 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1481 assert(pCreateInfo->pViewportState);
1482
1483 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1484 if (states & RADV_DYNAMIC_VIEWPORT) {
1485 typed_memcpy(dynamic->viewport.viewports,
1486 pCreateInfo->pViewportState->pViewports,
1487 pCreateInfo->pViewportState->viewportCount);
1488 }
1489 }
1490
1491 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1492 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1493 if (states & RADV_DYNAMIC_SCISSOR) {
1494 typed_memcpy(dynamic->scissor.scissors,
1495 pCreateInfo->pViewportState->pScissors,
1496 pCreateInfo->pViewportState->scissorCount);
1497 }
1498 }
1499
1500 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1501 assert(pCreateInfo->pRasterizationState);
1502 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1503 }
1504
1505 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1506 assert(pCreateInfo->pRasterizationState);
1507 dynamic->depth_bias.bias =
1508 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1509 dynamic->depth_bias.clamp =
1510 pCreateInfo->pRasterizationState->depthBiasClamp;
1511 dynamic->depth_bias.slope =
1512 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1513 }
1514
1515 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1516 *
1517 * pColorBlendState is [...] NULL if the pipeline has rasterization
1518 * disabled or if the subpass of the render pass the pipeline is
1519 * created against does not use any color attachments.
1520 */
1521 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1522 assert(pCreateInfo->pColorBlendState);
1523 typed_memcpy(dynamic->blend_constants,
1524 pCreateInfo->pColorBlendState->blendConstants, 4);
1525 }
1526
1527 /* If there is no depthstencil attachment, then don't read
1528 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1529 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1530 * no need to override the depthstencil defaults in
1531 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1532 *
1533 * Section 9.2 of the Vulkan 1.0.15 spec says:
1534 *
1535 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1536 * disabled or if the subpass of the render pass the pipeline is created
1537 * against does not use a depth/stencil attachment.
1538 */
1539 if (needed_states && subpass->depth_stencil_attachment) {
1540 assert(pCreateInfo->pDepthStencilState);
1541
1542 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1543 dynamic->depth_bounds.min =
1544 pCreateInfo->pDepthStencilState->minDepthBounds;
1545 dynamic->depth_bounds.max =
1546 pCreateInfo->pDepthStencilState->maxDepthBounds;
1547 }
1548
1549 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1550 dynamic->stencil_compare_mask.front =
1551 pCreateInfo->pDepthStencilState->front.compareMask;
1552 dynamic->stencil_compare_mask.back =
1553 pCreateInfo->pDepthStencilState->back.compareMask;
1554 }
1555
1556 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1557 dynamic->stencil_write_mask.front =
1558 pCreateInfo->pDepthStencilState->front.writeMask;
1559 dynamic->stencil_write_mask.back =
1560 pCreateInfo->pDepthStencilState->back.writeMask;
1561 }
1562
1563 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1564 dynamic->stencil_reference.front =
1565 pCreateInfo->pDepthStencilState->front.reference;
1566 dynamic->stencil_reference.back =
1567 pCreateInfo->pDepthStencilState->back.reference;
1568 }
1569 }
1570
1571 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1572 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1573 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1574 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1575 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1576 typed_memcpy(dynamic->discard_rectangle.rectangles,
1577 discard_rectangle_info->pDiscardRectangles,
1578 discard_rectangle_info->discardRectangleCount);
1579 }
1580 }
1581
1582 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1583 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1584 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1585 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1586 /* If sampleLocationsEnable is VK_FALSE, the default sample
1587 * locations are used and the values specified in
1588 * sampleLocationsInfo are ignored.
1589 */
1590 if (sample_location_info->sampleLocationsEnable) {
1591 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1592 &sample_location_info->sampleLocationsInfo;
1593
1594 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1595
1596 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1597 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1598 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1599 typed_memcpy(&dynamic->sample_location.locations[0],
1600 pSampleLocationsInfo->pSampleLocations,
1601 pSampleLocationsInfo->sampleLocationsCount);
1602 }
1603 }
1604
1605 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1606 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1607 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1608 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1609 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1610 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1611 }
1612
1613 pipeline->dynamic_state.mask = states;
1614 }
1615
1616 static void
1617 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1618 const struct radv_pipeline *pipeline,
1619 nir_shader **nir,
1620 struct radv_shader_info *infos,
1621 struct gfx9_gs_info *out)
1622 {
1623 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1624 struct radv_es_output_info *es_info;
1625 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1626 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1627 else
1628 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1629 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1630 &infos[MESA_SHADER_VERTEX].vs.es_info;
1631
1632 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1633 bool uses_adjacency;
1634 switch(key->topology) {
1635 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1636 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1637 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1638 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1639 uses_adjacency = true;
1640 break;
1641 default:
1642 uses_adjacency = false;
1643 break;
1644 }
1645
1646 /* All these are in dwords: */
1647 /* We can't allow using the whole LDS, because GS waves compete with
1648 * other shader stages for LDS space. */
1649 const unsigned max_lds_size = 8 * 1024;
1650 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1651 unsigned esgs_lds_size;
1652
1653 /* All these are per subgroup: */
1654 const unsigned max_out_prims = 32 * 1024;
1655 const unsigned max_es_verts = 255;
1656 const unsigned ideal_gs_prims = 64;
1657 unsigned max_gs_prims, gs_prims;
1658 unsigned min_es_verts, es_verts, worst_case_es_verts;
1659
1660 if (uses_adjacency || gs_num_invocations > 1)
1661 max_gs_prims = 127 / gs_num_invocations;
1662 else
1663 max_gs_prims = 255;
1664
1665 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1666 * Make sure we don't go over the maximum value.
1667 */
1668 if (gs_info->gs.vertices_out > 0) {
1669 max_gs_prims = MIN2(max_gs_prims,
1670 max_out_prims /
1671 (gs_info->gs.vertices_out * gs_num_invocations));
1672 }
1673 assert(max_gs_prims > 0);
1674
1675 /* If the primitive has adjacency, halve the number of vertices
1676 * that will be reused in multiple primitives.
1677 */
1678 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1679
1680 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1681 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1682
1683 /* Compute ESGS LDS size based on the worst case number of ES vertices
1684 * needed to create the target number of GS prims per subgroup.
1685 */
1686 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1687
1688 /* If total LDS usage is too big, refactor partitions based on ratio
1689 * of ESGS item sizes.
1690 */
1691 if (esgs_lds_size > max_lds_size) {
1692 /* Our target GS Prims Per Subgroup was too large. Calculate
1693 * the maximum number of GS Prims Per Subgroup that will fit
1694 * into LDS, capped by the maximum that the hardware can support.
1695 */
1696 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1697 max_gs_prims);
1698 assert(gs_prims > 0);
1699 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1700 max_es_verts);
1701
1702 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1703 assert(esgs_lds_size <= max_lds_size);
1704 }
1705
1706 /* Now calculate remaining ESGS information. */
1707 if (esgs_lds_size)
1708 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1709 else
1710 es_verts = max_es_verts;
1711
1712 /* Vertices for adjacency primitives are not always reused, so restore
1713 * it for ES_VERTS_PER_SUBGRP.
1714 */
1715 min_es_verts = gs_info->gs.vertices_in;
1716
1717 /* For normal primitives, the VGT only checks if they are past the ES
1718 * verts per subgroup after allocating a full GS primitive and if they
1719 * are, kick off a new subgroup. But if those additional ES verts are
1720 * unique (e.g. not reused) we need to make sure there is enough LDS
1721 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1722 */
1723 es_verts -= min_es_verts - 1;
1724
1725 uint32_t es_verts_per_subgroup = es_verts;
1726 uint32_t gs_prims_per_subgroup = gs_prims;
1727 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1728 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1729 out->lds_size = align(esgs_lds_size, 128) / 128;
1730 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1731 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1732 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1733 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1734 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1735 assert(max_prims_per_subgroup <= max_out_prims);
1736 }
1737
1738 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1739 unsigned min_verts_per_prim, bool use_adjacency)
1740 {
1741 unsigned max_reuse = max_esverts - min_verts_per_prim;
1742 if (use_adjacency)
1743 max_reuse /= 2;
1744 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1745 }
1746
1747 static unsigned
1748 radv_get_num_input_vertices(nir_shader **nir)
1749 {
1750 if (nir[MESA_SHADER_GEOMETRY]) {
1751 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1752
1753 return gs->info.gs.vertices_in;
1754 }
1755
1756 if (nir[MESA_SHADER_TESS_CTRL]) {
1757 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1758
1759 if (tes->info.tess.point_mode)
1760 return 1;
1761 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1762 return 2;
1763 return 3;
1764 }
1765
1766 return 3;
1767 }
1768
1769 static void
1770 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1771 struct radv_pipeline *pipeline,
1772 nir_shader **nir,
1773 struct radv_shader_info *infos,
1774 struct gfx10_ngg_info *ngg)
1775 {
1776 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1777 struct radv_es_output_info *es_info =
1778 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1779 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1780 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1781 unsigned min_verts_per_prim =
1782 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1783 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1784 bool uses_adjacency;
1785 switch(key->topology) {
1786 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1787 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1788 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1789 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1790 uses_adjacency = true;
1791 break;
1792 default:
1793 uses_adjacency = false;
1794 break;
1795 }
1796
1797 /* All these are in dwords: */
1798 /* We can't allow using the whole LDS, because GS waves compete with
1799 * other shader stages for LDS space.
1800 *
1801 * TODO: We should really take the shader's internal LDS use into
1802 * account. The linker will fail if the size is greater than
1803 * 8K dwords.
1804 */
1805 const unsigned max_lds_size = 8 * 1024 - 768;
1806 const unsigned target_lds_size = max_lds_size;
1807 unsigned esvert_lds_size = 0;
1808 unsigned gsprim_lds_size = 0;
1809
1810 /* All these are per subgroup: */
1811 bool max_vert_out_per_gs_instance = false;
1812 unsigned max_esverts_base = 256;
1813 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1814
1815 /* Hardware has the following non-natural restrictions on the value
1816 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1817 * the draw:
1818 * - at most 252 for any line input primitive type
1819 * - at most 251 for any quad input primitive type
1820 * - at most 251 for triangle strips with adjacency (this happens to
1821 * be the natural limit for triangle *lists* with adjacency)
1822 */
1823 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1824
1825 if (gs_type == MESA_SHADER_GEOMETRY) {
1826 unsigned max_out_verts_per_gsprim =
1827 gs_info->gs.vertices_out * gs_num_invocations;
1828
1829 if (max_out_verts_per_gsprim <= 256) {
1830 if (max_out_verts_per_gsprim) {
1831 max_gsprims_base = MIN2(max_gsprims_base,
1832 256 / max_out_verts_per_gsprim);
1833 }
1834 } else {
1835 /* Use special multi-cycling mode in which each GS
1836 * instance gets its own subgroup. Does not work with
1837 * tessellation. */
1838 max_vert_out_per_gs_instance = true;
1839 max_gsprims_base = 1;
1840 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1841 }
1842
1843 esvert_lds_size = es_info->esgs_itemsize / 4;
1844 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1845 } else {
1846 /* VS and TES. */
1847 /* LDS size for passing data from GS to ES. */
1848 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1849 ? &infos[MESA_SHADER_TESS_EVAL].so
1850 : &infos[MESA_SHADER_VERTEX].so;
1851
1852 if (so_info->num_outputs)
1853 esvert_lds_size = 4 * so_info->num_outputs + 1;
1854
1855 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1856 * corresponding to the ES thread of the provoking vertex. All
1857 * ES threads load and export PrimitiveID for their thread.
1858 */
1859 if (!nir[MESA_SHADER_TESS_CTRL] &&
1860 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1861 esvert_lds_size = MAX2(esvert_lds_size, 1);
1862 }
1863
1864 unsigned max_gsprims = max_gsprims_base;
1865 unsigned max_esverts = max_esverts_base;
1866
1867 if (esvert_lds_size)
1868 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1869 if (gsprim_lds_size)
1870 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1871
1872 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1873 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1874 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1875
1876 if (esvert_lds_size || gsprim_lds_size) {
1877 /* Now that we have a rough proportionality between esverts
1878 * and gsprims based on the primitive type, scale both of them
1879 * down simultaneously based on required LDS space.
1880 *
1881 * We could be smarter about this if we knew how much vertex
1882 * reuse to expect.
1883 */
1884 unsigned lds_total = max_esverts * esvert_lds_size +
1885 max_gsprims * gsprim_lds_size;
1886 if (lds_total > target_lds_size) {
1887 max_esverts = max_esverts * target_lds_size / lds_total;
1888 max_gsprims = max_gsprims * target_lds_size / lds_total;
1889
1890 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1891 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1892 min_verts_per_prim, uses_adjacency);
1893 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1894 }
1895 }
1896
1897 /* Round up towards full wave sizes for better ALU utilization. */
1898 if (!max_vert_out_per_gs_instance) {
1899 unsigned orig_max_esverts;
1900 unsigned orig_max_gsprims;
1901 unsigned wavesize;
1902
1903 if (gs_type == MESA_SHADER_GEOMETRY) {
1904 wavesize = gs_info->wave_size;
1905 } else {
1906 wavesize = nir[MESA_SHADER_TESS_CTRL]
1907 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1908 : infos[MESA_SHADER_VERTEX].wave_size;
1909 }
1910
1911 do {
1912 orig_max_esverts = max_esverts;
1913 orig_max_gsprims = max_gsprims;
1914
1915 max_esverts = align(max_esverts, wavesize);
1916 max_esverts = MIN2(max_esverts, max_esverts_base);
1917 if (esvert_lds_size)
1918 max_esverts = MIN2(max_esverts,
1919 (max_lds_size - max_gsprims * gsprim_lds_size) /
1920 esvert_lds_size);
1921 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1922
1923 max_gsprims = align(max_gsprims, wavesize);
1924 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1925 if (gsprim_lds_size)
1926 max_gsprims = MIN2(max_gsprims,
1927 (max_lds_size - max_esverts * esvert_lds_size) /
1928 gsprim_lds_size);
1929 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1930 min_verts_per_prim, uses_adjacency);
1931 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1932 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1933 }
1934
1935 /* Hardware restriction: minimum value of max_esverts */
1936 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1937
1938 unsigned max_out_vertices =
1939 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1940 gs_type == MESA_SHADER_GEOMETRY ?
1941 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1942 max_esverts;
1943 assert(max_out_vertices <= 256);
1944
1945 unsigned prim_amp_factor = 1;
1946 if (gs_type == MESA_SHADER_GEOMETRY) {
1947 /* Number of output primitives per GS input primitive after
1948 * GS instancing. */
1949 prim_amp_factor = gs_info->gs.vertices_out;
1950 }
1951
1952 /* The GE only checks against the maximum number of ES verts after
1953 * allocating a full GS primitive. So we need to ensure that whenever
1954 * this check passes, there is enough space for a full primitive without
1955 * vertex reuse.
1956 */
1957 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1958 ngg->max_gsprims = max_gsprims;
1959 ngg->max_out_verts = max_out_vertices;
1960 ngg->prim_amp_factor = prim_amp_factor;
1961 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1962 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1963 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1964
1965 if (gs_type == MESA_SHADER_GEOMETRY) {
1966 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1967 } else {
1968 ngg->vgt_esgs_ring_itemsize = 1;
1969 }
1970
1971 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1972
1973 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1974 }
1975
1976 static void
1977 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1978 const struct gfx9_gs_info *gs)
1979 {
1980 struct radv_device *device = pipeline->device;
1981 unsigned num_se = device->physical_device->rad_info.max_se;
1982 unsigned wave_size = 64;
1983 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1984 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1985 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1986 */
1987 unsigned gs_vertex_reuse =
1988 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1989 unsigned alignment = 256 * num_se;
1990 /* The maximum size is 63.999 MB per SE. */
1991 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1992 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1993
1994 /* Calculate the minimum size. */
1995 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1996 wave_size, alignment);
1997 /* These are recommended sizes, not minimum sizes. */
1998 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1999 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
2000 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2001 gs_info->gs.max_gsvs_emit_size;
2002
2003 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2004 esgs_ring_size = align(esgs_ring_size, alignment);
2005 gsvs_ring_size = align(gsvs_ring_size, alignment);
2006
2007 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
2008 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2009
2010 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2011 }
2012
2013 static void si_multiwave_lds_size_workaround(struct radv_device *device,
2014 unsigned *lds_size)
2015 {
2016 /* If tessellation is all offchip and on-chip GS isn't used, this
2017 * workaround is not needed.
2018 */
2019 return;
2020
2021 /* SPI barrier management bug:
2022 * Make sure we have at least 4k of LDS in use to avoid the bug.
2023 * It applies to workgroup sizes of more than one wavefront.
2024 */
2025 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
2026 device->physical_device->rad_info.family == CHIP_KABINI)
2027 *lds_size = MAX2(*lds_size, 8);
2028 }
2029
2030 struct radv_shader_variant *
2031 radv_get_shader(struct radv_pipeline *pipeline,
2032 gl_shader_stage stage)
2033 {
2034 if (stage == MESA_SHADER_VERTEX) {
2035 if (pipeline->shaders[MESA_SHADER_VERTEX])
2036 return pipeline->shaders[MESA_SHADER_VERTEX];
2037 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2038 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2039 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2040 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2041 } else if (stage == MESA_SHADER_TESS_EVAL) {
2042 if (!radv_pipeline_has_tess(pipeline))
2043 return NULL;
2044 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2045 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2046 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2047 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2048 }
2049 return pipeline->shaders[stage];
2050 }
2051
2052 static struct radv_tessellation_state
2053 calculate_tess_state(struct radv_pipeline *pipeline,
2054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2055 {
2056 unsigned num_tcs_input_cp;
2057 unsigned num_tcs_output_cp;
2058 unsigned lds_size;
2059 unsigned num_patches;
2060 struct radv_tessellation_state tess = {0};
2061
2062 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
2063 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2064 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2065
2066 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2067
2068 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2069 assert(lds_size <= 65536);
2070 lds_size = align(lds_size, 512) / 512;
2071 } else {
2072 assert(lds_size <= 32768);
2073 lds_size = align(lds_size, 256) / 256;
2074 }
2075 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
2076
2077 tess.lds_size = lds_size;
2078
2079 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2080 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2081 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2082 tess.num_patches = num_patches;
2083
2084 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2085 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2086
2087 switch (tes->info.tes.primitive_mode) {
2088 case GL_TRIANGLES:
2089 type = V_028B6C_TESS_TRIANGLE;
2090 break;
2091 case GL_QUADS:
2092 type = V_028B6C_TESS_QUAD;
2093 break;
2094 case GL_ISOLINES:
2095 type = V_028B6C_TESS_ISOLINE;
2096 break;
2097 }
2098
2099 switch (tes->info.tes.spacing) {
2100 case TESS_SPACING_EQUAL:
2101 partitioning = V_028B6C_PART_INTEGER;
2102 break;
2103 case TESS_SPACING_FRACTIONAL_ODD:
2104 partitioning = V_028B6C_PART_FRAC_ODD;
2105 break;
2106 case TESS_SPACING_FRACTIONAL_EVEN:
2107 partitioning = V_028B6C_PART_FRAC_EVEN;
2108 break;
2109 default:
2110 break;
2111 }
2112
2113 bool ccw = tes->info.tes.ccw;
2114 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2115 vk_find_struct_const(pCreateInfo->pTessellationState,
2116 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2117
2118 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2119 ccw = !ccw;
2120
2121 if (tes->info.tes.point_mode)
2122 topology = V_028B6C_OUTPUT_POINT;
2123 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2124 topology = V_028B6C_OUTPUT_LINE;
2125 else if (ccw)
2126 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2127 else
2128 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2129
2130 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2131 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2132 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2133 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2134 else
2135 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2136 } else
2137 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2138
2139 tess.tf_param = S_028B6C_TYPE(type) |
2140 S_028B6C_PARTITIONING(partitioning) |
2141 S_028B6C_TOPOLOGY(topology) |
2142 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2143
2144 return tess;
2145 }
2146
2147 static const struct radv_prim_vertex_count prim_size_table[] = {
2148 [V_008958_DI_PT_NONE] = {0, 0},
2149 [V_008958_DI_PT_POINTLIST] = {1, 1},
2150 [V_008958_DI_PT_LINELIST] = {2, 2},
2151 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2152 [V_008958_DI_PT_TRILIST] = {3, 3},
2153 [V_008958_DI_PT_TRIFAN] = {3, 1},
2154 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2155 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2156 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2157 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2158 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2159 [V_008958_DI_PT_RECTLIST] = {3, 3},
2160 [V_008958_DI_PT_LINELOOP] = {2, 1},
2161 [V_008958_DI_PT_POLYGON] = {3, 1},
2162 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2163 };
2164
2165 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2166 {
2167 if (radv_pipeline_has_gs(pipeline))
2168 if (radv_pipeline_has_ngg(pipeline))
2169 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2170 else
2171 return &pipeline->gs_copy_shader->info.vs.outinfo;
2172 else if (radv_pipeline_has_tess(pipeline))
2173 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2174 else
2175 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2176 }
2177
2178 static void
2179 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2180 {
2181 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2182 int shader_count = 0;
2183
2184 if(shaders[MESA_SHADER_FRAGMENT]) {
2185 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2186 }
2187 if(shaders[MESA_SHADER_GEOMETRY]) {
2188 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2189 }
2190 if(shaders[MESA_SHADER_TESS_EVAL]) {
2191 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2192 }
2193 if(shaders[MESA_SHADER_TESS_CTRL]) {
2194 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2195 }
2196 if(shaders[MESA_SHADER_VERTEX]) {
2197 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2198 }
2199
2200 if (shader_count > 1) {
2201 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2202 unsigned last = ordered_shaders[0]->info.stage;
2203
2204 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2205 ordered_shaders[1]->info.has_transform_feedback_varyings)
2206 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2207
2208 for (int i = 0; i < shader_count; ++i) {
2209 nir_variable_mode mask = 0;
2210
2211 if (ordered_shaders[i]->info.stage != first)
2212 mask = mask | nir_var_shader_in;
2213
2214 if (ordered_shaders[i]->info.stage != last)
2215 mask = mask | nir_var_shader_out;
2216
2217 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2218 radv_optimize_nir(ordered_shaders[i], false, false);
2219 }
2220 }
2221
2222 for (int i = 1; i < shader_count; ++i) {
2223 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2224 ordered_shaders[i - 1]);
2225
2226 if (nir_link_opt_varyings(ordered_shaders[i],
2227 ordered_shaders[i - 1]))
2228 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2229
2230 nir_remove_dead_variables(ordered_shaders[i],
2231 nir_var_shader_out);
2232 nir_remove_dead_variables(ordered_shaders[i - 1],
2233 nir_var_shader_in);
2234
2235 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2236 ordered_shaders[i - 1]);
2237
2238 nir_compact_varyings(ordered_shaders[i],
2239 ordered_shaders[i - 1], true);
2240
2241 if (progress) {
2242 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2243 ac_lower_indirect_derefs(ordered_shaders[i],
2244 pipeline->device->physical_device->rad_info.chip_class);
2245 }
2246 radv_optimize_nir(ordered_shaders[i], false, false);
2247
2248 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2249 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2250 pipeline->device->physical_device->rad_info.chip_class);
2251 }
2252 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2253 }
2254 }
2255 }
2256
2257 static uint32_t
2258 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2259 uint32_t attrib_binding)
2260 {
2261 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2262 const VkVertexInputBindingDescription *input_binding =
2263 &input_state->pVertexBindingDescriptions[i];
2264
2265 if (input_binding->binding == attrib_binding)
2266 return input_binding->stride;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static struct radv_pipeline_key
2273 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2274 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2275 const struct radv_blend_state *blend,
2276 bool has_view_index)
2277 {
2278 const VkPipelineVertexInputStateCreateInfo *input_state =
2279 pCreateInfo->pVertexInputState;
2280 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2281 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2282
2283 struct radv_pipeline_key key;
2284 memset(&key, 0, sizeof(key));
2285
2286 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2287 key.optimisations_disabled = 1;
2288
2289 key.has_multiview_view_index = has_view_index;
2290
2291 uint32_t binding_input_rate = 0;
2292 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2293 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2294 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2295 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2296 binding_input_rate |= 1u << binding;
2297 instance_rate_divisors[binding] = 1;
2298 }
2299 }
2300 if (divisor_state) {
2301 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2302 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2303 divisor_state->pVertexBindingDivisors[i].divisor;
2304 }
2305 }
2306
2307 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2308 const VkVertexInputAttributeDescription *desc =
2309 &input_state->pVertexAttributeDescriptions[i];
2310 const struct vk_format_description *format_desc;
2311 unsigned location = desc->location;
2312 unsigned binding = desc->binding;
2313 unsigned num_format, data_format;
2314 int first_non_void;
2315
2316 if (binding_input_rate & (1u << binding)) {
2317 key.instance_rate_inputs |= 1u << location;
2318 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2319 }
2320
2321 format_desc = vk_format_description(desc->format);
2322 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2323
2324 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2325 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2326
2327 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2328 key.vertex_attribute_bindings[location] = desc->binding;
2329 key.vertex_attribute_offsets[location] = desc->offset;
2330 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2331
2332 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2333 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2334 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2335 uint64_t adjust;
2336 switch(format) {
2337 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2338 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2339 adjust = RADV_ALPHA_ADJUST_SNORM;
2340 break;
2341 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2342 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2343 adjust = RADV_ALPHA_ADJUST_SSCALED;
2344 break;
2345 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2346 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2347 adjust = RADV_ALPHA_ADJUST_SINT;
2348 break;
2349 default:
2350 adjust = 0;
2351 break;
2352 }
2353 key.vertex_alpha_adjust |= adjust << (2 * location);
2354 }
2355
2356 switch (desc->format) {
2357 case VK_FORMAT_B8G8R8A8_UNORM:
2358 case VK_FORMAT_B8G8R8A8_SNORM:
2359 case VK_FORMAT_B8G8R8A8_USCALED:
2360 case VK_FORMAT_B8G8R8A8_SSCALED:
2361 case VK_FORMAT_B8G8R8A8_UINT:
2362 case VK_FORMAT_B8G8R8A8_SINT:
2363 case VK_FORMAT_B8G8R8A8_SRGB:
2364 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2365 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2366 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2367 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2368 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2369 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2370 key.vertex_post_shuffle |= 1 << location;
2371 break;
2372 default:
2373 break;
2374 }
2375 }
2376
2377 const VkPipelineTessellationStateCreateInfo *tess =
2378 radv_pipeline_get_tessellation_state(pCreateInfo);
2379 if (tess)
2380 key.tess_input_vertices = tess->patchControlPoints;
2381
2382 const VkPipelineMultisampleStateCreateInfo *vkms =
2383 radv_pipeline_get_multisample_state(pCreateInfo);
2384 if (vkms && vkms->rasterizationSamples > 1) {
2385 uint32_t num_samples = vkms->rasterizationSamples;
2386 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2387 key.num_samples = num_samples;
2388 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2389 }
2390
2391 key.col_format = blend->spi_shader_col_format;
2392 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2393 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2394
2395 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2396 key.topology = pCreateInfo->pInputAssemblyState->topology;
2397
2398 return key;
2399 }
2400
2401 static bool
2402 radv_nir_stage_uses_xfb(const nir_shader *nir)
2403 {
2404 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2405 bool uses_xfb = !!xfb;
2406
2407 ralloc_free(xfb);
2408 return uses_xfb;
2409 }
2410
2411 static void
2412 radv_fill_shader_keys(struct radv_device *device,
2413 struct radv_shader_variant_key *keys,
2414 const struct radv_pipeline_key *key,
2415 nir_shader **nir)
2416 {
2417 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2418 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2419 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2420 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2421 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2422 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2423 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2424 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2425 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2426 }
2427 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2428
2429 if (nir[MESA_SHADER_TESS_CTRL]) {
2430 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2431 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2432 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2433 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2434
2435 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2436 }
2437
2438 if (nir[MESA_SHADER_GEOMETRY]) {
2439 if (nir[MESA_SHADER_TESS_CTRL])
2440 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2441 else
2442 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2443 }
2444
2445 if (device->physical_device->use_ngg) {
2446 if (nir[MESA_SHADER_TESS_CTRL]) {
2447 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2448 } else {
2449 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2450 }
2451
2452 if (nir[MESA_SHADER_TESS_CTRL] &&
2453 nir[MESA_SHADER_GEOMETRY] &&
2454 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2455 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2456 /* Fallback to the legacy path if tessellation is
2457 * enabled with extreme geometry because
2458 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2459 * might hang.
2460 */
2461 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2462 }
2463
2464 if (!device->physical_device->use_ngg_gs) {
2465 if (nir[MESA_SHADER_GEOMETRY]) {
2466 if (nir[MESA_SHADER_TESS_CTRL])
2467 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2468 else
2469 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2470 }
2471 }
2472
2473 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2474
2475 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2476 if (nir[i])
2477 last_xfb_stage = i;
2478 }
2479
2480 bool uses_xfb = nir[last_xfb_stage] &&
2481 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2482
2483 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2484 if (nir[MESA_SHADER_TESS_CTRL])
2485 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2486 else
2487 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2488 }
2489
2490 /* Determine if the pipeline is eligible for the NGG passthrough
2491 * mode. It can't be enabled for geometry shaders, for NGG
2492 * streamout or for vertex shaders that export the primitive ID
2493 * (this is checked later because we don't have the info here.)
2494 */
2495 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2496 if (nir[MESA_SHADER_TESS_CTRL] &&
2497 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2498 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2499 } else if (nir[MESA_SHADER_VERTEX] &&
2500 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2501 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2502 }
2503 }
2504 }
2505
2506 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2507 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2508
2509 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2510 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2511 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2512 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2513 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2514
2515 if (nir[MESA_SHADER_COMPUTE]) {
2516 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2517 }
2518 }
2519
2520 static uint8_t
2521 radv_get_wave_size(struct radv_device *device,
2522 const VkPipelineShaderStageCreateInfo *pStage,
2523 gl_shader_stage stage,
2524 const struct radv_shader_variant_key *key)
2525 {
2526 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2527 return 64;
2528 else if (stage == MESA_SHADER_COMPUTE) {
2529 if (key->cs.subgroup_size) {
2530 /* Return the required subgroup size if specified. */
2531 return key->cs.subgroup_size;
2532 }
2533 return device->physical_device->cs_wave_size;
2534 }
2535 else if (stage == MESA_SHADER_FRAGMENT)
2536 return device->physical_device->ps_wave_size;
2537 else
2538 return device->physical_device->ge_wave_size;
2539 }
2540
2541 static uint8_t
2542 radv_get_ballot_bit_size(struct radv_device *device,
2543 const VkPipelineShaderStageCreateInfo *pStage,
2544 gl_shader_stage stage,
2545 const struct radv_shader_variant_key *key)
2546 {
2547 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2548 return key->cs.subgroup_size;
2549 return 64;
2550 }
2551
2552 static void
2553 radv_fill_shader_info(struct radv_pipeline *pipeline,
2554 const VkPipelineShaderStageCreateInfo **pStages,
2555 struct radv_shader_variant_key *keys,
2556 struct radv_shader_info *infos,
2557 nir_shader **nir)
2558 {
2559 unsigned active_stages = 0;
2560 unsigned filled_stages = 0;
2561
2562 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2563 if (nir[i])
2564 active_stages |= (1 << i);
2565 }
2566
2567 if (nir[MESA_SHADER_FRAGMENT]) {
2568 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2569 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2570 pipeline->layout,
2571 &keys[MESA_SHADER_FRAGMENT],
2572 &infos[MESA_SHADER_FRAGMENT]);
2573
2574 /* TODO: These are no longer used as keys we should refactor this */
2575 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2576 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2577 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2578 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2579 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2580 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2581 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2582 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2583 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2584 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2585 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2586 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2587
2588 /* NGG passthrough mode can't be enabled for vertex shaders
2589 * that export the primitive ID.
2590 *
2591 * TODO: I should really refactor the keys logic.
2592 */
2593 if (nir[MESA_SHADER_VERTEX] &&
2594 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2595 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2596 }
2597
2598 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2599 }
2600
2601 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2602 nir[MESA_SHADER_TESS_CTRL]) {
2603 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2604 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2605 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2606
2607 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2608
2609 for (int i = 0; i < 2; i++) {
2610 radv_nir_shader_info_pass(combined_nir[i],
2611 pipeline->layout, &key,
2612 &infos[MESA_SHADER_TESS_CTRL]);
2613 }
2614
2615 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2616 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2617 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2618 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2619
2620 filled_stages |= (1 << MESA_SHADER_VERTEX);
2621 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2622 }
2623
2624 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2625 nir[MESA_SHADER_GEOMETRY]) {
2626 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2627 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2628
2629 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2630
2631 for (int i = 0; i < 2; i++) {
2632 radv_nir_shader_info_pass(combined_nir[i],
2633 pipeline->layout,
2634 &keys[pre_stage],
2635 &infos[MESA_SHADER_GEOMETRY]);
2636 }
2637
2638 filled_stages |= (1 << pre_stage);
2639 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2640 }
2641
2642 active_stages ^= filled_stages;
2643 while (active_stages) {
2644 int i = u_bit_scan(&active_stages);
2645
2646 if (i == MESA_SHADER_TESS_CTRL) {
2647 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2648 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2649 }
2650
2651 if (i == MESA_SHADER_TESS_EVAL) {
2652 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2653 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2654 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2655 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2656 }
2657
2658 radv_nir_shader_info_init(&infos[i]);
2659 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2660 &keys[i], &infos[i]);
2661 }
2662
2663 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2664 if (nir[i]) {
2665 infos[i].wave_size =
2666 radv_get_wave_size(pipeline->device, pStages[i],
2667 i, &keys[i]);
2668 infos[i].ballot_bit_size =
2669 radv_get_ballot_bit_size(pipeline->device,
2670 pStages[i], i,
2671 &keys[i]);
2672 }
2673 }
2674 }
2675
2676 static void
2677 merge_tess_info(struct shader_info *tes_info,
2678 const struct shader_info *tcs_info)
2679 {
2680 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2681 *
2682 * "PointMode. Controls generation of points rather than triangles
2683 * or lines. This functionality defaults to disabled, and is
2684 * enabled if either shader stage includes the execution mode.
2685 *
2686 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2687 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2688 * and OutputVertices, it says:
2689 *
2690 * "One mode must be set in at least one of the tessellation
2691 * shader stages."
2692 *
2693 * So, the fields can be set in either the TCS or TES, but they must
2694 * agree if set in both. Our backend looks at TES, so bitwise-or in
2695 * the values from the TCS.
2696 */
2697 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2698 tes_info->tess.tcs_vertices_out == 0 ||
2699 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2700 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2701
2702 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2703 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2704 tcs_info->tess.spacing == tes_info->tess.spacing);
2705 tes_info->tess.spacing |= tcs_info->tess.spacing;
2706
2707 assert(tcs_info->tess.primitive_mode == 0 ||
2708 tes_info->tess.primitive_mode == 0 ||
2709 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2710 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2711 tes_info->tess.ccw |= tcs_info->tess.ccw;
2712 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2713 }
2714
2715 static
2716 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2717 {
2718 if (!ext)
2719 return;
2720
2721 if (ext->pPipelineCreationFeedback) {
2722 ext->pPipelineCreationFeedback->flags = 0;
2723 ext->pPipelineCreationFeedback->duration = 0;
2724 }
2725
2726 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2727 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2728 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2729 }
2730 }
2731
2732 static
2733 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2734 {
2735 if (!feedback)
2736 return;
2737
2738 feedback->duration -= radv_get_current_time();
2739 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2740 }
2741
2742 static
2743 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2744 {
2745 if (!feedback)
2746 return;
2747
2748 feedback->duration += radv_get_current_time();
2749 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2750 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2751 }
2752
2753 void radv_create_shaders(struct radv_pipeline *pipeline,
2754 struct radv_device *device,
2755 struct radv_pipeline_cache *cache,
2756 const struct radv_pipeline_key *key,
2757 const VkPipelineShaderStageCreateInfo **pStages,
2758 const VkPipelineCreateFlags flags,
2759 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2760 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2761 {
2762 struct radv_shader_module fs_m = {0};
2763 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2764 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2765 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2766 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2767 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2768 unsigned char hash[20], gs_copy_hash[20];
2769 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2770 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) || device->keep_shader_info;
2771
2772 radv_start_feedback(pipeline_feedback);
2773
2774 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2775 if (pStages[i]) {
2776 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2777 if (modules[i]->nir)
2778 _mesa_sha1_compute(modules[i]->nir->info.name,
2779 strlen(modules[i]->nir->info.name),
2780 modules[i]->sha1);
2781
2782 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2783 }
2784 }
2785
2786 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2787 memcpy(gs_copy_hash, hash, 20);
2788 gs_copy_hash[0] ^= 1;
2789
2790 bool found_in_application_cache = true;
2791 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2792 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2793 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2794 &found_in_application_cache);
2795 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2796 }
2797
2798 if (!keep_executable_info && !keep_statistic_info &&
2799 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2800 &found_in_application_cache) &&
2801 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2802 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2803 return;
2804 }
2805
2806 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2807 nir_builder fs_b;
2808 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2809 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2810 fs_m.nir = fs_b.shader;
2811 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2812 }
2813
2814 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2815 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2816 unsigned subgroup_size = 64, ballot_bit_size = 64;
2817
2818 if (!modules[i])
2819 continue;
2820
2821 radv_start_feedback(stage_feedbacks[i]);
2822
2823 if (key->compute_subgroup_size) {
2824 /* Only compute shaders currently support requiring a
2825 * specific subgroup size.
2826 */
2827 assert(i == MESA_SHADER_COMPUTE);
2828 subgroup_size = key->compute_subgroup_size;
2829 ballot_bit_size = key->compute_subgroup_size;
2830 }
2831
2832 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2833 stage ? stage->pName : "main", i,
2834 stage ? stage->pSpecializationInfo : NULL,
2835 flags, pipeline->layout,
2836 subgroup_size, ballot_bit_size);
2837
2838 /* We don't want to alter meta shaders IR directly so clone it
2839 * first.
2840 */
2841 if (nir[i]->info.name) {
2842 nir[i] = nir_shader_clone(NULL, nir[i]);
2843 }
2844
2845 radv_stop_feedback(stage_feedbacks[i], false);
2846 }
2847
2848 if (nir[MESA_SHADER_TESS_CTRL]) {
2849 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2850 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2851 }
2852
2853 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2854 radv_link_shaders(pipeline, nir);
2855
2856 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2857 if (nir[i]) {
2858 /* do this again since information such as outputs_read can be out-of-date */
2859 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2860
2861 if (device->physical_device->use_aco) {
2862 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2863 nir_lower_non_uniform_ubo_access |
2864 nir_lower_non_uniform_ssbo_access |
2865 nir_lower_non_uniform_texture_access |
2866 nir_lower_non_uniform_image_access);
2867 } else
2868 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2869 }
2870 }
2871
2872 if (nir[MESA_SHADER_FRAGMENT])
2873 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2874
2875 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2876 if (radv_can_dump_shader(device, modules[i], false))
2877 nir_print_shader(nir[i], stderr);
2878 }
2879
2880 radv_fill_shader_keys(device, keys, key, nir);
2881
2882 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2883
2884 if ((nir[MESA_SHADER_VERTEX] &&
2885 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2886 (nir[MESA_SHADER_TESS_EVAL] &&
2887 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2888 struct gfx10_ngg_info *ngg_info;
2889
2890 if (nir[MESA_SHADER_GEOMETRY])
2891 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2892 else if (nir[MESA_SHADER_TESS_CTRL])
2893 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2894 else
2895 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2896
2897 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2898 } else if (nir[MESA_SHADER_GEOMETRY]) {
2899 struct gfx9_gs_info *gs_info =
2900 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2901
2902 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2903 }
2904
2905 if(modules[MESA_SHADER_GEOMETRY]) {
2906 struct radv_shader_binary *gs_copy_binary = NULL;
2907 if (!pipeline->gs_copy_shader &&
2908 !radv_pipeline_has_ngg(pipeline)) {
2909 struct radv_shader_info info = {};
2910 struct radv_shader_variant_key key = {};
2911
2912 key.has_multiview_view_index =
2913 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2914
2915 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2916 pipeline->layout, &key,
2917 &info);
2918 info.wave_size = 64; /* Wave32 not supported. */
2919 info.ballot_bit_size = 64;
2920
2921 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2922 device, nir[MESA_SHADER_GEOMETRY], &info,
2923 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2924 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2925 }
2926
2927 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2928 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2929 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2930
2931 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2932 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2933
2934 radv_pipeline_cache_insert_shaders(device, cache,
2935 gs_copy_hash,
2936 variants,
2937 binaries);
2938 }
2939 free(gs_copy_binary);
2940 }
2941
2942 if (nir[MESA_SHADER_FRAGMENT]) {
2943 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2944 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2945
2946 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2947 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2948 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2949 infos + MESA_SHADER_FRAGMENT,
2950 keep_executable_info, keep_statistic_info,
2951 &binaries[MESA_SHADER_FRAGMENT]);
2952
2953 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2954 }
2955 }
2956
2957 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2958 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2959 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2960 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2961 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2962
2963 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2964
2965 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2966 pipeline->layout,
2967 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2968 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2969
2970 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2971 }
2972 modules[MESA_SHADER_VERTEX] = NULL;
2973 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2974 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2975 }
2976
2977 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2978 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2979 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2980 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2981
2982 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2983
2984 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2985 pipeline->layout,
2986 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2987 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2988
2989 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2990 }
2991 modules[pre_stage] = NULL;
2992 }
2993
2994 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2995 if(modules[i] && !pipeline->shaders[i]) {
2996 if (i == MESA_SHADER_TESS_CTRL) {
2997 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2998 }
2999 if (i == MESA_SHADER_TESS_EVAL) {
3000 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3001 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3002 }
3003
3004 radv_start_feedback(stage_feedbacks[i]);
3005
3006 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3007 pipeline->layout,
3008 keys + i, infos + i, keep_executable_info,
3009 keep_statistic_info, &binaries[i]);
3010
3011 radv_stop_feedback(stage_feedbacks[i], false);
3012 }
3013 }
3014
3015 if (!keep_executable_info && !keep_statistic_info) {
3016 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3017 binaries);
3018 }
3019
3020 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3021 free(binaries[i]);
3022 if (nir[i]) {
3023 ralloc_free(nir[i]);
3024
3025 if (radv_can_dump_shader_stats(device, modules[i]))
3026 radv_shader_dump_stats(device,
3027 pipeline->shaders[i],
3028 i, stderr);
3029 }
3030 }
3031
3032 if (fs_m.nir)
3033 ralloc_free(fs_m.nir);
3034
3035 radv_stop_feedback(pipeline_feedback, false);
3036 }
3037
3038 static uint32_t
3039 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3040 gl_shader_stage stage, enum chip_class chip_class)
3041 {
3042 bool has_gs = radv_pipeline_has_gs(pipeline);
3043 bool has_tess = radv_pipeline_has_tess(pipeline);
3044 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3045
3046 switch (stage) {
3047 case MESA_SHADER_FRAGMENT:
3048 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3049 case MESA_SHADER_VERTEX:
3050 if (has_tess) {
3051 if (chip_class >= GFX10) {
3052 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3053 } else if (chip_class == GFX9) {
3054 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3055 } else {
3056 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3057 }
3058
3059 }
3060
3061 if (has_gs) {
3062 if (chip_class >= GFX10) {
3063 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3064 } else {
3065 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3066 }
3067 }
3068
3069 if (has_ngg)
3070 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3071
3072 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3073 case MESA_SHADER_GEOMETRY:
3074 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3075 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3076 case MESA_SHADER_COMPUTE:
3077 return R_00B900_COMPUTE_USER_DATA_0;
3078 case MESA_SHADER_TESS_CTRL:
3079 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3080 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3081 case MESA_SHADER_TESS_EVAL:
3082 if (has_gs) {
3083 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3084 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3085 } else if (has_ngg) {
3086 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3087 } else {
3088 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3089 }
3090 default:
3091 unreachable("unknown shader");
3092 }
3093 }
3094
3095 struct radv_bin_size_entry {
3096 unsigned bpp;
3097 VkExtent2D extent;
3098 };
3099
3100 static VkExtent2D
3101 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3102 {
3103 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3104 {
3105 /* One RB / SE */
3106 {
3107 /* One shader engine */
3108 { 0, {128, 128}},
3109 { 1, { 64, 128}},
3110 { 2, { 32, 128}},
3111 { 3, { 16, 128}},
3112 { 17, { 0, 0}},
3113 { UINT_MAX, { 0, 0}},
3114 },
3115 {
3116 /* Two shader engines */
3117 { 0, {128, 128}},
3118 { 2, { 64, 128}},
3119 { 3, { 32, 128}},
3120 { 5, { 16, 128}},
3121 { 17, { 0, 0}},
3122 { UINT_MAX, { 0, 0}},
3123 },
3124 {
3125 /* Four shader engines */
3126 { 0, {128, 128}},
3127 { 3, { 64, 128}},
3128 { 5, { 16, 128}},
3129 { 17, { 0, 0}},
3130 { UINT_MAX, { 0, 0}},
3131 },
3132 },
3133 {
3134 /* Two RB / SE */
3135 {
3136 /* One shader engine */
3137 { 0, {128, 128}},
3138 { 2, { 64, 128}},
3139 { 3, { 32, 128}},
3140 { 5, { 16, 128}},
3141 { 33, { 0, 0}},
3142 { UINT_MAX, { 0, 0}},
3143 },
3144 {
3145 /* Two shader engines */
3146 { 0, {128, 128}},
3147 { 3, { 64, 128}},
3148 { 5, { 32, 128}},
3149 { 9, { 16, 128}},
3150 { 33, { 0, 0}},
3151 { UINT_MAX, { 0, 0}},
3152 },
3153 {
3154 /* Four shader engines */
3155 { 0, {256, 256}},
3156 { 2, {128, 256}},
3157 { 3, {128, 128}},
3158 { 5, { 64, 128}},
3159 { 9, { 16, 128}},
3160 { 33, { 0, 0}},
3161 { UINT_MAX, { 0, 0}},
3162 },
3163 },
3164 {
3165 /* Four RB / SE */
3166 {
3167 /* One shader engine */
3168 { 0, {128, 256}},
3169 { 2, {128, 128}},
3170 { 3, { 64, 128}},
3171 { 5, { 32, 128}},
3172 { 9, { 16, 128}},
3173 { 33, { 0, 0}},
3174 { UINT_MAX, { 0, 0}},
3175 },
3176 {
3177 /* Two shader engines */
3178 { 0, {256, 256}},
3179 { 2, {128, 256}},
3180 { 3, {128, 128}},
3181 { 5, { 64, 128}},
3182 { 9, { 32, 128}},
3183 { 17, { 16, 128}},
3184 { 33, { 0, 0}},
3185 { UINT_MAX, { 0, 0}},
3186 },
3187 {
3188 /* Four shader engines */
3189 { 0, {256, 512}},
3190 { 2, {256, 256}},
3191 { 3, {128, 256}},
3192 { 5, {128, 128}},
3193 { 9, { 64, 128}},
3194 { 17, { 16, 128}},
3195 { 33, { 0, 0}},
3196 { UINT_MAX, { 0, 0}},
3197 },
3198 },
3199 };
3200 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3201 {
3202 // One RB / SE
3203 {
3204 // One shader engine
3205 { 0, {128, 256}},
3206 { 2, {128, 128}},
3207 { 4, { 64, 128}},
3208 { 7, { 32, 128}},
3209 { 13, { 16, 128}},
3210 { 49, { 0, 0}},
3211 { UINT_MAX, { 0, 0}},
3212 },
3213 {
3214 // Two shader engines
3215 { 0, {256, 256}},
3216 { 2, {128, 256}},
3217 { 4, {128, 128}},
3218 { 7, { 64, 128}},
3219 { 13, { 32, 128}},
3220 { 25, { 16, 128}},
3221 { 49, { 0, 0}},
3222 { UINT_MAX, { 0, 0}},
3223 },
3224 {
3225 // Four shader engines
3226 { 0, {256, 512}},
3227 { 2, {256, 256}},
3228 { 4, {128, 256}},
3229 { 7, {128, 128}},
3230 { 13, { 64, 128}},
3231 { 25, { 16, 128}},
3232 { 49, { 0, 0}},
3233 { UINT_MAX, { 0, 0}},
3234 },
3235 },
3236 {
3237 // Two RB / SE
3238 {
3239 // One shader engine
3240 { 0, {256, 256}},
3241 { 2, {128, 256}},
3242 { 4, {128, 128}},
3243 { 7, { 64, 128}},
3244 { 13, { 32, 128}},
3245 { 25, { 16, 128}},
3246 { 97, { 0, 0}},
3247 { UINT_MAX, { 0, 0}},
3248 },
3249 {
3250 // Two shader engines
3251 { 0, {256, 512}},
3252 { 2, {256, 256}},
3253 { 4, {128, 256}},
3254 { 7, {128, 128}},
3255 { 13, { 64, 128}},
3256 { 25, { 32, 128}},
3257 { 49, { 16, 128}},
3258 { 97, { 0, 0}},
3259 { UINT_MAX, { 0, 0}},
3260 },
3261 {
3262 // Four shader engines
3263 { 0, {512, 512}},
3264 { 2, {256, 512}},
3265 { 4, {256, 256}},
3266 { 7, {128, 256}},
3267 { 13, {128, 128}},
3268 { 25, { 64, 128}},
3269 { 49, { 16, 128}},
3270 { 97, { 0, 0}},
3271 { UINT_MAX, { 0, 0}},
3272 },
3273 },
3274 {
3275 // Four RB / SE
3276 {
3277 // One shader engine
3278 { 0, {256, 512}},
3279 { 2, {256, 256}},
3280 { 4, {128, 256}},
3281 { 7, {128, 128}},
3282 { 13, { 64, 128}},
3283 { 25, { 32, 128}},
3284 { 49, { 16, 128}},
3285 { UINT_MAX, { 0, 0}},
3286 },
3287 {
3288 // Two shader engines
3289 { 0, {512, 512}},
3290 { 2, {256, 512}},
3291 { 4, {256, 256}},
3292 { 7, {128, 256}},
3293 { 13, {128, 128}},
3294 { 25, { 64, 128}},
3295 { 49, { 32, 128}},
3296 { 97, { 16, 128}},
3297 { UINT_MAX, { 0, 0}},
3298 },
3299 {
3300 // Four shader engines
3301 { 0, {512, 512}},
3302 { 4, {256, 512}},
3303 { 7, {256, 256}},
3304 { 13, {128, 256}},
3305 { 25, {128, 128}},
3306 { 49, { 64, 128}},
3307 { 97, { 16, 128}},
3308 { UINT_MAX, { 0, 0}},
3309 },
3310 },
3311 };
3312
3313 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3314 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3315 VkExtent2D extent = {512, 512};
3316
3317 unsigned log_num_rb_per_se =
3318 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3319 pipeline->device->physical_device->rad_info.max_se);
3320 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3321
3322 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3323 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3324 unsigned effective_samples = total_samples;
3325 unsigned color_bytes_per_pixel = 0;
3326
3327 const VkPipelineColorBlendStateCreateInfo *vkblend =
3328 radv_pipeline_get_color_blend_state(pCreateInfo);
3329 if (vkblend) {
3330 for (unsigned i = 0; i < subpass->color_count; i++) {
3331 if (!vkblend->pAttachments[i].colorWriteMask)
3332 continue;
3333
3334 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3335 continue;
3336
3337 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3338 color_bytes_per_pixel += vk_format_get_blocksize(format);
3339 }
3340
3341 /* MSAA images typically don't use all samples all the time. */
3342 if (effective_samples >= 2 && ps_iter_samples <= 1)
3343 effective_samples = 2;
3344 color_bytes_per_pixel *= effective_samples;
3345 }
3346
3347 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3348 while(color_entry[1].bpp <= color_bytes_per_pixel)
3349 ++color_entry;
3350
3351 extent = color_entry->extent;
3352
3353 if (subpass->depth_stencil_attachment) {
3354 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3355
3356 /* Coefficients taken from AMDVLK */
3357 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3358 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3359 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3360
3361 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3362 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3363 ++ds_entry;
3364
3365 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3366 extent = ds_entry->extent;
3367 }
3368
3369 return extent;
3370 }
3371
3372 static VkExtent2D
3373 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3374 {
3375 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3376 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3377 VkExtent2D extent = {512, 512};
3378
3379 const unsigned db_tag_size = 64;
3380 const unsigned db_tag_count = 312;
3381 const unsigned color_tag_size = 1024;
3382 const unsigned color_tag_count = 31;
3383 const unsigned fmask_tag_size = 256;
3384 const unsigned fmask_tag_count = 44;
3385
3386 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3387 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3388
3389 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3390 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3391 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3392
3393 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3394 const unsigned samples_log = util_logbase2_ceil(total_samples);
3395
3396 unsigned color_bytes_per_pixel = 0;
3397 unsigned fmask_bytes_per_pixel = 0;
3398
3399 const VkPipelineColorBlendStateCreateInfo *vkblend =
3400 radv_pipeline_get_color_blend_state(pCreateInfo);
3401 if (vkblend) {
3402 for (unsigned i = 0; i < subpass->color_count; i++) {
3403 if (!vkblend->pAttachments[i].colorWriteMask)
3404 continue;
3405
3406 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3407 continue;
3408
3409 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3410 color_bytes_per_pixel += vk_format_get_blocksize(format);
3411
3412 if (total_samples > 1) {
3413 assert(samples_log <= 3);
3414 const unsigned fmask_array[] = {0, 1, 1, 4};
3415 fmask_bytes_per_pixel += fmask_array[samples_log];
3416 }
3417 }
3418
3419 color_bytes_per_pixel *= total_samples;
3420 }
3421 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3422
3423 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3424 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3425 extent.height = 1ull << (color_pixel_count_log / 2);
3426
3427 if (fmask_bytes_per_pixel) {
3428 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3429
3430 const VkExtent2D fmask_extent = (VkExtent2D){
3431 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3432 .height = 1ull << (color_pixel_count_log / 2)
3433 };
3434
3435 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3436 extent = fmask_extent;
3437 }
3438
3439 if (subpass->depth_stencil_attachment) {
3440 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3441
3442 /* Coefficients taken from AMDVLK */
3443 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3444 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3445 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3446
3447 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3448
3449 const VkExtent2D db_extent = (VkExtent2D){
3450 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3451 .height = 1ull << (color_pixel_count_log / 2)
3452 };
3453
3454 if (db_extent.width * db_extent.height < extent.width * extent.height)
3455 extent = db_extent;
3456 }
3457
3458 extent.width = MAX2(extent.width, 128);
3459 extent.height = MAX2(extent.width, 64);
3460
3461 return extent;
3462 }
3463
3464 static void
3465 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3466 struct radv_pipeline *pipeline,
3467 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3468 {
3469 uint32_t pa_sc_binner_cntl_0 =
3470 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3471 S_028C44_DISABLE_START_OF_PRIM(1);
3472 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3473
3474 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3475 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3476 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3477 const VkPipelineColorBlendStateCreateInfo *vkblend =
3478 radv_pipeline_get_color_blend_state(pCreateInfo);
3479 unsigned min_bytes_per_pixel = 0;
3480
3481 if (vkblend) {
3482 for (unsigned i = 0; i < subpass->color_count; i++) {
3483 if (!vkblend->pAttachments[i].colorWriteMask)
3484 continue;
3485
3486 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3487 continue;
3488
3489 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3490 unsigned bytes = vk_format_get_blocksize(format);
3491 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3492 min_bytes_per_pixel = bytes;
3493 }
3494 }
3495
3496 pa_sc_binner_cntl_0 =
3497 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3498 S_028C44_BIN_SIZE_X(0) |
3499 S_028C44_BIN_SIZE_Y(0) |
3500 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3501 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3502 S_028C44_DISABLE_START_OF_PRIM(1);
3503 }
3504
3505 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3506 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3507 }
3508
3509 struct radv_binning_settings
3510 radv_get_binning_settings(const struct radv_physical_device *pdev)
3511 {
3512 struct radv_binning_settings settings;
3513 if (pdev->rad_info.has_dedicated_vram) {
3514 if (pdev->rad_info.num_render_backends > 4) {
3515 settings.context_states_per_bin = 1;
3516 settings.persistent_states_per_bin = 1;
3517 } else {
3518 settings.context_states_per_bin = 3;
3519 settings.persistent_states_per_bin = 8;
3520 }
3521 settings.fpovs_per_batch = 63;
3522 } else {
3523 /* The context states are affected by the scissor bug. */
3524 settings.context_states_per_bin = 6;
3525 /* 32 causes hangs for RAVEN. */
3526 settings.persistent_states_per_bin = 16;
3527 settings.fpovs_per_batch = 63;
3528 }
3529
3530 if (pdev->rad_info.has_gfx9_scissor_bug)
3531 settings.context_states_per_bin = 1;
3532
3533 return settings;
3534 }
3535
3536 static void
3537 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3538 struct radv_pipeline *pipeline,
3539 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3540 const struct radv_blend_state *blend)
3541 {
3542 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3543 return;
3544
3545 VkExtent2D bin_size;
3546 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3547 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3548 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3549 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3550 } else
3551 unreachable("Unhandled generation for binning bin size calculation");
3552
3553 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3554 struct radv_binning_settings settings =
3555 radv_get_binning_settings(pipeline->device->physical_device);
3556
3557 bool disable_start_of_prim = true;
3558 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3559
3560 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3561
3562 if (pipeline->device->dfsm_allowed && ps &&
3563 !ps->info.ps.can_discard &&
3564 !ps->info.ps.writes_memory &&
3565 blend->cb_target_enabled_4bit) {
3566 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3567 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3568 }
3569
3570 const uint32_t pa_sc_binner_cntl_0 =
3571 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3572 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3573 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3574 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3575 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3576 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3577 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3578 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3579 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3580 S_028C44_OPTIMAL_BIN_SELECTION(1);
3581
3582 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3583 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3584 } else
3585 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3586 }
3587
3588
3589 static void
3590 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3591 struct radv_pipeline *pipeline,
3592 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3593 const struct radv_graphics_pipeline_create_info *extra)
3594 {
3595 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3596 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3597 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3598 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3599 struct radv_render_pass_attachment *attachment = NULL;
3600 uint32_t db_depth_control = 0, db_stencil_control = 0;
3601 uint32_t db_render_control = 0, db_render_override2 = 0;
3602 uint32_t db_render_override = 0;
3603
3604 if (subpass->depth_stencil_attachment)
3605 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3606
3607 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3608 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3609
3610 if (vkds && has_depth_attachment) {
3611 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3612 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3613 S_028800_ZFUNC(vkds->depthCompareOp) |
3614 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3615
3616 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3617 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3618 }
3619
3620 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3621 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3622 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3623 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3624 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3625 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3626
3627 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3628 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3629 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3630 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3631 }
3632
3633 if (attachment && extra) {
3634 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3635 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3636
3637 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3638 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3639 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3640 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3641 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3642 }
3643
3644 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3645 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3646
3647 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3648 ps->info.ps.writes_z) {
3649 /* From VK_EXT_depth_range_unrestricted spec:
3650 *
3651 * "The behavior described in Primitive Clipping still applies.
3652 * If depth clamping is disabled the depth values are still
3653 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3654 * depth clamping is enabled the above equation is ignored and
3655 * the depth values are instead clamped to the VkViewport
3656 * minDepth and maxDepth values, which in the case of this
3657 * extension can be outside of the 0.0 to 1.0 range."
3658 */
3659 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3660 }
3661
3662 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3663 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3664
3665 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3666 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3667 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3668 }
3669
3670 static void
3671 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3672 struct radv_pipeline *pipeline,
3673 const struct radv_blend_state *blend)
3674 {
3675 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3676 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3677 8);
3678 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3679 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3680
3681 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3682
3683 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3684 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3685 }
3686
3687 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3688
3689 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3690 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3691
3692 pipeline->graphics.col_format = blend->spi_shader_col_format;
3693 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3694 }
3695
3696 static const VkConservativeRasterizationModeEXT
3697 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3698 {
3699 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3700 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3701
3702 if (!conservative_raster)
3703 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3704 return conservative_raster->conservativeRasterizationMode;
3705 }
3706
3707 static void
3708 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3709 struct radv_pipeline *pipeline,
3710 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3711 {
3712 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3713 const VkConservativeRasterizationModeEXT mode =
3714 radv_get_conservative_raster_mode(vkraster);
3715 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3716 bool depth_clip_disable = vkraster->depthClampEnable;
3717
3718 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3719 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3720 if (depth_clip_state) {
3721 depth_clip_disable = !depth_clip_state->depthClipEnable;
3722 }
3723
3724 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3725 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3726 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3727 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3728 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3729 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3730
3731 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3732 S_0286D4_FLAT_SHADE_ENA(1) |
3733 S_0286D4_PNT_SPRITE_ENA(1) |
3734 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3735 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3736 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3737 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3738 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3739
3740 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3741 S_028BE4_PIX_CENTER(1) | // TODO verify
3742 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3743 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3744
3745 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3746 S_028814_FACE(vkraster->frontFace) |
3747 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3748 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3749 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3750 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3751 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3752 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3753 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3754 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3755
3756 /* Conservative rasterization. */
3757 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3758 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3759
3760 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3761 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3762 S_028804_OVERRASTERIZATION_AMOUNT(4);
3763
3764 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3765 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3766 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3767
3768 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3769 pa_sc_conservative_rast |=
3770 S_028C4C_OVER_RAST_ENABLE(1) |
3771 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3772 S_028C4C_UNDER_RAST_ENABLE(0) |
3773 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3774 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3775 } else {
3776 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3777 pa_sc_conservative_rast |=
3778 S_028C4C_OVER_RAST_ENABLE(0) |
3779 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3780 S_028C4C_UNDER_RAST_ENABLE(1) |
3781 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3782 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3783 }
3784 }
3785
3786 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3787 pa_sc_conservative_rast);
3788 }
3789
3790
3791 static void
3792 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3793 struct radv_pipeline *pipeline)
3794 {
3795 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3796
3797 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3798 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3799 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3800
3801 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3802 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3803 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3804 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3805 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3806
3807 /* The exclusion bits can be set to improve rasterization efficiency
3808 * if no sample lies on the pixel boundary (-8 sample offset). It's
3809 * currently always TRUE because the driver doesn't support 16 samples.
3810 */
3811 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3812 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3813 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3814 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3815
3816 /* GFX9: Flush DFSM when the AA mode changes. */
3817 if (pipeline->device->dfsm_allowed) {
3818 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3819 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3820 }
3821 }
3822
3823 static void
3824 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3825 struct radv_pipeline *pipeline)
3826 {
3827 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3828 const struct radv_shader_variant *vs =
3829 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3830 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3831 pipeline->shaders[MESA_SHADER_VERTEX];
3832 unsigned vgt_primitiveid_en = 0;
3833 uint32_t vgt_gs_mode = 0;
3834
3835 if (radv_pipeline_has_ngg(pipeline))
3836 return;
3837
3838 if (radv_pipeline_has_gs(pipeline)) {
3839 const struct radv_shader_variant *gs =
3840 pipeline->shaders[MESA_SHADER_GEOMETRY];
3841
3842 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3843 pipeline->device->physical_device->rad_info.chip_class);
3844 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3845 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3846 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3847 }
3848
3849 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3850 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3851 }
3852
3853 static void
3854 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3855 struct radeon_cmdbuf *cs,
3856 struct radv_pipeline *pipeline,
3857 struct radv_shader_variant *shader)
3858 {
3859 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3860
3861 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3862 radeon_emit(cs, va >> 8);
3863 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3864 radeon_emit(cs, shader->config.rsrc1);
3865 radeon_emit(cs, shader->config.rsrc2);
3866
3867 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3868 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3869 clip_dist_mask = outinfo->clip_dist_mask;
3870 cull_dist_mask = outinfo->cull_dist_mask;
3871 total_mask = clip_dist_mask | cull_dist_mask;
3872 bool misc_vec_ena = outinfo->writes_pointsize ||
3873 outinfo->writes_layer ||
3874 outinfo->writes_viewport_index;
3875 unsigned spi_vs_out_config, nparams;
3876
3877 /* VS is required to export at least one param. */
3878 nparams = MAX2(outinfo->param_exports, 1);
3879 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3880
3881 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3882 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3883 }
3884
3885 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3886
3887 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3888 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3889 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3890 V_02870C_SPI_SHADER_4COMP :
3891 V_02870C_SPI_SHADER_NONE) |
3892 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3893 V_02870C_SPI_SHADER_4COMP :
3894 V_02870C_SPI_SHADER_NONE) |
3895 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3896 V_02870C_SPI_SHADER_4COMP :
3897 V_02870C_SPI_SHADER_NONE));
3898
3899 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3900 S_028818_VTX_W0_FMT(1) |
3901 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3902 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3903 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3904
3905 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3906 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3907 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3908 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3909 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3910 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3911 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3912 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3913 cull_dist_mask << 8 |
3914 clip_dist_mask);
3915
3916 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3917 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3918 outinfo->writes_viewport_index);
3919 }
3920
3921 static void
3922 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3923 struct radv_pipeline *pipeline,
3924 struct radv_shader_variant *shader)
3925 {
3926 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3927
3928 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3929 radeon_emit(cs, va >> 8);
3930 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3931 radeon_emit(cs, shader->config.rsrc1);
3932 radeon_emit(cs, shader->config.rsrc2);
3933 }
3934
3935 static void
3936 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3937 struct radv_pipeline *pipeline,
3938 struct radv_shader_variant *shader,
3939 const struct radv_tessellation_state *tess)
3940 {
3941 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3942 uint32_t rsrc2 = shader->config.rsrc2;
3943
3944 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3945 radeon_emit(cs, va >> 8);
3946 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3947
3948 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3949 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3950 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3951 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3952
3953 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3954 radeon_emit(cs, shader->config.rsrc1);
3955 radeon_emit(cs, rsrc2);
3956 }
3957
3958 static void
3959 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3960 struct radeon_cmdbuf *cs,
3961 struct radv_pipeline *pipeline,
3962 struct radv_shader_variant *shader)
3963 {
3964 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3965 gl_shader_stage es_type =
3966 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3967 struct radv_shader_variant *es =
3968 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3969 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3970
3971 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3972 radeon_emit(cs, va >> 8);
3973 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3974 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3975 radeon_emit(cs, shader->config.rsrc1);
3976 radeon_emit(cs, shader->config.rsrc2);
3977
3978 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3979 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3980 clip_dist_mask = outinfo->clip_dist_mask;
3981 cull_dist_mask = outinfo->cull_dist_mask;
3982 total_mask = clip_dist_mask | cull_dist_mask;
3983 bool misc_vec_ena = outinfo->writes_pointsize ||
3984 outinfo->writes_layer ||
3985 outinfo->writes_viewport_index;
3986 bool es_enable_prim_id = outinfo->export_prim_id ||
3987 (es && es->info.uses_prim_id);
3988 bool break_wave_at_eoi = false;
3989 unsigned ge_cntl;
3990 unsigned nparams;
3991
3992 if (es_type == MESA_SHADER_TESS_EVAL) {
3993 struct radv_shader_variant *gs =
3994 pipeline->shaders[MESA_SHADER_GEOMETRY];
3995
3996 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3997 break_wave_at_eoi = true;
3998 }
3999
4000 nparams = MAX2(outinfo->param_exports, 1);
4001 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
4002 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
4003 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
4004
4005 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
4006 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
4007 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
4008 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
4009 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4010 V_02870C_SPI_SHADER_4COMP :
4011 V_02870C_SPI_SHADER_NONE) |
4012 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4013 V_02870C_SPI_SHADER_4COMP :
4014 V_02870C_SPI_SHADER_NONE) |
4015 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4016 V_02870C_SPI_SHADER_4COMP :
4017 V_02870C_SPI_SHADER_NONE));
4018
4019 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
4020 S_028818_VTX_W0_FMT(1) |
4021 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4022 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4023 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4024 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4025 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4026 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4027 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4028 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4029 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4030 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4031 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4032 cull_dist_mask << 8 |
4033 clip_dist_mask);
4034
4035 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4036 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4037 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4038
4039 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4040 ngg_state->vgt_esgs_ring_itemsize);
4041
4042 /* NGG specific registers. */
4043 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4044 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4045
4046 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4047 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4048 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4049 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4050 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4051 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4052 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4053 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4054 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4055 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4056 S_028B90_CNT(gs_num_invocations) |
4057 S_028B90_ENABLE(gs_num_invocations > 1) |
4058 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4059
4060 /* User edge flags are set by the pos exports. If user edge flags are
4061 * not used, we must use hw-generated edge flags and pass them via
4062 * the prim export to prevent drawing lines on internal edges of
4063 * decomposed primitives (such as quads) with polygon mode = lines.
4064 *
4065 * TODO: We should combine hw-generated edge flags with user edge
4066 * flags in the shader.
4067 */
4068 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4069 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4070 !radv_pipeline_has_gs(pipeline)));
4071
4072 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4073 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4074 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4075
4076 /* Bug workaround for a possible hang with non-tessellation cases.
4077 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4078 *
4079 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4080 */
4081 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
4082 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
4083 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
4084 !radv_pipeline_has_tess(pipeline) &&
4085 ngg_state->hw_max_esverts != 256) {
4086 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4087
4088 if (ngg_state->hw_max_esverts > 5) {
4089 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4090 }
4091 }
4092
4093 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4094 }
4095
4096 static void
4097 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4098 struct radv_pipeline *pipeline,
4099 struct radv_shader_variant *shader,
4100 const struct radv_tessellation_state *tess)
4101 {
4102 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4103
4104 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4105 unsigned hs_rsrc2 = shader->config.rsrc2;
4106
4107 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4108 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4109 } else {
4110 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4111 }
4112
4113 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4114 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4115 radeon_emit(cs, va >> 8);
4116 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4117 } else {
4118 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4119 radeon_emit(cs, va >> 8);
4120 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4121 }
4122
4123 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4124 radeon_emit(cs, shader->config.rsrc1);
4125 radeon_emit(cs, hs_rsrc2);
4126 } else {
4127 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4128 radeon_emit(cs, va >> 8);
4129 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4130 radeon_emit(cs, shader->config.rsrc1);
4131 radeon_emit(cs, shader->config.rsrc2);
4132 }
4133 }
4134
4135 static void
4136 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4137 struct radeon_cmdbuf *cs,
4138 struct radv_pipeline *pipeline,
4139 const struct radv_tessellation_state *tess)
4140 {
4141 struct radv_shader_variant *vs;
4142
4143 /* Skip shaders merged into HS/GS */
4144 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4145 if (!vs)
4146 return;
4147
4148 if (vs->info.vs.as_ls)
4149 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4150 else if (vs->info.vs.as_es)
4151 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4152 else if (vs->info.is_ngg)
4153 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4154 else
4155 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4156 }
4157
4158 static void
4159 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4160 struct radeon_cmdbuf *cs,
4161 struct radv_pipeline *pipeline,
4162 const struct radv_tessellation_state *tess)
4163 {
4164 if (!radv_pipeline_has_tess(pipeline))
4165 return;
4166
4167 struct radv_shader_variant *tes, *tcs;
4168
4169 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4170 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4171
4172 if (tes) {
4173 if (tes->info.is_ngg) {
4174 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4175 } else if (tes->info.tes.as_es)
4176 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4177 else
4178 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4179 }
4180
4181 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4182
4183 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4184 tess->tf_param);
4185
4186 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4187 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4188 tess->ls_hs_config);
4189 else
4190 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4191 tess->ls_hs_config);
4192
4193 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4194 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4195 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4196 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4197 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4198 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4199 }
4200 }
4201
4202 static void
4203 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4204 struct radeon_cmdbuf *cs,
4205 struct radv_pipeline *pipeline,
4206 struct radv_shader_variant *gs)
4207 {
4208 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4209 unsigned gs_max_out_vertices;
4210 uint8_t *num_components;
4211 uint8_t max_stream;
4212 unsigned offset;
4213 uint64_t va;
4214
4215 gs_max_out_vertices = gs->info.gs.vertices_out;
4216 max_stream = gs->info.gs.max_stream;
4217 num_components = gs->info.gs.num_stream_output_components;
4218
4219 offset = num_components[0] * gs_max_out_vertices;
4220
4221 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4222 radeon_emit(ctx_cs, offset);
4223 if (max_stream >= 1)
4224 offset += num_components[1] * gs_max_out_vertices;
4225 radeon_emit(ctx_cs, offset);
4226 if (max_stream >= 2)
4227 offset += num_components[2] * gs_max_out_vertices;
4228 radeon_emit(ctx_cs, offset);
4229 if (max_stream >= 3)
4230 offset += num_components[3] * gs_max_out_vertices;
4231 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4232
4233 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4234 radeon_emit(ctx_cs, num_components[0]);
4235 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4236 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4237 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4238
4239 uint32_t gs_num_invocations = gs->info.gs.invocations;
4240 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4241 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4242 S_028B90_ENABLE(gs_num_invocations > 0));
4243
4244 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4245 gs_state->vgt_esgs_ring_itemsize);
4246
4247 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4248
4249 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4250 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4251 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4252 radeon_emit(cs, va >> 8);
4253 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4254 } else {
4255 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4256 radeon_emit(cs, va >> 8);
4257 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4258 }
4259
4260 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4261 radeon_emit(cs, gs->config.rsrc1);
4262 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4263
4264 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4265 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4266 } else {
4267 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4268 radeon_emit(cs, va >> 8);
4269 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4270 radeon_emit(cs, gs->config.rsrc1);
4271 radeon_emit(cs, gs->config.rsrc2);
4272 }
4273
4274 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4275 }
4276
4277 static void
4278 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4279 struct radeon_cmdbuf *cs,
4280 struct radv_pipeline *pipeline)
4281 {
4282 struct radv_shader_variant *gs;
4283
4284 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4285 if (!gs)
4286 return;
4287
4288 if (gs->info.is_ngg)
4289 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4290 else
4291 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4292
4293 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4294 gs->info.gs.vertices_out);
4295 }
4296
4297 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4298 bool explicit, bool float16)
4299 {
4300 uint32_t ps_input_cntl;
4301 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4302 ps_input_cntl = S_028644_OFFSET(offset);
4303 if (flat_shade || explicit)
4304 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4305 if (explicit) {
4306 /* Force parameter cache to be read in passthrough
4307 * mode.
4308 */
4309 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4310 }
4311 if (float16) {
4312 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4313 S_028644_ATTR0_VALID(1);
4314 }
4315 } else {
4316 /* The input is a DEFAULT_VAL constant. */
4317 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4318 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4319 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4320 ps_input_cntl = S_028644_OFFSET(0x20) |
4321 S_028644_DEFAULT_VAL(offset);
4322 }
4323 return ps_input_cntl;
4324 }
4325
4326 static void
4327 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4328 struct radv_pipeline *pipeline)
4329 {
4330 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4331 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4332 uint32_t ps_input_cntl[32];
4333
4334 unsigned ps_offset = 0;
4335
4336 if (ps->info.ps.prim_id_input) {
4337 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4338 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4339 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4340 ++ps_offset;
4341 }
4342 }
4343
4344 if (ps->info.ps.layer_input ||
4345 ps->info.needs_multiview_view_index) {
4346 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4347 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4348 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4349 else
4350 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4351 ++ps_offset;
4352 }
4353
4354 if (ps->info.ps.has_pcoord) {
4355 unsigned val;
4356 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4357 ps_input_cntl[ps_offset] = val;
4358 ps_offset++;
4359 }
4360
4361 if (ps->info.ps.num_input_clips_culls) {
4362 unsigned vs_offset;
4363
4364 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4365 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4366 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4367 ++ps_offset;
4368 }
4369
4370 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4371 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4372 ps->info.ps.num_input_clips_culls > 4) {
4373 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4374 ++ps_offset;
4375 }
4376 }
4377
4378 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4379 unsigned vs_offset;
4380 bool flat_shade;
4381 bool explicit;
4382 bool float16;
4383 if (!(ps->info.ps.input_mask & (1u << i)))
4384 continue;
4385
4386 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4387 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4388 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4389 ++ps_offset;
4390 continue;
4391 }
4392
4393 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4394 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4395 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4396
4397 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4398 ++ps_offset;
4399 }
4400
4401 if (ps_offset) {
4402 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4403 for (unsigned i = 0; i < ps_offset; i++) {
4404 radeon_emit(ctx_cs, ps_input_cntl[i]);
4405 }
4406 }
4407 }
4408
4409 static uint32_t
4410 radv_compute_db_shader_control(const struct radv_device *device,
4411 const struct radv_pipeline *pipeline,
4412 const struct radv_shader_variant *ps)
4413 {
4414 unsigned z_order;
4415 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4416 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4417 else
4418 z_order = V_02880C_LATE_Z;
4419
4420 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4421 !device->physical_device->rad_info.rbplus_allowed;
4422
4423 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4424 * but this appears to break Project Cars (DXVK). See
4425 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4426 */
4427 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4428
4429 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4430 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4431 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4432 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4433 S_02880C_Z_ORDER(z_order) |
4434 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4435 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4436 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4437 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4438 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4439 }
4440
4441 static void
4442 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4443 struct radeon_cmdbuf *cs,
4444 struct radv_pipeline *pipeline)
4445 {
4446 struct radv_shader_variant *ps;
4447 uint64_t va;
4448 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4449
4450 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4451 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4452
4453 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4454 radeon_emit(cs, va >> 8);
4455 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4456 radeon_emit(cs, ps->config.rsrc1);
4457 radeon_emit(cs, ps->config.rsrc2);
4458
4459 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4460 radv_compute_db_shader_control(pipeline->device,
4461 pipeline, ps));
4462
4463 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4464 ps->config.spi_ps_input_ena);
4465
4466 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4467 ps->config.spi_ps_input_addr);
4468
4469 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4470 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4471 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4472
4473 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4474
4475 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4476 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4477 ps->info.ps.writes_stencil,
4478 ps->info.ps.writes_sample_mask));
4479
4480 if (pipeline->device->dfsm_allowed) {
4481 /* optimise this? */
4482 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4483 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4484 }
4485 }
4486
4487 static void
4488 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4489 struct radv_pipeline *pipeline)
4490 {
4491 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4492 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4493 return;
4494
4495 unsigned vtx_reuse_depth = 30;
4496 if (radv_pipeline_has_tess(pipeline) &&
4497 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4498 vtx_reuse_depth = 14;
4499 }
4500 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4501 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4502 }
4503
4504 static uint32_t
4505 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4506 {
4507 uint32_t stages = 0;
4508 if (radv_pipeline_has_tess(pipeline)) {
4509 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4510 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4511
4512 if (radv_pipeline_has_gs(pipeline))
4513 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4514 S_028B54_GS_EN(1);
4515 else if (radv_pipeline_has_ngg(pipeline))
4516 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4517 else
4518 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4519 } else if (radv_pipeline_has_gs(pipeline)) {
4520 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4521 S_028B54_GS_EN(1);
4522 } else if (radv_pipeline_has_ngg(pipeline)) {
4523 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4524 }
4525
4526 if (radv_pipeline_has_ngg(pipeline)) {
4527 stages |= S_028B54_PRIMGEN_EN(1);
4528 if (pipeline->streamout_shader)
4529 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4530 if (radv_pipeline_has_ngg_passthrough(pipeline))
4531 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4532 } else if (radv_pipeline_has_gs(pipeline)) {
4533 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4534 }
4535
4536 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4537 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4538
4539 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4540 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4541
4542 if (radv_pipeline_has_tess(pipeline))
4543 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4544
4545 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4546 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4547 if (pipeline->gs_copy_shader)
4548 vs_size = pipeline->gs_copy_shader->info.wave_size;
4549 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4550 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4551 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4552 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4553
4554 if (radv_pipeline_has_ngg(pipeline))
4555 gs_size = vs_size;
4556
4557 /* legacy GS only supports Wave64 */
4558 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4559 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4560 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4561 }
4562
4563 return stages;
4564 }
4565
4566 static uint32_t
4567 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4568 {
4569 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4570 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4571
4572 if (!discard_rectangle_info)
4573 return 0xffff;
4574
4575 unsigned mask = 0;
4576
4577 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4578 /* Interpret i as a bitmask, and then set the bit in the mask if
4579 * that combination of rectangles in which the pixel is contained
4580 * should pass the cliprect test. */
4581 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4582
4583 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4584 !relevant_subset)
4585 continue;
4586
4587 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4588 relevant_subset)
4589 continue;
4590
4591 mask |= 1u << i;
4592 }
4593
4594 return mask;
4595 }
4596
4597 static void
4598 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4599 struct radv_pipeline *pipeline,
4600 const struct radv_tessellation_state *tess)
4601 {
4602 bool break_wave_at_eoi = false;
4603 unsigned primgroup_size;
4604 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4605
4606 if (radv_pipeline_has_tess(pipeline)) {
4607 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4608 } else if (radv_pipeline_has_gs(pipeline)) {
4609 const struct gfx9_gs_info *gs_state =
4610 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4611 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4612 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4613 } else {
4614 primgroup_size = 128; /* recommended without a GS and tess */
4615 }
4616
4617 if (radv_pipeline_has_tess(pipeline)) {
4618 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4619 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4620 break_wave_at_eoi = true;
4621 }
4622
4623 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4624 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4625 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4626 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4627 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4628 }
4629
4630 static void
4631 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4632 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4633 const struct radv_graphics_pipeline_create_info *extra,
4634 const struct radv_blend_state *blend,
4635 const struct radv_tessellation_state *tess,
4636 unsigned prim, unsigned gs_out)
4637 {
4638 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4639 struct radeon_cmdbuf *cs = &pipeline->cs;
4640
4641 cs->max_dw = 64;
4642 ctx_cs->max_dw = 256;
4643 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4644 ctx_cs->buf = cs->buf + cs->max_dw;
4645
4646 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4647 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4648 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4649 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4650 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4651 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4652 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4653 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4654 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4655 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4656 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4657 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4658
4659 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4660 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4661
4662 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4663
4664 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4665 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4666 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4667 } else {
4668 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4669 }
4670 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4671
4672 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4673
4674 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4675
4676 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4677 assert(cs->cdw <= cs->max_dw);
4678 }
4679
4680 static struct radv_ia_multi_vgt_param_helpers
4681 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4682 const struct radv_tessellation_state *tess,
4683 uint32_t prim)
4684 {
4685 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4686 const struct radv_device *device = pipeline->device;
4687
4688 if (radv_pipeline_has_tess(pipeline))
4689 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4690 else if (radv_pipeline_has_gs(pipeline))
4691 ia_multi_vgt_param.primgroup_size = 64;
4692 else
4693 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4694
4695 /* GS requirement. */
4696 ia_multi_vgt_param.partial_es_wave = false;
4697 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4698 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4699 ia_multi_vgt_param.partial_es_wave = true;
4700
4701 ia_multi_vgt_param.wd_switch_on_eop = false;
4702 if (device->physical_device->rad_info.chip_class >= GFX7) {
4703 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4704 * 4 shader engines. Set 1 to pass the assertion below.
4705 * The other cases are hardware requirements. */
4706 if (device->physical_device->rad_info.max_se < 4 ||
4707 prim == V_008958_DI_PT_POLYGON ||
4708 prim == V_008958_DI_PT_LINELOOP ||
4709 prim == V_008958_DI_PT_TRIFAN ||
4710 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4711 (pipeline->graphics.prim_restart_enable &&
4712 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4713 (prim != V_008958_DI_PT_POINTLIST &&
4714 prim != V_008958_DI_PT_LINESTRIP))))
4715 ia_multi_vgt_param.wd_switch_on_eop = true;
4716 }
4717
4718 ia_multi_vgt_param.ia_switch_on_eoi = false;
4719 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4720 ia_multi_vgt_param.ia_switch_on_eoi = true;
4721 if (radv_pipeline_has_gs(pipeline) &&
4722 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4723 ia_multi_vgt_param.ia_switch_on_eoi = true;
4724 if (radv_pipeline_has_tess(pipeline)) {
4725 /* SWITCH_ON_EOI must be set if PrimID is used. */
4726 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4727 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4728 ia_multi_vgt_param.ia_switch_on_eoi = true;
4729 }
4730
4731 ia_multi_vgt_param.partial_vs_wave = false;
4732 if (radv_pipeline_has_tess(pipeline)) {
4733 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4734 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4735 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4736 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4737 radv_pipeline_has_gs(pipeline))
4738 ia_multi_vgt_param.partial_vs_wave = true;
4739 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4740 if (device->physical_device->rad_info.has_distributed_tess) {
4741 if (radv_pipeline_has_gs(pipeline)) {
4742 if (device->physical_device->rad_info.chip_class <= GFX8)
4743 ia_multi_vgt_param.partial_es_wave = true;
4744 } else {
4745 ia_multi_vgt_param.partial_vs_wave = true;
4746 }
4747 }
4748 }
4749
4750 /* Workaround for a VGT hang when strip primitive types are used with
4751 * primitive restart.
4752 */
4753 if (pipeline->graphics.prim_restart_enable &&
4754 (prim == V_008958_DI_PT_LINESTRIP ||
4755 prim == V_008958_DI_PT_TRISTRIP ||
4756 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4757 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4758 ia_multi_vgt_param.partial_vs_wave = true;
4759 }
4760
4761 if (radv_pipeline_has_gs(pipeline)) {
4762 /* On these chips there is the possibility of a hang if the
4763 * pipeline uses a GS and partial_vs_wave is not set.
4764 *
4765 * This mostly does not hit 4-SE chips, as those typically set
4766 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4767 * with GS due to another workaround.
4768 *
4769 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4770 */
4771 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4772 device->physical_device->rad_info.family == CHIP_FIJI ||
4773 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4774 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4775 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4776 device->physical_device->rad_info.family == CHIP_VEGAM) {
4777 ia_multi_vgt_param.partial_vs_wave = true;
4778 }
4779 }
4780
4781 ia_multi_vgt_param.base =
4782 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4783 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4784 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4785 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4786 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4787
4788 return ia_multi_vgt_param;
4789 }
4790
4791
4792 static void
4793 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4794 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4795 {
4796 const VkPipelineVertexInputStateCreateInfo *vi_info =
4797 pCreateInfo->pVertexInputState;
4798 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4799
4800 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4801 const VkVertexInputAttributeDescription *desc =
4802 &vi_info->pVertexAttributeDescriptions[i];
4803 unsigned loc = desc->location;
4804 const struct vk_format_description *format_desc;
4805
4806 format_desc = vk_format_description(desc->format);
4807
4808 velems->format_size[loc] = format_desc->block.bits / 8;
4809 }
4810
4811 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4812 const VkVertexInputBindingDescription *desc =
4813 &vi_info->pVertexBindingDescriptions[i];
4814
4815 pipeline->binding_stride[desc->binding] = desc->stride;
4816 pipeline->num_vertex_bindings =
4817 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4818 }
4819 }
4820
4821 static struct radv_shader_variant *
4822 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4823 {
4824 int i;
4825
4826 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4827 struct radv_shader_variant *shader =
4828 radv_get_shader(pipeline, i);
4829
4830 if (shader && shader->info.so.num_outputs > 0)
4831 return shader;
4832 }
4833
4834 return NULL;
4835 }
4836
4837 static VkResult
4838 radv_secure_compile(struct radv_pipeline *pipeline,
4839 struct radv_device *device,
4840 const struct radv_pipeline_key *key,
4841 const VkPipelineShaderStageCreateInfo **pStages,
4842 const VkPipelineCreateFlags flags,
4843 unsigned num_stages)
4844 {
4845 uint8_t allowed_pipeline_hashes[2][20];
4846 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4847 pipeline->layout, key, get_hash_flags(device));
4848
4849 /* Generate the GC copy hash */
4850 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4851 allowed_pipeline_hashes[1][0] ^= 1;
4852
4853 uint8_t allowed_hashes[2][20];
4854 for (unsigned i = 0; i < 2; ++i) {
4855 disk_cache_compute_key(device->physical_device->disk_cache,
4856 allowed_pipeline_hashes[i], 20,
4857 allowed_hashes[i]);
4858 }
4859
4860 /* Do an early exit if all cache entries are already there. */
4861 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4862 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4863 void *copy_entry = NULL;
4864 if (may_need_copy_shader)
4865 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4866
4867 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4868 free(main_entry);
4869 free(copy_entry);
4870
4871 if(has_all_cache_entries)
4872 return VK_SUCCESS;
4873
4874 unsigned process = 0;
4875 uint8_t sc_threads = device->instance->num_sc_threads;
4876 while (true) {
4877 mtx_lock(&device->sc_state->secure_compile_mutex);
4878 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4879 device->sc_state->secure_compile_thread_counter++;
4880 for (unsigned i = 0; i < sc_threads; i++) {
4881 if (!device->sc_state->secure_compile_processes[i].in_use) {
4882 device->sc_state->secure_compile_processes[i].in_use = true;
4883 process = i;
4884 break;
4885 }
4886 }
4887 mtx_unlock(&device->sc_state->secure_compile_mutex);
4888 break;
4889 }
4890 mtx_unlock(&device->sc_state->secure_compile_mutex);
4891 }
4892
4893 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4894 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4895
4896 /* Fork a copy of the slim untainted secure compile process */
4897 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4898 write(fd_secure_input, &sc_type, sizeof(sc_type));
4899
4900 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4901 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4902 return VK_ERROR_DEVICE_LOST;
4903
4904 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4905 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4906
4907 /* Write pipeline / shader module out to secure process via pipe */
4908 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4909 write(fd_secure_input, &sc_type, sizeof(sc_type));
4910
4911 /* Write pipeline layout out to secure process */
4912 struct radv_pipeline_layout *layout = pipeline->layout;
4913 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4914 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4915 for (uint32_t set = 0; set < layout->num_sets; set++) {
4916 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4917 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4918 }
4919
4920 /* Write pipeline key out to secure process */
4921 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4922
4923 /* Write pipeline create flags out to secure process */
4924 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4925
4926 /* Write stage and shader information out to secure process */
4927 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4928 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4929 if (!pStages[i])
4930 continue;
4931
4932 /* Write stage out to secure process */
4933 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4934 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4935
4936 /* Write entry point name out to secure process */
4937 size_t name_size = strlen(pStages[i]->pName) + 1;
4938 write(fd_secure_input, &name_size, sizeof(size_t));
4939 write(fd_secure_input, pStages[i]->pName, name_size);
4940
4941 /* Write shader module out to secure process */
4942 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4943 assert(!module->nir);
4944 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4945 write(fd_secure_input, &module_size, sizeof(size_t));
4946 write(fd_secure_input, module, module_size);
4947
4948 /* Write specialization info out to secure process */
4949 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4950 bool has_spec_info = specInfo ? true : false;
4951 write(fd_secure_input, &has_spec_info, sizeof(bool));
4952 if (specInfo) {
4953 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4954 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4955
4956 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4957 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4958 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4959 }
4960 }
4961
4962 /* Read the data returned from the secure process */
4963 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4964 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4965 return VK_ERROR_DEVICE_LOST;
4966
4967 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4968 assert(device->physical_device->disk_cache);
4969
4970 uint8_t disk_sha1[20];
4971 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4972 return VK_ERROR_DEVICE_LOST;
4973
4974 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4975 memcmp(disk_sha1, allowed_hashes[1], 20))
4976 return VK_ERROR_DEVICE_LOST;
4977
4978 uint32_t entry_size;
4979 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4980 return VK_ERROR_DEVICE_LOST;
4981
4982 struct cache_entry *entry = malloc(entry_size);
4983 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4984 return VK_ERROR_DEVICE_LOST;
4985
4986 disk_cache_put(device->physical_device->disk_cache,
4987 disk_sha1, entry, entry_size,
4988 NULL);
4989
4990 free(entry);
4991 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4992 uint8_t disk_sha1[20];
4993 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4994 return VK_ERROR_DEVICE_LOST;
4995
4996 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4997 memcmp(disk_sha1, allowed_hashes[1], 20))
4998 return VK_ERROR_DEVICE_LOST;
4999
5000 size_t size;
5001 struct cache_entry *entry = (struct cache_entry *)
5002 disk_cache_get(device->physical_device->disk_cache,
5003 disk_sha1, &size);
5004
5005 uint8_t found = entry ? 1 : 0;
5006 write(fd_secure_input, &found, sizeof(uint8_t));
5007
5008 if (found) {
5009 write(fd_secure_input, &size, sizeof(size_t));
5010 write(fd_secure_input, entry, size);
5011 }
5012
5013 free(entry);
5014 }
5015 }
5016
5017 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
5018 write(fd_secure_input, &sc_type, sizeof(sc_type));
5019
5020 mtx_lock(&device->sc_state->secure_compile_mutex);
5021 device->sc_state->secure_compile_thread_counter--;
5022 device->sc_state->secure_compile_processes[process].in_use = false;
5023 mtx_unlock(&device->sc_state->secure_compile_mutex);
5024
5025 return VK_SUCCESS;
5026 }
5027
5028 static VkResult
5029 radv_pipeline_init(struct radv_pipeline *pipeline,
5030 struct radv_device *device,
5031 struct radv_pipeline_cache *cache,
5032 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5033 const struct radv_graphics_pipeline_create_info *extra)
5034 {
5035 VkResult result;
5036 bool has_view_index = false;
5037
5038 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
5039 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
5040 if (subpass->view_mask)
5041 has_view_index = true;
5042
5043 pipeline->device = device;
5044 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5045 assert(pipeline->layout);
5046
5047 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
5048
5049 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5050 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5051 radv_init_feedback(creation_feedback);
5052
5053 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5054
5055 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5056 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5057 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
5058 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
5059 pStages[stage] = &pCreateInfo->pStages[i];
5060 if(creation_feedback)
5061 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5062 }
5063
5064 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5065 if (radv_device_use_secure_compile(device->instance)) {
5066 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5067 } else {
5068 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5069 }
5070
5071 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5072 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5073 uint32_t gs_out;
5074 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5075
5076 pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
5077 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5078
5079 if (radv_pipeline_has_gs(pipeline)) {
5080 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5081 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5082 } else if (radv_pipeline_has_tess(pipeline)) {
5083 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5084 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5085 else
5086 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5087 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5088 } else {
5089 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5090 }
5091 if (extra && extra->use_rectlist) {
5092 prim = V_008958_DI_PT_RECTLIST;
5093 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5094 pipeline->graphics.can_use_guardband = true;
5095 if (radv_pipeline_has_ngg(pipeline))
5096 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5097 }
5098 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5099 /* prim vertex count will need TESS changes */
5100 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5101
5102 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5103
5104 /* Ensure that some export memory is always allocated, for two reasons:
5105 *
5106 * 1) Correctness: The hardware ignores the EXEC mask if no export
5107 * memory is allocated, so KILL and alpha test do not work correctly
5108 * without this.
5109 * 2) Performance: Every shader needs at least a NULL export, even when
5110 * it writes no color/depth output. The NULL export instruction
5111 * stalls without this setting.
5112 *
5113 * Don't add this to CB_SHADER_MASK.
5114 *
5115 * GFX10 supports pixel shaders without exports by setting both the
5116 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5117 * instructions if any are present.
5118 */
5119 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5120 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5121 ps->info.ps.can_discard) &&
5122 !blend.spi_shader_col_format) {
5123 if (!ps->info.ps.writes_z &&
5124 !ps->info.ps.writes_stencil &&
5125 !ps->info.ps.writes_sample_mask)
5126 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5127 }
5128
5129 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5130 if (pipeline->shaders[i]) {
5131 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5132 }
5133 }
5134
5135 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5136 struct radv_shader_variant *gs =
5137 pipeline->shaders[MESA_SHADER_GEOMETRY];
5138
5139 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5140 }
5141
5142 struct radv_tessellation_state tess = {0};
5143 if (radv_pipeline_has_tess(pipeline)) {
5144 if (prim == V_008958_DI_PT_PATCH) {
5145 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5146 pipeline->graphics.prim_vertex_count.incr = 1;
5147 }
5148 tess = calculate_tess_state(pipeline, pCreateInfo);
5149 }
5150
5151 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5152
5153 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5154
5155 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5156 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5157
5158 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5159 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5160 if (loc->sgpr_idx != -1) {
5161 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5162 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5163 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5164 pipeline->graphics.vtx_emit_num = 3;
5165 else
5166 pipeline->graphics.vtx_emit_num = 2;
5167 }
5168
5169 /* Find the last vertex shader stage that eventually uses streamout. */
5170 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5171
5172 result = radv_pipeline_scratch_init(device, pipeline);
5173 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5174
5175 return result;
5176 }
5177
5178 VkResult
5179 radv_graphics_pipeline_create(
5180 VkDevice _device,
5181 VkPipelineCache _cache,
5182 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5183 const struct radv_graphics_pipeline_create_info *extra,
5184 const VkAllocationCallbacks *pAllocator,
5185 VkPipeline *pPipeline)
5186 {
5187 RADV_FROM_HANDLE(radv_device, device, _device);
5188 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5189 struct radv_pipeline *pipeline;
5190 VkResult result;
5191
5192 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5193 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5194 if (pipeline == NULL)
5195 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5196
5197 result = radv_pipeline_init(pipeline, device, cache,
5198 pCreateInfo, extra);
5199 if (result != VK_SUCCESS) {
5200 radv_pipeline_destroy(device, pipeline, pAllocator);
5201 return result;
5202 }
5203
5204 *pPipeline = radv_pipeline_to_handle(pipeline);
5205
5206 return VK_SUCCESS;
5207 }
5208
5209 VkResult radv_CreateGraphicsPipelines(
5210 VkDevice _device,
5211 VkPipelineCache pipelineCache,
5212 uint32_t count,
5213 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5214 const VkAllocationCallbacks* pAllocator,
5215 VkPipeline* pPipelines)
5216 {
5217 VkResult result = VK_SUCCESS;
5218 unsigned i = 0;
5219
5220 for (; i < count; i++) {
5221 VkResult r;
5222 r = radv_graphics_pipeline_create(_device,
5223 pipelineCache,
5224 &pCreateInfos[i],
5225 NULL, pAllocator, &pPipelines[i]);
5226 if (r != VK_SUCCESS) {
5227 result = r;
5228 pPipelines[i] = VK_NULL_HANDLE;
5229 }
5230 }
5231
5232 return result;
5233 }
5234
5235
5236 static void
5237 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5238 {
5239 struct radv_shader_variant *compute_shader;
5240 struct radv_device *device = pipeline->device;
5241 unsigned threads_per_threadgroup;
5242 unsigned threadgroups_per_cu = 1;
5243 unsigned waves_per_threadgroup;
5244 unsigned max_waves_per_sh = 0;
5245 uint64_t va;
5246
5247 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5248 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5249
5250 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5251 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5252
5253 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5254 radeon_emit(&pipeline->cs, va >> 8);
5255 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5256
5257 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5258 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5259 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5260 if (device->physical_device->rad_info.chip_class >= GFX10) {
5261 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5262 }
5263
5264 /* Calculate best compute resource limits. */
5265 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5266 compute_shader->info.cs.block_size[1] *
5267 compute_shader->info.cs.block_size[2];
5268 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5269 compute_shader->info.wave_size);
5270
5271 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5272 waves_per_threadgroup == 1)
5273 threadgroups_per_cu = 2;
5274
5275 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5276 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5277 waves_per_threadgroup,
5278 max_waves_per_sh,
5279 threadgroups_per_cu));
5280
5281 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5282 radeon_emit(&pipeline->cs,
5283 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5284 radeon_emit(&pipeline->cs,
5285 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5286 radeon_emit(&pipeline->cs,
5287 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5288
5289 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5290 }
5291
5292 static struct radv_pipeline_key
5293 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5294 const VkComputePipelineCreateInfo *pCreateInfo)
5295 {
5296 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5297 struct radv_pipeline_key key;
5298 memset(&key, 0, sizeof(key));
5299
5300 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5301 key.optimisations_disabled = 1;
5302
5303 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5304 vk_find_struct_const(stage->pNext,
5305 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5306
5307 if (subgroup_size) {
5308 assert(subgroup_size->requiredSubgroupSize == 32 ||
5309 subgroup_size->requiredSubgroupSize == 64);
5310 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5311 }
5312
5313 return key;
5314 }
5315
5316 static VkResult radv_compute_pipeline_create(
5317 VkDevice _device,
5318 VkPipelineCache _cache,
5319 const VkComputePipelineCreateInfo* pCreateInfo,
5320 const VkAllocationCallbacks* pAllocator,
5321 VkPipeline* pPipeline)
5322 {
5323 RADV_FROM_HANDLE(radv_device, device, _device);
5324 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5325 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5326 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5327 struct radv_pipeline *pipeline;
5328 VkResult result;
5329
5330 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5331 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5332 if (pipeline == NULL)
5333 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5334
5335 pipeline->device = device;
5336 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5337 assert(pipeline->layout);
5338
5339 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5340 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5341 radv_init_feedback(creation_feedback);
5342
5343 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5344 if (creation_feedback)
5345 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5346
5347 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5348
5349 struct radv_pipeline_key key =
5350 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5351
5352 if (radv_device_use_secure_compile(device->instance)) {
5353 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5354 *pPipeline = radv_pipeline_to_handle(pipeline);
5355
5356 return result;
5357 } else {
5358 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5359 }
5360
5361 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5362 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5363 result = radv_pipeline_scratch_init(device, pipeline);
5364 if (result != VK_SUCCESS) {
5365 radv_pipeline_destroy(device, pipeline, pAllocator);
5366 return result;
5367 }
5368
5369 radv_compute_generate_pm4(pipeline);
5370
5371 *pPipeline = radv_pipeline_to_handle(pipeline);
5372
5373 return VK_SUCCESS;
5374 }
5375
5376 VkResult radv_CreateComputePipelines(
5377 VkDevice _device,
5378 VkPipelineCache pipelineCache,
5379 uint32_t count,
5380 const VkComputePipelineCreateInfo* pCreateInfos,
5381 const VkAllocationCallbacks* pAllocator,
5382 VkPipeline* pPipelines)
5383 {
5384 VkResult result = VK_SUCCESS;
5385
5386 unsigned i = 0;
5387 for (; i < count; i++) {
5388 VkResult r;
5389 r = radv_compute_pipeline_create(_device, pipelineCache,
5390 &pCreateInfos[i],
5391 pAllocator, &pPipelines[i]);
5392 if (r != VK_SUCCESS) {
5393 result = r;
5394 pPipelines[i] = VK_NULL_HANDLE;
5395 }
5396 }
5397
5398 return result;
5399 }
5400
5401
5402 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5403 {
5404 uint32_t ret = 0;
5405 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5406 if (!pipeline->shaders[i])
5407 continue;
5408
5409 if (i == MESA_SHADER_GEOMETRY &&
5410 !radv_pipeline_has_ngg(pipeline)) {
5411 ret += 2u;
5412 } else {
5413 ret += 1u;
5414 }
5415
5416 }
5417 return ret;
5418 }
5419
5420 static struct radv_shader_variant *
5421 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5422 {
5423 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5424 if (!pipeline->shaders[i])
5425 continue;
5426 if (!index) {
5427 *stage = i;
5428 return pipeline->shaders[i];
5429 }
5430
5431 --index;
5432
5433 if (i == MESA_SHADER_GEOMETRY &&
5434 !radv_pipeline_has_ngg(pipeline)) {
5435 if (!index) {
5436 *stage = i;
5437 return pipeline->gs_copy_shader;
5438 }
5439 --index;
5440 }
5441 }
5442
5443 *stage = -1;
5444 return NULL;
5445 }
5446
5447 /* Basically strlcpy (which does not exist on linux) specialized for
5448 * descriptions. */
5449 static void desc_copy(char *desc, const char *src) {
5450 int len = strlen(src);
5451 assert(len < VK_MAX_DESCRIPTION_SIZE);
5452 memcpy(desc, src, len);
5453 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5454 }
5455
5456 VkResult radv_GetPipelineExecutablePropertiesKHR(
5457 VkDevice _device,
5458 const VkPipelineInfoKHR* pPipelineInfo,
5459 uint32_t* pExecutableCount,
5460 VkPipelineExecutablePropertiesKHR* pProperties)
5461 {
5462 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5463 const uint32_t total_count = radv_get_executable_count(pipeline);
5464
5465 if (!pProperties) {
5466 *pExecutableCount = total_count;
5467 return VK_SUCCESS;
5468 }
5469
5470 const uint32_t count = MIN2(total_count, *pExecutableCount);
5471 for (unsigned i = 0, executable_idx = 0;
5472 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5473 if (!pipeline->shaders[i])
5474 continue;
5475 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5476 const char *name = NULL;
5477 const char *description = NULL;
5478 switch(i) {
5479 case MESA_SHADER_VERTEX:
5480 name = "Vertex Shader";
5481 description = "Vulkan Vertex Shader";
5482 break;
5483 case MESA_SHADER_TESS_CTRL:
5484 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5485 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5486 name = "Vertex + Tessellation Control Shaders";
5487 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5488 } else {
5489 name = "Tessellation Control Shader";
5490 description = "Vulkan Tessellation Control Shader";
5491 }
5492 break;
5493 case MESA_SHADER_TESS_EVAL:
5494 name = "Tessellation Evaluation Shader";
5495 description = "Vulkan Tessellation Evaluation Shader";
5496 break;
5497 case MESA_SHADER_GEOMETRY:
5498 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5499 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5500 name = "Tessellation Evaluation + Geometry Shaders";
5501 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5502 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5503 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5504 name = "Vertex + Geometry Shader";
5505 description = "Combined Vulkan Vertex and Geometry Shaders";
5506 } else {
5507 name = "Geometry Shader";
5508 description = "Vulkan Geometry Shader";
5509 }
5510 break;
5511 case MESA_SHADER_FRAGMENT:
5512 name = "Fragment Shader";
5513 description = "Vulkan Fragment Shader";
5514 break;
5515 case MESA_SHADER_COMPUTE:
5516 name = "Compute Shader";
5517 description = "Vulkan Compute Shader";
5518 break;
5519 }
5520
5521 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5522 desc_copy(pProperties[executable_idx].name, name);
5523 desc_copy(pProperties[executable_idx].description, description);
5524
5525 ++executable_idx;
5526 if (i == MESA_SHADER_GEOMETRY &&
5527 !radv_pipeline_has_ngg(pipeline)) {
5528 assert(pipeline->gs_copy_shader);
5529 if (executable_idx >= count)
5530 break;
5531
5532 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5533 pProperties[executable_idx].subgroupSize = 64;
5534 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5535 desc_copy(pProperties[executable_idx].description,
5536 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5537
5538 ++executable_idx;
5539 }
5540 }
5541
5542 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5543 *pExecutableCount = count;
5544 return result;
5545 }
5546
5547 VkResult radv_GetPipelineExecutableStatisticsKHR(
5548 VkDevice _device,
5549 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5550 uint32_t* pStatisticCount,
5551 VkPipelineExecutableStatisticKHR* pStatistics)
5552 {
5553 RADV_FROM_HANDLE(radv_device, device, _device);
5554 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5555 gl_shader_stage stage;
5556 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5557
5558 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5559 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5560 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5561
5562 VkPipelineExecutableStatisticKHR *s = pStatistics;
5563 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5564 VkResult result = VK_SUCCESS;
5565
5566 if (s < end) {
5567 desc_copy(s->name, "SGPRs");
5568 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5569 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5570 s->value.u64 = shader->config.num_sgprs;
5571 }
5572 ++s;
5573
5574 if (s < end) {
5575 desc_copy(s->name, "VGPRs");
5576 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5577 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5578 s->value.u64 = shader->config.num_vgprs;
5579 }
5580 ++s;
5581
5582 if (s < end) {
5583 desc_copy(s->name, "Spilled SGPRs");
5584 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5585 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5586 s->value.u64 = shader->config.spilled_sgprs;
5587 }
5588 ++s;
5589
5590 if (s < end) {
5591 desc_copy(s->name, "Spilled VGPRs");
5592 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5593 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5594 s->value.u64 = shader->config.spilled_vgprs;
5595 }
5596 ++s;
5597
5598 if (s < end) {
5599 desc_copy(s->name, "PrivMem VGPRs");
5600 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5601 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5602 s->value.u64 = shader->info.private_mem_vgprs;
5603 }
5604 ++s;
5605
5606 if (s < end) {
5607 desc_copy(s->name, "Code size");
5608 desc_copy(s->description, "Code size in bytes");
5609 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5610 s->value.u64 = shader->exec_size;
5611 }
5612 ++s;
5613
5614 if (s < end) {
5615 desc_copy(s->name, "LDS size");
5616 desc_copy(s->description, "LDS size in bytes per workgroup");
5617 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5618 s->value.u64 = shader->config.lds_size * lds_increment;
5619 }
5620 ++s;
5621
5622 if (s < end) {
5623 desc_copy(s->name, "Scratch size");
5624 desc_copy(s->description, "Private memory in bytes per subgroup");
5625 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5626 s->value.u64 = shader->config.scratch_bytes_per_wave;
5627 }
5628 ++s;
5629
5630 if (s < end) {
5631 desc_copy(s->name, "Subgroups per SIMD");
5632 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5633 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5634 s->value.u64 = max_waves;
5635 }
5636 ++s;
5637
5638 if (shader->statistics) {
5639 for (unsigned i = 0; i < shader->statistics->count; i++) {
5640 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5641 uint32_t value = shader->statistics->values[i];
5642 if (s < end) {
5643 desc_copy(s->name, info->name);
5644 desc_copy(s->description, info->desc);
5645 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5646 s->value.u64 = value;
5647 }
5648 ++s;
5649 }
5650 }
5651
5652 if (!pStatistics)
5653 *pStatisticCount = s - pStatistics;
5654 else if (s > end) {
5655 *pStatisticCount = end - pStatistics;
5656 result = VK_INCOMPLETE;
5657 } else {
5658 *pStatisticCount = s - pStatistics;
5659 }
5660
5661 return result;
5662 }
5663
5664 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5665 {
5666 size_t total_size = strlen(src) + 1;
5667
5668 if (!data) {
5669 *data_size = total_size;
5670 return VK_SUCCESS;
5671 }
5672
5673 size_t size = MIN2(total_size, *data_size);
5674
5675 memcpy(data, src, size);
5676 if (size)
5677 *((char*)data + size - 1) = 0;
5678 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5679 }
5680
5681 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5682 VkDevice device,
5683 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5684 uint32_t* pInternalRepresentationCount,
5685 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5686 {
5687 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5688 gl_shader_stage stage;
5689 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5690
5691 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5692 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5693 VkResult result = VK_SUCCESS;
5694 /* optimized NIR */
5695 if (p < end) {
5696 p->isText = true;
5697 desc_copy(p->name, "NIR Shader(s)");
5698 desc_copy(p->description, "The optimized NIR shader(s)");
5699 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5700 result = VK_INCOMPLETE;
5701 }
5702 ++p;
5703
5704 /* backend IR */
5705 if (p < end) {
5706 p->isText = true;
5707 if (pipeline->device->physical_device->use_aco) {
5708 desc_copy(p->name, "ACO IR");
5709 desc_copy(p->description, "The ACO IR after some optimizations");
5710 } else {
5711 desc_copy(p->name, "LLVM IR");
5712 desc_copy(p->description, "The LLVM IR after some optimizations");
5713 }
5714 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5715 result = VK_INCOMPLETE;
5716 }
5717 ++p;
5718
5719 /* Disassembler */
5720 if (p < end) {
5721 p->isText = true;
5722 desc_copy(p->name, "Assembly");
5723 desc_copy(p->description, "Final Assembly");
5724 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5725 result = VK_INCOMPLETE;
5726 }
5727 ++p;
5728
5729 if (!pInternalRepresentations)
5730 *pInternalRepresentationCount = p - pInternalRepresentations;
5731 else if(p > end) {
5732 result = VK_INCOMPLETE;
5733 *pInternalRepresentationCount = end - pInternalRepresentations;
5734 } else {
5735 *pInternalRepresentationCount = p - pInternalRepresentations;
5736 }
5737
5738 return result;
5739 }