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radv: Enable lowering fdiv in nir.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44
45 void radv_shader_variant_destroy(struct radv_device *device,
46 struct radv_shader_variant *variant);
47
48 static const struct nir_shader_compiler_options nir_options = {
49 .vertex_id_zero_based = true,
50 .lower_scmp = true,
51 .lower_flrp32 = true,
52 .lower_fsat = true,
53 .lower_fdiv = true,
54 .lower_pack_snorm_2x16 = true,
55 .lower_pack_snorm_4x8 = true,
56 .lower_pack_unorm_2x16 = true,
57 .lower_pack_unorm_4x8 = true,
58 .lower_unpack_snorm_2x16 = true,
59 .lower_unpack_snorm_4x8 = true,
60 .lower_unpack_unorm_2x16 = true,
61 .lower_unpack_unorm_4x8 = true,
62 .lower_extract_byte = true,
63 .lower_extract_word = true,
64 };
65
66 VkResult radv_CreateShaderModule(
67 VkDevice _device,
68 const VkShaderModuleCreateInfo* pCreateInfo,
69 const VkAllocationCallbacks* pAllocator,
70 VkShaderModule* pShaderModule)
71 {
72 RADV_FROM_HANDLE(radv_device, device, _device);
73 struct radv_shader_module *module;
74
75 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
76 assert(pCreateInfo->flags == 0);
77
78 module = vk_alloc2(&device->alloc, pAllocator,
79 sizeof(*module) + pCreateInfo->codeSize, 8,
80 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
81 if (module == NULL)
82 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
83
84 module->nir = NULL;
85 module->size = pCreateInfo->codeSize;
86 memcpy(module->data, pCreateInfo->pCode, module->size);
87
88 _mesa_sha1_compute(module->data, module->size, module->sha1);
89
90 *pShaderModule = radv_shader_module_to_handle(module);
91
92 return VK_SUCCESS;
93 }
94
95 void radv_DestroyShaderModule(
96 VkDevice _device,
97 VkShaderModule _module,
98 const VkAllocationCallbacks* pAllocator)
99 {
100 RADV_FROM_HANDLE(radv_device, device, _device);
101 RADV_FROM_HANDLE(radv_shader_module, module, _module);
102
103 if (!module)
104 return;
105
106 vk_free2(&device->alloc, pAllocator, module);
107 }
108
109
110 static void
111 radv_pipeline_destroy(struct radv_device *device,
112 struct radv_pipeline *pipeline,
113 const VkAllocationCallbacks* allocator)
114 {
115 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
116 if (pipeline->shaders[i])
117 radv_shader_variant_destroy(device, pipeline->shaders[i]);
118
119 if (pipeline->gs_copy_shader)
120 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
121
122 vk_free2(&device->alloc, allocator, pipeline);
123 }
124
125 void radv_DestroyPipeline(
126 VkDevice _device,
127 VkPipeline _pipeline,
128 const VkAllocationCallbacks* pAllocator)
129 {
130 RADV_FROM_HANDLE(radv_device, device, _device);
131 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
132
133 if (!_pipeline)
134 return;
135
136 radv_pipeline_destroy(device, pipeline, pAllocator);
137 }
138
139
140 static void
141 radv_optimize_nir(struct nir_shader *shader)
142 {
143 bool progress;
144
145 do {
146 progress = false;
147
148 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
149 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
150 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
151
152 NIR_PASS(progress, shader, nir_copy_prop);
153 NIR_PASS(progress, shader, nir_opt_remove_phis);
154 NIR_PASS(progress, shader, nir_opt_dce);
155 NIR_PASS(progress, shader, nir_opt_dead_cf);
156 NIR_PASS(progress, shader, nir_opt_cse);
157 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
158 NIR_PASS(progress, shader, nir_opt_algebraic);
159 NIR_PASS(progress, shader, nir_opt_constant_folding);
160 NIR_PASS(progress, shader, nir_opt_undef);
161 NIR_PASS(progress, shader, nir_opt_conditional_discard);
162 } while (progress);
163 }
164
165 static nir_shader *
166 radv_shader_compile_to_nir(struct radv_device *device,
167 struct radv_shader_module *module,
168 const char *entrypoint_name,
169 gl_shader_stage stage,
170 const VkSpecializationInfo *spec_info,
171 bool dump)
172 {
173 if (strcmp(entrypoint_name, "main") != 0) {
174 radv_finishme("Multiple shaders per module not really supported");
175 }
176
177 nir_shader *nir;
178 nir_function *entry_point;
179 if (module->nir) {
180 /* Some things such as our meta clear/blit code will give us a NIR
181 * shader directly. In that case, we just ignore the SPIR-V entirely
182 * and just use the NIR shader */
183 nir = module->nir;
184 nir->options = &nir_options;
185 nir_validate_shader(nir);
186
187 assert(exec_list_length(&nir->functions) == 1);
188 struct exec_node *node = exec_list_get_head(&nir->functions);
189 entry_point = exec_node_data(nir_function, node, node);
190 } else {
191 uint32_t *spirv = (uint32_t *) module->data;
192 assert(module->size % 4 == 0);
193
194 uint32_t num_spec_entries = 0;
195 struct nir_spirv_specialization *spec_entries = NULL;
196 if (spec_info && spec_info->mapEntryCount > 0) {
197 num_spec_entries = spec_info->mapEntryCount;
198 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
199 for (uint32_t i = 0; i < num_spec_entries; i++) {
200 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
201 const void *data = spec_info->pData + entry.offset;
202 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
203
204 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
205 if (spec_info->dataSize == 8)
206 spec_entries[i].data64 = *(const uint64_t *)data;
207 else
208 spec_entries[i].data32 = *(const uint32_t *)data;
209 }
210 }
211 const struct nir_spirv_supported_extensions supported_ext = {
212 .draw_parameters = true,
213 .float64 = true,
214 .image_read_without_format = true,
215 .image_write_without_format = true,
216 .tessellation = true,
217 };
218 entry_point = spirv_to_nir(spirv, module->size / 4,
219 spec_entries, num_spec_entries,
220 stage, entrypoint_name, &supported_ext, &nir_options);
221 nir = entry_point->shader;
222 assert(nir->stage == stage);
223 nir_validate_shader(nir);
224
225 free(spec_entries);
226
227 /* We have to lower away local constant initializers right before we
228 * inline functions. That way they get properly initialized at the top
229 * of the function and not at the top of its caller.
230 */
231 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
232 NIR_PASS_V(nir, nir_lower_returns);
233 NIR_PASS_V(nir, nir_inline_functions);
234
235 /* Pick off the single entrypoint that we want */
236 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
237 if (func != entry_point)
238 exec_node_remove(&func->node);
239 }
240 assert(exec_list_length(&nir->functions) == 1);
241 entry_point->name = ralloc_strdup(entry_point, "main");
242
243 NIR_PASS_V(nir, nir_remove_dead_variables,
244 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
245
246 /* Now that we've deleted all but the main function, we can go ahead and
247 * lower the rest of the constant initializers.
248 */
249 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
250 NIR_PASS_V(nir, nir_lower_system_values);
251 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
252 }
253
254 /* Vulkan uses the separate-shader linking model */
255 nir->info->separate_shader = true;
256
257 nir_shader_gather_info(nir, entry_point->impl);
258
259 nir_variable_mode indirect_mask = 0;
260 indirect_mask |= nir_var_shader_in;
261 indirect_mask |= nir_var_local;
262
263 nir_lower_indirect_derefs(nir, indirect_mask);
264
265 static const nir_lower_tex_options tex_options = {
266 .lower_txp = ~0,
267 };
268
269 nir_lower_tex(nir, &tex_options);
270
271 nir_lower_vars_to_ssa(nir);
272 nir_lower_var_copies(nir);
273 nir_lower_global_vars_to_local(nir);
274 nir_remove_dead_variables(nir, nir_var_local);
275 radv_optimize_nir(nir);
276
277 if (dump)
278 nir_print_shader(nir, stderr);
279
280 return nir;
281 }
282
283 static const char *radv_get_shader_name(struct radv_shader_variant *var,
284 gl_shader_stage stage)
285 {
286 switch (stage) {
287 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
288 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
289 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
290 case MESA_SHADER_COMPUTE: return "Compute Shader";
291 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
292 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
293 default:
294 return "Unknown shader";
295 };
296
297 }
298 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
299 {
300 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
301 struct radv_shader_variant *var;
302 struct ac_shader_config *conf;
303 int i;
304 FILE *file = stderr;
305 unsigned max_simd_waves = 10;
306 unsigned lds_per_wave = 0;
307
308 for (i = 0; i < MESA_SHADER_STAGES; i++) {
309 if (!pipeline->shaders[i])
310 continue;
311 var = pipeline->shaders[i];
312
313 conf = &var->config;
314
315 if (i == MESA_SHADER_FRAGMENT) {
316 lds_per_wave = conf->lds_size * lds_increment +
317 align(var->info.fs.num_interp * 48, lds_increment);
318 }
319
320 if (conf->num_sgprs) {
321 if (device->physical_device->rad_info.chip_class >= VI)
322 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
323 else
324 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
325 }
326
327 if (conf->num_vgprs)
328 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
329
330 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
331 * that PS can use.
332 */
333 if (lds_per_wave)
334 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
335
336 fprintf(file, "\n%s:\n",
337 radv_get_shader_name(var, i));
338 if (i == MESA_SHADER_FRAGMENT) {
339 fprintf(file, "*** SHADER CONFIG ***\n"
340 "SPI_PS_INPUT_ADDR = 0x%04x\n"
341 "SPI_PS_INPUT_ENA = 0x%04x\n",
342 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
343 }
344 fprintf(file, "*** SHADER STATS ***\n"
345 "SGPRS: %d\n"
346 "VGPRS: %d\n"
347 "Spilled SGPRs: %d\n"
348 "Spilled VGPRs: %d\n"
349 "Code Size: %d bytes\n"
350 "LDS: %d blocks\n"
351 "Scratch: %d bytes per wave\n"
352 "Max Waves: %d\n"
353 "********************\n\n\n",
354 conf->num_sgprs, conf->num_vgprs,
355 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
356 conf->lds_size, conf->scratch_bytes_per_wave,
357 max_simd_waves);
358 }
359 }
360
361 void radv_shader_variant_destroy(struct radv_device *device,
362 struct radv_shader_variant *variant)
363 {
364 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
365 return;
366
367 device->ws->buffer_destroy(variant->bo);
368 free(variant);
369 }
370
371 static void radv_fill_shader_variant(struct radv_device *device,
372 struct radv_shader_variant *variant,
373 struct ac_shader_binary *binary,
374 gl_shader_stage stage)
375 {
376 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
377 unsigned vgpr_comp_cnt = 0;
378
379 if (scratch_enabled && !device->llvm_supports_spill)
380 radv_finishme("shader scratch support only available with LLVM 4.0");
381
382 variant->code_size = binary->code_size;
383 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
384 S_00B12C_SCRATCH_EN(scratch_enabled);
385
386 switch (stage) {
387 case MESA_SHADER_TESS_EVAL:
388 vgpr_comp_cnt = 3;
389 /* fallthrough */
390 case MESA_SHADER_TESS_CTRL:
391 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
392 break;
393 case MESA_SHADER_VERTEX:
394 case MESA_SHADER_GEOMETRY:
395 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
396 break;
397 case MESA_SHADER_FRAGMENT:
398 break;
399 case MESA_SHADER_COMPUTE:
400 variant->rsrc2 |=
401 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
402 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
403 S_00B84C_TG_SIZE_EN(1) |
404 S_00B84C_LDS_SIZE(variant->config.lds_size);
405 break;
406 default:
407 unreachable("unsupported shader type");
408 break;
409 }
410
411 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
412 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
413 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
414 S_00B848_DX10_CLAMP(1) |
415 S_00B848_FLOAT_MODE(variant->config.float_mode);
416
417 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
418 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
419
420 void *ptr = device->ws->buffer_map(variant->bo);
421 memcpy(ptr, binary->code, binary->code_size);
422 device->ws->buffer_unmap(variant->bo);
423
424
425 }
426
427 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
428 struct nir_shader *shader,
429 struct radv_pipeline_layout *layout,
430 const union ac_shader_variant_key *key,
431 void** code_out,
432 unsigned *code_size_out,
433 bool dump)
434 {
435 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
436 enum radeon_family chip_family = device->physical_device->rad_info.family;
437 LLVMTargetMachineRef tm;
438 if (!variant)
439 return NULL;
440
441 struct ac_nir_compiler_options options = {0};
442 options.layout = layout;
443 if (key)
444 options.key = *key;
445
446 struct ac_shader_binary binary;
447
448 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
449 options.family = chip_family;
450 options.chip_class = device->physical_device->rad_info.chip_class;
451 options.supports_spill = device->llvm_supports_spill;
452 tm = ac_create_target_machine(chip_family, options.supports_spill);
453 ac_compile_nir_shader(tm, &binary, &variant->config,
454 &variant->info, shader, &options, dump);
455 LLVMDisposeTargetMachine(tm);
456
457 radv_fill_shader_variant(device, variant, &binary, shader->stage);
458
459 if (code_out) {
460 *code_out = binary.code;
461 *code_size_out = binary.code_size;
462 } else
463 free(binary.code);
464 free(binary.config);
465 free(binary.rodata);
466 free(binary.global_symbol_offsets);
467 free(binary.relocs);
468 free(binary.disasm_string);
469 variant->ref_count = 1;
470 return variant;
471 }
472
473 static struct radv_shader_variant *
474 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
475 struct nir_shader *nir,
476 void** code_out,
477 unsigned *code_size_out,
478 bool dump_shader)
479 {
480 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
481 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
482 LLVMTargetMachineRef tm;
483 if (!variant)
484 return NULL;
485
486 struct ac_nir_compiler_options options = {0};
487 struct ac_shader_binary binary;
488 options.family = chip_family;
489 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
490 options.supports_spill = pipeline->device->llvm_supports_spill;
491 tm = ac_create_target_machine(chip_family, options.supports_spill);
492 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
493 LLVMDisposeTargetMachine(tm);
494
495 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
496
497 if (code_out) {
498 *code_out = binary.code;
499 *code_size_out = binary.code_size;
500 } else
501 free(binary.code);
502 free(binary.config);
503 free(binary.rodata);
504 free(binary.global_symbol_offsets);
505 free(binary.relocs);
506 free(binary.disasm_string);
507 variant->ref_count = 1;
508 return variant;
509 }
510
511 static struct radv_shader_variant *
512 radv_pipeline_compile(struct radv_pipeline *pipeline,
513 struct radv_pipeline_cache *cache,
514 struct radv_shader_module *module,
515 const char *entrypoint,
516 gl_shader_stage stage,
517 const VkSpecializationInfo *spec_info,
518 struct radv_pipeline_layout *layout,
519 const union ac_shader_variant_key *key)
520 {
521 unsigned char sha1[20];
522 unsigned char gs_copy_sha1[20];
523 struct radv_shader_variant *variant;
524 nir_shader *nir;
525 void *code = NULL;
526 unsigned code_size = 0;
527 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
528
529 if (module->nir)
530 _mesa_sha1_compute(module->nir->info->name,
531 strlen(module->nir->info->name),
532 module->sha1);
533
534 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
535 if (stage == MESA_SHADER_GEOMETRY)
536 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
537 layout, key, 1);
538
539 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
540 cache,
541 sha1);
542
543 if (stage == MESA_SHADER_GEOMETRY) {
544 pipeline->gs_copy_shader =
545 radv_create_shader_variant_from_pipeline_cache(
546 pipeline->device,
547 cache,
548 gs_copy_sha1);
549 }
550
551 if (variant &&
552 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
553 return variant;
554
555 nir = radv_shader_compile_to_nir(pipeline->device,
556 module, entrypoint, stage,
557 spec_info, dump);
558 if (nir == NULL)
559 return NULL;
560
561 if (!variant) {
562 variant = radv_shader_variant_create(pipeline->device, nir,
563 layout, key, &code,
564 &code_size, dump);
565 }
566
567 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
568 void *gs_copy_code = NULL;
569 unsigned gs_copy_code_size = 0;
570 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
571 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
572
573 if (pipeline->gs_copy_shader) {
574 pipeline->gs_copy_shader =
575 radv_pipeline_cache_insert_shader(cache,
576 gs_copy_sha1,
577 pipeline->gs_copy_shader,
578 gs_copy_code,
579 gs_copy_code_size);
580 }
581 }
582 if (!module->nir)
583 ralloc_free(nir);
584
585 if (variant)
586 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
587 code, code_size);
588
589 if (code)
590 free(code);
591 return variant;
592 }
593
594 static union ac_shader_variant_key
595 radv_compute_tes_key(bool as_es)
596 {
597 union ac_shader_variant_key key;
598 memset(&key, 0, sizeof(key));
599 key.tes.as_es = as_es;
600 return key;
601 }
602
603 static union ac_shader_variant_key
604 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
605 {
606 union ac_shader_variant_key key;
607 memset(&key, 0, sizeof(key));
608 key.tcs.primitive_mode = primitive_mode;
609 key.tcs.input_vertices = input_vertices;
610 return key;
611 }
612
613 static void
614 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
615 struct radv_pipeline_cache *cache,
616 struct radv_shader_module *tcs_module,
617 struct radv_shader_module *tes_module,
618 const char *tcs_entrypoint,
619 const char *tes_entrypoint,
620 const VkSpecializationInfo *tcs_spec_info,
621 const VkSpecializationInfo *tes_spec_info,
622 struct radv_pipeline_layout *layout,
623 unsigned input_vertices)
624 {
625 unsigned char tcs_sha1[20], tes_sha1[20];
626 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
627 nir_shader *tes_nir, *tcs_nir;
628 void *tes_code = NULL, *tcs_code = NULL;
629 unsigned tes_code_size = 0, tcs_code_size = 0;
630 union ac_shader_variant_key tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline));
631 union ac_shader_variant_key tcs_key;
632 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
633
634 if (tes_module->nir)
635 _mesa_sha1_compute(tes_module->nir->info->name,
636 strlen(tes_module->nir->info->name),
637 tes_module->sha1);
638 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
639
640 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
641 cache,
642 tes_sha1);
643
644 if (tes_variant) {
645 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
646
647 if (tcs_module->nir)
648 _mesa_sha1_compute(tcs_module->nir->info->name,
649 strlen(tcs_module->nir->info->name),
650 tcs_module->sha1);
651
652 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
653
654 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
655 cache,
656 tcs_sha1);
657 }
658
659 if (tcs_variant && tes_variant) {
660 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
661 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
662 return;
663 }
664
665 tes_nir = radv_shader_compile_to_nir(pipeline->device,
666 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
667 tes_spec_info, dump);
668 if (tes_nir == NULL)
669 return;
670
671 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
672 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
673 tcs_spec_info, dump);
674 if (tcs_nir == NULL)
675 return;
676
677 nir_lower_tes_patch_vertices(tes_nir,
678 tcs_nir->info->tess.tcs_vertices_out);
679
680 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
681 layout, &tes_key, &tes_code,
682 &tes_code_size, dump);
683
684 tcs_key = radv_compute_tcs_key(tes_nir->info->tess.primitive_mode, input_vertices);
685 if (tcs_module->nir)
686 _mesa_sha1_compute(tcs_module->nir->info->name,
687 strlen(tcs_module->nir->info->name),
688 tcs_module->sha1);
689
690 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
691
692 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
693 layout, &tcs_key, &tcs_code,
694 &tcs_code_size, dump);
695
696 if (!tes_module->nir)
697 ralloc_free(tes_nir);
698
699 if (!tcs_module->nir)
700 ralloc_free(tcs_nir);
701
702 if (tes_variant)
703 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
704 tes_code, tes_code_size);
705
706 if (tcs_variant)
707 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
708 tcs_code, tcs_code_size);
709
710 if (tes_code)
711 free(tes_code);
712 if (tcs_code)
713 free(tcs_code);
714 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
715 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
716 return;
717 }
718
719 static VkResult
720 radv_pipeline_scratch_init(struct radv_device *device,
721 struct radv_pipeline *pipeline)
722 {
723 unsigned scratch_bytes_per_wave = 0;
724 unsigned max_waves = 0;
725 unsigned min_waves = 1;
726
727 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
728 if (pipeline->shaders[i]) {
729 unsigned max_stage_waves = device->scratch_waves;
730
731 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
732 pipeline->shaders[i]->config.scratch_bytes_per_wave);
733
734 max_stage_waves = MIN2(max_stage_waves,
735 4 * device->physical_device->rad_info.num_good_compute_units *
736 (256 / pipeline->shaders[i]->config.num_vgprs));
737 max_waves = MAX2(max_waves, max_stage_waves);
738 }
739 }
740
741 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
742 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
743 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
744 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
745 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
746 }
747
748 if (scratch_bytes_per_wave)
749 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
750
751 if (scratch_bytes_per_wave && max_waves < min_waves) {
752 /* Not really true at this moment, but will be true on first
753 * execution. Avoid having hanging shaders. */
754 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
755 }
756 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
757 pipeline->max_waves = max_waves;
758 return VK_SUCCESS;
759 }
760
761 static uint32_t si_translate_blend_function(VkBlendOp op)
762 {
763 switch (op) {
764 case VK_BLEND_OP_ADD:
765 return V_028780_COMB_DST_PLUS_SRC;
766 case VK_BLEND_OP_SUBTRACT:
767 return V_028780_COMB_SRC_MINUS_DST;
768 case VK_BLEND_OP_REVERSE_SUBTRACT:
769 return V_028780_COMB_DST_MINUS_SRC;
770 case VK_BLEND_OP_MIN:
771 return V_028780_COMB_MIN_DST_SRC;
772 case VK_BLEND_OP_MAX:
773 return V_028780_COMB_MAX_DST_SRC;
774 default:
775 return 0;
776 }
777 }
778
779 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
780 {
781 switch (factor) {
782 case VK_BLEND_FACTOR_ZERO:
783 return V_028780_BLEND_ZERO;
784 case VK_BLEND_FACTOR_ONE:
785 return V_028780_BLEND_ONE;
786 case VK_BLEND_FACTOR_SRC_COLOR:
787 return V_028780_BLEND_SRC_COLOR;
788 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
789 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
790 case VK_BLEND_FACTOR_DST_COLOR:
791 return V_028780_BLEND_DST_COLOR;
792 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
793 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
794 case VK_BLEND_FACTOR_SRC_ALPHA:
795 return V_028780_BLEND_SRC_ALPHA;
796 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
797 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
798 case VK_BLEND_FACTOR_DST_ALPHA:
799 return V_028780_BLEND_DST_ALPHA;
800 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
801 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
802 case VK_BLEND_FACTOR_CONSTANT_COLOR:
803 return V_028780_BLEND_CONSTANT_COLOR;
804 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
805 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
806 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
807 return V_028780_BLEND_CONSTANT_ALPHA;
808 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
809 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
810 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
811 return V_028780_BLEND_SRC_ALPHA_SATURATE;
812 case VK_BLEND_FACTOR_SRC1_COLOR:
813 return V_028780_BLEND_SRC1_COLOR;
814 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
815 return V_028780_BLEND_INV_SRC1_COLOR;
816 case VK_BLEND_FACTOR_SRC1_ALPHA:
817 return V_028780_BLEND_SRC1_ALPHA;
818 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
819 return V_028780_BLEND_INV_SRC1_ALPHA;
820 default:
821 return 0;
822 }
823 }
824
825 static bool is_dual_src(VkBlendFactor factor)
826 {
827 switch (factor) {
828 case VK_BLEND_FACTOR_SRC1_COLOR:
829 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
830 case VK_BLEND_FACTOR_SRC1_ALPHA:
831 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
832 return true;
833 default:
834 return false;
835 }
836 }
837
838 static unsigned si_choose_spi_color_format(VkFormat vk_format,
839 bool blend_enable,
840 bool blend_need_alpha)
841 {
842 const struct vk_format_description *desc = vk_format_description(vk_format);
843 unsigned format, ntype, swap;
844
845 /* Alpha is needed for alpha-to-coverage.
846 * Blending may be with or without alpha.
847 */
848 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
849 unsigned alpha = 0; /* exports alpha, but may not support blending */
850 unsigned blend = 0; /* supports blending, but may not export alpha */
851 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
852
853 format = radv_translate_colorformat(vk_format);
854 ntype = radv_translate_color_numformat(vk_format, desc,
855 vk_format_get_first_non_void_channel(vk_format));
856 swap = radv_translate_colorswap(vk_format, false);
857
858 /* Choose the SPI color formats. These are required values for Stoney/RB+.
859 * Other chips have multiple choices, though they are not necessarily better.
860 */
861 switch (format) {
862 case V_028C70_COLOR_5_6_5:
863 case V_028C70_COLOR_1_5_5_5:
864 case V_028C70_COLOR_5_5_5_1:
865 case V_028C70_COLOR_4_4_4_4:
866 case V_028C70_COLOR_10_11_11:
867 case V_028C70_COLOR_11_11_10:
868 case V_028C70_COLOR_8:
869 case V_028C70_COLOR_8_8:
870 case V_028C70_COLOR_8_8_8_8:
871 case V_028C70_COLOR_10_10_10_2:
872 case V_028C70_COLOR_2_10_10_10:
873 if (ntype == V_028C70_NUMBER_UINT)
874 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
875 else if (ntype == V_028C70_NUMBER_SINT)
876 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
877 else
878 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
879 break;
880
881 case V_028C70_COLOR_16:
882 case V_028C70_COLOR_16_16:
883 case V_028C70_COLOR_16_16_16_16:
884 if (ntype == V_028C70_NUMBER_UNORM ||
885 ntype == V_028C70_NUMBER_SNORM) {
886 /* UNORM16 and SNORM16 don't support blending */
887 if (ntype == V_028C70_NUMBER_UNORM)
888 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
889 else
890 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
891
892 /* Use 32 bits per channel for blending. */
893 if (format == V_028C70_COLOR_16) {
894 if (swap == V_028C70_SWAP_STD) { /* R */
895 blend = V_028714_SPI_SHADER_32_R;
896 blend_alpha = V_028714_SPI_SHADER_32_AR;
897 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
898 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
899 else
900 assert(0);
901 } else if (format == V_028C70_COLOR_16_16) {
902 if (swap == V_028C70_SWAP_STD) { /* RG */
903 blend = V_028714_SPI_SHADER_32_GR;
904 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
905 } else if (swap == V_028C70_SWAP_ALT) /* RA */
906 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
907 else
908 assert(0);
909 } else /* 16_16_16_16 */
910 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
911 } else if (ntype == V_028C70_NUMBER_UINT)
912 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
913 else if (ntype == V_028C70_NUMBER_SINT)
914 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
915 else if (ntype == V_028C70_NUMBER_FLOAT)
916 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
917 else
918 assert(0);
919 break;
920
921 case V_028C70_COLOR_32:
922 if (swap == V_028C70_SWAP_STD) { /* R */
923 blend = normal = V_028714_SPI_SHADER_32_R;
924 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
925 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
926 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
927 else
928 assert(0);
929 break;
930
931 case V_028C70_COLOR_32_32:
932 if (swap == V_028C70_SWAP_STD) { /* RG */
933 blend = normal = V_028714_SPI_SHADER_32_GR;
934 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
935 } else if (swap == V_028C70_SWAP_ALT) /* RA */
936 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
937 else
938 assert(0);
939 break;
940
941 case V_028C70_COLOR_32_32_32_32:
942 case V_028C70_COLOR_8_24:
943 case V_028C70_COLOR_24_8:
944 case V_028C70_COLOR_X24_8_32_FLOAT:
945 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
946 break;
947
948 default:
949 unreachable("unhandled blend format");
950 }
951
952 if (blend_enable && blend_need_alpha)
953 return blend_alpha;
954 else if(blend_need_alpha)
955 return alpha;
956 else if(blend_enable)
957 return blend;
958 else
959 return normal;
960 }
961
962 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
963 {
964 unsigned i, cb_shader_mask = 0;
965
966 for (i = 0; i < 8; i++) {
967 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
968 case V_028714_SPI_SHADER_ZERO:
969 break;
970 case V_028714_SPI_SHADER_32_R:
971 cb_shader_mask |= 0x1 << (i * 4);
972 break;
973 case V_028714_SPI_SHADER_32_GR:
974 cb_shader_mask |= 0x3 << (i * 4);
975 break;
976 case V_028714_SPI_SHADER_32_AR:
977 cb_shader_mask |= 0x9 << (i * 4);
978 break;
979 case V_028714_SPI_SHADER_FP16_ABGR:
980 case V_028714_SPI_SHADER_UNORM16_ABGR:
981 case V_028714_SPI_SHADER_SNORM16_ABGR:
982 case V_028714_SPI_SHADER_UINT16_ABGR:
983 case V_028714_SPI_SHADER_SINT16_ABGR:
984 case V_028714_SPI_SHADER_32_ABGR:
985 cb_shader_mask |= 0xf << (i * 4);
986 break;
987 default:
988 assert(0);
989 }
990 }
991 return cb_shader_mask;
992 }
993
994 static void
995 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
996 const VkGraphicsPipelineCreateInfo *pCreateInfo,
997 uint32_t blend_enable,
998 uint32_t blend_need_alpha,
999 bool single_cb_enable,
1000 bool blend_mrt0_is_dual_src)
1001 {
1002 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1003 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1004 struct radv_blend_state *blend = &pipeline->graphics.blend;
1005 unsigned col_format = 0;
1006
1007 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1008 struct radv_render_pass_attachment *attachment;
1009 unsigned cf;
1010
1011 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1012
1013 cf = si_choose_spi_color_format(attachment->format,
1014 blend_enable & (1 << i),
1015 blend_need_alpha & (1 << i));
1016
1017 col_format |= cf << (4 * i);
1018 }
1019
1020 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1021
1022 if (blend_mrt0_is_dual_src)
1023 col_format |= (col_format & 0xf) << 4;
1024 blend->spi_shader_col_format = col_format;
1025 }
1026
1027 static bool
1028 format_is_int8(VkFormat format)
1029 {
1030 const struct vk_format_description *desc = vk_format_description(format);
1031 int channel = vk_format_get_first_non_void_channel(format);
1032
1033 return channel >= 0 && desc->channel[channel].pure_integer &&
1034 desc->channel[channel].size == 8;
1035 }
1036
1037 unsigned radv_format_meta_fs_key(VkFormat format)
1038 {
1039 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1040 bool is_int8 = format_is_int8(format);
1041
1042 return col_format + (is_int8 ? 3 : 0);
1043 }
1044
1045 static unsigned
1046 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1047 {
1048 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1049 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1050 unsigned is_int8 = 0;
1051
1052 for (unsigned i = 0; i < subpass->color_count; ++i) {
1053 struct radv_render_pass_attachment *attachment;
1054
1055 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1056
1057 if (format_is_int8(attachment->format))
1058 is_int8 |= 1 << i;
1059 }
1060
1061 return is_int8;
1062 }
1063
1064 static void
1065 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1066 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1067 const struct radv_graphics_pipeline_create_info *extra)
1068 {
1069 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1070 struct radv_blend_state *blend = &pipeline->graphics.blend;
1071 unsigned mode = V_028808_CB_NORMAL;
1072 uint32_t blend_enable = 0, blend_need_alpha = 0;
1073 bool blend_mrt0_is_dual_src = false;
1074 int i;
1075 bool single_cb_enable = false;
1076
1077 if (!vkblend)
1078 return;
1079
1080 if (extra && extra->custom_blend_mode) {
1081 single_cb_enable = true;
1082 mode = extra->custom_blend_mode;
1083 }
1084 blend->cb_color_control = 0;
1085 if (vkblend->logicOpEnable)
1086 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1087 else
1088 blend->cb_color_control |= S_028808_ROP3(0xcc);
1089
1090 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1091 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1092 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1093 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1094
1095 blend->cb_target_mask = 0;
1096 for (i = 0; i < vkblend->attachmentCount; i++) {
1097 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1098 unsigned blend_cntl = 0;
1099 VkBlendOp eqRGB = att->colorBlendOp;
1100 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1101 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1102 VkBlendOp eqA = att->alphaBlendOp;
1103 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1104 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1105
1106 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1107
1108 if (!att->colorWriteMask)
1109 continue;
1110
1111 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1112 if (!att->blendEnable) {
1113 blend->cb_blend_control[i] = blend_cntl;
1114 continue;
1115 }
1116
1117 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1118 if (i == 0)
1119 blend_mrt0_is_dual_src = true;
1120
1121 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1122 srcRGB = VK_BLEND_FACTOR_ONE;
1123 dstRGB = VK_BLEND_FACTOR_ONE;
1124 }
1125 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1126 srcA = VK_BLEND_FACTOR_ONE;
1127 dstA = VK_BLEND_FACTOR_ONE;
1128 }
1129
1130 blend_cntl |= S_028780_ENABLE(1);
1131
1132 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1133 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1134 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1135 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1136 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1137 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1138 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1139 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1140 }
1141 blend->cb_blend_control[i] = blend_cntl;
1142
1143 blend_enable |= 1 << i;
1144
1145 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1146 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1147 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1148 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1149 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1150 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1151 blend_need_alpha |= 1 << i;
1152 }
1153 for (i = vkblend->attachmentCount; i < 8; i++)
1154 blend->cb_blend_control[i] = 0;
1155
1156 if (blend->cb_target_mask)
1157 blend->cb_color_control |= S_028808_MODE(mode);
1158 else
1159 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1160
1161 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1162 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1163 }
1164
1165 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1166 {
1167 switch (op) {
1168 case VK_STENCIL_OP_KEEP:
1169 return V_02842C_STENCIL_KEEP;
1170 case VK_STENCIL_OP_ZERO:
1171 return V_02842C_STENCIL_ZERO;
1172 case VK_STENCIL_OP_REPLACE:
1173 return V_02842C_STENCIL_REPLACE_TEST;
1174 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1175 return V_02842C_STENCIL_ADD_CLAMP;
1176 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1177 return V_02842C_STENCIL_SUB_CLAMP;
1178 case VK_STENCIL_OP_INVERT:
1179 return V_02842C_STENCIL_INVERT;
1180 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1181 return V_02842C_STENCIL_ADD_WRAP;
1182 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1183 return V_02842C_STENCIL_SUB_WRAP;
1184 default:
1185 return 0;
1186 }
1187 }
1188 static void
1189 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1190 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1191 const struct radv_graphics_pipeline_create_info *extra)
1192 {
1193 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1194 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1195
1196 memset(ds, 0, sizeof(*ds));
1197 if (!vkds)
1198 return;
1199 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1200 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1201 S_028800_ZFUNC(vkds->depthCompareOp) |
1202 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1203
1204 if (vkds->stencilTestEnable) {
1205 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1206 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1207 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1208 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1209 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1210
1211 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1212 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1213 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1214 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1215 }
1216
1217 if (extra) {
1218
1219 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1220 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1221
1222 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1223 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1224 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1225 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1226 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1227 }
1228 }
1229
1230 static uint32_t si_translate_fill(VkPolygonMode func)
1231 {
1232 switch(func) {
1233 case VK_POLYGON_MODE_FILL:
1234 return V_028814_X_DRAW_TRIANGLES;
1235 case VK_POLYGON_MODE_LINE:
1236 return V_028814_X_DRAW_LINES;
1237 case VK_POLYGON_MODE_POINT:
1238 return V_028814_X_DRAW_POINTS;
1239 default:
1240 assert(0);
1241 return V_028814_X_DRAW_POINTS;
1242 }
1243 }
1244 static void
1245 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1246 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1247 {
1248 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1249 struct radv_raster_state *raster = &pipeline->graphics.raster;
1250
1251 memset(raster, 0, sizeof(*raster));
1252
1253 raster->spi_interp_control =
1254 S_0286D4_FLAT_SHADE_ENA(1) |
1255 S_0286D4_PNT_SPRITE_ENA(1) |
1256 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1257 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1258 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1259 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1260 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1261
1262
1263 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1264 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1265 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1266 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1267 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1268 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1269
1270 raster->pa_su_vtx_cntl =
1271 S_028BE4_PIX_CENTER(1) | // TODO verify
1272 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1273 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1274
1275 raster->pa_su_sc_mode_cntl =
1276 S_028814_FACE(vkraster->frontFace) |
1277 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1278 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1279 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1280 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1281 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1282 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1283 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1284 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1285
1286 }
1287
1288 static void
1289 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1290 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1291 {
1292 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1293 struct radv_blend_state *blend = &pipeline->graphics.blend;
1294 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1295 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1296 int ps_iter_samples = 1;
1297 uint32_t mask = 0xffff;
1298
1299 if (vkms)
1300 ms->num_samples = vkms->rasterizationSamples;
1301 else
1302 ms->num_samples = 1;
1303
1304 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1305 ps_iter_samples = ms->num_samples;
1306 }
1307
1308 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1309 ms->pa_sc_aa_config = 0;
1310 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1311 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1312 ms->pa_sc_mode_cntl_1 =
1313 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1314 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1315 /* always 1: */
1316 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1317 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1318 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1319 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1320 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1321 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1322
1323 if (ms->num_samples > 1) {
1324 unsigned log_samples = util_logbase2(ms->num_samples);
1325 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1326 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1327 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1328 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1329 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1330 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1331 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1332 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1333 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1334 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1335 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1336 }
1337
1338 if (vkms) {
1339 if (vkms->alphaToCoverageEnable)
1340 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1341
1342 if (vkms->pSampleMask)
1343 mask = vkms->pSampleMask[0] & 0xffff;
1344 }
1345
1346 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1347 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1348 }
1349
1350 static bool
1351 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1352 {
1353 switch (topology) {
1354 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1355 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1356 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1357 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1358 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1359 return false;
1360 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1361 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1362 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1363 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1364 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1365 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1366 return true;
1367 default:
1368 unreachable("unhandled primitive type");
1369 }
1370 }
1371
1372 static uint32_t
1373 si_translate_prim(enum VkPrimitiveTopology topology)
1374 {
1375 switch (topology) {
1376 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1377 return V_008958_DI_PT_POINTLIST;
1378 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1379 return V_008958_DI_PT_LINELIST;
1380 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1381 return V_008958_DI_PT_LINESTRIP;
1382 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1383 return V_008958_DI_PT_TRILIST;
1384 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1385 return V_008958_DI_PT_TRISTRIP;
1386 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1387 return V_008958_DI_PT_TRIFAN;
1388 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1389 return V_008958_DI_PT_LINELIST_ADJ;
1390 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1391 return V_008958_DI_PT_LINESTRIP_ADJ;
1392 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1393 return V_008958_DI_PT_TRILIST_ADJ;
1394 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1395 return V_008958_DI_PT_TRISTRIP_ADJ;
1396 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1397 return V_008958_DI_PT_PATCH;
1398 default:
1399 assert(0);
1400 return 0;
1401 }
1402 }
1403
1404 static uint32_t
1405 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1406 {
1407 switch (gl_prim) {
1408 case 0: /* GL_POINTS */
1409 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1410 case 1: /* GL_LINES */
1411 case 3: /* GL_LINE_STRIP */
1412 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1413 case 0x8E7A: /* GL_ISOLINES */
1414 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1415
1416 case 4: /* GL_TRIANGLES */
1417 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1418 case 5: /* GL_TRIANGLE_STRIP */
1419 case 7: /* GL_QUADS */
1420 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1421 default:
1422 assert(0);
1423 return 0;
1424 }
1425 }
1426
1427 static uint32_t
1428 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1429 {
1430 switch (topology) {
1431 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1432 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1433 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1434 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1435 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1436 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1437 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1438 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1439 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1440 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1441 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1442 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1443 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1444 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1445 default:
1446 assert(0);
1447 return 0;
1448 }
1449 }
1450
1451 static unsigned si_map_swizzle(unsigned swizzle)
1452 {
1453 switch (swizzle) {
1454 case VK_SWIZZLE_Y:
1455 return V_008F0C_SQ_SEL_Y;
1456 case VK_SWIZZLE_Z:
1457 return V_008F0C_SQ_SEL_Z;
1458 case VK_SWIZZLE_W:
1459 return V_008F0C_SQ_SEL_W;
1460 case VK_SWIZZLE_0:
1461 return V_008F0C_SQ_SEL_0;
1462 case VK_SWIZZLE_1:
1463 return V_008F0C_SQ_SEL_1;
1464 default: /* VK_SWIZZLE_X */
1465 return V_008F0C_SQ_SEL_X;
1466 }
1467 }
1468
1469 static void
1470 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1471 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1472 {
1473 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1474 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1475 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1476
1477 pipeline->dynamic_state = default_dynamic_state;
1478
1479 if (pCreateInfo->pDynamicState) {
1480 /* Remove all of the states that are marked as dynamic */
1481 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1482 for (uint32_t s = 0; s < count; s++)
1483 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1484 }
1485
1486 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1487
1488 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1489 *
1490 * pViewportState is [...] NULL if the pipeline
1491 * has rasterization disabled.
1492 */
1493 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1494 assert(pCreateInfo->pViewportState);
1495
1496 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1497 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1498 typed_memcpy(dynamic->viewport.viewports,
1499 pCreateInfo->pViewportState->pViewports,
1500 pCreateInfo->pViewportState->viewportCount);
1501 }
1502
1503 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1504 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1505 typed_memcpy(dynamic->scissor.scissors,
1506 pCreateInfo->pViewportState->pScissors,
1507 pCreateInfo->pViewportState->scissorCount);
1508 }
1509 }
1510
1511 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1512 assert(pCreateInfo->pRasterizationState);
1513 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1514 }
1515
1516 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1517 assert(pCreateInfo->pRasterizationState);
1518 dynamic->depth_bias.bias =
1519 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1520 dynamic->depth_bias.clamp =
1521 pCreateInfo->pRasterizationState->depthBiasClamp;
1522 dynamic->depth_bias.slope =
1523 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1524 }
1525
1526 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1527 *
1528 * pColorBlendState is [...] NULL if the pipeline has rasterization
1529 * disabled or if the subpass of the render pass the pipeline is
1530 * created against does not use any color attachments.
1531 */
1532 bool uses_color_att = false;
1533 for (unsigned i = 0; i < subpass->color_count; ++i) {
1534 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1535 uses_color_att = true;
1536 break;
1537 }
1538 }
1539
1540 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1541 assert(pCreateInfo->pColorBlendState);
1542 typed_memcpy(dynamic->blend_constants,
1543 pCreateInfo->pColorBlendState->blendConstants, 4);
1544 }
1545
1546 /* If there is no depthstencil attachment, then don't read
1547 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1548 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1549 * no need to override the depthstencil defaults in
1550 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1551 *
1552 * Section 9.2 of the Vulkan 1.0.15 spec says:
1553 *
1554 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1555 * disabled or if the subpass of the render pass the pipeline is created
1556 * against does not use a depth/stencil attachment.
1557 */
1558 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1559 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1560 assert(pCreateInfo->pDepthStencilState);
1561
1562 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1563 dynamic->depth_bounds.min =
1564 pCreateInfo->pDepthStencilState->minDepthBounds;
1565 dynamic->depth_bounds.max =
1566 pCreateInfo->pDepthStencilState->maxDepthBounds;
1567 }
1568
1569 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1570 dynamic->stencil_compare_mask.front =
1571 pCreateInfo->pDepthStencilState->front.compareMask;
1572 dynamic->stencil_compare_mask.back =
1573 pCreateInfo->pDepthStencilState->back.compareMask;
1574 }
1575
1576 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1577 dynamic->stencil_write_mask.front =
1578 pCreateInfo->pDepthStencilState->front.writeMask;
1579 dynamic->stencil_write_mask.back =
1580 pCreateInfo->pDepthStencilState->back.writeMask;
1581 }
1582
1583 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1584 dynamic->stencil_reference.front =
1585 pCreateInfo->pDepthStencilState->front.reference;
1586 dynamic->stencil_reference.back =
1587 pCreateInfo->pDepthStencilState->back.reference;
1588 }
1589 }
1590
1591 pipeline->dynamic_state_mask = states;
1592 }
1593
1594 static union ac_shader_variant_key
1595 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
1596 {
1597 union ac_shader_variant_key key;
1598 const VkPipelineVertexInputStateCreateInfo *input_state =
1599 pCreateInfo->pVertexInputState;
1600
1601 memset(&key, 0, sizeof(key));
1602 key.vs.instance_rate_inputs = 0;
1603 key.vs.as_es = as_es;
1604 key.vs.as_ls = as_ls;
1605
1606 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1607 unsigned binding;
1608 binding = input_state->pVertexAttributeDescriptions[i].binding;
1609 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1610 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1611 }
1612 return key;
1613 }
1614
1615 static void
1616 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1617 {
1618 struct radv_device *device = pipeline->device;
1619 unsigned num_se = device->physical_device->rad_info.max_se;
1620 unsigned wave_size = 64;
1621 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1622 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1623 unsigned alignment = 256 * num_se;
1624 /* The maximum size is 63.999 MB per SE. */
1625 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1626 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1627 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1628 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1629 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1630
1631 /* Calculate the minimum size. */
1632 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1633 wave_size, alignment);
1634 /* These are recommended sizes, not minimum sizes. */
1635 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1636 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1637 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1638 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1639
1640 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1641 esgs_ring_size = align(esgs_ring_size, alignment);
1642 gsvs_ring_size = align(gsvs_ring_size, alignment);
1643
1644 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1645 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1646 }
1647
1648 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1649 unsigned *lds_size)
1650 {
1651 /* SPI barrier management bug:
1652 * Make sure we have at least 4k of LDS in use to avoid the bug.
1653 * It applies to workgroup sizes of more than one wavefront.
1654 */
1655 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1656 device->physical_device->rad_info.family == CHIP_KABINI ||
1657 device->physical_device->rad_info.family == CHIP_MULLINS)
1658 *lds_size = MAX2(*lds_size, 8);
1659 }
1660
1661 static void
1662 calculate_tess_state(struct radv_pipeline *pipeline,
1663 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1664 {
1665 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1666 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1667 unsigned num_tcs_patch_outputs;
1668 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1669 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1670 unsigned lds_size, hardware_lds_size;
1671 unsigned perpatch_output_offset;
1672 unsigned num_patches;
1673 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1674
1675 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1676 * are laid out in LDS. */
1677 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1678
1679 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1680 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1681 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1682
1683 /* Ensure that we only need one wave per SIMD so we don't need to check
1684 * resource usage. Also ensures that the number of tcs in and out
1685 * vertices per threadgroup are at most 256.
1686 */
1687 input_vertex_size = num_tcs_inputs * 16;
1688 output_vertex_size = num_tcs_outputs * 16;
1689
1690 input_patch_size = num_tcs_input_cp * input_vertex_size;
1691
1692 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1693 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1694 /* Ensure that we only need one wave per SIMD so we don't need to check
1695 * resource usage. Also ensures that the number of tcs in and out
1696 * vertices per threadgroup are at most 256.
1697 */
1698 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1699
1700 /* Make sure that the data fits in LDS. This assumes the shaders only
1701 * use LDS for the inputs and outputs.
1702 */
1703 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1704 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1705
1706 /* Make sure the output data fits in the offchip buffer */
1707 num_patches = MIN2(num_patches,
1708 (pipeline->device->tess_offchip_block_dw_size * 4) /
1709 output_patch_size);
1710
1711 /* Not necessary for correctness, but improves performance. The
1712 * specific value is taken from the proprietary driver.
1713 */
1714 num_patches = MIN2(num_patches, 40);
1715
1716 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1717 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1718 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1719 num_patches = MIN2(num_patches, one_wave);
1720 }
1721
1722 output_patch0_offset = input_patch_size * num_patches;
1723 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1724
1725 lds_size = output_patch0_offset + output_patch_size * num_patches;
1726
1727 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1728 assert(lds_size <= 65536);
1729 lds_size = align(lds_size, 512) / 512;
1730 } else {
1731 assert(lds_size <= 32768);
1732 lds_size = align(lds_size, 256) / 256;
1733 }
1734 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1735
1736 tess->lds_size = lds_size;
1737
1738 tess->tcs_in_layout = (input_patch_size / 4) |
1739 ((input_vertex_size / 4) << 13);
1740 tess->tcs_out_layout = (output_patch_size / 4) |
1741 ((output_vertex_size / 4) << 13);
1742 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1743 ((perpatch_output_offset / 16) << 16);
1744 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1745 (num_tcs_output_cp << 9) | num_patches;
1746
1747 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1748 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1749 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1750 tess->num_patches = num_patches;
1751 tess->num_tcs_input_cp = num_tcs_input_cp;
1752
1753 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1754 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1755
1756 switch (tes->info.tes.primitive_mode) {
1757 case GL_TRIANGLES:
1758 type = V_028B6C_TESS_TRIANGLE;
1759 break;
1760 case GL_QUADS:
1761 type = V_028B6C_TESS_QUAD;
1762 break;
1763 case GL_ISOLINES:
1764 type = V_028B6C_TESS_ISOLINE;
1765 break;
1766 }
1767
1768 switch (tes->info.tes.spacing) {
1769 case TESS_SPACING_EQUAL:
1770 partitioning = V_028B6C_PART_INTEGER;
1771 break;
1772 case TESS_SPACING_FRACTIONAL_ODD:
1773 partitioning = V_028B6C_PART_FRAC_ODD;
1774 break;
1775 case TESS_SPACING_FRACTIONAL_EVEN:
1776 partitioning = V_028B6C_PART_FRAC_EVEN;
1777 break;
1778 default:
1779 break;
1780 }
1781
1782 if (tes->info.tes.point_mode)
1783 topology = V_028B6C_OUTPUT_POINT;
1784 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1785 topology = V_028B6C_OUTPUT_LINE;
1786 else if (tes->info.tes.ccw)
1787 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1788 else
1789 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1790
1791 if (pipeline->device->has_distributed_tess) {
1792 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1793 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1794 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1795 else
1796 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1797 } else
1798 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1799
1800 tess->tf_param = S_028B6C_TYPE(type) |
1801 S_028B6C_PARTITIONING(partitioning) |
1802 S_028B6C_TOPOLOGY(topology) |
1803 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1804 }
1805
1806 static const struct radv_prim_vertex_count prim_size_table[] = {
1807 [V_008958_DI_PT_NONE] = {0, 0},
1808 [V_008958_DI_PT_POINTLIST] = {1, 1},
1809 [V_008958_DI_PT_LINELIST] = {2, 2},
1810 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1811 [V_008958_DI_PT_TRILIST] = {3, 3},
1812 [V_008958_DI_PT_TRIFAN] = {3, 1},
1813 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1814 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1815 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1816 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1817 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1818 [V_008958_DI_PT_RECTLIST] = {3, 3},
1819 [V_008958_DI_PT_LINELOOP] = {2, 1},
1820 [V_008958_DI_PT_POLYGON] = {3, 1},
1821 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1822 };
1823
1824 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1825 {
1826 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1827 unsigned cut_mode;
1828
1829 if (gs_max_vert_out <= 128) {
1830 cut_mode = V_028A40_GS_CUT_128;
1831 } else if (gs_max_vert_out <= 256) {
1832 cut_mode = V_028A40_GS_CUT_256;
1833 } else if (gs_max_vert_out <= 512) {
1834 cut_mode = V_028A40_GS_CUT_512;
1835 } else {
1836 assert(gs_max_vert_out <= 1024);
1837 cut_mode = V_028A40_GS_CUT_1024;
1838 }
1839
1840 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1841 S_028A40_CUT_MODE(cut_mode)|
1842 S_028A40_ES_WRITE_OPTIMIZE(1) |
1843 S_028A40_GS_WRITE_OPTIMIZE(1);
1844 }
1845
1846 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1847 {
1848 struct radv_shader_variant *vs;
1849 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1850
1851 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1852
1853 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1854 clip_dist_mask = outinfo->clip_dist_mask;
1855 cull_dist_mask = outinfo->cull_dist_mask;
1856 total_mask = clip_dist_mask | cull_dist_mask;
1857
1858 bool misc_vec_ena = outinfo->writes_pointsize ||
1859 outinfo->writes_layer ||
1860 outinfo->writes_viewport_index;
1861 pipeline->graphics.pa_cl_vs_out_cntl =
1862 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1863 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1864 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1865 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1866 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1867 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1868 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1869 cull_dist_mask << 8 |
1870 clip_dist_mask;
1871
1872 }
1873 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1874 {
1875 struct radv_shader_variant *ps, *vs;
1876 struct ac_vs_output_info *outinfo;
1877
1878 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1879 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1880
1881 outinfo = &vs->info.vs.outinfo;
1882
1883 unsigned ps_offset = 0;
1884 if (ps->info.fs.has_pcoord) {
1885 unsigned val;
1886 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1887 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1888 ps_offset++;
1889 }
1890
1891 if (ps->info.fs.prim_id_input && (outinfo->prim_id_output != 0xffffffff)) {
1892 unsigned vs_offset, flat_shade;
1893 unsigned val;
1894 vs_offset = outinfo->prim_id_output;
1895 flat_shade = true;
1896 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1897 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1898 ++ps_offset;
1899 }
1900
1901 if (ps->info.fs.layer_input && (outinfo->layer_output != 0xffffffff)) {
1902 unsigned vs_offset, flat_shade;
1903 unsigned val;
1904 vs_offset = outinfo->layer_output;
1905 flat_shade = true;
1906 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1907 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1908 ++ps_offset;
1909 }
1910
1911 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1912 unsigned vs_offset, flat_shade;
1913 unsigned val;
1914
1915 if (!(ps->info.fs.input_mask & (1u << i)))
1916 continue;
1917
1918 if (!(outinfo->export_mask & (1u << i))) {
1919 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1920 ++ps_offset;
1921 continue;
1922 }
1923
1924 vs_offset = util_bitcount(outinfo->export_mask & ((1u << i) - 1));
1925 if (outinfo->prim_id_output != 0xffffffff) {
1926 if (vs_offset >= outinfo->prim_id_output)
1927 vs_offset++;
1928 }
1929 if (outinfo->layer_output != 0xffffffff) {
1930 if (vs_offset >= outinfo->layer_output)
1931 vs_offset++;
1932 }
1933 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1934
1935 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1936 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1937 ++ps_offset;
1938 }
1939
1940 pipeline->graphics.ps_input_cntl_num = ps_offset;
1941 }
1942
1943 VkResult
1944 radv_pipeline_init(struct radv_pipeline *pipeline,
1945 struct radv_device *device,
1946 struct radv_pipeline_cache *cache,
1947 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1948 const struct radv_graphics_pipeline_create_info *extra,
1949 const VkAllocationCallbacks *alloc)
1950 {
1951 struct radv_shader_module fs_m = {0};
1952 VkResult result;
1953
1954 if (alloc == NULL)
1955 alloc = &device->alloc;
1956
1957 pipeline->device = device;
1958 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1959
1960 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1961 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1962 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1963 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1964 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1965 pStages[stage] = &pCreateInfo->pStages[i];
1966 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1967 }
1968
1969 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1970
1971 if (modules[MESA_SHADER_VERTEX]) {
1972 bool as_es = false;
1973 bool as_ls = false;
1974 if (modules[MESA_SHADER_TESS_CTRL])
1975 as_ls = true;
1976 else if (modules[MESA_SHADER_GEOMETRY])
1977 as_es = true;
1978 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
1979
1980 pipeline->shaders[MESA_SHADER_VERTEX] =
1981 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1982 pStages[MESA_SHADER_VERTEX]->pName,
1983 MESA_SHADER_VERTEX,
1984 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1985 pipeline->layout, &key);
1986
1987 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1988 }
1989
1990 if (modules[MESA_SHADER_GEOMETRY]) {
1991 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false);
1992
1993 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1994 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1995 pStages[MESA_SHADER_GEOMETRY]->pName,
1996 MESA_SHADER_GEOMETRY,
1997 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1998 pipeline->layout, &key);
1999
2000 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2001
2002 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2003 } else
2004 pipeline->graphics.vgt_gs_mode = 0;
2005
2006 if (modules[MESA_SHADER_TESS_EVAL]) {
2007 assert(modules[MESA_SHADER_TESS_CTRL]);
2008
2009 radv_tess_pipeline_compile(pipeline,
2010 cache,
2011 modules[MESA_SHADER_TESS_CTRL],
2012 modules[MESA_SHADER_TESS_EVAL],
2013 pStages[MESA_SHADER_TESS_CTRL]->pName,
2014 pStages[MESA_SHADER_TESS_EVAL]->pName,
2015 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2016 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2017 pipeline->layout,
2018 pCreateInfo->pTessellationState->patchControlPoints);
2019 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2020 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2021 }
2022
2023 if (!modules[MESA_SHADER_FRAGMENT]) {
2024 nir_builder fs_b;
2025 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2026 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
2027 fs_m.nir = fs_b.shader;
2028 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2029 }
2030
2031 if (modules[MESA_SHADER_FRAGMENT]) {
2032 union ac_shader_variant_key key;
2033 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2034 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2035
2036 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2037
2038 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2039 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2040 stage ? stage->pName : "main",
2041 MESA_SHADER_FRAGMENT,
2042 stage ? stage->pSpecializationInfo : NULL,
2043 pipeline->layout, &key);
2044 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2045 }
2046
2047 if (fs_m.nir)
2048 ralloc_free(fs_m.nir);
2049
2050 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2051 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2052 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2053 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2054 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2055
2056 if (radv_pipeline_has_gs(pipeline)) {
2057 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2058 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2059 } else {
2060 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2061 }
2062 if (extra && extra->use_rectlist) {
2063 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2064 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2065 pipeline->graphics.can_use_guardband = true;
2066 }
2067 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2068 /* prim vertex count will need TESS changes */
2069 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2070
2071 /* Ensure that some export memory is always allocated, for two reasons:
2072 *
2073 * 1) Correctness: The hardware ignores the EXEC mask if no export
2074 * memory is allocated, so KILL and alpha test do not work correctly
2075 * without this.
2076 * 2) Performance: Every shader needs at least a NULL export, even when
2077 * it writes no color/depth output. The NULL export instruction
2078 * stalls without this setting.
2079 *
2080 * Don't add this to CB_SHADER_MASK.
2081 */
2082 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2083 if (!pipeline->graphics.blend.spi_shader_col_format) {
2084 if (!ps->info.fs.writes_z &&
2085 !ps->info.fs.writes_stencil &&
2086 !ps->info.fs.writes_sample_mask)
2087 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2088 }
2089
2090 unsigned z_order;
2091 pipeline->graphics.db_shader_control = 0;
2092 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2093 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2094 else
2095 z_order = V_02880C_LATE_Z;
2096
2097 pipeline->graphics.db_shader_control =
2098 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2099 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2100 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2101 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2102 S_02880C_Z_ORDER(z_order) |
2103 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2104 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2105 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2106
2107 pipeline->graphics.shader_z_format =
2108 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2109 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2110 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2111 V_028710_SPI_SHADER_ZERO;
2112
2113 calculate_pa_cl_vs_out_cntl(pipeline);
2114 calculate_ps_inputs(pipeline);
2115
2116 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2117 if (pipeline->shaders[i]) {
2118 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2119 }
2120 }
2121
2122 uint32_t stages = 0;
2123 if (radv_pipeline_has_tess(pipeline)) {
2124 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2125 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2126
2127 if (radv_pipeline_has_gs(pipeline))
2128 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2129 S_028B54_GS_EN(1) |
2130 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2131 else
2132 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2133 } else if (radv_pipeline_has_gs(pipeline))
2134 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2135 S_028B54_GS_EN(1) |
2136 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2137 pipeline->graphics.vgt_shader_stages_en = stages;
2138
2139 if (radv_pipeline_has_gs(pipeline))
2140 calculate_gs_ring_sizes(pipeline);
2141
2142 if (radv_pipeline_has_tess(pipeline)) {
2143 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2144 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2145 pipeline->graphics.prim_vertex_count.incr = 1;
2146 }
2147 calculate_tess_state(pipeline, pCreateInfo);
2148 }
2149
2150 const VkPipelineVertexInputStateCreateInfo *vi_info =
2151 pCreateInfo->pVertexInputState;
2152 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2153 const VkVertexInputAttributeDescription *desc =
2154 &vi_info->pVertexAttributeDescriptions[i];
2155 unsigned loc = desc->location;
2156 const struct vk_format_description *format_desc;
2157 int first_non_void;
2158 uint32_t num_format, data_format;
2159 format_desc = vk_format_description(desc->format);
2160 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2161
2162 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2163 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2164
2165 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2166 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2167 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2168 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2169 S_008F0C_NUM_FORMAT(num_format) |
2170 S_008F0C_DATA_FORMAT(data_format);
2171 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2172 pipeline->va_offset[loc] = desc->offset;
2173 pipeline->va_binding[loc] = desc->binding;
2174 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2175 }
2176
2177 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2178 const VkVertexInputBindingDescription *desc =
2179 &vi_info->pVertexBindingDescriptions[i];
2180
2181 pipeline->binding_stride[desc->binding] = desc->stride;
2182 }
2183
2184 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2185 radv_dump_pipeline_stats(device, pipeline);
2186 }
2187
2188 result = radv_pipeline_scratch_init(device, pipeline);
2189 return result;
2190 }
2191
2192 VkResult
2193 radv_graphics_pipeline_create(
2194 VkDevice _device,
2195 VkPipelineCache _cache,
2196 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2197 const struct radv_graphics_pipeline_create_info *extra,
2198 const VkAllocationCallbacks *pAllocator,
2199 VkPipeline *pPipeline)
2200 {
2201 RADV_FROM_HANDLE(radv_device, device, _device);
2202 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2203 struct radv_pipeline *pipeline;
2204 VkResult result;
2205
2206 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2207 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2208 if (pipeline == NULL)
2209 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2210
2211 memset(pipeline, 0, sizeof(*pipeline));
2212 result = radv_pipeline_init(pipeline, device, cache,
2213 pCreateInfo, extra, pAllocator);
2214 if (result != VK_SUCCESS) {
2215 radv_pipeline_destroy(device, pipeline, pAllocator);
2216 return result;
2217 }
2218
2219 *pPipeline = radv_pipeline_to_handle(pipeline);
2220
2221 return VK_SUCCESS;
2222 }
2223
2224 VkResult radv_CreateGraphicsPipelines(
2225 VkDevice _device,
2226 VkPipelineCache pipelineCache,
2227 uint32_t count,
2228 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2229 const VkAllocationCallbacks* pAllocator,
2230 VkPipeline* pPipelines)
2231 {
2232 VkResult result = VK_SUCCESS;
2233 unsigned i = 0;
2234
2235 for (; i < count; i++) {
2236 VkResult r;
2237 r = radv_graphics_pipeline_create(_device,
2238 pipelineCache,
2239 &pCreateInfos[i],
2240 NULL, pAllocator, &pPipelines[i]);
2241 if (r != VK_SUCCESS) {
2242 result = r;
2243 pPipelines[i] = VK_NULL_HANDLE;
2244 }
2245 }
2246
2247 return result;
2248 }
2249
2250 static VkResult radv_compute_pipeline_create(
2251 VkDevice _device,
2252 VkPipelineCache _cache,
2253 const VkComputePipelineCreateInfo* pCreateInfo,
2254 const VkAllocationCallbacks* pAllocator,
2255 VkPipeline* pPipeline)
2256 {
2257 RADV_FROM_HANDLE(radv_device, device, _device);
2258 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2259 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2260 struct radv_pipeline *pipeline;
2261 VkResult result;
2262
2263 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2265 if (pipeline == NULL)
2266 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2267
2268 memset(pipeline, 0, sizeof(*pipeline));
2269 pipeline->device = device;
2270 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2271
2272 pipeline->shaders[MESA_SHADER_COMPUTE] =
2273 radv_pipeline_compile(pipeline, cache, module,
2274 pCreateInfo->stage.pName,
2275 MESA_SHADER_COMPUTE,
2276 pCreateInfo->stage.pSpecializationInfo,
2277 pipeline->layout, NULL);
2278
2279
2280 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2281 result = radv_pipeline_scratch_init(device, pipeline);
2282 if (result != VK_SUCCESS) {
2283 radv_pipeline_destroy(device, pipeline, pAllocator);
2284 return result;
2285 }
2286
2287 *pPipeline = radv_pipeline_to_handle(pipeline);
2288
2289 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2290 radv_dump_pipeline_stats(device, pipeline);
2291 }
2292 return VK_SUCCESS;
2293 }
2294 VkResult radv_CreateComputePipelines(
2295 VkDevice _device,
2296 VkPipelineCache pipelineCache,
2297 uint32_t count,
2298 const VkComputePipelineCreateInfo* pCreateInfos,
2299 const VkAllocationCallbacks* pAllocator,
2300 VkPipeline* pPipelines)
2301 {
2302 VkResult result = VK_SUCCESS;
2303
2304 unsigned i = 0;
2305 for (; i < count; i++) {
2306 VkResult r;
2307 r = radv_compute_pipeline_create(_device, pipelineCache,
2308 &pCreateInfos[i],
2309 pAllocator, &pPipelines[i]);
2310 if (r != VK_SUCCESS) {
2311 result = r;
2312 pPipelines[i] = VK_NULL_HANDLE;
2313 }
2314 }
2315
2316 return result;
2317 }