2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
33 #include "radv_shader.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50 #include "main/menums.h"
52 struct radv_blend_state
{
53 uint32_t blend_enable_4bit
;
54 uint32_t need_src_alpha
;
56 uint32_t cb_color_control
;
57 uint32_t cb_target_mask
;
58 uint32_t cb_target_enabled_4bit
;
59 uint32_t sx_mrt_blend_opt
[8];
60 uint32_t cb_blend_control
[8];
62 uint32_t spi_shader_col_format
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 struct radv_gs_state
{
93 uint32_t vgt_gs_onchip_cntl
;
94 uint32_t vgt_gs_max_prims_per_subgroup
;
95 uint32_t vgt_esgs_ring_itemsize
;
99 struct radv_ngg_state
{
100 uint16_t ngg_emit_size
; /* in dwords */
101 uint32_t hw_max_esverts
;
102 uint32_t max_gsprims
;
103 uint32_t max_out_verts
;
104 uint32_t prim_amp_factor
;
105 uint32_t vgt_esgs_ring_itemsize
;
106 bool max_vert_out_per_gs_instance
;
109 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
111 struct radv_shader_variant
*variant
= NULL
;
112 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
113 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
114 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
115 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
116 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
117 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
120 return variant
->info
.is_ngg
;
123 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
125 if (!radv_pipeline_has_gs(pipeline
))
128 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
129 * On GFX10, it might be required in rare cases if it's not possible to
132 if (radv_pipeline_has_ngg(pipeline
))
135 assert(pipeline
->gs_copy_shader
);
140 radv_pipeline_destroy(struct radv_device
*device
,
141 struct radv_pipeline
*pipeline
,
142 const VkAllocationCallbacks
* allocator
)
144 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
145 if (pipeline
->shaders
[i
])
146 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
148 if (pipeline
->gs_copy_shader
)
149 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
152 free(pipeline
->cs
.buf
);
153 vk_free2(&device
->alloc
, allocator
, pipeline
);
156 void radv_DestroyPipeline(
158 VkPipeline _pipeline
,
159 const VkAllocationCallbacks
* pAllocator
)
161 RADV_FROM_HANDLE(radv_device
, device
, _device
);
162 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
167 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
170 static uint32_t get_hash_flags(struct radv_device
*device
)
172 uint32_t hash_flags
= 0;
174 if (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
)
175 hash_flags
|= RADV_HASH_SHADER_UNSAFE_MATH
;
176 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
177 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
178 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
179 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
184 radv_pipeline_scratch_init(struct radv_device
*device
,
185 struct radv_pipeline
*pipeline
)
187 unsigned scratch_bytes_per_wave
= 0;
188 unsigned max_waves
= 0;
189 unsigned min_waves
= 1;
191 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
192 if (pipeline
->shaders
[i
]) {
193 unsigned max_stage_waves
= device
->scratch_waves
;
195 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
196 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
198 max_stage_waves
= MIN2(max_stage_waves
,
199 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
200 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
201 max_waves
= MAX2(max_waves
, max_stage_waves
);
205 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
206 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
207 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
208 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
209 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
212 if (scratch_bytes_per_wave
)
213 max_waves
= MIN2(max_waves
, 0xffffffffu
/ scratch_bytes_per_wave
);
215 if (scratch_bytes_per_wave
&& max_waves
< min_waves
) {
216 /* Not really true at this moment, but will be true on first
217 * execution. Avoid having hanging shaders. */
218 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
220 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
221 pipeline
->max_waves
= max_waves
;
225 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
228 case VK_LOGIC_OP_CLEAR
:
229 return V_028808_ROP3_CLEAR
;
230 case VK_LOGIC_OP_AND
:
231 return V_028808_ROP3_AND
;
232 case VK_LOGIC_OP_AND_REVERSE
:
233 return V_028808_ROP3_AND_REVERSE
;
234 case VK_LOGIC_OP_COPY
:
235 return V_028808_ROP3_COPY
;
236 case VK_LOGIC_OP_AND_INVERTED
:
237 return V_028808_ROP3_AND_INVERTED
;
238 case VK_LOGIC_OP_NO_OP
:
239 return V_028808_ROP3_NO_OP
;
240 case VK_LOGIC_OP_XOR
:
241 return V_028808_ROP3_XOR
;
243 return V_028808_ROP3_OR
;
244 case VK_LOGIC_OP_NOR
:
245 return V_028808_ROP3_NOR
;
246 case VK_LOGIC_OP_EQUIVALENT
:
247 return V_028808_ROP3_EQUIVALENT
;
248 case VK_LOGIC_OP_INVERT
:
249 return V_028808_ROP3_INVERT
;
250 case VK_LOGIC_OP_OR_REVERSE
:
251 return V_028808_ROP3_OR_REVERSE
;
252 case VK_LOGIC_OP_COPY_INVERTED
:
253 return V_028808_ROP3_COPY_INVERTED
;
254 case VK_LOGIC_OP_OR_INVERTED
:
255 return V_028808_ROP3_OR_INVERTED
;
256 case VK_LOGIC_OP_NAND
:
257 return V_028808_ROP3_NAND
;
258 case VK_LOGIC_OP_SET
:
259 return V_028808_ROP3_SET
;
261 unreachable("Unhandled logic op");
266 static uint32_t si_translate_blend_function(VkBlendOp op
)
269 case VK_BLEND_OP_ADD
:
270 return V_028780_COMB_DST_PLUS_SRC
;
271 case VK_BLEND_OP_SUBTRACT
:
272 return V_028780_COMB_SRC_MINUS_DST
;
273 case VK_BLEND_OP_REVERSE_SUBTRACT
:
274 return V_028780_COMB_DST_MINUS_SRC
;
275 case VK_BLEND_OP_MIN
:
276 return V_028780_COMB_MIN_DST_SRC
;
277 case VK_BLEND_OP_MAX
:
278 return V_028780_COMB_MAX_DST_SRC
;
284 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
287 case VK_BLEND_FACTOR_ZERO
:
288 return V_028780_BLEND_ZERO
;
289 case VK_BLEND_FACTOR_ONE
:
290 return V_028780_BLEND_ONE
;
291 case VK_BLEND_FACTOR_SRC_COLOR
:
292 return V_028780_BLEND_SRC_COLOR
;
293 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
294 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
295 case VK_BLEND_FACTOR_DST_COLOR
:
296 return V_028780_BLEND_DST_COLOR
;
297 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
298 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
299 case VK_BLEND_FACTOR_SRC_ALPHA
:
300 return V_028780_BLEND_SRC_ALPHA
;
301 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
302 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
303 case VK_BLEND_FACTOR_DST_ALPHA
:
304 return V_028780_BLEND_DST_ALPHA
;
305 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
306 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
307 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
308 return V_028780_BLEND_CONSTANT_COLOR
;
309 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
311 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
312 return V_028780_BLEND_CONSTANT_ALPHA
;
313 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
315 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
316 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
317 case VK_BLEND_FACTOR_SRC1_COLOR
:
318 return V_028780_BLEND_SRC1_COLOR
;
319 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
320 return V_028780_BLEND_INV_SRC1_COLOR
;
321 case VK_BLEND_FACTOR_SRC1_ALPHA
:
322 return V_028780_BLEND_SRC1_ALPHA
;
323 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
324 return V_028780_BLEND_INV_SRC1_ALPHA
;
330 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
333 case VK_BLEND_OP_ADD
:
334 return V_028760_OPT_COMB_ADD
;
335 case VK_BLEND_OP_SUBTRACT
:
336 return V_028760_OPT_COMB_SUBTRACT
;
337 case VK_BLEND_OP_REVERSE_SUBTRACT
:
338 return V_028760_OPT_COMB_REVSUBTRACT
;
339 case VK_BLEND_OP_MIN
:
340 return V_028760_OPT_COMB_MIN
;
341 case VK_BLEND_OP_MAX
:
342 return V_028760_OPT_COMB_MAX
;
344 return V_028760_OPT_COMB_BLEND_DISABLED
;
348 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
351 case VK_BLEND_FACTOR_ZERO
:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
353 case VK_BLEND_FACTOR_ONE
:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
355 case VK_BLEND_FACTOR_SRC_COLOR
:
356 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
358 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
359 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
361 case VK_BLEND_FACTOR_SRC_ALPHA
:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
365 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
378 unsigned *dst_factor
, unsigned expected_dst
,
379 unsigned replacement_src
)
381 if (*src_factor
== expected_dst
&&
382 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
383 *src_factor
= VK_BLEND_FACTOR_ZERO
;
384 *dst_factor
= replacement_src
;
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func
== VK_BLEND_OP_SUBTRACT
)
388 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
389 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
390 *func
= VK_BLEND_OP_SUBTRACT
;
394 static bool si_blend_factor_uses_dst(unsigned factor
)
396 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
397 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
398 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
399 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
400 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
403 static bool is_dual_src(VkBlendFactor factor
)
406 case VK_BLEND_FACTOR_SRC1_COLOR
:
407 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
408 case VK_BLEND_FACTOR_SRC1_ALPHA
:
409 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
416 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
418 bool blend_need_alpha
)
420 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
421 unsigned format
, ntype
, swap
;
423 /* Alpha is needed for alpha-to-coverage.
424 * Blending may be with or without alpha.
426 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
427 unsigned alpha
= 0; /* exports alpha, but may not support blending */
428 unsigned blend
= 0; /* supports blending, but may not export alpha */
429 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
431 format
= radv_translate_colorformat(vk_format
);
432 ntype
= radv_translate_color_numformat(vk_format
, desc
,
433 vk_format_get_first_non_void_channel(vk_format
));
434 swap
= radv_translate_colorswap(vk_format
, false);
436 /* Choose the SPI color formats. These are required values for Stoney/RB+.
437 * Other chips have multiple choices, though they are not necessarily better.
440 case V_028C70_COLOR_5_6_5
:
441 case V_028C70_COLOR_1_5_5_5
:
442 case V_028C70_COLOR_5_5_5_1
:
443 case V_028C70_COLOR_4_4_4_4
:
444 case V_028C70_COLOR_10_11_11
:
445 case V_028C70_COLOR_11_11_10
:
446 case V_028C70_COLOR_8
:
447 case V_028C70_COLOR_8_8
:
448 case V_028C70_COLOR_8_8_8_8
:
449 case V_028C70_COLOR_10_10_10_2
:
450 case V_028C70_COLOR_2_10_10_10
:
451 if (ntype
== V_028C70_NUMBER_UINT
)
452 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
453 else if (ntype
== V_028C70_NUMBER_SINT
)
454 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
456 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
459 case V_028C70_COLOR_16
:
460 case V_028C70_COLOR_16_16
:
461 case V_028C70_COLOR_16_16_16_16
:
462 if (ntype
== V_028C70_NUMBER_UNORM
||
463 ntype
== V_028C70_NUMBER_SNORM
) {
464 /* UNORM16 and SNORM16 don't support blending */
465 if (ntype
== V_028C70_NUMBER_UNORM
)
466 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
468 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
470 /* Use 32 bits per channel for blending. */
471 if (format
== V_028C70_COLOR_16
) {
472 if (swap
== V_028C70_SWAP_STD
) { /* R */
473 blend
= V_028714_SPI_SHADER_32_R
;
474 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
475 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
476 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
479 } else if (format
== V_028C70_COLOR_16_16
) {
480 if (swap
== V_028C70_SWAP_STD
) { /* RG */
481 blend
= V_028714_SPI_SHADER_32_GR
;
482 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
483 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
484 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
487 } else /* 16_16_16_16 */
488 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
489 } else if (ntype
== V_028C70_NUMBER_UINT
)
490 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
491 else if (ntype
== V_028C70_NUMBER_SINT
)
492 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
493 else if (ntype
== V_028C70_NUMBER_FLOAT
)
494 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
499 case V_028C70_COLOR_32
:
500 if (swap
== V_028C70_SWAP_STD
) { /* R */
501 blend
= normal
= V_028714_SPI_SHADER_32_R
;
502 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
503 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
504 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
509 case V_028C70_COLOR_32_32
:
510 if (swap
== V_028C70_SWAP_STD
) { /* RG */
511 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
512 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
513 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
514 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
519 case V_028C70_COLOR_32_32_32_32
:
520 case V_028C70_COLOR_8_24
:
521 case V_028C70_COLOR_24_8
:
522 case V_028C70_COLOR_X24_8_32_FLOAT
:
523 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
527 unreachable("unhandled blend format");
530 if (blend_enable
&& blend_need_alpha
)
532 else if(blend_need_alpha
)
534 else if(blend_enable
)
541 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
542 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
543 struct radv_blend_state
*blend
)
545 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
546 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
547 unsigned col_format
= 0;
548 unsigned num_targets
;
550 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
553 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
554 cf
= V_028714_SPI_SHADER_ZERO
;
556 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
558 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
560 cf
= si_choose_spi_color_format(attachment
->format
,
562 blend
->need_src_alpha
& (1 << i
));
565 col_format
|= cf
<< (4 * i
);
568 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
569 /* When a subpass doesn't have any color attachments, write the
570 * alpha channel of MRT0 when alpha coverage is enabled because
571 * the depth attachment needs it.
573 col_format
|= V_028714_SPI_SHADER_32_AR
;
576 /* If the i-th target format is set, all previous target formats must
577 * be non-zero to avoid hangs.
579 num_targets
= (util_last_bit(col_format
) + 3) / 4;
580 for (unsigned i
= 0; i
< num_targets
; i
++) {
581 if (!(col_format
& (0xf << (i
* 4)))) {
582 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
586 /* The output for dual source blending should have the same format as
589 if (blend
->mrt0_is_dual_src
)
590 col_format
|= (col_format
& 0xf) << 4;
592 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
593 blend
->spi_shader_col_format
= col_format
;
597 format_is_int8(VkFormat format
)
599 const struct vk_format_description
*desc
= vk_format_description(format
);
600 int channel
= vk_format_get_first_non_void_channel(format
);
602 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
603 desc
->channel
[channel
].size
== 8;
607 format_is_int10(VkFormat format
)
609 const struct vk_format_description
*desc
= vk_format_description(format
);
611 if (desc
->nr_channels
!= 4)
613 for (unsigned i
= 0; i
< 4; i
++) {
614 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
621 * Ordered so that for each i,
622 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
624 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
625 VK_FORMAT_R32_SFLOAT
,
626 VK_FORMAT_R32G32_SFLOAT
,
627 VK_FORMAT_R8G8B8A8_UNORM
,
628 VK_FORMAT_R16G16B16A16_UNORM
,
629 VK_FORMAT_R16G16B16A16_SNORM
,
630 VK_FORMAT_R16G16B16A16_UINT
,
631 VK_FORMAT_R16G16B16A16_SINT
,
632 VK_FORMAT_R32G32B32A32_SFLOAT
,
633 VK_FORMAT_R8G8B8A8_UINT
,
634 VK_FORMAT_R8G8B8A8_SINT
,
635 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
636 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
639 unsigned radv_format_meta_fs_key(VkFormat format
)
641 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
643 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
644 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
645 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
647 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
648 bool is_int8
= format_is_int8(format
);
649 bool is_int10
= format_is_int10(format
);
651 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
655 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
656 unsigned *is_int8
, unsigned *is_int10
)
658 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
659 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
663 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
664 struct radv_render_pass_attachment
*attachment
;
666 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
669 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
671 if (format_is_int8(attachment
->format
))
673 if (format_is_int10(attachment
->format
))
679 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
680 VkBlendOp op
, VkBlendFactor src
,
681 VkBlendFactor dst
, unsigned chanmask
)
683 /* Src factor is allowed when it does not depend on Dst. */
684 static const uint32_t src_allowed
=
685 (1u << VK_BLEND_FACTOR_ONE
) |
686 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
687 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
688 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
689 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
690 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
691 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
692 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
693 (1u << VK_BLEND_FACTOR_ZERO
) |
694 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
695 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
696 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
697 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
698 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
699 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
701 if (dst
== VK_BLEND_FACTOR_ONE
&&
702 (src_allowed
& (1u << src
))) {
703 /* Addition is commutative, but floating point addition isn't
704 * associative: subtle changes can be introduced via different
705 * rounding. Be conservative, only enable for min and max.
707 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
708 blend
->commutative_4bit
|= chanmask
;
712 static struct radv_blend_state
713 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
714 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
715 const struct radv_graphics_pipeline_create_info
*extra
)
717 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
718 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
719 struct radv_blend_state blend
= {0};
720 unsigned mode
= V_028808_CB_NORMAL
;
726 if (extra
&& extra
->custom_blend_mode
) {
727 blend
.single_cb_enable
= true;
728 mode
= extra
->custom_blend_mode
;
730 blend
.cb_color_control
= 0;
731 if (vkblend
->logicOpEnable
)
732 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
734 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
736 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
737 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
738 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
739 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
740 S_028B70_OFFSET_ROUND(1);
742 if (vkms
&& vkms
->alphaToCoverageEnable
) {
743 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
744 blend
.need_src_alpha
|= 0x1;
747 blend
.cb_target_mask
= 0;
748 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
749 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
750 unsigned blend_cntl
= 0;
751 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
752 VkBlendOp eqRGB
= att
->colorBlendOp
;
753 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
754 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
755 VkBlendOp eqA
= att
->alphaBlendOp
;
756 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
757 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
759 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
761 if (!att
->colorWriteMask
)
764 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
765 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
766 if (!att
->blendEnable
) {
767 blend
.cb_blend_control
[i
] = blend_cntl
;
771 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
773 blend
.mrt0_is_dual_src
= true;
775 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
776 srcRGB
= VK_BLEND_FACTOR_ONE
;
777 dstRGB
= VK_BLEND_FACTOR_ONE
;
779 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
780 srcA
= VK_BLEND_FACTOR_ONE
;
781 dstA
= VK_BLEND_FACTOR_ONE
;
784 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
786 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
789 /* Blending optimizations for RB+.
790 * These transformations don't change the behavior.
792 * First, get rid of DST in the blend factors:
793 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
795 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
796 VK_BLEND_FACTOR_DST_COLOR
,
797 VK_BLEND_FACTOR_SRC_COLOR
);
799 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
800 VK_BLEND_FACTOR_DST_COLOR
,
801 VK_BLEND_FACTOR_SRC_COLOR
);
803 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
804 VK_BLEND_FACTOR_DST_ALPHA
,
805 VK_BLEND_FACTOR_SRC_ALPHA
);
807 /* Look up the ideal settings from tables. */
808 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
809 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
810 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
811 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
813 /* Handle interdependencies. */
814 if (si_blend_factor_uses_dst(srcRGB
))
815 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
816 if (si_blend_factor_uses_dst(srcA
))
817 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
819 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
820 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
821 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
822 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
823 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
825 /* Set the final value. */
826 blend
.sx_mrt_blend_opt
[i
] =
827 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
828 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
829 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
830 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
831 S_028760_ALPHA_DST_OPT(dstA_opt
) |
832 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
833 blend_cntl
|= S_028780_ENABLE(1);
835 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
836 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
837 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
838 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
839 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
840 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
841 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
842 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
844 blend
.cb_blend_control
[i
] = blend_cntl
;
846 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
848 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
849 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
850 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
851 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
852 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
853 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
854 blend
.need_src_alpha
|= 1 << i
;
856 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
857 blend
.cb_blend_control
[i
] = 0;
858 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
861 if (pipeline
->device
->physical_device
->has_rbplus
) {
862 /* Disable RB+ blend optimizations for dual source blending. */
863 if (blend
.mrt0_is_dual_src
) {
864 for (i
= 0; i
< 8; i
++) {
865 blend
.sx_mrt_blend_opt
[i
] =
866 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
867 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
871 /* RB+ doesn't work with dual source blending, logic op and
874 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
875 mode
== V_028808_CB_RESOLVE
)
876 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
879 if (blend
.cb_target_mask
)
880 blend
.cb_color_control
|= S_028808_MODE(mode
);
882 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
884 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
888 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
891 case VK_STENCIL_OP_KEEP
:
892 return V_02842C_STENCIL_KEEP
;
893 case VK_STENCIL_OP_ZERO
:
894 return V_02842C_STENCIL_ZERO
;
895 case VK_STENCIL_OP_REPLACE
:
896 return V_02842C_STENCIL_REPLACE_TEST
;
897 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
898 return V_02842C_STENCIL_ADD_CLAMP
;
899 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
900 return V_02842C_STENCIL_SUB_CLAMP
;
901 case VK_STENCIL_OP_INVERT
:
902 return V_02842C_STENCIL_INVERT
;
903 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
904 return V_02842C_STENCIL_ADD_WRAP
;
905 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
906 return V_02842C_STENCIL_SUB_WRAP
;
912 static uint32_t si_translate_fill(VkPolygonMode func
)
915 case VK_POLYGON_MODE_FILL
:
916 return V_028814_X_DRAW_TRIANGLES
;
917 case VK_POLYGON_MODE_LINE
:
918 return V_028814_X_DRAW_LINES
;
919 case VK_POLYGON_MODE_POINT
:
920 return V_028814_X_DRAW_POINTS
;
923 return V_028814_X_DRAW_POINTS
;
927 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
929 uint32_t num_samples
= vkms
->rasterizationSamples
;
930 uint32_t ps_iter_samples
= 1;
932 if (vkms
->sampleShadingEnable
) {
933 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
934 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
936 return ps_iter_samples
;
940 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
942 return pCreateInfo
->depthTestEnable
&&
943 pCreateInfo
->depthWriteEnable
&&
944 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
948 radv_writes_stencil(const VkStencilOpState
*state
)
950 return state
->writeMask
&&
951 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
952 state
->passOp
!= VK_STENCIL_OP_KEEP
||
953 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
957 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
959 return pCreateInfo
->stencilTestEnable
&&
960 (radv_writes_stencil(&pCreateInfo
->front
) ||
961 radv_writes_stencil(&pCreateInfo
->back
));
965 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
967 return radv_is_depth_write_enabled(pCreateInfo
) ||
968 radv_is_stencil_write_enabled(pCreateInfo
);
972 radv_order_invariant_stencil_op(VkStencilOp op
)
974 /* REPLACE is normally order invariant, except when the stencil
975 * reference value is written by the fragment shader. Tracking this
976 * interaction does not seem worth the effort, so be conservative.
978 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
979 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
980 op
!= VK_STENCIL_OP_REPLACE
;
984 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
986 /* Compute whether, assuming Z writes are disabled, this stencil state
987 * is order invariant in the sense that the set of passing fragments as
988 * well as the final stencil buffer result does not depend on the order
991 return !state
->writeMask
||
992 /* The following assumes that Z writes are disabled. */
993 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
994 radv_order_invariant_stencil_op(state
->passOp
) &&
995 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
996 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
997 radv_order_invariant_stencil_op(state
->failOp
));
1001 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1002 struct radv_blend_state
*blend
,
1003 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1005 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1006 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1007 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1009 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1012 /* Be conservative if a logic operation is enabled with color buffers. */
1013 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
1016 /* Default depth/stencil invariance when no attachment is bound. */
1017 struct radv_dsa_order_invariance dsa_order_invariant
= {
1018 .zs
= true, .pass_set
= true
1021 if (pCreateInfo
->pDepthStencilState
&&
1022 subpass
->depth_stencil_attachment
) {
1023 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
1024 pCreateInfo
->pDepthStencilState
;
1025 struct radv_render_pass_attachment
*attachment
=
1026 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1027 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1028 struct radv_dsa_order_invariance order_invariance
[2];
1029 struct radv_shader_variant
*ps
=
1030 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1032 /* Compute depth/stencil order invariance in order to know if
1033 * it's safe to enable out-of-order.
1035 bool zfunc_is_ordered
=
1036 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1037 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1038 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1039 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1040 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1042 bool nozwrite_and_order_invariant_stencil
=
1043 !radv_is_ds_write_enabled(vkds
) ||
1044 (!radv_is_depth_write_enabled(vkds
) &&
1045 radv_order_invariant_stencil_state(&vkds
->front
) &&
1046 radv_order_invariant_stencil_state(&vkds
->back
));
1048 order_invariance
[1].zs
=
1049 nozwrite_and_order_invariant_stencil
||
1050 (!radv_is_stencil_write_enabled(vkds
) &&
1052 order_invariance
[0].zs
=
1053 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1055 order_invariance
[1].pass_set
=
1056 nozwrite_and_order_invariant_stencil
||
1057 (!radv_is_stencil_write_enabled(vkds
) &&
1058 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1059 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1060 order_invariance
[0].pass_set
=
1061 !radv_is_depth_write_enabled(vkds
) ||
1062 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1063 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1065 dsa_order_invariant
= order_invariance
[has_stencil
];
1066 if (!dsa_order_invariant
.zs
)
1069 /* The set of PS invocations is always order invariant,
1070 * except when early Z/S tests are requested.
1073 ps
->info
.info
.ps
.writes_memory
&&
1074 ps
->info
.fs
.early_fragment_test
&&
1075 !dsa_order_invariant
.pass_set
)
1078 /* Determine if out-of-order rasterization should be disabled
1079 * when occlusion queries are used.
1081 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1082 !dsa_order_invariant
.pass_set
;
1085 /* No color buffers are enabled for writing. */
1089 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1092 /* Only commutative blending. */
1093 if (blendmask
& ~blend
->commutative_4bit
)
1096 if (!dsa_order_invariant
.pass_set
)
1100 if (colormask
& ~blendmask
)
1107 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1108 struct radv_blend_state
*blend
,
1109 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1111 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1112 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1113 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1114 bool out_of_order_rast
= false;
1115 int ps_iter_samples
= 1;
1116 uint32_t mask
= 0xffff;
1119 ms
->num_samples
= vkms
->rasterizationSamples
;
1121 ms
->num_samples
= 1;
1124 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1125 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.force_persample
) {
1126 ps_iter_samples
= ms
->num_samples
;
1129 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1130 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1131 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1132 /* Out-of-order rasterization is explicitly enabled by the
1135 out_of_order_rast
= true;
1137 /* Determine if the driver can enable out-of-order
1138 * rasterization internally.
1141 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1144 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1145 ms
->pa_sc_aa_config
= 0;
1146 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1147 S_028804_INCOHERENT_EQAA_READS(1) |
1148 S_028804_INTERPOLATE_COMP_Z(1) |
1149 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1150 ms
->pa_sc_mode_cntl_1
=
1151 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1152 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1153 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1154 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1156 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1157 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1158 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1159 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1160 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1161 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1162 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1163 S_028A48_VPORT_SCISSOR_ENABLE(1);
1165 if (ms
->num_samples
> 1) {
1166 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1167 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1168 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1169 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1170 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1171 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1172 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1173 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1174 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1175 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1176 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1177 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1178 if (ps_iter_samples
> 1)
1179 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1182 if (vkms
&& vkms
->pSampleMask
) {
1183 mask
= vkms
->pSampleMask
[0] & 0xffff;
1186 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1187 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1191 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1194 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1205 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1208 unreachable("unhandled primitive type");
1213 si_translate_prim(enum VkPrimitiveTopology topology
)
1216 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1217 return V_008958_DI_PT_POINTLIST
;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1219 return V_008958_DI_PT_LINELIST
;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1221 return V_008958_DI_PT_LINESTRIP
;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1223 return V_008958_DI_PT_TRILIST
;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1225 return V_008958_DI_PT_TRISTRIP
;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1227 return V_008958_DI_PT_TRIFAN
;
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1229 return V_008958_DI_PT_LINELIST_ADJ
;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1231 return V_008958_DI_PT_LINESTRIP_ADJ
;
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1233 return V_008958_DI_PT_TRILIST_ADJ
;
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1235 return V_008958_DI_PT_TRISTRIP_ADJ
;
1236 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1237 return V_008958_DI_PT_PATCH
;
1245 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1248 case 0: /* GL_POINTS */
1249 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1250 case 1: /* GL_LINES */
1251 case 3: /* GL_LINE_STRIP */
1252 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1253 case 0x8E7A: /* GL_ISOLINES */
1254 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1256 case 4: /* GL_TRIANGLES */
1257 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1258 case 5: /* GL_TRIANGLE_STRIP */
1259 case 7: /* GL_QUADS */
1260 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1268 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1271 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1272 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1273 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1278 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1284 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1291 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1294 case VK_DYNAMIC_STATE_VIEWPORT
:
1295 return RADV_DYNAMIC_VIEWPORT
;
1296 case VK_DYNAMIC_STATE_SCISSOR
:
1297 return RADV_DYNAMIC_SCISSOR
;
1298 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1299 return RADV_DYNAMIC_LINE_WIDTH
;
1300 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1301 return RADV_DYNAMIC_DEPTH_BIAS
;
1302 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1303 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1304 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1305 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1306 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1307 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1308 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1309 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1310 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1311 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1312 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1313 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1314 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1315 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1317 unreachable("Unhandled dynamic state");
1321 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1323 uint32_t states
= RADV_DYNAMIC_ALL
;
1325 /* If rasterization is disabled we do not care about any of the dynamic states,
1326 * since they are all rasterization related only. */
1327 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1330 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1331 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1333 if (!pCreateInfo
->pDepthStencilState
||
1334 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1335 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1337 if (!pCreateInfo
->pDepthStencilState
||
1338 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1339 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1340 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1341 RADV_DYNAMIC_STENCIL_REFERENCE
);
1343 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1344 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1346 if (!pCreateInfo
->pMultisampleState
||
1347 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1348 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1349 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1351 /* TODO: blend constants & line width. */
1358 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1359 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1361 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1362 uint32_t states
= needed_states
;
1363 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1364 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1366 pipeline
->dynamic_state
= default_dynamic_state
;
1367 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1369 if (pCreateInfo
->pDynamicState
) {
1370 /* Remove all of the states that are marked as dynamic */
1371 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1372 for (uint32_t s
= 0; s
< count
; s
++)
1373 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1376 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1378 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1379 assert(pCreateInfo
->pViewportState
);
1381 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1382 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1383 typed_memcpy(dynamic
->viewport
.viewports
,
1384 pCreateInfo
->pViewportState
->pViewports
,
1385 pCreateInfo
->pViewportState
->viewportCount
);
1389 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1390 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1391 if (states
& RADV_DYNAMIC_SCISSOR
) {
1392 typed_memcpy(dynamic
->scissor
.scissors
,
1393 pCreateInfo
->pViewportState
->pScissors
,
1394 pCreateInfo
->pViewportState
->scissorCount
);
1398 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1399 assert(pCreateInfo
->pRasterizationState
);
1400 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1403 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1404 assert(pCreateInfo
->pRasterizationState
);
1405 dynamic
->depth_bias
.bias
=
1406 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1407 dynamic
->depth_bias
.clamp
=
1408 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1409 dynamic
->depth_bias
.slope
=
1410 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1413 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1415 * pColorBlendState is [...] NULL if the pipeline has rasterization
1416 * disabled or if the subpass of the render pass the pipeline is
1417 * created against does not use any color attachments.
1419 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1420 assert(pCreateInfo
->pColorBlendState
);
1421 typed_memcpy(dynamic
->blend_constants
,
1422 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1425 /* If there is no depthstencil attachment, then don't read
1426 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1427 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1428 * no need to override the depthstencil defaults in
1429 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1431 * Section 9.2 of the Vulkan 1.0.15 spec says:
1433 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1434 * disabled or if the subpass of the render pass the pipeline is created
1435 * against does not use a depth/stencil attachment.
1437 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1438 assert(pCreateInfo
->pDepthStencilState
);
1440 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1441 dynamic
->depth_bounds
.min
=
1442 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1443 dynamic
->depth_bounds
.max
=
1444 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1447 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1448 dynamic
->stencil_compare_mask
.front
=
1449 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1450 dynamic
->stencil_compare_mask
.back
=
1451 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1454 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1455 dynamic
->stencil_write_mask
.front
=
1456 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1457 dynamic
->stencil_write_mask
.back
=
1458 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1461 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1462 dynamic
->stencil_reference
.front
=
1463 pCreateInfo
->pDepthStencilState
->front
.reference
;
1464 dynamic
->stencil_reference
.back
=
1465 pCreateInfo
->pDepthStencilState
->back
.reference
;
1469 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1470 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1471 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1472 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1473 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1474 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1475 discard_rectangle_info
->pDiscardRectangles
,
1476 discard_rectangle_info
->discardRectangleCount
);
1480 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1481 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1482 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1483 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1484 /* If sampleLocationsEnable is VK_FALSE, the default sample
1485 * locations are used and the values specified in
1486 * sampleLocationsInfo are ignored.
1488 if (sample_location_info
->sampleLocationsEnable
) {
1489 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1490 &sample_location_info
->sampleLocationsInfo
;
1492 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1494 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1495 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1496 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1497 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1498 pSampleLocationsInfo
->pSampleLocations
,
1499 pSampleLocationsInfo
->sampleLocationsCount
);
1503 pipeline
->dynamic_state
.mask
= states
;
1506 static struct radv_gs_state
1507 calculate_gs_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1508 const struct radv_pipeline
*pipeline
)
1510 struct radv_gs_state gs
= {0};
1511 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1512 struct radv_es_output_info
*es_info
;
1513 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1514 es_info
= radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1516 es_info
= radv_pipeline_has_tess(pipeline
) ?
1517 &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.es_info
:
1518 &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.es_info
;
1520 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1521 bool uses_adjacency
;
1522 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1523 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1525 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1527 uses_adjacency
= true;
1530 uses_adjacency
= false;
1534 /* All these are in dwords: */
1535 /* We can't allow using the whole LDS, because GS waves compete with
1536 * other shader stages for LDS space. */
1537 const unsigned max_lds_size
= 8 * 1024;
1538 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1539 unsigned esgs_lds_size
;
1541 /* All these are per subgroup: */
1542 const unsigned max_out_prims
= 32 * 1024;
1543 const unsigned max_es_verts
= 255;
1544 const unsigned ideal_gs_prims
= 64;
1545 unsigned max_gs_prims
, gs_prims
;
1546 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1548 if (uses_adjacency
|| gs_num_invocations
> 1)
1549 max_gs_prims
= 127 / gs_num_invocations
;
1553 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1554 * Make sure we don't go over the maximum value.
1556 if (gs_info
->gs
.vertices_out
> 0) {
1557 max_gs_prims
= MIN2(max_gs_prims
,
1559 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1561 assert(max_gs_prims
> 0);
1563 /* If the primitive has adjacency, halve the number of vertices
1564 * that will be reused in multiple primitives.
1566 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1568 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1569 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1571 /* Compute ESGS LDS size based on the worst case number of ES vertices
1572 * needed to create the target number of GS prims per subgroup.
1574 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1576 /* If total LDS usage is too big, refactor partitions based on ratio
1577 * of ESGS item sizes.
1579 if (esgs_lds_size
> max_lds_size
) {
1580 /* Our target GS Prims Per Subgroup was too large. Calculate
1581 * the maximum number of GS Prims Per Subgroup that will fit
1582 * into LDS, capped by the maximum that the hardware can support.
1584 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1586 assert(gs_prims
> 0);
1587 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1590 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1591 assert(esgs_lds_size
<= max_lds_size
);
1594 /* Now calculate remaining ESGS information. */
1596 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1598 es_verts
= max_es_verts
;
1600 /* Vertices for adjacency primitives are not always reused, so restore
1601 * it for ES_VERTS_PER_SUBGRP.
1603 min_es_verts
= gs_info
->gs
.vertices_in
;
1605 /* For normal primitives, the VGT only checks if they are past the ES
1606 * verts per subgroup after allocating a full GS primitive and if they
1607 * are, kick off a new subgroup. But if those additional ES verts are
1608 * unique (e.g. not reused) we need to make sure there is enough LDS
1609 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1611 es_verts
-= min_es_verts
- 1;
1613 uint32_t es_verts_per_subgroup
= es_verts
;
1614 uint32_t gs_prims_per_subgroup
= gs_prims
;
1615 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1616 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1617 gs
.lds_size
= align(esgs_lds_size
, 128) / 128;
1618 gs
.vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1619 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1620 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1621 gs
.vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1622 gs
.vgt_esgs_ring_itemsize
= esgs_itemsize
;
1623 assert(max_prims_per_subgroup
<= max_out_prims
);
1628 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1629 unsigned min_verts_per_prim
, bool use_adjacency
)
1631 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1634 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1638 radv_get_num_input_vertices(struct radv_pipeline
*pipeline
)
1640 if (radv_pipeline_has_gs(pipeline
)) {
1641 struct radv_shader_variant
*gs
=
1642 radv_get_shader(pipeline
, MESA_SHADER_GEOMETRY
);
1644 return gs
->info
.gs
.vertices_in
;
1647 if (radv_pipeline_has_tess(pipeline
)) {
1648 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1650 if (tes
->info
.tes
.point_mode
)
1652 if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1660 static struct radv_ngg_state
1661 calculate_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1662 struct radv_pipeline
*pipeline
)
1664 struct radv_ngg_state ngg
= {0};
1665 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1666 struct radv_es_output_info
*es_info
=
1667 radv_pipeline_has_tess(pipeline
) ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1668 unsigned gs_type
= radv_pipeline_has_gs(pipeline
) ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1669 unsigned max_verts_per_prim
= radv_get_num_input_vertices(pipeline
);
1670 unsigned min_verts_per_prim
=
1671 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1672 unsigned gs_num_invocations
= radv_pipeline_has_gs(pipeline
) ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1673 bool uses_adjacency
;
1674 switch(pCreateInfo
->pInputAssemblyState
->topology
) {
1675 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1676 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1677 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1678 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1679 uses_adjacency
= true;
1682 uses_adjacency
= false;
1686 /* All these are in dwords: */
1687 /* We can't allow using the whole LDS, because GS waves compete with
1688 * other shader stages for LDS space.
1690 * Streamout can increase the ESGS buffer size later on, so be more
1691 * conservative with streamout and use 4K dwords. This may be suboptimal.
1693 * Otherwise, use the limit of 7K dwords. The reason is that we need
1694 * to leave some headroom for the max_esverts increase at the end.
1696 * TODO: We should really take the shader's internal LDS use into
1697 * account. The linker will fail if the size is greater than
1700 const unsigned max_lds_size
= (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1701 const unsigned target_lds_size
= max_lds_size
;
1702 unsigned esvert_lds_size
= 0;
1703 unsigned gsprim_lds_size
= 0;
1705 /* All these are per subgroup: */
1706 bool max_vert_out_per_gs_instance
= false;
1707 unsigned max_esverts_base
= 256;
1708 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1710 /* Hardware has the following non-natural restrictions on the value
1711 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1713 * - at most 252 for any line input primitive type
1714 * - at most 251 for any quad input primitive type
1715 * - at most 251 for triangle strips with adjacency (this happens to
1716 * be the natural limit for triangle *lists* with adjacency)
1718 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1720 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1721 unsigned max_out_verts_per_gsprim
=
1722 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1724 if (max_out_verts_per_gsprim
<= 256) {
1725 if (max_out_verts_per_gsprim
) {
1726 max_gsprims_base
= MIN2(max_gsprims_base
,
1727 256 / max_out_verts_per_gsprim
);
1730 /* Use special multi-cycling mode in which each GS
1731 * instance gets its own subgroup. Does not work with
1733 max_vert_out_per_gs_instance
= true;
1734 max_gsprims_base
= 1;
1735 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1738 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1739 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1741 /* TODO: This needs to be adjusted once LDS use for compaction
1742 * after culling is implemented. */
1744 if (es_info->info.so.num_outputs)
1745 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1749 unsigned max_gsprims
= max_gsprims_base
;
1750 unsigned max_esverts
= max_esverts_base
;
1752 if (esvert_lds_size
)
1753 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1754 if (gsprim_lds_size
)
1755 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1757 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1758 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1759 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1761 if (esvert_lds_size
|| gsprim_lds_size
) {
1762 /* Now that we have a rough proportionality between esverts
1763 * and gsprims based on the primitive type, scale both of them
1764 * down simultaneously based on required LDS space.
1766 * We could be smarter about this if we knew how much vertex
1769 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1770 max_gsprims
* gsprim_lds_size
;
1771 if (lds_total
> target_lds_size
) {
1772 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1773 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1775 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1776 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1777 min_verts_per_prim
, uses_adjacency
);
1778 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1782 /* Round up towards full wave sizes for better ALU utilization. */
1783 if (!max_vert_out_per_gs_instance
) {
1784 const unsigned wavesize
= 64;
1785 unsigned orig_max_esverts
;
1786 unsigned orig_max_gsprims
;
1788 orig_max_esverts
= max_esverts
;
1789 orig_max_gsprims
= max_gsprims
;
1791 max_esverts
= align(max_esverts
, wavesize
);
1792 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1793 if (esvert_lds_size
)
1794 max_esverts
= MIN2(max_esverts
,
1795 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1797 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1799 max_gsprims
= align(max_gsprims
, wavesize
);
1800 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1801 if (gsprim_lds_size
)
1802 max_gsprims
= MIN2(max_gsprims
,
1803 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1805 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1806 min_verts_per_prim
, uses_adjacency
);
1807 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1808 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1811 /* Hardware restriction: minimum value of max_esverts */
1812 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1814 unsigned max_out_vertices
=
1815 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1816 gs_type
== MESA_SHADER_GEOMETRY
?
1817 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1819 assert(max_out_vertices
<= 256);
1821 unsigned prim_amp_factor
= 1;
1822 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1823 /* Number of output primitives per GS input primitive after
1825 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1828 /* The GE only checks against the maximum number of ES verts after
1829 * allocating a full GS primitive. So we need to ensure that whenever
1830 * this check passes, there is enough space for a full primitive without
1833 ngg
.hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1834 ngg
.max_gsprims
= max_gsprims
;
1835 ngg
.max_out_verts
= max_out_vertices
;
1836 ngg
.prim_amp_factor
= prim_amp_factor
;
1837 ngg
.max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1838 ngg
.ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1840 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1841 ngg
.vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1843 ngg
.vgt_esgs_ring_itemsize
= 1;
1846 pipeline
->graphics
.esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1848 assert(ngg
.hw_max_esverts
>= 24); /* HW limitation */
1854 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
, const struct radv_gs_state
*gs
)
1856 struct radv_device
*device
= pipeline
->device
;
1857 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1858 unsigned wave_size
= 64;
1859 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1860 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1861 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1863 unsigned gs_vertex_reuse
=
1864 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1865 unsigned alignment
= 256 * num_se
;
1866 /* The maximum size is 63.999 MB per SE. */
1867 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1868 struct radv_shader_variant_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1870 /* Calculate the minimum size. */
1871 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1872 wave_size
, alignment
);
1873 /* These are recommended sizes, not minimum sizes. */
1874 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1875 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1876 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1877 gs_info
->gs
.max_gsvs_emit_size
;
1879 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1880 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1881 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1883 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1884 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1886 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1889 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1892 /* If tessellation is all offchip and on-chip GS isn't used, this
1893 * workaround is not needed.
1897 /* SPI barrier management bug:
1898 * Make sure we have at least 4k of LDS in use to avoid the bug.
1899 * It applies to workgroup sizes of more than one wavefront.
1901 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1902 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1903 *lds_size
= MAX2(*lds_size
, 8);
1906 struct radv_shader_variant
*
1907 radv_get_shader(struct radv_pipeline
*pipeline
,
1908 gl_shader_stage stage
)
1910 if (stage
== MESA_SHADER_VERTEX
) {
1911 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1912 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1913 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1914 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1915 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1916 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1917 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1918 if (!radv_pipeline_has_tess(pipeline
))
1920 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1921 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1922 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1923 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1925 return pipeline
->shaders
[stage
];
1928 static struct radv_tessellation_state
1929 calculate_tess_state(struct radv_pipeline
*pipeline
,
1930 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1932 unsigned num_tcs_input_cp
;
1933 unsigned num_tcs_output_cp
;
1935 unsigned num_patches
;
1936 struct radv_tessellation_state tess
= {0};
1938 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1939 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1940 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1942 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1944 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1945 assert(lds_size
<= 65536);
1946 lds_size
= align(lds_size
, 512) / 512;
1948 assert(lds_size
<= 32768);
1949 lds_size
= align(lds_size
, 256) / 256;
1951 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1953 tess
.lds_size
= lds_size
;
1955 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1956 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1957 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1958 tess
.num_patches
= num_patches
;
1960 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1961 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1963 switch (tes
->info
.tes
.primitive_mode
) {
1965 type
= V_028B6C_TESS_TRIANGLE
;
1968 type
= V_028B6C_TESS_QUAD
;
1971 type
= V_028B6C_TESS_ISOLINE
;
1975 switch (tes
->info
.tes
.spacing
) {
1976 case TESS_SPACING_EQUAL
:
1977 partitioning
= V_028B6C_PART_INTEGER
;
1979 case TESS_SPACING_FRACTIONAL_ODD
:
1980 partitioning
= V_028B6C_PART_FRAC_ODD
;
1982 case TESS_SPACING_FRACTIONAL_EVEN
:
1983 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1989 bool ccw
= tes
->info
.tes
.ccw
;
1990 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1991 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1992 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1994 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1997 if (tes
->info
.tes
.point_mode
)
1998 topology
= V_028B6C_OUTPUT_POINT
;
1999 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2000 topology
= V_028B6C_OUTPUT_LINE
;
2002 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2004 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2006 if (pipeline
->device
->has_distributed_tess
) {
2007 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2008 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2009 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2011 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2013 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2015 tess
.tf_param
= S_028B6C_TYPE(type
) |
2016 S_028B6C_PARTITIONING(partitioning
) |
2017 S_028B6C_TOPOLOGY(topology
) |
2018 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2023 static const struct radv_prim_vertex_count prim_size_table
[] = {
2024 [V_008958_DI_PT_NONE
] = {0, 0},
2025 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2026 [V_008958_DI_PT_LINELIST
] = {2, 2},
2027 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2028 [V_008958_DI_PT_TRILIST
] = {3, 3},
2029 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2030 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2031 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2032 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2033 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2034 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2035 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2036 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2037 [V_008958_DI_PT_POLYGON
] = {3, 1},
2038 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2041 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2043 if (radv_pipeline_has_gs(pipeline
))
2044 if (radv_pipeline_has_ngg(pipeline
))
2045 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2047 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2048 else if (radv_pipeline_has_tess(pipeline
))
2049 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2051 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2055 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2057 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2058 int shader_count
= 0;
2060 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2061 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2063 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2064 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2066 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2067 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2069 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2070 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2072 if(shaders
[MESA_SHADER_VERTEX
]) {
2073 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2076 if (shader_count
> 1) {
2077 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2078 unsigned last
= ordered_shaders
[0]->info
.stage
;
2080 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2081 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2082 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2084 for (int i
= 0; i
< shader_count
; ++i
) {
2085 nir_variable_mode mask
= 0;
2087 if (ordered_shaders
[i
]->info
.stage
!= first
)
2088 mask
= mask
| nir_var_shader_in
;
2090 if (ordered_shaders
[i
]->info
.stage
!= last
)
2091 mask
= mask
| nir_var_shader_out
;
2093 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2094 radv_optimize_nir(ordered_shaders
[i
], false, false);
2098 for (int i
= 1; i
< shader_count
; ++i
) {
2099 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2100 ordered_shaders
[i
- 1]);
2102 if (nir_link_opt_varyings(ordered_shaders
[i
],
2103 ordered_shaders
[i
- 1]))
2104 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2106 nir_remove_dead_variables(ordered_shaders
[i
],
2107 nir_var_shader_out
);
2108 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2111 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2112 ordered_shaders
[i
- 1]);
2114 nir_compact_varyings(ordered_shaders
[i
],
2115 ordered_shaders
[i
- 1], true);
2118 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2119 ac_lower_indirect_derefs(ordered_shaders
[i
],
2120 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2122 radv_optimize_nir(ordered_shaders
[i
], false, false);
2124 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2125 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2126 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2128 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2134 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2135 uint32_t attrib_binding
)
2137 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2138 const VkVertexInputBindingDescription
*input_binding
=
2139 &input_state
->pVertexBindingDescriptions
[i
];
2141 if (input_binding
->binding
== attrib_binding
)
2142 return input_binding
->stride
;
2148 static struct radv_pipeline_key
2149 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2150 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2151 const struct radv_blend_state
*blend
,
2152 bool has_view_index
)
2154 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2155 pCreateInfo
->pVertexInputState
;
2156 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2157 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2159 struct radv_pipeline_key key
;
2160 memset(&key
, 0, sizeof(key
));
2162 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2163 key
.optimisations_disabled
= 1;
2165 key
.has_multiview_view_index
= has_view_index
;
2167 uint32_t binding_input_rate
= 0;
2168 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2169 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2170 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2171 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2172 binding_input_rate
|= 1u << binding
;
2173 instance_rate_divisors
[binding
] = 1;
2176 if (divisor_state
) {
2177 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2178 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2179 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2183 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2184 const VkVertexInputAttributeDescription
*desc
=
2185 &input_state
->pVertexAttributeDescriptions
[i
];
2186 const struct vk_format_description
*format_desc
;
2187 unsigned location
= desc
->location
;
2188 unsigned binding
= desc
->binding
;
2189 unsigned num_format
, data_format
;
2192 if (binding_input_rate
& (1u << binding
)) {
2193 key
.instance_rate_inputs
|= 1u << location
;
2194 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2197 format_desc
= vk_format_description(desc
->format
);
2198 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2200 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2201 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2203 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2204 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2205 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2206 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2208 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2209 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2210 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2213 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2214 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2215 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2217 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2218 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2219 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2221 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2222 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2223 adjust
= RADV_ALPHA_ADJUST_SINT
;
2229 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2232 switch (desc
->format
) {
2233 case VK_FORMAT_B8G8R8A8_UNORM
:
2234 case VK_FORMAT_B8G8R8A8_SNORM
:
2235 case VK_FORMAT_B8G8R8A8_USCALED
:
2236 case VK_FORMAT_B8G8R8A8_SSCALED
:
2237 case VK_FORMAT_B8G8R8A8_UINT
:
2238 case VK_FORMAT_B8G8R8A8_SINT
:
2239 case VK_FORMAT_B8G8R8A8_SRGB
:
2240 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2241 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2242 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2243 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2244 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2245 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2246 key
.vertex_post_shuffle
|= 1 << location
;
2253 if (pCreateInfo
->pTessellationState
)
2254 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2257 if (pCreateInfo
->pMultisampleState
&&
2258 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
2259 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
2260 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
2261 key
.num_samples
= num_samples
;
2262 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2265 key
.col_format
= blend
->spi_shader_col_format
;
2266 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2267 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2273 radv_fill_shader_keys(struct radv_device
*device
,
2274 struct radv_shader_variant_key
*keys
,
2275 const struct radv_pipeline_key
*key
,
2278 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2279 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2280 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2281 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2282 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2283 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2284 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2285 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2286 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2289 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2290 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2291 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2292 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2293 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2295 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2298 if (nir
[MESA_SHADER_GEOMETRY
]) {
2299 if (nir
[MESA_SHADER_TESS_CTRL
])
2300 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2302 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2305 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
2306 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)) {
2307 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2308 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2310 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2313 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2314 nir
[MESA_SHADER_GEOMETRY
] &&
2315 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2316 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2317 /* Fallback to the legacy path if tessellation is
2318 * enabled with extreme geometry because
2319 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2322 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2326 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2327 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2329 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2330 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2331 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2332 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2333 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2337 merge_tess_info(struct shader_info
*tes_info
,
2338 const struct shader_info
*tcs_info
)
2340 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2342 * "PointMode. Controls generation of points rather than triangles
2343 * or lines. This functionality defaults to disabled, and is
2344 * enabled if either shader stage includes the execution mode.
2346 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2347 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2348 * and OutputVertices, it says:
2350 * "One mode must be set in at least one of the tessellation
2353 * So, the fields can be set in either the TCS or TES, but they must
2354 * agree if set in both. Our backend looks at TES, so bitwise-or in
2355 * the values from the TCS.
2357 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2358 tes_info
->tess
.tcs_vertices_out
== 0 ||
2359 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2360 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2362 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2363 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2364 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2365 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2367 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2368 tes_info
->tess
.primitive_mode
== 0 ||
2369 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2370 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2371 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2372 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2376 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2381 if (ext
->pPipelineCreationFeedback
) {
2382 ext
->pPipelineCreationFeedback
->flags
= 0;
2383 ext
->pPipelineCreationFeedback
->duration
= 0;
2386 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2387 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2388 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2393 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2398 feedback
->duration
-= radv_get_current_time();
2399 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2403 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2408 feedback
->duration
+= radv_get_current_time();
2409 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2410 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2414 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2415 struct radv_device
*device
,
2416 struct radv_pipeline_cache
*cache
,
2417 const struct radv_pipeline_key
*key
,
2418 const VkPipelineShaderStageCreateInfo
**pStages
,
2419 const VkPipelineCreateFlags flags
,
2420 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2421 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2423 struct radv_shader_module fs_m
= {0};
2424 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2425 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2426 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2427 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2428 unsigned char hash
[20], gs_copy_hash
[20];
2430 radv_start_feedback(pipeline_feedback
);
2432 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2434 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2435 if (modules
[i
]->nir
)
2436 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2437 strlen(modules
[i
]->nir
->info
.name
),
2440 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2444 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2445 memcpy(gs_copy_hash
, hash
, 20);
2446 gs_copy_hash
[0] ^= 1;
2448 bool found_in_application_cache
= true;
2449 if (modules
[MESA_SHADER_GEOMETRY
]) {
2450 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2451 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2452 &found_in_application_cache
);
2453 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2456 if (radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2457 &found_in_application_cache
) &&
2458 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2459 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2463 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2465 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2466 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2467 fs_m
.nir
= fs_b
.shader
;
2468 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2471 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2472 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2477 radv_start_feedback(stage_feedbacks
[i
]);
2479 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2480 stage
? stage
->pName
: "main", i
,
2481 stage
? stage
->pSpecializationInfo
: NULL
,
2482 flags
, pipeline
->layout
);
2484 /* We don't want to alter meta shaders IR directly so clone it
2487 if (nir
[i
]->info
.name
) {
2488 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2491 radv_stop_feedback(stage_feedbacks
[i
], false);
2494 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2495 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2496 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2499 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2500 radv_link_shaders(pipeline
, nir
);
2502 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2504 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2505 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2506 nir_lower_non_uniform_ubo_access
|
2507 nir_lower_non_uniform_ssbo_access
|
2508 nir_lower_non_uniform_texture_access
|
2509 nir_lower_non_uniform_image_access
);
2512 if (radv_can_dump_shader(device
, modules
[i
], false))
2513 nir_print_shader(nir
[i
], stderr
);
2516 radv_fill_shader_keys(device
, keys
, key
, nir
);
2518 if (nir
[MESA_SHADER_FRAGMENT
]) {
2519 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2520 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2522 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2523 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2524 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2525 &binaries
[MESA_SHADER_FRAGMENT
]);
2527 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2530 /* TODO: These are no longer used as keys we should refactor this */
2531 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2532 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2533 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2534 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2535 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2536 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.num_input_clips_culls
;
2537 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2538 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
;
2539 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2540 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.layer_input
;
2541 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2542 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.num_input_clips_culls
;
2545 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2546 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2547 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2548 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2549 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2551 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2553 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2555 &key
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2557 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2559 modules
[MESA_SHADER_VERTEX
] = NULL
;
2560 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2561 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2564 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2565 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2566 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2567 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2569 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2571 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2573 &keys
[pre_stage
] , &binaries
[MESA_SHADER_GEOMETRY
]);
2575 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2577 modules
[pre_stage
] = NULL
;
2580 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2581 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2582 if (i
== MESA_SHADER_TESS_CTRL
) {
2583 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.info
.vs
.ls_outputs_written
);
2585 if (i
== MESA_SHADER_TESS_EVAL
) {
2586 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2587 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.tcs
.outputs_written
);
2590 radv_start_feedback(stage_feedbacks
[i
]);
2592 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2594 keys
+ i
, &binaries
[i
]);
2596 radv_stop_feedback(stage_feedbacks
[i
], false);
2600 if(modules
[MESA_SHADER_GEOMETRY
]) {
2601 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2602 if (!pipeline
->gs_copy_shader
) {
2603 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2604 device
, nir
[MESA_SHADER_GEOMETRY
], &gs_copy_binary
,
2605 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2608 if (pipeline
->gs_copy_shader
) {
2609 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2610 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2612 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2613 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2615 radv_pipeline_cache_insert_shaders(device
, cache
,
2620 free(gs_copy_binary
);
2623 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2626 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2629 if (!pipeline
->device
->keep_shader_info
)
2630 ralloc_free(nir
[i
]);
2632 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2633 radv_shader_dump_stats(device
,
2634 pipeline
->shaders
[i
],
2640 ralloc_free(fs_m
.nir
);
2642 radv_stop_feedback(pipeline_feedback
, false);
2646 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2647 gl_shader_stage stage
, enum chip_class chip_class
)
2649 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2650 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2651 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2654 case MESA_SHADER_FRAGMENT
:
2655 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2656 case MESA_SHADER_VERTEX
:
2658 if (chip_class
>= GFX10
) {
2659 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2660 } else if (chip_class
== GFX9
) {
2661 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2663 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2669 if (chip_class
>= GFX10
) {
2670 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2672 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2677 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2679 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2680 case MESA_SHADER_GEOMETRY
:
2681 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2682 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2683 case MESA_SHADER_COMPUTE
:
2684 return R_00B900_COMPUTE_USER_DATA_0
;
2685 case MESA_SHADER_TESS_CTRL
:
2686 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2687 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2688 case MESA_SHADER_TESS_EVAL
:
2690 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2691 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2692 } else if (has_ngg
) {
2693 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2695 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2698 unreachable("unknown shader");
2702 struct radv_bin_size_entry
{
2708 radv_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2710 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2714 /* One shader engine */
2720 { UINT_MAX
, { 0, 0}},
2723 /* Two shader engines */
2729 { UINT_MAX
, { 0, 0}},
2732 /* Four shader engines */
2737 { UINT_MAX
, { 0, 0}},
2743 /* One shader engine */
2749 { UINT_MAX
, { 0, 0}},
2752 /* Two shader engines */
2758 { UINT_MAX
, { 0, 0}},
2761 /* Four shader engines */
2768 { UINT_MAX
, { 0, 0}},
2774 /* One shader engine */
2781 { UINT_MAX
, { 0, 0}},
2784 /* Two shader engines */
2792 { UINT_MAX
, { 0, 0}},
2795 /* Four shader engines */
2803 { UINT_MAX
, { 0, 0}},
2807 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
2811 // One shader engine
2818 { UINT_MAX
, { 0, 0}},
2821 // Two shader engines
2829 { UINT_MAX
, { 0, 0}},
2832 // Four shader engines
2840 { UINT_MAX
, { 0, 0}},
2846 // One shader engine
2854 { UINT_MAX
, { 0, 0}},
2857 // Two shader engines
2866 { UINT_MAX
, { 0, 0}},
2869 // Four shader engines
2878 { UINT_MAX
, { 0, 0}},
2884 // One shader engine
2892 { UINT_MAX
, { 0, 0}},
2895 // Two shader engines
2904 { UINT_MAX
, { 0, 0}},
2907 // Four shader engines
2915 { UINT_MAX
, { 0, 0}},
2920 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2921 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2922 VkExtent2D extent
= {512, 512};
2924 unsigned log_num_rb_per_se
=
2925 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
2926 pipeline
->device
->physical_device
->rad_info
.max_se
);
2927 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
2929 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
2930 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
2931 unsigned effective_samples
= total_samples
;
2932 unsigned color_bytes_per_pixel
= 0;
2934 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2936 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2937 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2940 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
2943 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
2944 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
2947 /* MSAA images typically don't use all samples all the time. */
2948 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
2949 effective_samples
= 2;
2950 color_bytes_per_pixel
*= effective_samples
;
2953 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
2954 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
2957 extent
= color_entry
->extent
;
2959 if (subpass
->depth_stencil_attachment
) {
2960 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
2962 /* Coefficients taken from AMDVLK */
2963 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
2964 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
2965 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
2967 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
2968 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
2971 extent
.width
= MIN2(extent
.width
, ds_entry
->extent
.width
);
2972 extent
.height
= MIN2(extent
.height
, ds_entry
->extent
.height
);
2979 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
2980 struct radv_pipeline
*pipeline
,
2981 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2983 uint32_t pa_sc_binner_cntl_0
=
2984 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
2985 S_028C44_DISABLE_START_OF_PRIM(1);
2986 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
2988 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2989 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2990 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2991 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
2992 unsigned min_bytes_per_pixel
= 0;
2995 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2996 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
2999 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3002 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3003 unsigned bytes
= vk_format_get_blocksize(format
);
3004 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3005 min_bytes_per_pixel
= bytes
;
3009 pa_sc_binner_cntl_0
=
3010 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3011 S_028C44_BIN_SIZE_X(0) |
3012 S_028C44_BIN_SIZE_Y(0) |
3013 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3014 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3015 S_028C44_DISABLE_START_OF_PRIM(1);
3018 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3019 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3023 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3024 struct radv_pipeline
*pipeline
,
3025 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3027 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3030 VkExtent2D bin_size
= radv_compute_bin_size(pipeline
, pCreateInfo
);
3032 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3033 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3034 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3035 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3037 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3038 context_states_per_bin
= 1;
3039 persistent_states_per_bin
= 1;
3040 fpovs_per_batch
= 63;
3042 context_states_per_bin
= 6;
3043 persistent_states_per_bin
= 32;
3044 fpovs_per_batch
= 63;
3047 const uint32_t pa_sc_binner_cntl_0
=
3048 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3049 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3050 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3051 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3052 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3053 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3054 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3055 S_028C44_DISABLE_START_OF_PRIM(1) |
3056 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3057 S_028C44_OPTIMAL_BIN_SELECTION(1);
3059 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3061 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3062 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3064 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3069 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3070 struct radv_pipeline
*pipeline
,
3071 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3072 const struct radv_graphics_pipeline_create_info
*extra
)
3074 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
3075 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3076 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3077 struct radv_render_pass_attachment
*attachment
= NULL
;
3078 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3079 uint32_t db_render_control
= 0, db_render_override2
= 0;
3080 uint32_t db_render_override
= 0;
3082 if (subpass
->depth_stencil_attachment
)
3083 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3085 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3086 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3088 if (vkds
&& has_depth_attachment
) {
3089 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3090 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3091 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3092 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3094 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3095 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3098 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3099 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3100 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3101 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3102 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3103 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3105 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3106 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3107 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3108 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3111 if (attachment
&& extra
) {
3112 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3113 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3115 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3116 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3117 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3118 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3119 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3122 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3123 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3125 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
) {
3126 /* From VK_EXT_depth_range_unrestricted spec:
3128 * "The behavior described in Primitive Clipping still applies.
3129 * If depth clamping is disabled the depth values are still
3130 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3131 * depth clamping is enabled the above equation is ignored and
3132 * the depth values are instead clamped to the VkViewport
3133 * minDepth and maxDepth values, which in the case of this
3134 * extension can be outside of the 0.0 to 1.0 range."
3136 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3139 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3140 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3142 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3143 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3144 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3148 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3149 struct radv_pipeline
*pipeline
,
3150 const struct radv_blend_state
*blend
)
3152 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3153 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3155 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3156 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3158 if (pipeline
->device
->physical_device
->has_rbplus
) {
3160 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3161 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3164 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3166 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3167 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3169 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3170 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3173 static const VkConservativeRasterizationModeEXT
3174 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3176 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3177 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3179 if (!conservative_raster
)
3180 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3181 return conservative_raster
->conservativeRasterizationMode
;
3185 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3186 struct radv_pipeline
*pipeline
,
3187 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3189 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3190 const VkConservativeRasterizationModeEXT mode
=
3191 radv_get_conservative_raster_mode(vkraster
);
3192 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3193 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3195 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3196 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3197 if (depth_clip_state
) {
3198 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3201 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3202 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3203 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3204 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3205 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3206 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3208 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3209 S_0286D4_FLAT_SHADE_ENA(1) |
3210 S_0286D4_PNT_SPRITE_ENA(1) |
3211 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3212 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3213 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3214 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3215 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3217 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3218 S_028BE4_PIX_CENTER(1) | // TODO verify
3219 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3220 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3222 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3223 S_028814_FACE(vkraster
->frontFace
) |
3224 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3225 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3226 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3227 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3228 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3229 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3230 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3231 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3233 /* Conservative rasterization. */
3234 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3235 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3237 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3238 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3239 S_028804_OVERRASTERIZATION_AMOUNT(4);
3241 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3242 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3243 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3245 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3246 pa_sc_conservative_rast
|=
3247 S_028C4C_OVER_RAST_ENABLE(1) |
3248 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3249 S_028C4C_UNDER_RAST_ENABLE(0) |
3250 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3251 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3253 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3254 pa_sc_conservative_rast
|=
3255 S_028C4C_OVER_RAST_ENABLE(0) |
3256 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3257 S_028C4C_UNDER_RAST_ENABLE(1) |
3258 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3259 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3263 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3264 pa_sc_conservative_rast
);
3269 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3270 struct radv_pipeline
*pipeline
)
3272 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3274 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3275 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3276 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3278 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3279 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3281 /* The exclusion bits can be set to improve rasterization efficiency
3282 * if no sample lies on the pixel boundary (-8 sample offset). It's
3283 * currently always TRUE because the driver doesn't support 16 samples.
3285 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3286 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3287 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3288 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3292 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3293 struct radv_pipeline
*pipeline
)
3295 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3296 const struct radv_shader_variant
*vs
=
3297 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3298 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3299 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3300 unsigned vgt_primitiveid_en
= 0;
3301 uint32_t vgt_gs_mode
= 0;
3303 if (radv_pipeline_has_ngg(pipeline
))
3306 if (radv_pipeline_has_gs(pipeline
)) {
3307 const struct radv_shader_variant
*gs
=
3308 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3310 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3311 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3312 } else if (outinfo
->export_prim_id
|| vs
->info
.info
.uses_prim_id
) {
3313 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3314 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3317 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3318 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3322 gfx10_set_ge_pc_alloc(struct radeon_cmdbuf
*ctx_cs
,
3323 struct radv_pipeline
*pipeline
,
3326 struct radeon_info
*info
= &pipeline
->device
->physical_device
->rad_info
;
3328 radeon_set_uconfig_reg(ctx_cs
, R_030980_GE_PC_ALLOC
,
3329 S_030980_OVERSUB_EN(1) |
3330 S_030980_NUM_PC_LINES((culling
? 256 : 128) * info
->max_se
- 1));
3334 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3335 struct radeon_cmdbuf
*cs
,
3336 struct radv_pipeline
*pipeline
,
3337 struct radv_shader_variant
*shader
)
3339 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3341 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3342 radeon_emit(cs
, va
>> 8);
3343 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3344 radeon_emit(cs
, shader
->config
.rsrc1
);
3345 radeon_emit(cs
, shader
->config
.rsrc2
);
3347 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3348 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3349 clip_dist_mask
= outinfo
->clip_dist_mask
;
3350 cull_dist_mask
= outinfo
->cull_dist_mask
;
3351 total_mask
= clip_dist_mask
| cull_dist_mask
;
3352 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3353 outinfo
->writes_layer
||
3354 outinfo
->writes_viewport_index
;
3355 unsigned spi_vs_out_config
, nparams
;
3357 /* VS is required to export at least one param. */
3358 nparams
= MAX2(outinfo
->param_exports
, 1);
3359 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3361 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3362 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3365 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3367 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3368 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3369 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3370 V_02870C_SPI_SHADER_4COMP
:
3371 V_02870C_SPI_SHADER_NONE
) |
3372 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3373 V_02870C_SPI_SHADER_4COMP
:
3374 V_02870C_SPI_SHADER_NONE
) |
3375 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3376 V_02870C_SPI_SHADER_4COMP
:
3377 V_02870C_SPI_SHADER_NONE
));
3379 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3380 S_028818_VTX_W0_FMT(1) |
3381 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3382 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3383 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3385 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3386 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3387 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3388 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3389 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3390 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3391 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3392 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3393 cull_dist_mask
<< 8 |
3396 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3397 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3398 outinfo
->writes_viewport_index
);
3400 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
3401 gfx10_set_ge_pc_alloc(ctx_cs
, pipeline
, false);
3405 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3406 struct radv_pipeline
*pipeline
,
3407 struct radv_shader_variant
*shader
)
3409 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3411 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3412 radeon_emit(cs
, va
>> 8);
3413 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3414 radeon_emit(cs
, shader
->config
.rsrc1
);
3415 radeon_emit(cs
, shader
->config
.rsrc2
);
3419 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3420 struct radv_pipeline
*pipeline
,
3421 struct radv_shader_variant
*shader
,
3422 const struct radv_tessellation_state
*tess
)
3424 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3425 uint32_t rsrc2
= shader
->config
.rsrc2
;
3427 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3428 radeon_emit(cs
, va
>> 8);
3429 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3431 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3432 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3433 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3434 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3436 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3437 radeon_emit(cs
, shader
->config
.rsrc1
);
3438 radeon_emit(cs
, rsrc2
);
3442 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3443 struct radeon_cmdbuf
*cs
,
3444 struct radv_pipeline
*pipeline
,
3445 struct radv_shader_variant
*shader
,
3446 const struct radv_ngg_state
*ngg_state
)
3448 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3449 gl_shader_stage es_type
=
3450 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3451 struct radv_shader_variant
*es
=
3452 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3454 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3455 radeon_emit(cs
, va
>> 8);
3456 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3457 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3458 radeon_emit(cs
, shader
->config
.rsrc1
);
3459 radeon_emit(cs
, shader
->config
.rsrc2
);
3461 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3462 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3463 clip_dist_mask
= outinfo
->clip_dist_mask
;
3464 cull_dist_mask
= outinfo
->cull_dist_mask
;
3465 total_mask
= clip_dist_mask
| cull_dist_mask
;
3466 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3467 outinfo
->writes_layer
||
3468 outinfo
->writes_viewport_index
;
3469 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3470 (es
&& es
->info
.info
.uses_prim_id
);
3471 bool break_wave_at_eoi
= false;
3474 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3475 struct radv_shader_variant
*gs
=
3476 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3478 if (es_enable_prim_id
|| (gs
&& gs
->info
.info
.uses_prim_id
))
3479 break_wave_at_eoi
= true;
3482 nparams
= MAX2(outinfo
->param_exports
, 1);
3483 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3484 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3485 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3487 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3488 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3489 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3490 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3491 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3492 V_02870C_SPI_SHADER_4COMP
:
3493 V_02870C_SPI_SHADER_NONE
) |
3494 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3495 V_02870C_SPI_SHADER_4COMP
:
3496 V_02870C_SPI_SHADER_NONE
) |
3497 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3498 V_02870C_SPI_SHADER_4COMP
:
3499 V_02870C_SPI_SHADER_NONE
));
3501 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3502 S_028818_VTX_W0_FMT(1) |
3503 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3504 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3505 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3506 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3507 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3508 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3509 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3510 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3511 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3512 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3513 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3514 cull_dist_mask
<< 8 |
3517 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3518 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3519 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3521 bool vgt_reuse_off
= pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
&&
3522 pipeline
->device
->physical_device
->rad_info
.chip_external_rev
== 0x1 &&
3523 es_type
== MESA_SHADER_TESS_EVAL
;
3525 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3526 S_028AB4_REUSE_OFF(vgt_reuse_off
));
3527 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3528 ngg_state
->vgt_esgs_ring_itemsize
);
3530 /* NGG specific registers. */
3531 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3532 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3534 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3535 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3536 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3537 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3538 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3539 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3540 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3541 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3542 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3543 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3544 S_028B90_CNT(gs_num_invocations
) |
3545 S_028B90_ENABLE(gs_num_invocations
> 1) |
3546 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3548 /* User edge flags are set by the pos exports. If user edge flags are
3549 * not used, we must use hw-generated edge flags and pass them via
3550 * the prim export to prevent drawing lines on internal edges of
3551 * decomposed primitives (such as quads) with polygon mode = lines.
3553 * TODO: We should combine hw-generated edge flags with user edge
3554 * flags in the shader.
3556 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3557 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3558 !radv_pipeline_has_gs(pipeline
)));
3560 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
3561 S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3562 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3563 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
3565 gfx10_set_ge_pc_alloc(ctx_cs
, pipeline
, false);
3569 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3570 struct radv_pipeline
*pipeline
,
3571 struct radv_shader_variant
*shader
,
3572 const struct radv_tessellation_state
*tess
)
3574 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3576 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3577 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
3579 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3580 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
3582 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
3585 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3586 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3587 radeon_emit(cs
, va
>> 8);
3588 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3590 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3591 radeon_emit(cs
, va
>> 8);
3592 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3595 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3596 radeon_emit(cs
, shader
->config
.rsrc1
);
3597 radeon_emit(cs
, hs_rsrc2
);
3599 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3600 radeon_emit(cs
, va
>> 8);
3601 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3602 radeon_emit(cs
, shader
->config
.rsrc1
);
3603 radeon_emit(cs
, shader
->config
.rsrc2
);
3608 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3609 struct radeon_cmdbuf
*cs
,
3610 struct radv_pipeline
*pipeline
,
3611 const struct radv_tessellation_state
*tess
,
3612 const struct radv_ngg_state
*ngg
)
3614 struct radv_shader_variant
*vs
;
3616 /* Skip shaders merged into HS/GS */
3617 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3621 if (vs
->info
.vs
.as_ls
)
3622 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3623 else if (vs
->info
.vs
.as_es
)
3624 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3625 else if (vs
->info
.is_ngg
)
3626 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
, ngg
);
3628 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3632 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3633 struct radeon_cmdbuf
*cs
,
3634 struct radv_pipeline
*pipeline
,
3635 const struct radv_tessellation_state
*tess
,
3636 const struct radv_ngg_state
*ngg
)
3638 if (!radv_pipeline_has_tess(pipeline
))
3641 struct radv_shader_variant
*tes
, *tcs
;
3643 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3644 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3647 if (tes
->info
.is_ngg
) {
3648 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
, ngg
);
3649 } else if (tes
->info
.tes
.as_es
)
3650 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
3652 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
3655 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
3657 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
3660 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
3661 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
3662 tess
->ls_hs_config
);
3664 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
3665 tess
->ls_hs_config
);
3669 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
3670 struct radeon_cmdbuf
*cs
,
3671 struct radv_pipeline
*pipeline
,
3672 struct radv_shader_variant
*gs
,
3673 const struct radv_gs_state
*gs_state
)
3675 unsigned gs_max_out_vertices
;
3676 uint8_t *num_components
;
3681 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
3682 max_stream
= gs
->info
.info
.gs
.max_stream
;
3683 num_components
= gs
->info
.info
.gs
.num_stream_output_components
;
3685 offset
= num_components
[0] * gs_max_out_vertices
;
3687 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
3688 radeon_emit(ctx_cs
, offset
);
3689 if (max_stream
>= 1)
3690 offset
+= num_components
[1] * gs_max_out_vertices
;
3691 radeon_emit(ctx_cs
, offset
);
3692 if (max_stream
>= 2)
3693 offset
+= num_components
[2] * gs_max_out_vertices
;
3694 radeon_emit(ctx_cs
, offset
);
3695 if (max_stream
>= 3)
3696 offset
+= num_components
[3] * gs_max_out_vertices
;
3697 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
3699 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
3700 radeon_emit(ctx_cs
, num_components
[0]);
3701 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
3702 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
3703 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
3705 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
3706 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3707 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
3708 S_028B90_ENABLE(gs_num_invocations
> 0));
3710 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3711 gs_state
->vgt_esgs_ring_itemsize
);
3713 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
3715 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3716 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3717 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3718 radeon_emit(cs
, va
>> 8);
3719 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3721 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
3722 radeon_emit(cs
, va
>> 8);
3723 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
3726 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3727 radeon_emit(cs
, gs
->config
.rsrc1
);
3728 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
3730 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
3731 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
3733 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
3734 radeon_emit(cs
, va
>> 8);
3735 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
3736 radeon_emit(cs
, gs
->config
.rsrc1
);
3737 radeon_emit(cs
, gs
->config
.rsrc2
);
3740 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
3744 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
3745 struct radeon_cmdbuf
*cs
,
3746 struct radv_pipeline
*pipeline
,
3747 const struct radv_gs_state
*gs_state
,
3748 const struct radv_ngg_state
*ngg_state
)
3750 struct radv_shader_variant
*gs
;
3752 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3756 if (gs
->info
.is_ngg
)
3757 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
, ngg_state
);
3759 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
, gs_state
);
3761 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
3762 gs
->info
.gs
.vertices_out
);
3765 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
3767 uint32_t ps_input_cntl
;
3768 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3769 ps_input_cntl
= S_028644_OFFSET(offset
);
3771 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3773 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
3774 S_028644_ATTR0_VALID(1);
3777 /* The input is a DEFAULT_VAL constant. */
3778 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3779 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3780 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3781 ps_input_cntl
= S_028644_OFFSET(0x20) |
3782 S_028644_DEFAULT_VAL(offset
);
3784 return ps_input_cntl
;
3788 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
3789 struct radv_pipeline
*pipeline
)
3791 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3792 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3793 uint32_t ps_input_cntl
[32];
3795 unsigned ps_offset
= 0;
3797 if (ps
->info
.info
.ps
.prim_id_input
) {
3798 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
3799 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3800 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3805 if (ps
->info
.info
.ps
.layer_input
||
3806 ps
->info
.info
.needs_multiview_view_index
) {
3807 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
3808 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
3809 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
3811 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
3815 if (ps
->info
.info
.ps
.has_pcoord
) {
3817 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3818 ps_input_cntl
[ps_offset
] = val
;
3822 if (ps
->info
.info
.ps
.num_input_clips_culls
) {
3825 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
3826 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
3827 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3831 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
3832 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
3833 ps
->info
.info
.ps
.num_input_clips_culls
> 4) {
3834 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
3839 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.fs
.input_mask
; ++i
) {
3843 if (!(ps
->info
.fs
.input_mask
& (1u << i
)))
3846 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
3847 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
3848 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
3853 flat_shade
= !!(ps
->info
.fs
.flat_shaded_mask
& (1u << ps_offset
));
3854 float16
= !!(ps
->info
.fs
.float16_shaded_mask
& (1u << ps_offset
));
3856 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
3861 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
3862 for (unsigned i
= 0; i
< ps_offset
; i
++) {
3863 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
3869 radv_compute_db_shader_control(const struct radv_device
*device
,
3870 const struct radv_pipeline
*pipeline
,
3871 const struct radv_shader_variant
*ps
)
3874 if (ps
->info
.fs
.early_fragment_test
|| !ps
->info
.info
.ps
.writes_memory
)
3875 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
3877 z_order
= V_02880C_LATE_Z
;
3879 bool disable_rbplus
= device
->physical_device
->has_rbplus
&&
3880 !device
->physical_device
->rbplus_allowed
;
3882 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3883 * but this appears to break Project Cars (DXVK). See
3884 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
3886 bool mask_export_enable
= ps
->info
.info
.ps
.writes_sample_mask
;
3888 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_z
) |
3889 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.info
.ps
.writes_stencil
) |
3890 S_02880C_KILL_ENABLE(!!ps
->info
.fs
.can_discard
) |
3891 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
3892 S_02880C_Z_ORDER(z_order
) |
3893 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.fs
.early_fragment_test
) |
3894 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.fs
.post_depth_coverage
) |
3895 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.info
.ps
.writes_memory
) |
3896 S_02880C_EXEC_ON_NOOP(ps
->info
.info
.ps
.writes_memory
) |
3897 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
3901 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
3902 struct radeon_cmdbuf
*cs
,
3903 struct radv_pipeline
*pipeline
)
3905 struct radv_shader_variant
*ps
;
3907 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
3909 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3910 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
3912 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
3913 radeon_emit(cs
, va
>> 8);
3914 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
3915 radeon_emit(cs
, ps
->config
.rsrc1
);
3916 radeon_emit(cs
, ps
->config
.rsrc2
);
3918 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
3919 radv_compute_db_shader_control(pipeline
->device
,
3922 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
3923 ps
->config
.spi_ps_input_ena
);
3925 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
3926 ps
->config
.spi_ps_input_addr
);
3928 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
3929 S_0286D8_NUM_INTERP(ps
->info
.fs
.num_interp
));
3931 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
3933 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
3934 ac_get_spi_shader_z_format(ps
->info
.info
.ps
.writes_z
,
3935 ps
->info
.info
.ps
.writes_stencil
,
3936 ps
->info
.info
.ps
.writes_sample_mask
));
3938 if (pipeline
->device
->dfsm_allowed
) {
3939 /* optimise this? */
3940 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3941 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3946 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
3947 struct radv_pipeline
*pipeline
)
3949 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
3950 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
3953 unsigned vtx_reuse_depth
= 30;
3954 if (radv_pipeline_has_tess(pipeline
) &&
3955 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
3956 vtx_reuse_depth
= 14;
3958 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
3959 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
3963 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
3965 uint32_t stages
= 0;
3966 if (radv_pipeline_has_tess(pipeline
)) {
3967 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3968 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3970 if (radv_pipeline_has_gs(pipeline
))
3971 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3973 else if (radv_pipeline_has_ngg(pipeline
))
3974 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3976 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3977 } else if (radv_pipeline_has_gs(pipeline
)) {
3978 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3980 } else if (radv_pipeline_has_ngg(pipeline
)) {
3981 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3984 if (radv_pipeline_has_ngg(pipeline
)) {
3985 stages
|= S_028B54_PRIMGEN_EN(1);
3986 } else if (radv_pipeline_has_gs(pipeline
)) {
3987 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3990 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
3991 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3997 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3999 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4000 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4002 if (!discard_rectangle_info
)
4007 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4008 /* Interpret i as a bitmask, and then set the bit in the mask if
4009 * that combination of rectangles in which the pixel is contained
4010 * should pass the cliprect test. */
4011 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4013 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4017 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4028 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4029 struct radv_pipeline
*pipeline
,
4030 const struct radv_tessellation_state
*tess
,
4031 const struct radv_gs_state
*gs_state
)
4033 bool break_wave_at_eoi
= false;
4034 unsigned primgroup_size
;
4035 unsigned vertgroup_size
;
4037 if (radv_pipeline_has_tess(pipeline
)) {
4038 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4040 } else if (radv_pipeline_has_gs(pipeline
)) {
4041 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4042 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4043 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4045 primgroup_size
= 128; /* recommended without a GS and tess */
4049 if (radv_pipeline_has_tess(pipeline
)) {
4050 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
4051 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.info
.uses_prim_id
)
4052 break_wave_at_eoi
= true;
4055 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4056 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4057 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4058 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4059 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4063 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4064 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4065 const struct radv_graphics_pipeline_create_info
*extra
,
4066 const struct radv_blend_state
*blend
,
4067 const struct radv_tessellation_state
*tess
,
4068 const struct radv_gs_state
*gs
,
4069 const struct radv_ngg_state
*ngg
,
4070 unsigned prim
, unsigned gs_out
)
4072 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4073 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4076 ctx_cs
->max_dw
= 256;
4077 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4078 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4080 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4081 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4082 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4083 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4084 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4085 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
, ngg
);
4086 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
, ngg
);
4087 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
, gs
, ngg
);
4088 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4089 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4090 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4091 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
4093 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4094 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
, gs
);
4096 radeon_set_context_reg(ctx_cs
, R_0286E8_SPI_TMPRING_SIZE
,
4097 S_0286E8_WAVES(pipeline
->max_waves
) |
4098 S_0286E8_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
4100 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4102 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4103 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4104 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4106 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4108 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4110 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4112 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4114 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4115 assert(cs
->cdw
<= cs
->max_dw
);
4118 static struct radv_ia_multi_vgt_param_helpers
4119 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4120 const struct radv_tessellation_state
*tess
,
4123 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4124 const struct radv_device
*device
= pipeline
->device
;
4126 if (radv_pipeline_has_tess(pipeline
))
4127 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4128 else if (radv_pipeline_has_gs(pipeline
))
4129 ia_multi_vgt_param
.primgroup_size
= 64;
4131 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4133 /* GS requirement. */
4134 ia_multi_vgt_param
.partial_es_wave
= false;
4135 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4136 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4137 ia_multi_vgt_param
.partial_es_wave
= true;
4139 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4140 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4141 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4142 * 4 shader engines. Set 1 to pass the assertion below.
4143 * The other cases are hardware requirements. */
4144 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4145 prim
== V_008958_DI_PT_POLYGON
||
4146 prim
== V_008958_DI_PT_LINELOOP
||
4147 prim
== V_008958_DI_PT_TRIFAN
||
4148 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4149 (pipeline
->graphics
.prim_restart_enable
&&
4150 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4151 (prim
!= V_008958_DI_PT_POINTLIST
&&
4152 prim
!= V_008958_DI_PT_LINESTRIP
))))
4153 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4156 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4157 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.info
.ps
.prim_id_input
)
4158 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4159 if (radv_pipeline_has_gs(pipeline
) &&
4160 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.info
.uses_prim_id
)
4161 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4162 if (radv_pipeline_has_tess(pipeline
)) {
4163 /* SWITCH_ON_EOI must be set if PrimID is used. */
4164 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.info
.uses_prim_id
||
4165 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.info
.uses_prim_id
)
4166 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4169 ia_multi_vgt_param
.partial_vs_wave
= false;
4170 if (radv_pipeline_has_tess(pipeline
)) {
4171 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4172 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4173 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4174 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4175 radv_pipeline_has_gs(pipeline
))
4176 ia_multi_vgt_param
.partial_vs_wave
= true;
4177 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4178 if (device
->has_distributed_tess
) {
4179 if (radv_pipeline_has_gs(pipeline
)) {
4180 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4181 ia_multi_vgt_param
.partial_es_wave
= true;
4183 ia_multi_vgt_param
.partial_vs_wave
= true;
4188 /* Workaround for a VGT hang when strip primitive types are used with
4189 * primitive restart.
4191 if (pipeline
->graphics
.prim_restart_enable
&&
4192 (prim
== V_008958_DI_PT_LINESTRIP
||
4193 prim
== V_008958_DI_PT_TRISTRIP
||
4194 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4195 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4196 ia_multi_vgt_param
.partial_vs_wave
= true;
4199 if (radv_pipeline_has_gs(pipeline
)) {
4200 /* On these chips there is the possibility of a hang if the
4201 * pipeline uses a GS and partial_vs_wave is not set.
4203 * This mostly does not hit 4-SE chips, as those typically set
4204 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4205 * with GS due to another workaround.
4207 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4209 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4210 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4211 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4212 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4213 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4214 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4215 ia_multi_vgt_param
.partial_vs_wave
= true;
4219 ia_multi_vgt_param
.base
=
4220 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4221 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4222 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4223 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4224 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4226 return ia_multi_vgt_param
;
4231 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4232 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4234 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4235 pCreateInfo
->pVertexInputState
;
4236 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4238 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4239 const VkVertexInputAttributeDescription
*desc
=
4240 &vi_info
->pVertexAttributeDescriptions
[i
];
4241 unsigned loc
= desc
->location
;
4242 const struct vk_format_description
*format_desc
;
4244 format_desc
= vk_format_description(desc
->format
);
4246 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4249 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4250 const VkVertexInputBindingDescription
*desc
=
4251 &vi_info
->pVertexBindingDescriptions
[i
];
4253 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4254 pipeline
->num_vertex_bindings
=
4255 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4259 static struct radv_shader_variant
*
4260 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4264 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4265 struct radv_shader_variant
*shader
=
4266 radv_get_shader(pipeline
, i
);
4268 if (shader
&& shader
->info
.info
.so
.num_outputs
> 0)
4276 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4277 struct radv_device
*device
,
4278 struct radv_pipeline_cache
*cache
,
4279 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4280 const struct radv_graphics_pipeline_create_info
*extra
)
4283 bool has_view_index
= false;
4285 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4286 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4287 if (subpass
->view_mask
)
4288 has_view_index
= true;
4290 pipeline
->device
= device
;
4291 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4292 assert(pipeline
->layout
);
4294 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4296 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4297 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4298 radv_init_feedback(creation_feedback
);
4300 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4302 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4303 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4304 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4305 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4306 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4307 if(creation_feedback
)
4308 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4311 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4312 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
4314 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4315 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4317 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4319 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4321 if (radv_pipeline_has_gs(pipeline
)) {
4322 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4323 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4324 } else if (radv_pipeline_has_tess(pipeline
)) {
4325 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4326 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4328 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4329 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4331 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4333 if (extra
&& extra
->use_rectlist
) {
4334 prim
= V_008958_DI_PT_RECTLIST
;
4335 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4336 pipeline
->graphics
.can_use_guardband
= true;
4337 if (radv_pipeline_has_ngg(pipeline
))
4338 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4340 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4341 /* prim vertex count will need TESS changes */
4342 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4344 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4346 /* Ensure that some export memory is always allocated, for two reasons:
4348 * 1) Correctness: The hardware ignores the EXEC mask if no export
4349 * memory is allocated, so KILL and alpha test do not work correctly
4351 * 2) Performance: Every shader needs at least a NULL export, even when
4352 * it writes no color/depth output. The NULL export instruction
4353 * stalls without this setting.
4355 * Don't add this to CB_SHADER_MASK.
4357 * GFX10 supports pixel shaders without exports by setting both the
4358 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4359 * instructions if any are present.
4361 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4362 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4363 ps
->info
.fs
.can_discard
) &&
4364 !blend
.spi_shader_col_format
) {
4365 if (!ps
->info
.info
.ps
.writes_z
&&
4366 !ps
->info
.info
.ps
.writes_stencil
&&
4367 !ps
->info
.info
.ps
.writes_sample_mask
)
4368 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4371 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4372 if (pipeline
->shaders
[i
]) {
4373 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4377 struct radv_ngg_state ngg
= {0};
4378 struct radv_gs_state gs
= {0};
4380 if (radv_pipeline_has_ngg(pipeline
)) {
4381 ngg
= calculate_ngg_info(pCreateInfo
, pipeline
);
4382 } else if (radv_pipeline_has_gs(pipeline
)) {
4383 gs
= calculate_gs_info(pCreateInfo
, pipeline
);
4384 calculate_gs_ring_sizes(pipeline
, &gs
);
4387 struct radv_tessellation_state tess
= {0};
4388 if (radv_pipeline_has_tess(pipeline
)) {
4389 if (prim
== V_008958_DI_PT_PATCH
) {
4390 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4391 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
4393 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4396 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
4398 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4400 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4401 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4403 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4404 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4405 if (loc
->sgpr_idx
!= -1) {
4406 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4407 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4408 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.info
.vs
.needs_draw_id
)
4409 pipeline
->graphics
.vtx_emit_num
= 3;
4411 pipeline
->graphics
.vtx_emit_num
= 2;
4414 /* Find the last vertex shader stage that eventually uses streamout. */
4415 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4417 result
= radv_pipeline_scratch_init(device
, pipeline
);
4418 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, &gs
, &ngg
, prim
, gs_out
);
4424 radv_graphics_pipeline_create(
4426 VkPipelineCache _cache
,
4427 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4428 const struct radv_graphics_pipeline_create_info
*extra
,
4429 const VkAllocationCallbacks
*pAllocator
,
4430 VkPipeline
*pPipeline
)
4432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4433 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4434 struct radv_pipeline
*pipeline
;
4437 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4438 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4439 if (pipeline
== NULL
)
4440 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4442 result
= radv_pipeline_init(pipeline
, device
, cache
,
4443 pCreateInfo
, extra
);
4444 if (result
!= VK_SUCCESS
) {
4445 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4449 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4454 VkResult
radv_CreateGraphicsPipelines(
4456 VkPipelineCache pipelineCache
,
4458 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4459 const VkAllocationCallbacks
* pAllocator
,
4460 VkPipeline
* pPipelines
)
4462 VkResult result
= VK_SUCCESS
;
4465 for (; i
< count
; i
++) {
4467 r
= radv_graphics_pipeline_create(_device
,
4470 NULL
, pAllocator
, &pPipelines
[i
]);
4471 if (r
!= VK_SUCCESS
) {
4473 pPipelines
[i
] = VK_NULL_HANDLE
;
4482 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
4484 struct radv_shader_variant
*compute_shader
;
4485 struct radv_device
*device
= pipeline
->device
;
4486 unsigned threads_per_threadgroup
;
4487 unsigned threadgroups_per_cu
= 1;
4488 unsigned waves_per_threadgroup
;
4489 unsigned max_waves_per_sh
= 0;
4492 pipeline
->cs
.buf
= malloc(20 * 4);
4493 pipeline
->cs
.max_dw
= 20;
4495 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4496 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
4498 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
4499 radeon_emit(&pipeline
->cs
, va
>> 8);
4500 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
4502 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
4503 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
4504 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
4506 radeon_set_sh_reg(&pipeline
->cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
4507 S_00B860_WAVES(pipeline
->max_waves
) |
4508 S_00B860_WAVESIZE(pipeline
->scratch_bytes_per_wave
>> 10));
4510 /* Calculate best compute resource limits. */
4511 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
4512 compute_shader
->info
.cs
.block_size
[1] *
4513 compute_shader
->info
.cs
.block_size
[2];
4514 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
, 64);
4516 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4517 waves_per_threadgroup
== 1)
4518 threadgroups_per_cu
= 2;
4520 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
4521 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
4522 waves_per_threadgroup
,
4524 threadgroups_per_cu
));
4526 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
4527 radeon_emit(&pipeline
->cs
,
4528 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
4529 radeon_emit(&pipeline
->cs
,
4530 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
4531 radeon_emit(&pipeline
->cs
,
4532 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
4534 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
4537 static VkResult
radv_compute_pipeline_create(
4539 VkPipelineCache _cache
,
4540 const VkComputePipelineCreateInfo
* pCreateInfo
,
4541 const VkAllocationCallbacks
* pAllocator
,
4542 VkPipeline
* pPipeline
)
4544 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4545 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4546 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4547 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4548 struct radv_pipeline
*pipeline
;
4551 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4552 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4553 if (pipeline
== NULL
)
4554 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4556 pipeline
->device
= device
;
4557 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4558 assert(pipeline
->layout
);
4560 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4561 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4562 radv_init_feedback(creation_feedback
);
4564 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4565 if (creation_feedback
)
4566 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
4568 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
4569 radv_create_shaders(pipeline
, device
, cache
, &(struct radv_pipeline_key
) {0}, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
4571 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
4572 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
4573 result
= radv_pipeline_scratch_init(device
, pipeline
);
4574 if (result
!= VK_SUCCESS
) {
4575 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4579 radv_compute_generate_pm4(pipeline
);
4581 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4586 VkResult
radv_CreateComputePipelines(
4588 VkPipelineCache pipelineCache
,
4590 const VkComputePipelineCreateInfo
* pCreateInfos
,
4591 const VkAllocationCallbacks
* pAllocator
,
4592 VkPipeline
* pPipelines
)
4594 VkResult result
= VK_SUCCESS
;
4597 for (; i
< count
; i
++) {
4599 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
4601 pAllocator
, &pPipelines
[i
]);
4602 if (r
!= VK_SUCCESS
) {
4604 pPipelines
[i
] = VK_NULL_HANDLE
;