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radv: add an option for disabling NGG on GFX10
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49 #include "ac_shader_util.h"
50 #include "main/menums.h"
51
52 struct radv_blend_state {
53 uint32_t blend_enable_4bit;
54 uint32_t need_src_alpha;
55
56 uint32_t cb_color_control;
57 uint32_t cb_target_mask;
58 uint32_t cb_target_enabled_4bit;
59 uint32_t sx_mrt_blend_opt[8];
60 uint32_t cb_blend_control[8];
61
62 uint32_t spi_shader_col_format;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 struct radv_gs_state {
93 uint32_t vgt_gs_onchip_cntl;
94 uint32_t vgt_gs_max_prims_per_subgroup;
95 uint32_t vgt_esgs_ring_itemsize;
96 uint32_t lds_size;
97 };
98
99 struct radv_ngg_state {
100 uint16_t ngg_emit_size; /* in dwords */
101 uint32_t hw_max_esverts;
102 uint32_t max_gsprims;
103 uint32_t max_out_verts;
104 uint32_t prim_amp_factor;
105 uint32_t vgt_esgs_ring_itemsize;
106 bool max_vert_out_per_gs_instance;
107 };
108
109 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
110 {
111 struct radv_shader_variant *variant = NULL;
112 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
113 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
114 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
115 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
116 else if (pipeline->shaders[MESA_SHADER_VERTEX])
117 variant = pipeline->shaders[MESA_SHADER_VERTEX];
118 else
119 return false;
120 return variant->info.is_ngg;
121 }
122
123 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
124 {
125 if (!radv_pipeline_has_gs(pipeline))
126 return false;
127
128 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
129 * On GFX10, it might be required in rare cases if it's not possible to
130 * enable NGG.
131 */
132 if (radv_pipeline_has_ngg(pipeline))
133 return false;
134
135 assert(pipeline->gs_copy_shader);
136 return true;
137 }
138
139 static void
140 radv_pipeline_destroy(struct radv_device *device,
141 struct radv_pipeline *pipeline,
142 const VkAllocationCallbacks* allocator)
143 {
144 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
145 if (pipeline->shaders[i])
146 radv_shader_variant_destroy(device, pipeline->shaders[i]);
147
148 if (pipeline->gs_copy_shader)
149 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
150
151 if(pipeline->cs.buf)
152 free(pipeline->cs.buf);
153 vk_free2(&device->alloc, allocator, pipeline);
154 }
155
156 void radv_DestroyPipeline(
157 VkDevice _device,
158 VkPipeline _pipeline,
159 const VkAllocationCallbacks* pAllocator)
160 {
161 RADV_FROM_HANDLE(radv_device, device, _device);
162 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
163
164 if (!_pipeline)
165 return;
166
167 radv_pipeline_destroy(device, pipeline, pAllocator);
168 }
169
170 static uint32_t get_hash_flags(struct radv_device *device)
171 {
172 uint32_t hash_flags = 0;
173
174 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
175 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
176 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
177 hash_flags |= RADV_HASH_SHADER_NO_NGG;
178 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
179 hash_flags |= RADV_HASH_SHADER_SISCHED;
180 return hash_flags;
181 }
182
183 static VkResult
184 radv_pipeline_scratch_init(struct radv_device *device,
185 struct radv_pipeline *pipeline)
186 {
187 unsigned scratch_bytes_per_wave = 0;
188 unsigned max_waves = 0;
189 unsigned min_waves = 1;
190
191 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
192 if (pipeline->shaders[i]) {
193 unsigned max_stage_waves = device->scratch_waves;
194
195 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
196 pipeline->shaders[i]->config.scratch_bytes_per_wave);
197
198 max_stage_waves = MIN2(max_stage_waves,
199 4 * device->physical_device->rad_info.num_good_compute_units *
200 (256 / pipeline->shaders[i]->config.num_vgprs));
201 max_waves = MAX2(max_waves, max_stage_waves);
202 }
203 }
204
205 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
206 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
207 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
208 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
209 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
210 }
211
212 if (scratch_bytes_per_wave)
213 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
214
215 if (scratch_bytes_per_wave && max_waves < min_waves) {
216 /* Not really true at this moment, but will be true on first
217 * execution. Avoid having hanging shaders. */
218 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
219 }
220 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
221 pipeline->max_waves = max_waves;
222 return VK_SUCCESS;
223 }
224
225 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
226 {
227 switch (op) {
228 case VK_LOGIC_OP_CLEAR:
229 return V_028808_ROP3_CLEAR;
230 case VK_LOGIC_OP_AND:
231 return V_028808_ROP3_AND;
232 case VK_LOGIC_OP_AND_REVERSE:
233 return V_028808_ROP3_AND_REVERSE;
234 case VK_LOGIC_OP_COPY:
235 return V_028808_ROP3_COPY;
236 case VK_LOGIC_OP_AND_INVERTED:
237 return V_028808_ROP3_AND_INVERTED;
238 case VK_LOGIC_OP_NO_OP:
239 return V_028808_ROP3_NO_OP;
240 case VK_LOGIC_OP_XOR:
241 return V_028808_ROP3_XOR;
242 case VK_LOGIC_OP_OR:
243 return V_028808_ROP3_OR;
244 case VK_LOGIC_OP_NOR:
245 return V_028808_ROP3_NOR;
246 case VK_LOGIC_OP_EQUIVALENT:
247 return V_028808_ROP3_EQUIVALENT;
248 case VK_LOGIC_OP_INVERT:
249 return V_028808_ROP3_INVERT;
250 case VK_LOGIC_OP_OR_REVERSE:
251 return V_028808_ROP3_OR_REVERSE;
252 case VK_LOGIC_OP_COPY_INVERTED:
253 return V_028808_ROP3_COPY_INVERTED;
254 case VK_LOGIC_OP_OR_INVERTED:
255 return V_028808_ROP3_OR_INVERTED;
256 case VK_LOGIC_OP_NAND:
257 return V_028808_ROP3_NAND;
258 case VK_LOGIC_OP_SET:
259 return V_028808_ROP3_SET;
260 default:
261 unreachable("Unhandled logic op");
262 }
263 }
264
265
266 static uint32_t si_translate_blend_function(VkBlendOp op)
267 {
268 switch (op) {
269 case VK_BLEND_OP_ADD:
270 return V_028780_COMB_DST_PLUS_SRC;
271 case VK_BLEND_OP_SUBTRACT:
272 return V_028780_COMB_SRC_MINUS_DST;
273 case VK_BLEND_OP_REVERSE_SUBTRACT:
274 return V_028780_COMB_DST_MINUS_SRC;
275 case VK_BLEND_OP_MIN:
276 return V_028780_COMB_MIN_DST_SRC;
277 case VK_BLEND_OP_MAX:
278 return V_028780_COMB_MAX_DST_SRC;
279 default:
280 return 0;
281 }
282 }
283
284 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
285 {
286 switch (factor) {
287 case VK_BLEND_FACTOR_ZERO:
288 return V_028780_BLEND_ZERO;
289 case VK_BLEND_FACTOR_ONE:
290 return V_028780_BLEND_ONE;
291 case VK_BLEND_FACTOR_SRC_COLOR:
292 return V_028780_BLEND_SRC_COLOR;
293 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
294 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
295 case VK_BLEND_FACTOR_DST_COLOR:
296 return V_028780_BLEND_DST_COLOR;
297 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
298 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
299 case VK_BLEND_FACTOR_SRC_ALPHA:
300 return V_028780_BLEND_SRC_ALPHA;
301 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
302 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
303 case VK_BLEND_FACTOR_DST_ALPHA:
304 return V_028780_BLEND_DST_ALPHA;
305 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
307 case VK_BLEND_FACTOR_CONSTANT_COLOR:
308 return V_028780_BLEND_CONSTANT_COLOR;
309 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
310 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
311 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
312 return V_028780_BLEND_CONSTANT_ALPHA;
313 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
316 return V_028780_BLEND_SRC_ALPHA_SATURATE;
317 case VK_BLEND_FACTOR_SRC1_COLOR:
318 return V_028780_BLEND_SRC1_COLOR;
319 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case VK_BLEND_FACTOR_SRC1_ALPHA:
322 return V_028780_BLEND_SRC1_ALPHA;
323 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
324 return V_028780_BLEND_INV_SRC1_ALPHA;
325 default:
326 return 0;
327 }
328 }
329
330 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
331 {
332 switch (op) {
333 case VK_BLEND_OP_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case VK_BLEND_OP_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case VK_BLEND_OP_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case VK_BLEND_OP_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case VK_BLEND_OP_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
349 {
350 switch (factor) {
351 case VK_BLEND_FACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case VK_BLEND_FACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case VK_BLEND_FACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case VK_BLEND_FACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == VK_BLEND_FACTOR_ZERO) {
383 *src_factor = VK_BLEND_FACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == VK_BLEND_OP_SUBTRACT)
388 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
389 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
390 *func = VK_BLEND_OP_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == VK_BLEND_FACTOR_DST_COLOR ||
397 factor == VK_BLEND_FACTOR_DST_ALPHA ||
398 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
399 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
400 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
401 }
402
403 static bool is_dual_src(VkBlendFactor factor)
404 {
405 switch (factor) {
406 case VK_BLEND_FACTOR_SRC1_COLOR:
407 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
408 case VK_BLEND_FACTOR_SRC1_ALPHA:
409 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
410 return true;
411 default:
412 return false;
413 }
414 }
415
416 static unsigned si_choose_spi_color_format(VkFormat vk_format,
417 bool blend_enable,
418 bool blend_need_alpha)
419 {
420 const struct vk_format_description *desc = vk_format_description(vk_format);
421 unsigned format, ntype, swap;
422
423 /* Alpha is needed for alpha-to-coverage.
424 * Blending may be with or without alpha.
425 */
426 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
427 unsigned alpha = 0; /* exports alpha, but may not support blending */
428 unsigned blend = 0; /* supports blending, but may not export alpha */
429 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
430
431 format = radv_translate_colorformat(vk_format);
432 ntype = radv_translate_color_numformat(vk_format, desc,
433 vk_format_get_first_non_void_channel(vk_format));
434 swap = radv_translate_colorswap(vk_format, false);
435
436 /* Choose the SPI color formats. These are required values for Stoney/RB+.
437 * Other chips have multiple choices, though they are not necessarily better.
438 */
439 switch (format) {
440 case V_028C70_COLOR_5_6_5:
441 case V_028C70_COLOR_1_5_5_5:
442 case V_028C70_COLOR_5_5_5_1:
443 case V_028C70_COLOR_4_4_4_4:
444 case V_028C70_COLOR_10_11_11:
445 case V_028C70_COLOR_11_11_10:
446 case V_028C70_COLOR_8:
447 case V_028C70_COLOR_8_8:
448 case V_028C70_COLOR_8_8_8_8:
449 case V_028C70_COLOR_10_10_10_2:
450 case V_028C70_COLOR_2_10_10_10:
451 if (ntype == V_028C70_NUMBER_UINT)
452 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
453 else if (ntype == V_028C70_NUMBER_SINT)
454 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
455 else
456 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
457 break;
458
459 case V_028C70_COLOR_16:
460 case V_028C70_COLOR_16_16:
461 case V_028C70_COLOR_16_16_16_16:
462 if (ntype == V_028C70_NUMBER_UNORM ||
463 ntype == V_028C70_NUMBER_SNORM) {
464 /* UNORM16 and SNORM16 don't support blending */
465 if (ntype == V_028C70_NUMBER_UNORM)
466 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
467 else
468 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
469
470 /* Use 32 bits per channel for blending. */
471 if (format == V_028C70_COLOR_16) {
472 if (swap == V_028C70_SWAP_STD) { /* R */
473 blend = V_028714_SPI_SHADER_32_R;
474 blend_alpha = V_028714_SPI_SHADER_32_AR;
475 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
476 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
477 else
478 assert(0);
479 } else if (format == V_028C70_COLOR_16_16) {
480 if (swap == V_028C70_SWAP_STD) { /* RG */
481 blend = V_028714_SPI_SHADER_32_GR;
482 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
483 } else if (swap == V_028C70_SWAP_ALT) /* RA */
484 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
485 else
486 assert(0);
487 } else /* 16_16_16_16 */
488 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
489 } else if (ntype == V_028C70_NUMBER_UINT)
490 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
491 else if (ntype == V_028C70_NUMBER_SINT)
492 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
493 else if (ntype == V_028C70_NUMBER_FLOAT)
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
495 else
496 assert(0);
497 break;
498
499 case V_028C70_COLOR_32:
500 if (swap == V_028C70_SWAP_STD) { /* R */
501 blend = normal = V_028714_SPI_SHADER_32_R;
502 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
503 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
504 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
505 else
506 assert(0);
507 break;
508
509 case V_028C70_COLOR_32_32:
510 if (swap == V_028C70_SWAP_STD) { /* RG */
511 blend = normal = V_028714_SPI_SHADER_32_GR;
512 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
513 } else if (swap == V_028C70_SWAP_ALT) /* RA */
514 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
515 else
516 assert(0);
517 break;
518
519 case V_028C70_COLOR_32_32_32_32:
520 case V_028C70_COLOR_8_24:
521 case V_028C70_COLOR_24_8:
522 case V_028C70_COLOR_X24_8_32_FLOAT:
523 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
524 break;
525
526 default:
527 unreachable("unhandled blend format");
528 }
529
530 if (blend_enable && blend_need_alpha)
531 return blend_alpha;
532 else if(blend_need_alpha)
533 return alpha;
534 else if(blend_enable)
535 return blend;
536 else
537 return normal;
538 }
539
540 static void
541 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
542 const VkGraphicsPipelineCreateInfo *pCreateInfo,
543 struct radv_blend_state *blend)
544 {
545 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
546 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
547 unsigned col_format = 0;
548 unsigned num_targets;
549
550 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
551 unsigned cf;
552
553 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
554 cf = V_028714_SPI_SHADER_ZERO;
555 } else {
556 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
557 bool blend_enable =
558 blend->blend_enable_4bit & (0xfu << (i * 4));
559
560 cf = si_choose_spi_color_format(attachment->format,
561 blend_enable,
562 blend->need_src_alpha & (1 << i));
563 }
564
565 col_format |= cf << (4 * i);
566 }
567
568 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
569 /* When a subpass doesn't have any color attachments, write the
570 * alpha channel of MRT0 when alpha coverage is enabled because
571 * the depth attachment needs it.
572 */
573 col_format |= V_028714_SPI_SHADER_32_AR;
574 }
575
576 /* If the i-th target format is set, all previous target formats must
577 * be non-zero to avoid hangs.
578 */
579 num_targets = (util_last_bit(col_format) + 3) / 4;
580 for (unsigned i = 0; i < num_targets; i++) {
581 if (!(col_format & (0xf << (i * 4)))) {
582 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
583 }
584 }
585
586 /* The output for dual source blending should have the same format as
587 * the first output.
588 */
589 if (blend->mrt0_is_dual_src)
590 col_format |= (col_format & 0xf) << 4;
591
592 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
593 blend->spi_shader_col_format = col_format;
594 }
595
596 static bool
597 format_is_int8(VkFormat format)
598 {
599 const struct vk_format_description *desc = vk_format_description(format);
600 int channel = vk_format_get_first_non_void_channel(format);
601
602 return channel >= 0 && desc->channel[channel].pure_integer &&
603 desc->channel[channel].size == 8;
604 }
605
606 static bool
607 format_is_int10(VkFormat format)
608 {
609 const struct vk_format_description *desc = vk_format_description(format);
610
611 if (desc->nr_channels != 4)
612 return false;
613 for (unsigned i = 0; i < 4; i++) {
614 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
615 return true;
616 }
617 return false;
618 }
619
620 /*
621 * Ordered so that for each i,
622 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
623 */
624 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
625 VK_FORMAT_R32_SFLOAT,
626 VK_FORMAT_R32G32_SFLOAT,
627 VK_FORMAT_R8G8B8A8_UNORM,
628 VK_FORMAT_R16G16B16A16_UNORM,
629 VK_FORMAT_R16G16B16A16_SNORM,
630 VK_FORMAT_R16G16B16A16_UINT,
631 VK_FORMAT_R16G16B16A16_SINT,
632 VK_FORMAT_R32G32B32A32_SFLOAT,
633 VK_FORMAT_R8G8B8A8_UINT,
634 VK_FORMAT_R8G8B8A8_SINT,
635 VK_FORMAT_A2R10G10B10_UINT_PACK32,
636 VK_FORMAT_A2R10G10B10_SINT_PACK32,
637 };
638
639 unsigned radv_format_meta_fs_key(VkFormat format)
640 {
641 unsigned col_format = si_choose_spi_color_format(format, false, false);
642
643 assert(col_format != V_028714_SPI_SHADER_32_AR);
644 if (col_format >= V_028714_SPI_SHADER_32_AR)
645 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
646
647 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
648 bool is_int8 = format_is_int8(format);
649 bool is_int10 = format_is_int10(format);
650
651 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
652 }
653
654 static void
655 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
656 unsigned *is_int8, unsigned *is_int10)
657 {
658 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
659 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
660 *is_int8 = 0;
661 *is_int10 = 0;
662
663 for (unsigned i = 0; i < subpass->color_count; ++i) {
664 struct radv_render_pass_attachment *attachment;
665
666 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
667 continue;
668
669 attachment = pass->attachments + subpass->color_attachments[i].attachment;
670
671 if (format_is_int8(attachment->format))
672 *is_int8 |= 1 << i;
673 if (format_is_int10(attachment->format))
674 *is_int10 |= 1 << i;
675 }
676 }
677
678 static void
679 radv_blend_check_commutativity(struct radv_blend_state *blend,
680 VkBlendOp op, VkBlendFactor src,
681 VkBlendFactor dst, unsigned chanmask)
682 {
683 /* Src factor is allowed when it does not depend on Dst. */
684 static const uint32_t src_allowed =
685 (1u << VK_BLEND_FACTOR_ONE) |
686 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
687 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
688 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
689 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
690 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
691 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
692 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
693 (1u << VK_BLEND_FACTOR_ZERO) |
694 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
695 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
696 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
697 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
698 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
699 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
700
701 if (dst == VK_BLEND_FACTOR_ONE &&
702 (src_allowed & (1u << src))) {
703 /* Addition is commutative, but floating point addition isn't
704 * associative: subtle changes can be introduced via different
705 * rounding. Be conservative, only enable for min and max.
706 */
707 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
708 blend->commutative_4bit |= chanmask;
709 }
710 }
711
712 static struct radv_blend_state
713 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
714 const VkGraphicsPipelineCreateInfo *pCreateInfo,
715 const struct radv_graphics_pipeline_create_info *extra)
716 {
717 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
718 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
719 struct radv_blend_state blend = {0};
720 unsigned mode = V_028808_CB_NORMAL;
721 int i;
722
723 if (!vkblend)
724 return blend;
725
726 if (extra && extra->custom_blend_mode) {
727 blend.single_cb_enable = true;
728 mode = extra->custom_blend_mode;
729 }
730 blend.cb_color_control = 0;
731 if (vkblend->logicOpEnable)
732 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
733 else
734 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
735
736 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
737 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
738 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
739 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
740 S_028B70_OFFSET_ROUND(1);
741
742 if (vkms && vkms->alphaToCoverageEnable) {
743 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
744 blend.need_src_alpha |= 0x1;
745 }
746
747 blend.cb_target_mask = 0;
748 for (i = 0; i < vkblend->attachmentCount; i++) {
749 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
750 unsigned blend_cntl = 0;
751 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
752 VkBlendOp eqRGB = att->colorBlendOp;
753 VkBlendFactor srcRGB = att->srcColorBlendFactor;
754 VkBlendFactor dstRGB = att->dstColorBlendFactor;
755 VkBlendOp eqA = att->alphaBlendOp;
756 VkBlendFactor srcA = att->srcAlphaBlendFactor;
757 VkBlendFactor dstA = att->dstAlphaBlendFactor;
758
759 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
760
761 if (!att->colorWriteMask)
762 continue;
763
764 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
765 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
766 if (!att->blendEnable) {
767 blend.cb_blend_control[i] = blend_cntl;
768 continue;
769 }
770
771 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
772 if (i == 0)
773 blend.mrt0_is_dual_src = true;
774
775 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
776 srcRGB = VK_BLEND_FACTOR_ONE;
777 dstRGB = VK_BLEND_FACTOR_ONE;
778 }
779 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
780 srcA = VK_BLEND_FACTOR_ONE;
781 dstA = VK_BLEND_FACTOR_ONE;
782 }
783
784 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
785 0x7 << (4 * i));
786 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
787 0x8 << (4 * i));
788
789 /* Blending optimizations for RB+.
790 * These transformations don't change the behavior.
791 *
792 * First, get rid of DST in the blend factors:
793 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
794 */
795 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
796 VK_BLEND_FACTOR_DST_COLOR,
797 VK_BLEND_FACTOR_SRC_COLOR);
798
799 si_blend_remove_dst(&eqA, &srcA, &dstA,
800 VK_BLEND_FACTOR_DST_COLOR,
801 VK_BLEND_FACTOR_SRC_COLOR);
802
803 si_blend_remove_dst(&eqA, &srcA, &dstA,
804 VK_BLEND_FACTOR_DST_ALPHA,
805 VK_BLEND_FACTOR_SRC_ALPHA);
806
807 /* Look up the ideal settings from tables. */
808 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
809 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
810 srcA_opt = si_translate_blend_opt_factor(srcA, true);
811 dstA_opt = si_translate_blend_opt_factor(dstA, true);
812
813 /* Handle interdependencies. */
814 if (si_blend_factor_uses_dst(srcRGB))
815 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
816 if (si_blend_factor_uses_dst(srcA))
817 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
818
819 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
820 (dstRGB == VK_BLEND_FACTOR_ZERO ||
821 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
822 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
823 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
824
825 /* Set the final value. */
826 blend.sx_mrt_blend_opt[i] =
827 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
828 S_028760_COLOR_DST_OPT(dstRGB_opt) |
829 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
830 S_028760_ALPHA_SRC_OPT(srcA_opt) |
831 S_028760_ALPHA_DST_OPT(dstA_opt) |
832 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
833 blend_cntl |= S_028780_ENABLE(1);
834
835 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
836 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
837 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
838 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
839 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
840 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
841 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
842 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
843 }
844 blend.cb_blend_control[i] = blend_cntl;
845
846 blend.blend_enable_4bit |= 0xfu << (i * 4);
847
848 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
849 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
850 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
851 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
852 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
853 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
854 blend.need_src_alpha |= 1 << i;
855 }
856 for (i = vkblend->attachmentCount; i < 8; i++) {
857 blend.cb_blend_control[i] = 0;
858 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
859 }
860
861 if (pipeline->device->physical_device->has_rbplus) {
862 /* Disable RB+ blend optimizations for dual source blending. */
863 if (blend.mrt0_is_dual_src) {
864 for (i = 0; i < 8; i++) {
865 blend.sx_mrt_blend_opt[i] =
866 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
867 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
868 }
869 }
870
871 /* RB+ doesn't work with dual source blending, logic op and
872 * RESOLVE.
873 */
874 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
875 mode == V_028808_CB_RESOLVE)
876 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
877 }
878
879 if (blend.cb_target_mask)
880 blend.cb_color_control |= S_028808_MODE(mode);
881 else
882 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
883
884 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
885 return blend;
886 }
887
888 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
889 {
890 switch (op) {
891 case VK_STENCIL_OP_KEEP:
892 return V_02842C_STENCIL_KEEP;
893 case VK_STENCIL_OP_ZERO:
894 return V_02842C_STENCIL_ZERO;
895 case VK_STENCIL_OP_REPLACE:
896 return V_02842C_STENCIL_REPLACE_TEST;
897 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
898 return V_02842C_STENCIL_ADD_CLAMP;
899 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
900 return V_02842C_STENCIL_SUB_CLAMP;
901 case VK_STENCIL_OP_INVERT:
902 return V_02842C_STENCIL_INVERT;
903 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
904 return V_02842C_STENCIL_ADD_WRAP;
905 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
906 return V_02842C_STENCIL_SUB_WRAP;
907 default:
908 return 0;
909 }
910 }
911
912 static uint32_t si_translate_fill(VkPolygonMode func)
913 {
914 switch(func) {
915 case VK_POLYGON_MODE_FILL:
916 return V_028814_X_DRAW_TRIANGLES;
917 case VK_POLYGON_MODE_LINE:
918 return V_028814_X_DRAW_LINES;
919 case VK_POLYGON_MODE_POINT:
920 return V_028814_X_DRAW_POINTS;
921 default:
922 assert(0);
923 return V_028814_X_DRAW_POINTS;
924 }
925 }
926
927 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
928 {
929 uint32_t num_samples = vkms->rasterizationSamples;
930 uint32_t ps_iter_samples = 1;
931
932 if (vkms->sampleShadingEnable) {
933 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
934 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
935 }
936 return ps_iter_samples;
937 }
938
939 static bool
940 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
941 {
942 return pCreateInfo->depthTestEnable &&
943 pCreateInfo->depthWriteEnable &&
944 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
945 }
946
947 static bool
948 radv_writes_stencil(const VkStencilOpState *state)
949 {
950 return state->writeMask &&
951 (state->failOp != VK_STENCIL_OP_KEEP ||
952 state->passOp != VK_STENCIL_OP_KEEP ||
953 state->depthFailOp != VK_STENCIL_OP_KEEP);
954 }
955
956 static bool
957 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
958 {
959 return pCreateInfo->stencilTestEnable &&
960 (radv_writes_stencil(&pCreateInfo->front) ||
961 radv_writes_stencil(&pCreateInfo->back));
962 }
963
964 static bool
965 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
966 {
967 return radv_is_depth_write_enabled(pCreateInfo) ||
968 radv_is_stencil_write_enabled(pCreateInfo);
969 }
970
971 static bool
972 radv_order_invariant_stencil_op(VkStencilOp op)
973 {
974 /* REPLACE is normally order invariant, except when the stencil
975 * reference value is written by the fragment shader. Tracking this
976 * interaction does not seem worth the effort, so be conservative.
977 */
978 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
979 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
980 op != VK_STENCIL_OP_REPLACE;
981 }
982
983 static bool
984 radv_order_invariant_stencil_state(const VkStencilOpState *state)
985 {
986 /* Compute whether, assuming Z writes are disabled, this stencil state
987 * is order invariant in the sense that the set of passing fragments as
988 * well as the final stencil buffer result does not depend on the order
989 * of fragments.
990 */
991 return !state->writeMask ||
992 /* The following assumes that Z writes are disabled. */
993 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
994 radv_order_invariant_stencil_op(state->passOp) &&
995 radv_order_invariant_stencil_op(state->depthFailOp)) ||
996 (state->compareOp == VK_COMPARE_OP_NEVER &&
997 radv_order_invariant_stencil_op(state->failOp));
998 }
999
1000 static bool
1001 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1002 struct radv_blend_state *blend,
1003 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1004 {
1005 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1006 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1007 unsigned colormask = blend->cb_target_enabled_4bit;
1008
1009 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1010 return false;
1011
1012 /* Be conservative if a logic operation is enabled with color buffers. */
1013 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1014 return false;
1015
1016 /* Default depth/stencil invariance when no attachment is bound. */
1017 struct radv_dsa_order_invariance dsa_order_invariant = {
1018 .zs = true, .pass_set = true
1019 };
1020
1021 if (pCreateInfo->pDepthStencilState &&
1022 subpass->depth_stencil_attachment) {
1023 const VkPipelineDepthStencilStateCreateInfo *vkds =
1024 pCreateInfo->pDepthStencilState;
1025 struct radv_render_pass_attachment *attachment =
1026 pass->attachments + subpass->depth_stencil_attachment->attachment;
1027 bool has_stencil = vk_format_is_stencil(attachment->format);
1028 struct radv_dsa_order_invariance order_invariance[2];
1029 struct radv_shader_variant *ps =
1030 pipeline->shaders[MESA_SHADER_FRAGMENT];
1031
1032 /* Compute depth/stencil order invariance in order to know if
1033 * it's safe to enable out-of-order.
1034 */
1035 bool zfunc_is_ordered =
1036 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1037 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1038 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1039 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1040 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1041
1042 bool nozwrite_and_order_invariant_stencil =
1043 !radv_is_ds_write_enabled(vkds) ||
1044 (!radv_is_depth_write_enabled(vkds) &&
1045 radv_order_invariant_stencil_state(&vkds->front) &&
1046 radv_order_invariant_stencil_state(&vkds->back));
1047
1048 order_invariance[1].zs =
1049 nozwrite_and_order_invariant_stencil ||
1050 (!radv_is_stencil_write_enabled(vkds) &&
1051 zfunc_is_ordered);
1052 order_invariance[0].zs =
1053 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1054
1055 order_invariance[1].pass_set =
1056 nozwrite_and_order_invariant_stencil ||
1057 (!radv_is_stencil_write_enabled(vkds) &&
1058 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1059 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1060 order_invariance[0].pass_set =
1061 !radv_is_depth_write_enabled(vkds) ||
1062 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1063 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1064
1065 dsa_order_invariant = order_invariance[has_stencil];
1066 if (!dsa_order_invariant.zs)
1067 return false;
1068
1069 /* The set of PS invocations is always order invariant,
1070 * except when early Z/S tests are requested.
1071 */
1072 if (ps &&
1073 ps->info.info.ps.writes_memory &&
1074 ps->info.fs.early_fragment_test &&
1075 !dsa_order_invariant.pass_set)
1076 return false;
1077
1078 /* Determine if out-of-order rasterization should be disabled
1079 * when occlusion queries are used.
1080 */
1081 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1082 !dsa_order_invariant.pass_set;
1083 }
1084
1085 /* No color buffers are enabled for writing. */
1086 if (!colormask)
1087 return true;
1088
1089 unsigned blendmask = colormask & blend->blend_enable_4bit;
1090
1091 if (blendmask) {
1092 /* Only commutative blending. */
1093 if (blendmask & ~blend->commutative_4bit)
1094 return false;
1095
1096 if (!dsa_order_invariant.pass_set)
1097 return false;
1098 }
1099
1100 if (colormask & ~blendmask)
1101 return false;
1102
1103 return true;
1104 }
1105
1106 static void
1107 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1108 struct radv_blend_state *blend,
1109 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1110 {
1111 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1112 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1113 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1114 bool out_of_order_rast = false;
1115 int ps_iter_samples = 1;
1116 uint32_t mask = 0xffff;
1117
1118 if (vkms)
1119 ms->num_samples = vkms->rasterizationSamples;
1120 else
1121 ms->num_samples = 1;
1122
1123 if (vkms)
1124 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1125 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1126 ps_iter_samples = ms->num_samples;
1127 }
1128
1129 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1130 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1131 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1132 /* Out-of-order rasterization is explicitly enabled by the
1133 * application.
1134 */
1135 out_of_order_rast = true;
1136 } else {
1137 /* Determine if the driver can enable out-of-order
1138 * rasterization internally.
1139 */
1140 out_of_order_rast =
1141 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1142 }
1143
1144 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1145 ms->pa_sc_aa_config = 0;
1146 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1147 S_028804_INCOHERENT_EQAA_READS(1) |
1148 S_028804_INTERPOLATE_COMP_Z(1) |
1149 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1150 ms->pa_sc_mode_cntl_1 =
1151 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1152 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1153 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1154 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1155 /* always 1: */
1156 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1157 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1158 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1159 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1160 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1161 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1162 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1163 S_028A48_VPORT_SCISSOR_ENABLE(1);
1164
1165 if (ms->num_samples > 1) {
1166 unsigned log_samples = util_logbase2(ms->num_samples);
1167 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1168 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1169 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1170 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1171 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1172 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1173 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1174 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1175 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1176 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1177 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1178 if (ps_iter_samples > 1)
1179 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1180 }
1181
1182 if (vkms && vkms->pSampleMask) {
1183 mask = vkms->pSampleMask[0] & 0xffff;
1184 }
1185
1186 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1187 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1188 }
1189
1190 static bool
1191 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1192 {
1193 switch (topology) {
1194 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1199 return false;
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1206 return true;
1207 default:
1208 unreachable("unhandled primitive type");
1209 }
1210 }
1211
1212 static uint32_t
1213 si_translate_prim(enum VkPrimitiveTopology topology)
1214 {
1215 switch (topology) {
1216 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1217 return V_008958_DI_PT_POINTLIST;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1219 return V_008958_DI_PT_LINELIST;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1221 return V_008958_DI_PT_LINESTRIP;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1223 return V_008958_DI_PT_TRILIST;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1225 return V_008958_DI_PT_TRISTRIP;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1227 return V_008958_DI_PT_TRIFAN;
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1229 return V_008958_DI_PT_LINELIST_ADJ;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1231 return V_008958_DI_PT_LINESTRIP_ADJ;
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1233 return V_008958_DI_PT_TRILIST_ADJ;
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1235 return V_008958_DI_PT_TRISTRIP_ADJ;
1236 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1237 return V_008958_DI_PT_PATCH;
1238 default:
1239 assert(0);
1240 return 0;
1241 }
1242 }
1243
1244 static uint32_t
1245 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1246 {
1247 switch (gl_prim) {
1248 case 0: /* GL_POINTS */
1249 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1250 case 1: /* GL_LINES */
1251 case 3: /* GL_LINE_STRIP */
1252 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1253 case 0x8E7A: /* GL_ISOLINES */
1254 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1255
1256 case 4: /* GL_TRIANGLES */
1257 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1258 case 5: /* GL_TRIANGLE_STRIP */
1259 case 7: /* GL_QUADS */
1260 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1261 default:
1262 assert(0);
1263 return 0;
1264 }
1265 }
1266
1267 static uint32_t
1268 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1269 {
1270 switch (topology) {
1271 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1272 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1273 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1278 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1284 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1285 default:
1286 assert(0);
1287 return 0;
1288 }
1289 }
1290
1291 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1292 {
1293 switch(state) {
1294 case VK_DYNAMIC_STATE_VIEWPORT:
1295 return RADV_DYNAMIC_VIEWPORT;
1296 case VK_DYNAMIC_STATE_SCISSOR:
1297 return RADV_DYNAMIC_SCISSOR;
1298 case VK_DYNAMIC_STATE_LINE_WIDTH:
1299 return RADV_DYNAMIC_LINE_WIDTH;
1300 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1301 return RADV_DYNAMIC_DEPTH_BIAS;
1302 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1303 return RADV_DYNAMIC_BLEND_CONSTANTS;
1304 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1305 return RADV_DYNAMIC_DEPTH_BOUNDS;
1306 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1307 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1308 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1309 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1310 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1311 return RADV_DYNAMIC_STENCIL_REFERENCE;
1312 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1313 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1314 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1315 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1316 default:
1317 unreachable("Unhandled dynamic state");
1318 }
1319 }
1320
1321 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1322 {
1323 uint32_t states = RADV_DYNAMIC_ALL;
1324
1325 /* If rasterization is disabled we do not care about any of the dynamic states,
1326 * since they are all rasterization related only. */
1327 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1328 return 0;
1329
1330 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1331 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1332
1333 if (!pCreateInfo->pDepthStencilState ||
1334 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1335 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1336
1337 if (!pCreateInfo->pDepthStencilState ||
1338 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1339 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1340 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1341 RADV_DYNAMIC_STENCIL_REFERENCE);
1342
1343 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1344 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1345
1346 if (!pCreateInfo->pMultisampleState ||
1347 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1348 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1349 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1350
1351 /* TODO: blend constants & line width. */
1352
1353 return states;
1354 }
1355
1356
1357 static void
1358 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1359 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1360 {
1361 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1362 uint32_t states = needed_states;
1363 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1364 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1365
1366 pipeline->dynamic_state = default_dynamic_state;
1367 pipeline->graphics.needed_dynamic_state = needed_states;
1368
1369 if (pCreateInfo->pDynamicState) {
1370 /* Remove all of the states that are marked as dynamic */
1371 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1372 for (uint32_t s = 0; s < count; s++)
1373 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1374 }
1375
1376 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1377
1378 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1379 assert(pCreateInfo->pViewportState);
1380
1381 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1382 if (states & RADV_DYNAMIC_VIEWPORT) {
1383 typed_memcpy(dynamic->viewport.viewports,
1384 pCreateInfo->pViewportState->pViewports,
1385 pCreateInfo->pViewportState->viewportCount);
1386 }
1387 }
1388
1389 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1390 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1391 if (states & RADV_DYNAMIC_SCISSOR) {
1392 typed_memcpy(dynamic->scissor.scissors,
1393 pCreateInfo->pViewportState->pScissors,
1394 pCreateInfo->pViewportState->scissorCount);
1395 }
1396 }
1397
1398 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1399 assert(pCreateInfo->pRasterizationState);
1400 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1401 }
1402
1403 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1404 assert(pCreateInfo->pRasterizationState);
1405 dynamic->depth_bias.bias =
1406 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1407 dynamic->depth_bias.clamp =
1408 pCreateInfo->pRasterizationState->depthBiasClamp;
1409 dynamic->depth_bias.slope =
1410 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1411 }
1412
1413 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1414 *
1415 * pColorBlendState is [...] NULL if the pipeline has rasterization
1416 * disabled or if the subpass of the render pass the pipeline is
1417 * created against does not use any color attachments.
1418 */
1419 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1420 assert(pCreateInfo->pColorBlendState);
1421 typed_memcpy(dynamic->blend_constants,
1422 pCreateInfo->pColorBlendState->blendConstants, 4);
1423 }
1424
1425 /* If there is no depthstencil attachment, then don't read
1426 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1427 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1428 * no need to override the depthstencil defaults in
1429 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1430 *
1431 * Section 9.2 of the Vulkan 1.0.15 spec says:
1432 *
1433 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1434 * disabled or if the subpass of the render pass the pipeline is created
1435 * against does not use a depth/stencil attachment.
1436 */
1437 if (needed_states && subpass->depth_stencil_attachment) {
1438 assert(pCreateInfo->pDepthStencilState);
1439
1440 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1441 dynamic->depth_bounds.min =
1442 pCreateInfo->pDepthStencilState->minDepthBounds;
1443 dynamic->depth_bounds.max =
1444 pCreateInfo->pDepthStencilState->maxDepthBounds;
1445 }
1446
1447 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1448 dynamic->stencil_compare_mask.front =
1449 pCreateInfo->pDepthStencilState->front.compareMask;
1450 dynamic->stencil_compare_mask.back =
1451 pCreateInfo->pDepthStencilState->back.compareMask;
1452 }
1453
1454 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1455 dynamic->stencil_write_mask.front =
1456 pCreateInfo->pDepthStencilState->front.writeMask;
1457 dynamic->stencil_write_mask.back =
1458 pCreateInfo->pDepthStencilState->back.writeMask;
1459 }
1460
1461 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1462 dynamic->stencil_reference.front =
1463 pCreateInfo->pDepthStencilState->front.reference;
1464 dynamic->stencil_reference.back =
1465 pCreateInfo->pDepthStencilState->back.reference;
1466 }
1467 }
1468
1469 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1470 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1471 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1472 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1473 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1474 typed_memcpy(dynamic->discard_rectangle.rectangles,
1475 discard_rectangle_info->pDiscardRectangles,
1476 discard_rectangle_info->discardRectangleCount);
1477 }
1478 }
1479
1480 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1481 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1482 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1483 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1484 /* If sampleLocationsEnable is VK_FALSE, the default sample
1485 * locations are used and the values specified in
1486 * sampleLocationsInfo are ignored.
1487 */
1488 if (sample_location_info->sampleLocationsEnable) {
1489 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1490 &sample_location_info->sampleLocationsInfo;
1491
1492 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1493
1494 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1495 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1496 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1497 typed_memcpy(&dynamic->sample_location.locations[0],
1498 pSampleLocationsInfo->pSampleLocations,
1499 pSampleLocationsInfo->sampleLocationsCount);
1500 }
1501 }
1502
1503 pipeline->dynamic_state.mask = states;
1504 }
1505
1506 static struct radv_gs_state
1507 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1508 const struct radv_pipeline *pipeline)
1509 {
1510 struct radv_gs_state gs = {0};
1511 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1512 struct radv_es_output_info *es_info;
1513 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1514 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1515 else
1516 es_info = radv_pipeline_has_tess(pipeline) ?
1517 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1518 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1519
1520 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1521 bool uses_adjacency;
1522 switch(pCreateInfo->pInputAssemblyState->topology) {
1523 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1525 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1527 uses_adjacency = true;
1528 break;
1529 default:
1530 uses_adjacency = false;
1531 break;
1532 }
1533
1534 /* All these are in dwords: */
1535 /* We can't allow using the whole LDS, because GS waves compete with
1536 * other shader stages for LDS space. */
1537 const unsigned max_lds_size = 8 * 1024;
1538 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1539 unsigned esgs_lds_size;
1540
1541 /* All these are per subgroup: */
1542 const unsigned max_out_prims = 32 * 1024;
1543 const unsigned max_es_verts = 255;
1544 const unsigned ideal_gs_prims = 64;
1545 unsigned max_gs_prims, gs_prims;
1546 unsigned min_es_verts, es_verts, worst_case_es_verts;
1547
1548 if (uses_adjacency || gs_num_invocations > 1)
1549 max_gs_prims = 127 / gs_num_invocations;
1550 else
1551 max_gs_prims = 255;
1552
1553 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1554 * Make sure we don't go over the maximum value.
1555 */
1556 if (gs_info->gs.vertices_out > 0) {
1557 max_gs_prims = MIN2(max_gs_prims,
1558 max_out_prims /
1559 (gs_info->gs.vertices_out * gs_num_invocations));
1560 }
1561 assert(max_gs_prims > 0);
1562
1563 /* If the primitive has adjacency, halve the number of vertices
1564 * that will be reused in multiple primitives.
1565 */
1566 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1567
1568 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1569 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1570
1571 /* Compute ESGS LDS size based on the worst case number of ES vertices
1572 * needed to create the target number of GS prims per subgroup.
1573 */
1574 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1575
1576 /* If total LDS usage is too big, refactor partitions based on ratio
1577 * of ESGS item sizes.
1578 */
1579 if (esgs_lds_size > max_lds_size) {
1580 /* Our target GS Prims Per Subgroup was too large. Calculate
1581 * the maximum number of GS Prims Per Subgroup that will fit
1582 * into LDS, capped by the maximum that the hardware can support.
1583 */
1584 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1585 max_gs_prims);
1586 assert(gs_prims > 0);
1587 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1588 max_es_verts);
1589
1590 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1591 assert(esgs_lds_size <= max_lds_size);
1592 }
1593
1594 /* Now calculate remaining ESGS information. */
1595 if (esgs_lds_size)
1596 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1597 else
1598 es_verts = max_es_verts;
1599
1600 /* Vertices for adjacency primitives are not always reused, so restore
1601 * it for ES_VERTS_PER_SUBGRP.
1602 */
1603 min_es_verts = gs_info->gs.vertices_in;
1604
1605 /* For normal primitives, the VGT only checks if they are past the ES
1606 * verts per subgroup after allocating a full GS primitive and if they
1607 * are, kick off a new subgroup. But if those additional ES verts are
1608 * unique (e.g. not reused) we need to make sure there is enough LDS
1609 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1610 */
1611 es_verts -= min_es_verts - 1;
1612
1613 uint32_t es_verts_per_subgroup = es_verts;
1614 uint32_t gs_prims_per_subgroup = gs_prims;
1615 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1616 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1617 gs.lds_size = align(esgs_lds_size, 128) / 128;
1618 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1619 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1620 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1621 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1622 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1623 assert(max_prims_per_subgroup <= max_out_prims);
1624
1625 return gs;
1626 }
1627
1628 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1629 unsigned min_verts_per_prim, bool use_adjacency)
1630 {
1631 unsigned max_reuse = max_esverts - min_verts_per_prim;
1632 if (use_adjacency)
1633 max_reuse /= 2;
1634 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1635 }
1636
1637 static unsigned
1638 radv_get_num_input_vertices(struct radv_pipeline *pipeline)
1639 {
1640 if (radv_pipeline_has_gs(pipeline)) {
1641 struct radv_shader_variant *gs =
1642 radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
1643
1644 return gs->info.gs.vertices_in;
1645 }
1646
1647 if (radv_pipeline_has_tess(pipeline)) {
1648 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1649
1650 if (tes->info.tes.point_mode)
1651 return 1;
1652 if (tes->info.tes.primitive_mode == GL_ISOLINES)
1653 return 2;
1654 return 3;
1655 }
1656
1657 return 3;
1658 }
1659
1660 static struct radv_ngg_state
1661 calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1662 struct radv_pipeline *pipeline)
1663 {
1664 struct radv_ngg_state ngg = {0};
1665 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1666 struct radv_es_output_info *es_info =
1667 radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1668 unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1669 unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
1670 unsigned min_verts_per_prim =
1671 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1672 unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1;
1673 bool uses_adjacency;
1674 switch(pCreateInfo->pInputAssemblyState->topology) {
1675 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1676 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1677 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1678 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1679 uses_adjacency = true;
1680 break;
1681 default:
1682 uses_adjacency = false;
1683 break;
1684 }
1685
1686 /* All these are in dwords: */
1687 /* We can't allow using the whole LDS, because GS waves compete with
1688 * other shader stages for LDS space.
1689 *
1690 * Streamout can increase the ESGS buffer size later on, so be more
1691 * conservative with streamout and use 4K dwords. This may be suboptimal.
1692 *
1693 * Otherwise, use the limit of 7K dwords. The reason is that we need
1694 * to leave some headroom for the max_esverts increase at the end.
1695 *
1696 * TODO: We should really take the shader's internal LDS use into
1697 * account. The linker will fail if the size is greater than
1698 * 8K dwords.
1699 */
1700 const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1701 const unsigned target_lds_size = max_lds_size;
1702 unsigned esvert_lds_size = 0;
1703 unsigned gsprim_lds_size = 0;
1704
1705 /* All these are per subgroup: */
1706 bool max_vert_out_per_gs_instance = false;
1707 unsigned max_esverts_base = 256;
1708 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1709
1710 /* Hardware has the following non-natural restrictions on the value
1711 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1712 * the draw:
1713 * - at most 252 for any line input primitive type
1714 * - at most 251 for any quad input primitive type
1715 * - at most 251 for triangle strips with adjacency (this happens to
1716 * be the natural limit for triangle *lists* with adjacency)
1717 */
1718 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1719
1720 if (gs_type == MESA_SHADER_GEOMETRY) {
1721 unsigned max_out_verts_per_gsprim =
1722 gs_info->gs.vertices_out * gs_num_invocations;
1723
1724 if (max_out_verts_per_gsprim <= 256) {
1725 if (max_out_verts_per_gsprim) {
1726 max_gsprims_base = MIN2(max_gsprims_base,
1727 256 / max_out_verts_per_gsprim);
1728 }
1729 } else {
1730 /* Use special multi-cycling mode in which each GS
1731 * instance gets its own subgroup. Does not work with
1732 * tessellation. */
1733 max_vert_out_per_gs_instance = true;
1734 max_gsprims_base = 1;
1735 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1736 }
1737
1738 esvert_lds_size = es_info->esgs_itemsize / 4;
1739 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1740 } else {
1741 /* TODO: This needs to be adjusted once LDS use for compaction
1742 * after culling is implemented. */
1743 /*
1744 if (es_info->info.so.num_outputs)
1745 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1746 */
1747 }
1748
1749 unsigned max_gsprims = max_gsprims_base;
1750 unsigned max_esverts = max_esverts_base;
1751
1752 if (esvert_lds_size)
1753 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1754 if (gsprim_lds_size)
1755 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1756
1757 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1758 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1759 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1760
1761 if (esvert_lds_size || gsprim_lds_size) {
1762 /* Now that we have a rough proportionality between esverts
1763 * and gsprims based on the primitive type, scale both of them
1764 * down simultaneously based on required LDS space.
1765 *
1766 * We could be smarter about this if we knew how much vertex
1767 * reuse to expect.
1768 */
1769 unsigned lds_total = max_esverts * esvert_lds_size +
1770 max_gsprims * gsprim_lds_size;
1771 if (lds_total > target_lds_size) {
1772 max_esverts = max_esverts * target_lds_size / lds_total;
1773 max_gsprims = max_gsprims * target_lds_size / lds_total;
1774
1775 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1776 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1777 min_verts_per_prim, uses_adjacency);
1778 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1779 }
1780 }
1781
1782 /* Round up towards full wave sizes for better ALU utilization. */
1783 if (!max_vert_out_per_gs_instance) {
1784 const unsigned wavesize = 64;
1785 unsigned orig_max_esverts;
1786 unsigned orig_max_gsprims;
1787 do {
1788 orig_max_esverts = max_esverts;
1789 orig_max_gsprims = max_gsprims;
1790
1791 max_esverts = align(max_esverts, wavesize);
1792 max_esverts = MIN2(max_esverts, max_esverts_base);
1793 if (esvert_lds_size)
1794 max_esverts = MIN2(max_esverts,
1795 (max_lds_size - max_gsprims * gsprim_lds_size) /
1796 esvert_lds_size);
1797 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1798
1799 max_gsprims = align(max_gsprims, wavesize);
1800 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1801 if (gsprim_lds_size)
1802 max_gsprims = MIN2(max_gsprims,
1803 (max_lds_size - max_esverts * esvert_lds_size) /
1804 gsprim_lds_size);
1805 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1806 min_verts_per_prim, uses_adjacency);
1807 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1808 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1809 }
1810
1811 /* Hardware restriction: minimum value of max_esverts */
1812 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1813
1814 unsigned max_out_vertices =
1815 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1816 gs_type == MESA_SHADER_GEOMETRY ?
1817 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1818 max_esverts;
1819 assert(max_out_vertices <= 256);
1820
1821 unsigned prim_amp_factor = 1;
1822 if (gs_type == MESA_SHADER_GEOMETRY) {
1823 /* Number of output primitives per GS input primitive after
1824 * GS instancing. */
1825 prim_amp_factor = gs_info->gs.vertices_out;
1826 }
1827
1828 /* The GE only checks against the maximum number of ES verts after
1829 * allocating a full GS primitive. So we need to ensure that whenever
1830 * this check passes, there is enough space for a full primitive without
1831 * vertex reuse.
1832 */
1833 ngg.hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1834 ngg.max_gsprims = max_gsprims;
1835 ngg.max_out_verts = max_out_vertices;
1836 ngg.prim_amp_factor = prim_amp_factor;
1837 ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1838 ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
1839
1840 if (gs_type == MESA_SHADER_GEOMETRY) {
1841 ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1842 } else {
1843 ngg.vgt_esgs_ring_itemsize = 1;
1844 }
1845
1846 pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1847
1848 assert(ngg.hw_max_esverts >= 24); /* HW limitation */
1849
1850 return ngg;
1851 }
1852
1853 static void
1854 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1855 {
1856 struct radv_device *device = pipeline->device;
1857 unsigned num_se = device->physical_device->rad_info.max_se;
1858 unsigned wave_size = 64;
1859 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1860 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1861 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1862 */
1863 unsigned gs_vertex_reuse =
1864 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1865 unsigned alignment = 256 * num_se;
1866 /* The maximum size is 63.999 MB per SE. */
1867 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1868 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1869
1870 /* Calculate the minimum size. */
1871 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1872 wave_size, alignment);
1873 /* These are recommended sizes, not minimum sizes. */
1874 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1875 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1876 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1877 gs_info->gs.max_gsvs_emit_size;
1878
1879 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1880 esgs_ring_size = align(esgs_ring_size, alignment);
1881 gsvs_ring_size = align(gsvs_ring_size, alignment);
1882
1883 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1884 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1885
1886 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1887 }
1888
1889 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1890 unsigned *lds_size)
1891 {
1892 /* If tessellation is all offchip and on-chip GS isn't used, this
1893 * workaround is not needed.
1894 */
1895 return;
1896
1897 /* SPI barrier management bug:
1898 * Make sure we have at least 4k of LDS in use to avoid the bug.
1899 * It applies to workgroup sizes of more than one wavefront.
1900 */
1901 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1902 device->physical_device->rad_info.family == CHIP_KABINI)
1903 *lds_size = MAX2(*lds_size, 8);
1904 }
1905
1906 struct radv_shader_variant *
1907 radv_get_shader(struct radv_pipeline *pipeline,
1908 gl_shader_stage stage)
1909 {
1910 if (stage == MESA_SHADER_VERTEX) {
1911 if (pipeline->shaders[MESA_SHADER_VERTEX])
1912 return pipeline->shaders[MESA_SHADER_VERTEX];
1913 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1914 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1915 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1916 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1917 } else if (stage == MESA_SHADER_TESS_EVAL) {
1918 if (!radv_pipeline_has_tess(pipeline))
1919 return NULL;
1920 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1921 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1922 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1923 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1924 }
1925 return pipeline->shaders[stage];
1926 }
1927
1928 static struct radv_tessellation_state
1929 calculate_tess_state(struct radv_pipeline *pipeline,
1930 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1931 {
1932 unsigned num_tcs_input_cp;
1933 unsigned num_tcs_output_cp;
1934 unsigned lds_size;
1935 unsigned num_patches;
1936 struct radv_tessellation_state tess = {0};
1937
1938 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1939 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1940 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1941
1942 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1943
1944 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1945 assert(lds_size <= 65536);
1946 lds_size = align(lds_size, 512) / 512;
1947 } else {
1948 assert(lds_size <= 32768);
1949 lds_size = align(lds_size, 256) / 256;
1950 }
1951 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1952
1953 tess.lds_size = lds_size;
1954
1955 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1956 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1957 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1958 tess.num_patches = num_patches;
1959
1960 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1961 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1962
1963 switch (tes->info.tes.primitive_mode) {
1964 case GL_TRIANGLES:
1965 type = V_028B6C_TESS_TRIANGLE;
1966 break;
1967 case GL_QUADS:
1968 type = V_028B6C_TESS_QUAD;
1969 break;
1970 case GL_ISOLINES:
1971 type = V_028B6C_TESS_ISOLINE;
1972 break;
1973 }
1974
1975 switch (tes->info.tes.spacing) {
1976 case TESS_SPACING_EQUAL:
1977 partitioning = V_028B6C_PART_INTEGER;
1978 break;
1979 case TESS_SPACING_FRACTIONAL_ODD:
1980 partitioning = V_028B6C_PART_FRAC_ODD;
1981 break;
1982 case TESS_SPACING_FRACTIONAL_EVEN:
1983 partitioning = V_028B6C_PART_FRAC_EVEN;
1984 break;
1985 default:
1986 break;
1987 }
1988
1989 bool ccw = tes->info.tes.ccw;
1990 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1991 vk_find_struct_const(pCreateInfo->pTessellationState,
1992 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1993
1994 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1995 ccw = !ccw;
1996
1997 if (tes->info.tes.point_mode)
1998 topology = V_028B6C_OUTPUT_POINT;
1999 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2000 topology = V_028B6C_OUTPUT_LINE;
2001 else if (ccw)
2002 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2003 else
2004 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2005
2006 if (pipeline->device->has_distributed_tess) {
2007 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2008 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2009 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2010 else
2011 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2012 } else
2013 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2014
2015 tess.tf_param = S_028B6C_TYPE(type) |
2016 S_028B6C_PARTITIONING(partitioning) |
2017 S_028B6C_TOPOLOGY(topology) |
2018 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2019
2020 return tess;
2021 }
2022
2023 static const struct radv_prim_vertex_count prim_size_table[] = {
2024 [V_008958_DI_PT_NONE] = {0, 0},
2025 [V_008958_DI_PT_POINTLIST] = {1, 1},
2026 [V_008958_DI_PT_LINELIST] = {2, 2},
2027 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2028 [V_008958_DI_PT_TRILIST] = {3, 3},
2029 [V_008958_DI_PT_TRIFAN] = {3, 1},
2030 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2031 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2032 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2033 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2034 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2035 [V_008958_DI_PT_RECTLIST] = {3, 3},
2036 [V_008958_DI_PT_LINELOOP] = {2, 1},
2037 [V_008958_DI_PT_POLYGON] = {3, 1},
2038 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2039 };
2040
2041 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2042 {
2043 if (radv_pipeline_has_gs(pipeline))
2044 if (radv_pipeline_has_ngg(pipeline))
2045 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2046 else
2047 return &pipeline->gs_copy_shader->info.vs.outinfo;
2048 else if (radv_pipeline_has_tess(pipeline))
2049 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2050 else
2051 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2052 }
2053
2054 static void
2055 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2056 {
2057 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2058 int shader_count = 0;
2059
2060 if(shaders[MESA_SHADER_FRAGMENT]) {
2061 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2062 }
2063 if(shaders[MESA_SHADER_GEOMETRY]) {
2064 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2065 }
2066 if(shaders[MESA_SHADER_TESS_EVAL]) {
2067 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2068 }
2069 if(shaders[MESA_SHADER_TESS_CTRL]) {
2070 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2071 }
2072 if(shaders[MESA_SHADER_VERTEX]) {
2073 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2074 }
2075
2076 if (shader_count > 1) {
2077 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2078 unsigned last = ordered_shaders[0]->info.stage;
2079
2080 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2081 ordered_shaders[1]->info.has_transform_feedback_varyings)
2082 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2083
2084 for (int i = 0; i < shader_count; ++i) {
2085 nir_variable_mode mask = 0;
2086
2087 if (ordered_shaders[i]->info.stage != first)
2088 mask = mask | nir_var_shader_in;
2089
2090 if (ordered_shaders[i]->info.stage != last)
2091 mask = mask | nir_var_shader_out;
2092
2093 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2094 radv_optimize_nir(ordered_shaders[i], false, false);
2095 }
2096 }
2097
2098 for (int i = 1; i < shader_count; ++i) {
2099 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2100 ordered_shaders[i - 1]);
2101
2102 if (nir_link_opt_varyings(ordered_shaders[i],
2103 ordered_shaders[i - 1]))
2104 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2105
2106 nir_remove_dead_variables(ordered_shaders[i],
2107 nir_var_shader_out);
2108 nir_remove_dead_variables(ordered_shaders[i - 1],
2109 nir_var_shader_in);
2110
2111 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2112 ordered_shaders[i - 1]);
2113
2114 nir_compact_varyings(ordered_shaders[i],
2115 ordered_shaders[i - 1], true);
2116
2117 if (progress) {
2118 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2119 ac_lower_indirect_derefs(ordered_shaders[i],
2120 pipeline->device->physical_device->rad_info.chip_class);
2121 }
2122 radv_optimize_nir(ordered_shaders[i], false, false);
2123
2124 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2125 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2126 pipeline->device->physical_device->rad_info.chip_class);
2127 }
2128 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2129 }
2130 }
2131 }
2132
2133 static uint32_t
2134 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2135 uint32_t attrib_binding)
2136 {
2137 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2138 const VkVertexInputBindingDescription *input_binding =
2139 &input_state->pVertexBindingDescriptions[i];
2140
2141 if (input_binding->binding == attrib_binding)
2142 return input_binding->stride;
2143 }
2144
2145 return 0;
2146 }
2147
2148 static struct radv_pipeline_key
2149 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2150 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2151 const struct radv_blend_state *blend,
2152 bool has_view_index)
2153 {
2154 const VkPipelineVertexInputStateCreateInfo *input_state =
2155 pCreateInfo->pVertexInputState;
2156 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2157 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2158
2159 struct radv_pipeline_key key;
2160 memset(&key, 0, sizeof(key));
2161
2162 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2163 key.optimisations_disabled = 1;
2164
2165 key.has_multiview_view_index = has_view_index;
2166
2167 uint32_t binding_input_rate = 0;
2168 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2169 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2170 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2171 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2172 binding_input_rate |= 1u << binding;
2173 instance_rate_divisors[binding] = 1;
2174 }
2175 }
2176 if (divisor_state) {
2177 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2178 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2179 divisor_state->pVertexBindingDivisors[i].divisor;
2180 }
2181 }
2182
2183 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2184 const VkVertexInputAttributeDescription *desc =
2185 &input_state->pVertexAttributeDescriptions[i];
2186 const struct vk_format_description *format_desc;
2187 unsigned location = desc->location;
2188 unsigned binding = desc->binding;
2189 unsigned num_format, data_format;
2190 int first_non_void;
2191
2192 if (binding_input_rate & (1u << binding)) {
2193 key.instance_rate_inputs |= 1u << location;
2194 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2195 }
2196
2197 format_desc = vk_format_description(desc->format);
2198 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2199
2200 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2201 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2202
2203 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2204 key.vertex_attribute_bindings[location] = desc->binding;
2205 key.vertex_attribute_offsets[location] = desc->offset;
2206 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2207
2208 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2209 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2210 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2211 uint64_t adjust;
2212 switch(format) {
2213 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2214 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2215 adjust = RADV_ALPHA_ADJUST_SNORM;
2216 break;
2217 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2218 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2219 adjust = RADV_ALPHA_ADJUST_SSCALED;
2220 break;
2221 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2222 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2223 adjust = RADV_ALPHA_ADJUST_SINT;
2224 break;
2225 default:
2226 adjust = 0;
2227 break;
2228 }
2229 key.vertex_alpha_adjust |= adjust << (2 * location);
2230 }
2231
2232 switch (desc->format) {
2233 case VK_FORMAT_B8G8R8A8_UNORM:
2234 case VK_FORMAT_B8G8R8A8_SNORM:
2235 case VK_FORMAT_B8G8R8A8_USCALED:
2236 case VK_FORMAT_B8G8R8A8_SSCALED:
2237 case VK_FORMAT_B8G8R8A8_UINT:
2238 case VK_FORMAT_B8G8R8A8_SINT:
2239 case VK_FORMAT_B8G8R8A8_SRGB:
2240 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2241 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2242 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2243 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2244 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2245 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2246 key.vertex_post_shuffle |= 1 << location;
2247 break;
2248 default:
2249 break;
2250 }
2251 }
2252
2253 if (pCreateInfo->pTessellationState)
2254 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2255
2256
2257 if (pCreateInfo->pMultisampleState &&
2258 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2259 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2260 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2261 key.num_samples = num_samples;
2262 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2263 }
2264
2265 key.col_format = blend->spi_shader_col_format;
2266 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2267 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2268
2269 return key;
2270 }
2271
2272 static void
2273 radv_fill_shader_keys(struct radv_device *device,
2274 struct radv_shader_variant_key *keys,
2275 const struct radv_pipeline_key *key,
2276 nir_shader **nir)
2277 {
2278 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2279 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2280 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2281 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2282 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2283 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2284 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2285 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2286 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2287 }
2288
2289 if (nir[MESA_SHADER_TESS_CTRL]) {
2290 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2291 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2292 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2293 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2294
2295 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2296 }
2297
2298 if (nir[MESA_SHADER_GEOMETRY]) {
2299 if (nir[MESA_SHADER_TESS_CTRL])
2300 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2301 else
2302 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2303 }
2304
2305 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2306 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2307 if (nir[MESA_SHADER_TESS_CTRL]) {
2308 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2309 } else {
2310 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2311 }
2312
2313 if (nir[MESA_SHADER_TESS_CTRL] &&
2314 nir[MESA_SHADER_GEOMETRY] &&
2315 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2316 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2317 /* Fallback to the legacy path if tessellation is
2318 * enabled with extreme geometry because
2319 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2320 * might hang.
2321 */
2322 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2323 }
2324 }
2325
2326 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2327 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2328
2329 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2330 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2331 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2332 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2333 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2334 }
2335
2336 static void
2337 merge_tess_info(struct shader_info *tes_info,
2338 const struct shader_info *tcs_info)
2339 {
2340 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2341 *
2342 * "PointMode. Controls generation of points rather than triangles
2343 * or lines. This functionality defaults to disabled, and is
2344 * enabled if either shader stage includes the execution mode.
2345 *
2346 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2347 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2348 * and OutputVertices, it says:
2349 *
2350 * "One mode must be set in at least one of the tessellation
2351 * shader stages."
2352 *
2353 * So, the fields can be set in either the TCS or TES, but they must
2354 * agree if set in both. Our backend looks at TES, so bitwise-or in
2355 * the values from the TCS.
2356 */
2357 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2358 tes_info->tess.tcs_vertices_out == 0 ||
2359 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2360 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2361
2362 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2363 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2364 tcs_info->tess.spacing == tes_info->tess.spacing);
2365 tes_info->tess.spacing |= tcs_info->tess.spacing;
2366
2367 assert(tcs_info->tess.primitive_mode == 0 ||
2368 tes_info->tess.primitive_mode == 0 ||
2369 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2370 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2371 tes_info->tess.ccw |= tcs_info->tess.ccw;
2372 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2373 }
2374
2375 static
2376 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2377 {
2378 if (!ext)
2379 return;
2380
2381 if (ext->pPipelineCreationFeedback) {
2382 ext->pPipelineCreationFeedback->flags = 0;
2383 ext->pPipelineCreationFeedback->duration = 0;
2384 }
2385
2386 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2387 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2388 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2389 }
2390 }
2391
2392 static
2393 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2394 {
2395 if (!feedback)
2396 return;
2397
2398 feedback->duration -= radv_get_current_time();
2399 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2400 }
2401
2402 static
2403 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2404 {
2405 if (!feedback)
2406 return;
2407
2408 feedback->duration += radv_get_current_time();
2409 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2410 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2411 }
2412
2413 static
2414 void radv_create_shaders(struct radv_pipeline *pipeline,
2415 struct radv_device *device,
2416 struct radv_pipeline_cache *cache,
2417 const struct radv_pipeline_key *key,
2418 const VkPipelineShaderStageCreateInfo **pStages,
2419 const VkPipelineCreateFlags flags,
2420 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2421 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2422 {
2423 struct radv_shader_module fs_m = {0};
2424 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2425 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2426 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2427 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2428 unsigned char hash[20], gs_copy_hash[20];
2429
2430 radv_start_feedback(pipeline_feedback);
2431
2432 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2433 if (pStages[i]) {
2434 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2435 if (modules[i]->nir)
2436 _mesa_sha1_compute(modules[i]->nir->info.name,
2437 strlen(modules[i]->nir->info.name),
2438 modules[i]->sha1);
2439
2440 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2441 }
2442 }
2443
2444 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2445 memcpy(gs_copy_hash, hash, 20);
2446 gs_copy_hash[0] ^= 1;
2447
2448 bool found_in_application_cache = true;
2449 if (modules[MESA_SHADER_GEOMETRY]) {
2450 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2451 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2452 &found_in_application_cache);
2453 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2454 }
2455
2456 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2457 &found_in_application_cache) &&
2458 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2459 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2460 return;
2461 }
2462
2463 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2464 nir_builder fs_b;
2465 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2466 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2467 fs_m.nir = fs_b.shader;
2468 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2469 }
2470
2471 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2472 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2473
2474 if (!modules[i])
2475 continue;
2476
2477 radv_start_feedback(stage_feedbacks[i]);
2478
2479 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2480 stage ? stage->pName : "main", i,
2481 stage ? stage->pSpecializationInfo : NULL,
2482 flags, pipeline->layout);
2483
2484 /* We don't want to alter meta shaders IR directly so clone it
2485 * first.
2486 */
2487 if (nir[i]->info.name) {
2488 nir[i] = nir_shader_clone(NULL, nir[i]);
2489 }
2490
2491 radv_stop_feedback(stage_feedbacks[i], false);
2492 }
2493
2494 if (nir[MESA_SHADER_TESS_CTRL]) {
2495 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2496 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2497 }
2498
2499 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2500 radv_link_shaders(pipeline, nir);
2501
2502 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2503 if (nir[i]) {
2504 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2505 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2506 nir_lower_non_uniform_ubo_access |
2507 nir_lower_non_uniform_ssbo_access |
2508 nir_lower_non_uniform_texture_access |
2509 nir_lower_non_uniform_image_access);
2510 }
2511
2512 if (radv_can_dump_shader(device, modules[i], false))
2513 nir_print_shader(nir[i], stderr);
2514 }
2515
2516 radv_fill_shader_keys(device, keys, key, nir);
2517
2518 if (nir[MESA_SHADER_FRAGMENT]) {
2519 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2520 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2521
2522 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2523 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2524 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2525 &binaries[MESA_SHADER_FRAGMENT]);
2526
2527 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2528 }
2529
2530 /* TODO: These are no longer used as keys we should refactor this */
2531 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2532 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2533 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2534 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2535 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2536 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2537 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2538 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2539 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2540 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2541 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2542 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2543 }
2544
2545 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2546 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2547 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2548 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2549 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2550
2551 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2552
2553 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2554 pipeline->layout,
2555 &key, &binaries[MESA_SHADER_TESS_CTRL]);
2556
2557 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2558 }
2559 modules[MESA_SHADER_VERTEX] = NULL;
2560 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2561 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2562 }
2563
2564 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2565 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2566 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2567 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2568
2569 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2570
2571 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2572 pipeline->layout,
2573 &keys[pre_stage] , &binaries[MESA_SHADER_GEOMETRY]);
2574
2575 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2576 }
2577 modules[pre_stage] = NULL;
2578 }
2579
2580 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2581 if(modules[i] && !pipeline->shaders[i]) {
2582 if (i == MESA_SHADER_TESS_CTRL) {
2583 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2584 }
2585 if (i == MESA_SHADER_TESS_EVAL) {
2586 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2587 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2588 }
2589
2590 radv_start_feedback(stage_feedbacks[i]);
2591
2592 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2593 pipeline->layout,
2594 keys + i, &binaries[i]);
2595
2596 radv_stop_feedback(stage_feedbacks[i], false);
2597 }
2598 }
2599
2600 if(modules[MESA_SHADER_GEOMETRY]) {
2601 struct radv_shader_binary *gs_copy_binary = NULL;
2602 if (!pipeline->gs_copy_shader) {
2603 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2604 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
2605 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2606 }
2607
2608 if (pipeline->gs_copy_shader) {
2609 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2610 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2611
2612 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2613 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2614
2615 radv_pipeline_cache_insert_shaders(device, cache,
2616 gs_copy_hash,
2617 variants,
2618 binaries);
2619 }
2620 free(gs_copy_binary);
2621 }
2622
2623 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2624 binaries);
2625
2626 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2627 free(binaries[i]);
2628 if (nir[i]) {
2629 if (!pipeline->device->keep_shader_info)
2630 ralloc_free(nir[i]);
2631
2632 if (radv_can_dump_shader_stats(device, modules[i]))
2633 radv_shader_dump_stats(device,
2634 pipeline->shaders[i],
2635 i, stderr);
2636 }
2637 }
2638
2639 if (fs_m.nir)
2640 ralloc_free(fs_m.nir);
2641
2642 radv_stop_feedback(pipeline_feedback, false);
2643 }
2644
2645 static uint32_t
2646 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2647 gl_shader_stage stage, enum chip_class chip_class)
2648 {
2649 bool has_gs = radv_pipeline_has_gs(pipeline);
2650 bool has_tess = radv_pipeline_has_tess(pipeline);
2651 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2652
2653 switch (stage) {
2654 case MESA_SHADER_FRAGMENT:
2655 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2656 case MESA_SHADER_VERTEX:
2657 if (has_tess) {
2658 if (chip_class >= GFX10) {
2659 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2660 } else if (chip_class == GFX9) {
2661 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2662 } else {
2663 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2664 }
2665
2666 }
2667
2668 if (has_gs) {
2669 if (chip_class >= GFX10) {
2670 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2671 } else {
2672 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2673 }
2674 }
2675
2676 if (has_ngg)
2677 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2678
2679 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2680 case MESA_SHADER_GEOMETRY:
2681 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2682 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2683 case MESA_SHADER_COMPUTE:
2684 return R_00B900_COMPUTE_USER_DATA_0;
2685 case MESA_SHADER_TESS_CTRL:
2686 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2687 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2688 case MESA_SHADER_TESS_EVAL:
2689 if (has_gs) {
2690 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2691 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2692 } else if (has_ngg) {
2693 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2694 } else {
2695 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2696 }
2697 default:
2698 unreachable("unknown shader");
2699 }
2700 }
2701
2702 struct radv_bin_size_entry {
2703 unsigned bpp;
2704 VkExtent2D extent;
2705 };
2706
2707 static VkExtent2D
2708 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2709 {
2710 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2711 {
2712 /* One RB / SE */
2713 {
2714 /* One shader engine */
2715 { 0, {128, 128}},
2716 { 1, { 64, 128}},
2717 { 2, { 32, 128}},
2718 { 3, { 16, 128}},
2719 { 17, { 0, 0}},
2720 { UINT_MAX, { 0, 0}},
2721 },
2722 {
2723 /* Two shader engines */
2724 { 0, {128, 128}},
2725 { 2, { 64, 128}},
2726 { 3, { 32, 128}},
2727 { 5, { 16, 128}},
2728 { 17, { 0, 0}},
2729 { UINT_MAX, { 0, 0}},
2730 },
2731 {
2732 /* Four shader engines */
2733 { 0, {128, 128}},
2734 { 3, { 64, 128}},
2735 { 5, { 16, 128}},
2736 { 17, { 0, 0}},
2737 { UINT_MAX, { 0, 0}},
2738 },
2739 },
2740 {
2741 /* Two RB / SE */
2742 {
2743 /* One shader engine */
2744 { 0, {128, 128}},
2745 { 2, { 64, 128}},
2746 { 3, { 32, 128}},
2747 { 5, { 16, 128}},
2748 { 33, { 0, 0}},
2749 { UINT_MAX, { 0, 0}},
2750 },
2751 {
2752 /* Two shader engines */
2753 { 0, {128, 128}},
2754 { 3, { 64, 128}},
2755 { 5, { 32, 128}},
2756 { 9, { 16, 128}},
2757 { 33, { 0, 0}},
2758 { UINT_MAX, { 0, 0}},
2759 },
2760 {
2761 /* Four shader engines */
2762 { 0, {256, 256}},
2763 { 2, {128, 256}},
2764 { 3, {128, 128}},
2765 { 5, { 64, 128}},
2766 { 9, { 16, 128}},
2767 { 33, { 0, 0}},
2768 { UINT_MAX, { 0, 0}},
2769 },
2770 },
2771 {
2772 /* Four RB / SE */
2773 {
2774 /* One shader engine */
2775 { 0, {128, 256}},
2776 { 2, {128, 128}},
2777 { 3, { 64, 128}},
2778 { 5, { 32, 128}},
2779 { 9, { 16, 128}},
2780 { 33, { 0, 0}},
2781 { UINT_MAX, { 0, 0}},
2782 },
2783 {
2784 /* Two shader engines */
2785 { 0, {256, 256}},
2786 { 2, {128, 256}},
2787 { 3, {128, 128}},
2788 { 5, { 64, 128}},
2789 { 9, { 32, 128}},
2790 { 17, { 16, 128}},
2791 { 33, { 0, 0}},
2792 { UINT_MAX, { 0, 0}},
2793 },
2794 {
2795 /* Four shader engines */
2796 { 0, {256, 512}},
2797 { 2, {256, 256}},
2798 { 3, {128, 256}},
2799 { 5, {128, 128}},
2800 { 9, { 64, 128}},
2801 { 17, { 16, 128}},
2802 { 33, { 0, 0}},
2803 { UINT_MAX, { 0, 0}},
2804 },
2805 },
2806 };
2807 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2808 {
2809 // One RB / SE
2810 {
2811 // One shader engine
2812 { 0, {128, 256}},
2813 { 2, {128, 128}},
2814 { 4, { 64, 128}},
2815 { 7, { 32, 128}},
2816 { 13, { 16, 128}},
2817 { 49, { 0, 0}},
2818 { UINT_MAX, { 0, 0}},
2819 },
2820 {
2821 // Two shader engines
2822 { 0, {256, 256}},
2823 { 2, {128, 256}},
2824 { 4, {128, 128}},
2825 { 7, { 64, 128}},
2826 { 13, { 32, 128}},
2827 { 25, { 16, 128}},
2828 { 49, { 0, 0}},
2829 { UINT_MAX, { 0, 0}},
2830 },
2831 {
2832 // Four shader engines
2833 { 0, {256, 512}},
2834 { 2, {256, 256}},
2835 { 4, {128, 256}},
2836 { 7, {128, 128}},
2837 { 13, { 64, 128}},
2838 { 25, { 16, 128}},
2839 { 49, { 0, 0}},
2840 { UINT_MAX, { 0, 0}},
2841 },
2842 },
2843 {
2844 // Two RB / SE
2845 {
2846 // One shader engine
2847 { 0, {256, 256}},
2848 { 2, {128, 256}},
2849 { 4, {128, 128}},
2850 { 7, { 64, 128}},
2851 { 13, { 32, 128}},
2852 { 25, { 16, 128}},
2853 { 97, { 0, 0}},
2854 { UINT_MAX, { 0, 0}},
2855 },
2856 {
2857 // Two shader engines
2858 { 0, {256, 512}},
2859 { 2, {256, 256}},
2860 { 4, {128, 256}},
2861 { 7, {128, 128}},
2862 { 13, { 64, 128}},
2863 { 25, { 32, 128}},
2864 { 49, { 16, 128}},
2865 { 97, { 0, 0}},
2866 { UINT_MAX, { 0, 0}},
2867 },
2868 {
2869 // Four shader engines
2870 { 0, {512, 512}},
2871 { 2, {256, 512}},
2872 { 4, {256, 256}},
2873 { 7, {128, 256}},
2874 { 13, {128, 128}},
2875 { 25, { 64, 128}},
2876 { 49, { 16, 128}},
2877 { 97, { 0, 0}},
2878 { UINT_MAX, { 0, 0}},
2879 },
2880 },
2881 {
2882 // Four RB / SE
2883 {
2884 // One shader engine
2885 { 0, {256, 512}},
2886 { 2, {256, 256}},
2887 { 4, {128, 256}},
2888 { 7, {128, 128}},
2889 { 13, { 64, 128}},
2890 { 25, { 32, 128}},
2891 { 49, { 16, 128}},
2892 { UINT_MAX, { 0, 0}},
2893 },
2894 {
2895 // Two shader engines
2896 { 0, {512, 512}},
2897 { 2, {256, 512}},
2898 { 4, {256, 256}},
2899 { 7, {128, 256}},
2900 { 13, {128, 128}},
2901 { 25, { 64, 128}},
2902 { 49, { 32, 128}},
2903 { 97, { 16, 128}},
2904 { UINT_MAX, { 0, 0}},
2905 },
2906 {
2907 // Four shader engines
2908 { 0, {512, 512}},
2909 { 4, {256, 512}},
2910 { 7, {256, 256}},
2911 { 13, {128, 256}},
2912 { 25, {128, 128}},
2913 { 49, { 64, 128}},
2914 { 97, { 16, 128}},
2915 { UINT_MAX, { 0, 0}},
2916 },
2917 },
2918 };
2919
2920 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2921 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2922 VkExtent2D extent = {512, 512};
2923
2924 unsigned log_num_rb_per_se =
2925 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2926 pipeline->device->physical_device->rad_info.max_se);
2927 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2928
2929 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
2930 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2931 unsigned effective_samples = total_samples;
2932 unsigned color_bytes_per_pixel = 0;
2933
2934 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2935 if (vkblend) {
2936 for (unsigned i = 0; i < subpass->color_count; i++) {
2937 if (!vkblend->pAttachments[i].colorWriteMask)
2938 continue;
2939
2940 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2941 continue;
2942
2943 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2944 color_bytes_per_pixel += vk_format_get_blocksize(format);
2945 }
2946
2947 /* MSAA images typically don't use all samples all the time. */
2948 if (effective_samples >= 2 && ps_iter_samples <= 1)
2949 effective_samples = 2;
2950 color_bytes_per_pixel *= effective_samples;
2951 }
2952
2953 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2954 while(color_entry[1].bpp <= color_bytes_per_pixel)
2955 ++color_entry;
2956
2957 extent = color_entry->extent;
2958
2959 if (subpass->depth_stencil_attachment) {
2960 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
2961
2962 /* Coefficients taken from AMDVLK */
2963 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2964 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2965 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2966
2967 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2968 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
2969 ++ds_entry;
2970
2971 extent.width = MIN2(extent.width, ds_entry->extent.width);
2972 extent.height = MIN2(extent.height, ds_entry->extent.height);
2973 }
2974
2975 return extent;
2976 }
2977
2978 static void
2979 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
2980 struct radv_pipeline *pipeline,
2981 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2982 {
2983 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2984 return;
2985
2986 uint32_t pa_sc_binner_cntl_0 =
2987 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2988 S_028C44_DISABLE_START_OF_PRIM(1);
2989 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2990
2991 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2992
2993 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2994 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2995 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2996 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2997
2998 switch (pipeline->device->physical_device->rad_info.family) {
2999 case CHIP_VEGA10:
3000 case CHIP_VEGA12:
3001 case CHIP_VEGA20:
3002 context_states_per_bin = 1;
3003 persistent_states_per_bin = 1;
3004 fpovs_per_batch = 63;
3005 break;
3006 case CHIP_RAVEN:
3007 case CHIP_RAVEN2:
3008 context_states_per_bin = 6;
3009 persistent_states_per_bin = 32;
3010 fpovs_per_batch = 63;
3011 break;
3012 default:
3013 unreachable("unhandled family while determining binning state.");
3014 }
3015
3016 pa_sc_binner_cntl_0 =
3017 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3018 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3019 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3020 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3021 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3022 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3023 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3024 S_028C44_DISABLE_START_OF_PRIM(1) |
3025 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3026 S_028C44_OPTIMAL_BIN_SELECTION(1);
3027 }
3028
3029 radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
3030 pa_sc_binner_cntl_0);
3031
3032 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3033 radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL,
3034 db_dfsm_control);
3035 } else {
3036 radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
3037 db_dfsm_control);
3038 }
3039 }
3040
3041
3042 static void
3043 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3044 struct radv_pipeline *pipeline,
3045 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3046 const struct radv_graphics_pipeline_create_info *extra)
3047 {
3048 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3049 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3050 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3051 struct radv_render_pass_attachment *attachment = NULL;
3052 uint32_t db_depth_control = 0, db_stencil_control = 0;
3053 uint32_t db_render_control = 0, db_render_override2 = 0;
3054 uint32_t db_render_override = 0;
3055
3056 if (subpass->depth_stencil_attachment)
3057 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3058
3059 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3060 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3061
3062 if (vkds && has_depth_attachment) {
3063 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3064 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3065 S_028800_ZFUNC(vkds->depthCompareOp) |
3066 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3067
3068 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3069 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3070 }
3071
3072 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3073 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3074 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3075 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3076 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3077 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3078
3079 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3080 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3081 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3082 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3083 }
3084
3085 if (attachment && extra) {
3086 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3087 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3088
3089 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3090 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3091 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3092 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3093 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3094 }
3095
3096 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3097 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3098
3099 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3100 /* From VK_EXT_depth_range_unrestricted spec:
3101 *
3102 * "The behavior described in Primitive Clipping still applies.
3103 * If depth clamping is disabled the depth values are still
3104 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3105 * depth clamping is enabled the above equation is ignored and
3106 * the depth values are instead clamped to the VkViewport
3107 * minDepth and maxDepth values, which in the case of this
3108 * extension can be outside of the 0.0 to 1.0 range."
3109 */
3110 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3111 }
3112
3113 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3114 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3115
3116 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3117 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3118 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3119 }
3120
3121 static void
3122 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3123 struct radv_pipeline *pipeline,
3124 const struct radv_blend_state *blend)
3125 {
3126 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3127 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3128 8);
3129 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3130 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3131
3132 if (pipeline->device->physical_device->has_rbplus) {
3133
3134 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3135 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3136 }
3137
3138 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3139
3140 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3141 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3142
3143 pipeline->graphics.col_format = blend->spi_shader_col_format;
3144 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3145 }
3146
3147 static const VkConservativeRasterizationModeEXT
3148 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3149 {
3150 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3151 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3152
3153 if (!conservative_raster)
3154 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3155 return conservative_raster->conservativeRasterizationMode;
3156 }
3157
3158 static void
3159 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3160 struct radv_pipeline *pipeline,
3161 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3162 {
3163 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3164 const VkConservativeRasterizationModeEXT mode =
3165 radv_get_conservative_raster_mode(vkraster);
3166 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3167 bool depth_clip_disable = vkraster->depthClampEnable;
3168
3169 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3170 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3171 if (depth_clip_state) {
3172 depth_clip_disable = !depth_clip_state->depthClipEnable;
3173 }
3174
3175 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3176 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3177 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3178 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3179 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3180 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3181
3182 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3183 S_0286D4_FLAT_SHADE_ENA(1) |
3184 S_0286D4_PNT_SPRITE_ENA(1) |
3185 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3186 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3187 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3188 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3189 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3190
3191 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3192 S_028BE4_PIX_CENTER(1) | // TODO verify
3193 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3194 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3195
3196 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3197 S_028814_FACE(vkraster->frontFace) |
3198 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3199 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3200 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3201 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3202 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3203 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3204 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3205 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3206
3207 /* Conservative rasterization. */
3208 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3209 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3210
3211 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3212 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3213 S_028804_OVERRASTERIZATION_AMOUNT(4);
3214
3215 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3216 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3217 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3218
3219 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3220 pa_sc_conservative_rast |=
3221 S_028C4C_OVER_RAST_ENABLE(1) |
3222 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3223 S_028C4C_UNDER_RAST_ENABLE(0) |
3224 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3225 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3226 } else {
3227 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3228 pa_sc_conservative_rast |=
3229 S_028C4C_OVER_RAST_ENABLE(0) |
3230 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3231 S_028C4C_UNDER_RAST_ENABLE(1) |
3232 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3233 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3234 }
3235 }
3236
3237 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3238 pa_sc_conservative_rast);
3239 }
3240
3241
3242 static void
3243 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3244 struct radv_pipeline *pipeline)
3245 {
3246 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3247
3248 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3249 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3250 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3251
3252 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3253 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3254
3255 /* The exclusion bits can be set to improve rasterization efficiency
3256 * if no sample lies on the pixel boundary (-8 sample offset). It's
3257 * currently always TRUE because the driver doesn't support 16 samples.
3258 */
3259 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3260 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3261 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3262 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3263 }
3264
3265 static void
3266 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3267 struct radv_pipeline *pipeline)
3268 {
3269 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3270 unsigned vgt_primitiveid_en = 0;
3271 uint32_t vgt_gs_mode = 0;
3272
3273 if (radv_pipeline_has_gs(pipeline)) {
3274 const struct radv_shader_variant *gs =
3275 pipeline->shaders[MESA_SHADER_GEOMETRY];
3276
3277 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3278 pipeline->device->physical_device->rad_info.chip_class);
3279 } else if (radv_pipeline_has_ngg(pipeline)) {
3280 const struct radv_shader_variant *vs =
3281 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3282 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3283 pipeline->shaders[MESA_SHADER_VERTEX];
3284 bool enable_prim_id =
3285 outinfo->export_prim_id || vs->info.info.uses_prim_id;
3286
3287 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(enable_prim_id) |
3288 S_028A84_NGG_DISABLE_PROVOK_REUSE(enable_prim_id);
3289 } else if (outinfo->export_prim_id) {
3290 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3291 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3292 }
3293
3294 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3295 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3296 }
3297
3298 static void
3299 gfx10_set_ge_pc_alloc(struct radeon_cmdbuf *ctx_cs,
3300 struct radv_pipeline *pipeline,
3301 bool culling)
3302 {
3303 struct radeon_info *info = &pipeline->device->physical_device->rad_info;
3304
3305 radeon_set_uconfig_reg(ctx_cs, R_030980_GE_PC_ALLOC,
3306 S_030980_OVERSUB_EN(1) |
3307 S_030980_NUM_PC_LINES((culling ? 256 : 128) * info->max_se - 1));
3308 }
3309
3310 static void
3311 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3312 struct radeon_cmdbuf *cs,
3313 struct radv_pipeline *pipeline,
3314 struct radv_shader_variant *shader)
3315 {
3316 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3317
3318 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3319 radeon_emit(cs, va >> 8);
3320 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3321 radeon_emit(cs, shader->config.rsrc1);
3322 radeon_emit(cs, shader->config.rsrc2);
3323
3324 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3325 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3326 clip_dist_mask = outinfo->clip_dist_mask;
3327 cull_dist_mask = outinfo->cull_dist_mask;
3328 total_mask = clip_dist_mask | cull_dist_mask;
3329 bool misc_vec_ena = outinfo->writes_pointsize ||
3330 outinfo->writes_layer ||
3331 outinfo->writes_viewport_index;
3332 unsigned spi_vs_out_config, nparams;
3333
3334 /* VS is required to export at least one param. */
3335 nparams = MAX2(outinfo->param_exports, 1);
3336 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3337
3338 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3339 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3340 }
3341
3342 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3343
3344 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3346 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3347 V_02870C_SPI_SHADER_4COMP :
3348 V_02870C_SPI_SHADER_NONE) |
3349 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3350 V_02870C_SPI_SHADER_4COMP :
3351 V_02870C_SPI_SHADER_NONE) |
3352 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3353 V_02870C_SPI_SHADER_4COMP :
3354 V_02870C_SPI_SHADER_NONE));
3355
3356 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3357 S_028818_VTX_W0_FMT(1) |
3358 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3359 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3360 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3361
3362 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3363 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3364 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3365 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3366 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3367 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3368 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3369 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3370 cull_dist_mask << 8 |
3371 clip_dist_mask);
3372
3373 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3374 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3375 outinfo->writes_viewport_index);
3376
3377 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
3378 gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false);
3379 }
3380
3381 static void
3382 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3383 struct radv_pipeline *pipeline,
3384 struct radv_shader_variant *shader)
3385 {
3386 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3387
3388 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3389 radeon_emit(cs, va >> 8);
3390 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3391 radeon_emit(cs, shader->config.rsrc1);
3392 radeon_emit(cs, shader->config.rsrc2);
3393 }
3394
3395 static void
3396 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3397 struct radv_pipeline *pipeline,
3398 struct radv_shader_variant *shader,
3399 const struct radv_tessellation_state *tess)
3400 {
3401 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3402 uint32_t rsrc2 = shader->config.rsrc2;
3403
3404 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3405 radeon_emit(cs, va >> 8);
3406 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3407
3408 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3409 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3410 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3411 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3412
3413 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3414 radeon_emit(cs, shader->config.rsrc1);
3415 radeon_emit(cs, rsrc2);
3416 }
3417
3418 static void
3419 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3420 struct radeon_cmdbuf *cs,
3421 struct radv_pipeline *pipeline,
3422 struct radv_shader_variant *shader,
3423 const struct radv_ngg_state *ngg_state)
3424 {
3425 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3426 gl_shader_stage es_type =
3427 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3428
3429 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3430 radeon_emit(cs, va >> 8);
3431 radeon_emit(cs, va >> 40);
3432 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3433 radeon_emit(cs, shader->config.rsrc1);
3434 radeon_emit(cs, shader->config.rsrc2);
3435
3436 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3437 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3438 clip_dist_mask = outinfo->clip_dist_mask;
3439 cull_dist_mask = outinfo->cull_dist_mask;
3440 total_mask = clip_dist_mask | cull_dist_mask;
3441 bool misc_vec_ena = outinfo->writes_pointsize ||
3442 outinfo->writes_layer ||
3443 outinfo->writes_viewport_index;
3444 bool break_wave_at_eoi = false;
3445 unsigned nparams;
3446
3447 nparams = MAX2(outinfo->param_exports, 1);
3448 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3449 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3450 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3451
3452 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3453 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3454 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3455 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3456 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3457 V_02870C_SPI_SHADER_4COMP :
3458 V_02870C_SPI_SHADER_NONE) |
3459 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3460 V_02870C_SPI_SHADER_4COMP :
3461 V_02870C_SPI_SHADER_NONE) |
3462 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3463 V_02870C_SPI_SHADER_4COMP :
3464 V_02870C_SPI_SHADER_NONE));
3465
3466 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3467 S_028818_VTX_W0_FMT(1) |
3468 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3469 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3470 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3471 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3472 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3473 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3474 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3475 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3476 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3477 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3478 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3479 cull_dist_mask << 8 |
3480 clip_dist_mask);
3481
3482 bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 &&
3483 pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
3484 es_type == MESA_SHADER_TESS_EVAL;
3485
3486 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3487 S_028AB4_REUSE_OFF(vgt_reuse_off));
3488 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3489 ngg_state->vgt_esgs_ring_itemsize);
3490
3491 /* NGG specific registers. */
3492 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3493 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3494
3495 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3496 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3497 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3498 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3499 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3500 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3501 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3502 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3503 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3504 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3505 S_028B90_CNT(gs_num_invocations) |
3506 S_028B90_ENABLE(gs_num_invocations > 1) |
3507 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3508
3509 /* User edge flags are set by the pos exports. If user edge flags are
3510 * not used, we must use hw-generated edge flags and pass them via
3511 * the prim export to prevent drawing lines on internal edges of
3512 * decomposed primitives (such as quads) with polygon mode = lines.
3513 *
3514 * TODO: We should combine hw-generated edge flags with user edge
3515 * flags in the shader.
3516 */
3517 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3518 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3519 !radv_pipeline_has_gs(pipeline)));
3520
3521 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
3522 S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3523 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3524 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
3525
3526 gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false);
3527 }
3528
3529 static void
3530 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3531 struct radv_pipeline *pipeline,
3532 struct radv_shader_variant *shader,
3533 const struct radv_tessellation_state *tess)
3534 {
3535 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3536
3537 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3538 unsigned hs_rsrc2 = shader->config.rsrc2;
3539
3540 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3541 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3542 } else {
3543 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3544 }
3545
3546 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3547 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3548 radeon_emit(cs, va >> 8);
3549 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3550 } else {
3551 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3552 radeon_emit(cs, va >> 8);
3553 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3554 }
3555
3556 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3557 radeon_emit(cs, shader->config.rsrc1);
3558 radeon_emit(cs, hs_rsrc2);
3559 } else {
3560 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3561 radeon_emit(cs, va >> 8);
3562 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3563 radeon_emit(cs, shader->config.rsrc1);
3564 radeon_emit(cs, shader->config.rsrc2);
3565 }
3566 }
3567
3568 static void
3569 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3570 struct radeon_cmdbuf *cs,
3571 struct radv_pipeline *pipeline,
3572 const struct radv_tessellation_state *tess,
3573 const struct radv_ngg_state *ngg)
3574 {
3575 struct radv_shader_variant *vs;
3576
3577 /* Skip shaders merged into HS/GS */
3578 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3579 if (!vs)
3580 return;
3581
3582 if (vs->info.vs.as_ls)
3583 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3584 else if (vs->info.vs.as_es)
3585 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3586 else if (vs->info.is_ngg)
3587 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs, ngg);
3588 else
3589 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3590 }
3591
3592 static void
3593 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3594 struct radeon_cmdbuf *cs,
3595 struct radv_pipeline *pipeline,
3596 const struct radv_tessellation_state *tess,
3597 const struct radv_ngg_state *ngg)
3598 {
3599 if (!radv_pipeline_has_tess(pipeline))
3600 return;
3601
3602 struct radv_shader_variant *tes, *tcs;
3603
3604 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3605 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3606
3607 if (tes) {
3608 if (tes->info.is_ngg) {
3609 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes, ngg);
3610 } else if (tes->info.tes.as_es)
3611 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3612 else
3613 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3614 }
3615
3616 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3617
3618 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3619 tess->tf_param);
3620
3621 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3622 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3623 tess->ls_hs_config);
3624 else
3625 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3626 tess->ls_hs_config);
3627 }
3628
3629 static void
3630 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3631 struct radeon_cmdbuf *cs,
3632 struct radv_pipeline *pipeline,
3633 struct radv_shader_variant *gs,
3634 const struct radv_gs_state *gs_state)
3635 {
3636 unsigned gs_max_out_vertices;
3637 uint8_t *num_components;
3638 uint8_t max_stream;
3639 unsigned offset;
3640 uint64_t va;
3641
3642 gs_max_out_vertices = gs->info.gs.vertices_out;
3643 max_stream = gs->info.info.gs.max_stream;
3644 num_components = gs->info.info.gs.num_stream_output_components;
3645
3646 offset = num_components[0] * gs_max_out_vertices;
3647
3648 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3649 radeon_emit(ctx_cs, offset);
3650 if (max_stream >= 1)
3651 offset += num_components[1] * gs_max_out_vertices;
3652 radeon_emit(ctx_cs, offset);
3653 if (max_stream >= 2)
3654 offset += num_components[2] * gs_max_out_vertices;
3655 radeon_emit(ctx_cs, offset);
3656 if (max_stream >= 3)
3657 offset += num_components[3] * gs_max_out_vertices;
3658 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3659
3660 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3661 radeon_emit(ctx_cs, num_components[0]);
3662 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3663 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3664 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3665
3666 uint32_t gs_num_invocations = gs->info.gs.invocations;
3667 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3668 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3669 S_028B90_ENABLE(gs_num_invocations > 0));
3670
3671 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3672 gs_state->vgt_esgs_ring_itemsize);
3673
3674 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3675
3676 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3677 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3678 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3679 radeon_emit(cs, va >> 8);
3680 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3681 } else {
3682 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3683 radeon_emit(cs, va >> 8);
3684 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3685 }
3686
3687 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3688 radeon_emit(cs, gs->config.rsrc1);
3689 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3690
3691 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3692 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3693 } else {
3694 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3695 radeon_emit(cs, va >> 8);
3696 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3697 radeon_emit(cs, gs->config.rsrc1);
3698 radeon_emit(cs, gs->config.rsrc2);
3699 }
3700
3701 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
3702 }
3703
3704 static void
3705 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
3706 struct radeon_cmdbuf *cs,
3707 struct radv_pipeline *pipeline,
3708 const struct radv_gs_state *gs_state,
3709 const struct radv_ngg_state *ngg_state)
3710 {
3711 struct radv_shader_variant *gs;
3712
3713 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3714 if (!gs)
3715 return;
3716
3717 if (gs->info.is_ngg)
3718 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state);
3719 else
3720 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
3721
3722 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
3723 gs->info.gs.vertices_out);
3724 }
3725
3726 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
3727 {
3728 uint32_t ps_input_cntl;
3729 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3730 ps_input_cntl = S_028644_OFFSET(offset);
3731 if (flat_shade)
3732 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3733 if (float16) {
3734 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
3735 S_028644_ATTR0_VALID(1);
3736 }
3737 } else {
3738 /* The input is a DEFAULT_VAL constant. */
3739 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3740 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3741 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3742 ps_input_cntl = S_028644_OFFSET(0x20) |
3743 S_028644_DEFAULT_VAL(offset);
3744 }
3745 return ps_input_cntl;
3746 }
3747
3748 static void
3749 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
3750 struct radv_pipeline *pipeline)
3751 {
3752 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3753 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3754 uint32_t ps_input_cntl[32];
3755
3756 unsigned ps_offset = 0;
3757
3758 if (ps->info.info.ps.prim_id_input) {
3759 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3760 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3761 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3762 ++ps_offset;
3763 }
3764 }
3765
3766 if (ps->info.info.ps.layer_input ||
3767 ps->info.info.needs_multiview_view_index) {
3768 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3769 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3770 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3771 else
3772 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
3773 ++ps_offset;
3774 }
3775
3776 if (ps->info.info.ps.has_pcoord) {
3777 unsigned val;
3778 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3779 ps_input_cntl[ps_offset] = val;
3780 ps_offset++;
3781 }
3782
3783 if (ps->info.info.ps.num_input_clips_culls) {
3784 unsigned vs_offset;
3785
3786 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3787 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3788 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3789 ++ps_offset;
3790 }
3791
3792 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3793 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
3794 ps->info.info.ps.num_input_clips_culls > 4) {
3795 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3796 ++ps_offset;
3797 }
3798 }
3799
3800 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3801 unsigned vs_offset;
3802 bool flat_shade;
3803 bool float16;
3804 if (!(ps->info.fs.input_mask & (1u << i)))
3805 continue;
3806
3807 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3808 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3809 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3810 ++ps_offset;
3811 continue;
3812 }
3813
3814 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3815 float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset));
3816
3817 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
3818 ++ps_offset;
3819 }
3820
3821 if (ps_offset) {
3822 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3823 for (unsigned i = 0; i < ps_offset; i++) {
3824 radeon_emit(ctx_cs, ps_input_cntl[i]);
3825 }
3826 }
3827 }
3828
3829 static uint32_t
3830 radv_compute_db_shader_control(const struct radv_device *device,
3831 const struct radv_pipeline *pipeline,
3832 const struct radv_shader_variant *ps)
3833 {
3834 unsigned z_order;
3835 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3836 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3837 else
3838 z_order = V_02880C_LATE_Z;
3839
3840 bool disable_rbplus = device->physical_device->has_rbplus &&
3841 !device->physical_device->rbplus_allowed;
3842
3843 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3844 * but this appears to break Project Cars (DXVK). See
3845 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
3846 */
3847 bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
3848
3849 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3850 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3851 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3852 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
3853 S_02880C_Z_ORDER(z_order) |
3854 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3855 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
3856 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3857 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3858 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3859 }
3860
3861 static void
3862 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
3863 struct radeon_cmdbuf *cs,
3864 struct radv_pipeline *pipeline)
3865 {
3866 struct radv_shader_variant *ps;
3867 uint64_t va;
3868 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3869
3870 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3871 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3872
3873 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3874 radeon_emit(cs, va >> 8);
3875 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3876 radeon_emit(cs, ps->config.rsrc1);
3877 radeon_emit(cs, ps->config.rsrc2);
3878
3879 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
3880 radv_compute_db_shader_control(pipeline->device,
3881 pipeline, ps));
3882
3883 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
3884 ps->config.spi_ps_input_ena);
3885
3886 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
3887 ps->config.spi_ps_input_addr);
3888
3889 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
3890 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3891
3892 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3893
3894 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
3895 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3896 ps->info.info.ps.writes_stencil,
3897 ps->info.info.ps.writes_sample_mask));
3898
3899 if (pipeline->device->dfsm_allowed) {
3900 /* optimise this? */
3901 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3902 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3903 }
3904 }
3905
3906 static void
3907 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
3908 struct radv_pipeline *pipeline)
3909 {
3910 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3911 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
3912 return;
3913
3914 unsigned vtx_reuse_depth = 30;
3915 if (radv_pipeline_has_tess(pipeline) &&
3916 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3917 vtx_reuse_depth = 14;
3918 }
3919 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3920 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3921 }
3922
3923 static uint32_t
3924 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3925 {
3926 uint32_t stages = 0;
3927 if (radv_pipeline_has_tess(pipeline)) {
3928 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3929 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3930
3931 if (radv_pipeline_has_gs(pipeline))
3932 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3933 S_028B54_GS_EN(1);
3934 else if (radv_pipeline_has_ngg(pipeline))
3935 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3936 else
3937 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3938 } else if (radv_pipeline_has_gs(pipeline)) {
3939 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3940 S_028B54_GS_EN(1);
3941 } else if (radv_pipeline_has_ngg(pipeline)) {
3942 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3943 }
3944
3945 if (radv_pipeline_has_ngg(pipeline)) {
3946 stages |= S_028B54_PRIMGEN_EN(1);
3947 } else if (radv_pipeline_has_gs(pipeline)) {
3948 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3949 }
3950
3951 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3952 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3953
3954 return stages;
3955 }
3956
3957 static uint32_t
3958 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3959 {
3960 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3961 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3962
3963 if (!discard_rectangle_info)
3964 return 0xffff;
3965
3966 unsigned mask = 0;
3967
3968 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3969 /* Interpret i as a bitmask, and then set the bit in the mask if
3970 * that combination of rectangles in which the pixel is contained
3971 * should pass the cliprect test. */
3972 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3973
3974 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3975 !relevant_subset)
3976 continue;
3977
3978 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3979 relevant_subset)
3980 continue;
3981
3982 mask |= 1u << i;
3983 }
3984
3985 return mask;
3986 }
3987
3988 static void
3989 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
3990 struct radv_pipeline *pipeline,
3991 const struct radv_tessellation_state *tess,
3992 const struct radv_gs_state *gs_state)
3993 {
3994 bool break_wave_at_eoi = false;
3995 unsigned primgroup_size;
3996 unsigned vertgroup_size;
3997
3998 if (radv_pipeline_has_tess(pipeline)) {
3999 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4000 vertgroup_size = 0;
4001 } else if (radv_pipeline_has_gs(pipeline)) {
4002 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4003 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4004 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4005 } else {
4006 primgroup_size = 128; /* recommended without a GS and tess */
4007 vertgroup_size = 0;
4008 }
4009
4010 if (radv_pipeline_has_tess(pipeline)) {
4011 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4012 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4013 break_wave_at_eoi = true;
4014 }
4015
4016 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4017 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4018 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4019 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4020 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4021 }
4022
4023 static void
4024 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4025 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4026 const struct radv_graphics_pipeline_create_info *extra,
4027 const struct radv_blend_state *blend,
4028 const struct radv_tessellation_state *tess,
4029 const struct radv_gs_state *gs,
4030 const struct radv_ngg_state *ngg,
4031 unsigned prim, unsigned gs_out)
4032 {
4033 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4034 struct radeon_cmdbuf *cs = &pipeline->cs;
4035
4036 cs->max_dw = 64;
4037 ctx_cs->max_dw = 256;
4038 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4039 ctx_cs->buf = cs->buf + cs->max_dw;
4040
4041 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4042 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4043 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4044 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4045 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4046 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
4047 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
4048 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);
4049 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4050 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4051 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4052 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4053
4054 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4055 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
4056
4057 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4058 S_0286E8_WAVES(pipeline->max_waves) |
4059 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4060
4061 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4062
4063 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4064 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4065 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4066 } else {
4067 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4068 }
4069 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4070
4071 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4072
4073 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4074
4075 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4076 assert(cs->cdw <= cs->max_dw);
4077 }
4078
4079 static struct radv_ia_multi_vgt_param_helpers
4080 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4081 const struct radv_tessellation_state *tess,
4082 uint32_t prim)
4083 {
4084 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4085 const struct radv_device *device = pipeline->device;
4086
4087 if (radv_pipeline_has_tess(pipeline))
4088 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4089 else if (radv_pipeline_has_gs(pipeline))
4090 ia_multi_vgt_param.primgroup_size = 64;
4091 else
4092 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4093
4094 /* GS requirement. */
4095 ia_multi_vgt_param.partial_es_wave = false;
4096 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4097 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4098 ia_multi_vgt_param.partial_es_wave = true;
4099
4100 ia_multi_vgt_param.wd_switch_on_eop = false;
4101 if (device->physical_device->rad_info.chip_class >= GFX7) {
4102 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4103 * 4 shader engines. Set 1 to pass the assertion below.
4104 * The other cases are hardware requirements. */
4105 if (device->physical_device->rad_info.max_se < 4 ||
4106 prim == V_008958_DI_PT_POLYGON ||
4107 prim == V_008958_DI_PT_LINELOOP ||
4108 prim == V_008958_DI_PT_TRIFAN ||
4109 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4110 (pipeline->graphics.prim_restart_enable &&
4111 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4112 (prim != V_008958_DI_PT_POINTLIST &&
4113 prim != V_008958_DI_PT_LINESTRIP))))
4114 ia_multi_vgt_param.wd_switch_on_eop = true;
4115 }
4116
4117 ia_multi_vgt_param.ia_switch_on_eoi = false;
4118 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
4119 ia_multi_vgt_param.ia_switch_on_eoi = true;
4120 if (radv_pipeline_has_gs(pipeline) &&
4121 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
4122 ia_multi_vgt_param.ia_switch_on_eoi = true;
4123 if (radv_pipeline_has_tess(pipeline)) {
4124 /* SWITCH_ON_EOI must be set if PrimID is used. */
4125 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4126 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4127 ia_multi_vgt_param.ia_switch_on_eoi = true;
4128 }
4129
4130 ia_multi_vgt_param.partial_vs_wave = false;
4131 if (radv_pipeline_has_tess(pipeline)) {
4132 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4133 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4134 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4135 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4136 radv_pipeline_has_gs(pipeline))
4137 ia_multi_vgt_param.partial_vs_wave = true;
4138 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4139 if (device->has_distributed_tess) {
4140 if (radv_pipeline_has_gs(pipeline)) {
4141 if (device->physical_device->rad_info.chip_class <= GFX8)
4142 ia_multi_vgt_param.partial_es_wave = true;
4143 } else {
4144 ia_multi_vgt_param.partial_vs_wave = true;
4145 }
4146 }
4147 }
4148
4149 /* Workaround for a VGT hang when strip primitive types are used with
4150 * primitive restart.
4151 */
4152 if (pipeline->graphics.prim_restart_enable &&
4153 (prim == V_008958_DI_PT_LINESTRIP ||
4154 prim == V_008958_DI_PT_TRISTRIP ||
4155 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4156 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4157 ia_multi_vgt_param.partial_vs_wave = true;
4158 }
4159
4160 if (radv_pipeline_has_gs(pipeline)) {
4161 /* On these chips there is the possibility of a hang if the
4162 * pipeline uses a GS and partial_vs_wave is not set.
4163 *
4164 * This mostly does not hit 4-SE chips, as those typically set
4165 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4166 * with GS due to another workaround.
4167 *
4168 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4169 */
4170 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4171 device->physical_device->rad_info.family == CHIP_FIJI ||
4172 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4173 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4174 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4175 device->physical_device->rad_info.family == CHIP_VEGAM) {
4176 ia_multi_vgt_param.partial_vs_wave = true;
4177 }
4178 }
4179
4180 ia_multi_vgt_param.base =
4181 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4182 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4183 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4184 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4185 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4186
4187 return ia_multi_vgt_param;
4188 }
4189
4190
4191 static void
4192 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4193 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4194 {
4195 const VkPipelineVertexInputStateCreateInfo *vi_info =
4196 pCreateInfo->pVertexInputState;
4197 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4198
4199 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4200 const VkVertexInputAttributeDescription *desc =
4201 &vi_info->pVertexAttributeDescriptions[i];
4202 unsigned loc = desc->location;
4203 const struct vk_format_description *format_desc;
4204
4205 format_desc = vk_format_description(desc->format);
4206
4207 velems->format_size[loc] = format_desc->block.bits / 8;
4208 }
4209
4210 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4211 const VkVertexInputBindingDescription *desc =
4212 &vi_info->pVertexBindingDescriptions[i];
4213
4214 pipeline->binding_stride[desc->binding] = desc->stride;
4215 pipeline->num_vertex_bindings =
4216 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4217 }
4218 }
4219
4220 static struct radv_shader_variant *
4221 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4222 {
4223 int i;
4224
4225 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4226 struct radv_shader_variant *shader =
4227 radv_get_shader(pipeline, i);
4228
4229 if (shader && shader->info.info.so.num_outputs > 0)
4230 return shader;
4231 }
4232
4233 return NULL;
4234 }
4235
4236 static VkResult
4237 radv_pipeline_init(struct radv_pipeline *pipeline,
4238 struct radv_device *device,
4239 struct radv_pipeline_cache *cache,
4240 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4241 const struct radv_graphics_pipeline_create_info *extra)
4242 {
4243 VkResult result;
4244 bool has_view_index = false;
4245
4246 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4247 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4248 if (subpass->view_mask)
4249 has_view_index = true;
4250
4251 pipeline->device = device;
4252 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4253 assert(pipeline->layout);
4254
4255 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4256
4257 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4258 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4259 radv_init_feedback(creation_feedback);
4260
4261 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4262
4263 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4264 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4265 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4266 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4267 pStages[stage] = &pCreateInfo->pStages[i];
4268 if(creation_feedback)
4269 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4270 }
4271
4272 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4273 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4274
4275 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4276 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4277 uint32_t gs_out;
4278 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4279
4280 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4281
4282 if (radv_pipeline_has_gs(pipeline)) {
4283 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4284 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4285 } else if (radv_pipeline_has_tess(pipeline)) {
4286 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4287 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4288 else
4289 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4290 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4291 } else {
4292 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4293 }
4294 if (extra && extra->use_rectlist) {
4295 prim = V_008958_DI_PT_RECTLIST;
4296 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4297 pipeline->graphics.can_use_guardband = true;
4298 if (radv_pipeline_has_ngg(pipeline))
4299 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4300 }
4301 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4302 /* prim vertex count will need TESS changes */
4303 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4304
4305 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4306
4307 /* Ensure that some export memory is always allocated, for two reasons:
4308 *
4309 * 1) Correctness: The hardware ignores the EXEC mask if no export
4310 * memory is allocated, so KILL and alpha test do not work correctly
4311 * without this.
4312 * 2) Performance: Every shader needs at least a NULL export, even when
4313 * it writes no color/depth output. The NULL export instruction
4314 * stalls without this setting.
4315 *
4316 * Don't add this to CB_SHADER_MASK.
4317 *
4318 * GFX10 supports pixel shaders without exports by setting both the
4319 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4320 * instructions if any are present.
4321 */
4322 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4323 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4324 ps->info.fs.can_discard) &&
4325 !blend.spi_shader_col_format) {
4326 if (!ps->info.info.ps.writes_z &&
4327 !ps->info.info.ps.writes_stencil &&
4328 !ps->info.info.ps.writes_sample_mask)
4329 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4330 }
4331
4332 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4333 if (pipeline->shaders[i]) {
4334 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4335 }
4336 }
4337
4338 struct radv_ngg_state ngg = {0};
4339 struct radv_gs_state gs = {0};
4340
4341 if (radv_pipeline_has_ngg(pipeline)) {
4342 ngg = calculate_ngg_info(pCreateInfo, pipeline);
4343 } else if (radv_pipeline_has_gs(pipeline)) {
4344 gs = calculate_gs_info(pCreateInfo, pipeline);
4345 calculate_gs_ring_sizes(pipeline, &gs);
4346 }
4347
4348 struct radv_tessellation_state tess = {0};
4349 if (radv_pipeline_has_tess(pipeline)) {
4350 if (prim == V_008958_DI_PT_PATCH) {
4351 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4352 pipeline->graphics.prim_vertex_count.incr = 1;
4353 }
4354 tess = calculate_tess_state(pipeline, pCreateInfo);
4355 }
4356
4357 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4358
4359 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4360
4361 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4362 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4363
4364 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4365 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4366 if (loc->sgpr_idx != -1) {
4367 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4368 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4369 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
4370 pipeline->graphics.vtx_emit_num = 3;
4371 else
4372 pipeline->graphics.vtx_emit_num = 2;
4373 }
4374
4375 /* Find the last vertex shader stage that eventually uses streamout. */
4376 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4377
4378 result = radv_pipeline_scratch_init(device, pipeline);
4379 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, &ngg, prim, gs_out);
4380
4381 return result;
4382 }
4383
4384 VkResult
4385 radv_graphics_pipeline_create(
4386 VkDevice _device,
4387 VkPipelineCache _cache,
4388 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4389 const struct radv_graphics_pipeline_create_info *extra,
4390 const VkAllocationCallbacks *pAllocator,
4391 VkPipeline *pPipeline)
4392 {
4393 RADV_FROM_HANDLE(radv_device, device, _device);
4394 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4395 struct radv_pipeline *pipeline;
4396 VkResult result;
4397
4398 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4399 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4400 if (pipeline == NULL)
4401 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4402
4403 result = radv_pipeline_init(pipeline, device, cache,
4404 pCreateInfo, extra);
4405 if (result != VK_SUCCESS) {
4406 radv_pipeline_destroy(device, pipeline, pAllocator);
4407 return result;
4408 }
4409
4410 *pPipeline = radv_pipeline_to_handle(pipeline);
4411
4412 return VK_SUCCESS;
4413 }
4414
4415 VkResult radv_CreateGraphicsPipelines(
4416 VkDevice _device,
4417 VkPipelineCache pipelineCache,
4418 uint32_t count,
4419 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4420 const VkAllocationCallbacks* pAllocator,
4421 VkPipeline* pPipelines)
4422 {
4423 VkResult result = VK_SUCCESS;
4424 unsigned i = 0;
4425
4426 for (; i < count; i++) {
4427 VkResult r;
4428 r = radv_graphics_pipeline_create(_device,
4429 pipelineCache,
4430 &pCreateInfos[i],
4431 NULL, pAllocator, &pPipelines[i]);
4432 if (r != VK_SUCCESS) {
4433 result = r;
4434 pPipelines[i] = VK_NULL_HANDLE;
4435 }
4436 }
4437
4438 return result;
4439 }
4440
4441
4442 static void
4443 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4444 {
4445 struct radv_shader_variant *compute_shader;
4446 struct radv_device *device = pipeline->device;
4447 unsigned threads_per_threadgroup;
4448 unsigned threadgroups_per_cu = 1;
4449 unsigned waves_per_threadgroup;
4450 unsigned max_waves_per_sh = 0;
4451 uint64_t va;
4452
4453 pipeline->cs.buf = malloc(20 * 4);
4454 pipeline->cs.max_dw = 20;
4455
4456 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4457 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4458
4459 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4460 radeon_emit(&pipeline->cs, va >> 8);
4461 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4462
4463 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4464 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4465 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4466
4467 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4468 S_00B860_WAVES(pipeline->max_waves) |
4469 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4470
4471 /* Calculate best compute resource limits. */
4472 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4473 compute_shader->info.cs.block_size[1] *
4474 compute_shader->info.cs.block_size[2];
4475 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup, 64);
4476
4477 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4478 waves_per_threadgroup == 1)
4479 threadgroups_per_cu = 2;
4480
4481 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4482 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4483 waves_per_threadgroup,
4484 max_waves_per_sh,
4485 threadgroups_per_cu));
4486
4487 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4488 radeon_emit(&pipeline->cs,
4489 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4490 radeon_emit(&pipeline->cs,
4491 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4492 radeon_emit(&pipeline->cs,
4493 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4494
4495 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4496 }
4497
4498 static VkResult radv_compute_pipeline_create(
4499 VkDevice _device,
4500 VkPipelineCache _cache,
4501 const VkComputePipelineCreateInfo* pCreateInfo,
4502 const VkAllocationCallbacks* pAllocator,
4503 VkPipeline* pPipeline)
4504 {
4505 RADV_FROM_HANDLE(radv_device, device, _device);
4506 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4507 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4508 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4509 struct radv_pipeline *pipeline;
4510 VkResult result;
4511
4512 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4513 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4514 if (pipeline == NULL)
4515 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4516
4517 pipeline->device = device;
4518 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4519 assert(pipeline->layout);
4520
4521 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4522 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4523 radv_init_feedback(creation_feedback);
4524
4525 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4526 if (creation_feedback)
4527 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4528
4529 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4530 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4531
4532 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4533 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4534 result = radv_pipeline_scratch_init(device, pipeline);
4535 if (result != VK_SUCCESS) {
4536 radv_pipeline_destroy(device, pipeline, pAllocator);
4537 return result;
4538 }
4539
4540 radv_compute_generate_pm4(pipeline);
4541
4542 *pPipeline = radv_pipeline_to_handle(pipeline);
4543
4544 return VK_SUCCESS;
4545 }
4546
4547 VkResult radv_CreateComputePipelines(
4548 VkDevice _device,
4549 VkPipelineCache pipelineCache,
4550 uint32_t count,
4551 const VkComputePipelineCreateInfo* pCreateInfos,
4552 const VkAllocationCallbacks* pAllocator,
4553 VkPipeline* pPipelines)
4554 {
4555 VkResult result = VK_SUCCESS;
4556
4557 unsigned i = 0;
4558 for (; i < count; i++) {
4559 VkResult r;
4560 r = radv_compute_pipeline_create(_device, pipelineCache,
4561 &pCreateInfos[i],
4562 pAllocator, &pPipelines[i]);
4563 if (r != VK_SUCCESS) {
4564 result = r;
4565 pPipelines[i] = VK_NULL_HANDLE;
4566 }
4567 }
4568
4569 return result;
4570 }