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radv/ac: Add compiler support for spilling.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107 void radv_DestroyPipeline(
108 VkDevice _device,
109 VkPipeline _pipeline,
110 const VkAllocationCallbacks* pAllocator)
111 {
112 RADV_FROM_HANDLE(radv_device, device, _device);
113 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
114
115 if (!_pipeline)
116 return;
117
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 vk_free2(&device->alloc, pAllocator, pipeline);
123 }
124
125
126 static void
127 radv_optimize_nir(struct nir_shader *shader)
128 {
129 bool progress;
130
131 do {
132 progress = false;
133
134 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
135 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
136 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
137
138 NIR_PASS(progress, shader, nir_copy_prop);
139 NIR_PASS(progress, shader, nir_opt_remove_phis);
140 NIR_PASS(progress, shader, nir_opt_dce);
141 NIR_PASS(progress, shader, nir_opt_dead_cf);
142 NIR_PASS(progress, shader, nir_opt_cse);
143 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
144 NIR_PASS(progress, shader, nir_opt_algebraic);
145 NIR_PASS(progress, shader, nir_opt_constant_folding);
146 NIR_PASS(progress, shader, nir_opt_undef);
147 NIR_PASS(progress, shader, nir_opt_conditional_discard);
148 } while (progress);
149 }
150
151 static nir_shader *
152 radv_shader_compile_to_nir(struct radv_device *device,
153 struct radv_shader_module *module,
154 const char *entrypoint_name,
155 gl_shader_stage stage,
156 const VkSpecializationInfo *spec_info,
157 bool dump)
158 {
159 if (strcmp(entrypoint_name, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
161 }
162
163 nir_shader *nir;
164 nir_function *entry_point;
165 if (module->nir) {
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
169 nir = module->nir;
170 nir->options = &nir_options;
171 nir_validate_shader(nir);
172
173 assert(exec_list_length(&nir->functions) == 1);
174 struct exec_node *node = exec_list_get_head(&nir->functions);
175 entry_point = exec_node_data(nir_function, node, node);
176 } else {
177 uint32_t *spirv = (uint32_t *) module->data;
178 assert(module->size % 4 == 0);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 if (spec_info->dataSize == 8)
192 spec_entries[i].data64 = *(const uint64_t *)data;
193 else
194 spec_entries[i].data32 = *(const uint32_t *)data;
195 }
196 }
197 const struct nir_spirv_supported_extensions supported_ext = {
198 };
199 entry_point = spirv_to_nir(spirv, module->size / 4,
200 spec_entries, num_spec_entries,
201 stage, entrypoint_name, &supported_ext, &nir_options);
202 nir = entry_point->shader;
203 assert(nir->stage == stage);
204 nir_validate_shader(nir);
205
206 free(spec_entries);
207
208 /* We have to lower away local constant initializers right before we
209 * inline functions. That way they get properly initialized at the top
210 * of the function and not at the top of its caller.
211 */
212 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
213 NIR_PASS_V(nir, nir_lower_returns);
214 NIR_PASS_V(nir, nir_inline_functions);
215
216 /* Pick off the single entrypoint that we want */
217 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
218 if (func != entry_point)
219 exec_node_remove(&func->node);
220 }
221 assert(exec_list_length(&nir->functions) == 1);
222 entry_point->name = ralloc_strdup(entry_point, "main");
223
224 NIR_PASS_V(nir, nir_remove_dead_variables,
225 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
226
227 /* Now that we've deleted all but the main function, we can go ahead and
228 * lower the rest of the constant initializers.
229 */
230 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
231 NIR_PASS_V(nir, nir_lower_system_values);
232 }
233
234 /* Vulkan uses the separate-shader linking model */
235 nir->info->separate_shader = true;
236
237 // nir = brw_preprocess_nir(compiler, nir);
238
239 nir_shader_gather_info(nir, entry_point->impl);
240
241 nir_variable_mode indirect_mask = 0;
242 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
243 indirect_mask |= nir_var_shader_in;
244 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
245 indirect_mask |= nir_var_local;
246
247 nir_lower_indirect_derefs(nir, indirect_mask);
248
249 static const nir_lower_tex_options tex_options = {
250 .lower_txp = ~0,
251 };
252
253 nir_lower_tex(nir, &tex_options);
254
255 nir_lower_vars_to_ssa(nir);
256 nir_lower_var_copies(nir);
257 nir_lower_global_vars_to_local(nir);
258 nir_remove_dead_variables(nir, nir_var_local);
259 radv_optimize_nir(nir);
260
261 if (dump)
262 nir_print_shader(nir, stderr);
263
264 return nir;
265 }
266
267 static const char *radv_get_shader_name(struct radv_shader_variant *var,
268 gl_shader_stage stage)
269 {
270 switch (stage) {
271 case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
272 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
273 case MESA_SHADER_COMPUTE: return "Compute Shader";
274 default:
275 return "Unknown shader";
276 };
277
278 }
279 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
280 {
281 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
282 struct radv_shader_variant *var;
283 struct ac_shader_config *conf;
284 int i;
285 FILE *file = stderr;
286 unsigned max_simd_waves = 10;
287 unsigned lds_per_wave = 0;
288
289 for (i = 0; i < MESA_SHADER_STAGES; i++) {
290 if (!pipeline->shaders[i])
291 continue;
292 var = pipeline->shaders[i];
293
294 conf = &var->config;
295
296 if (i == MESA_SHADER_FRAGMENT) {
297 lds_per_wave = conf->lds_size * lds_increment +
298 align(var->info.fs.num_interp * 48, lds_increment);
299 }
300
301 if (conf->num_sgprs) {
302 if (device->physical_device->rad_info.chip_class >= VI)
303 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
304 else
305 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
306 }
307
308 if (conf->num_vgprs)
309 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
310
311 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
312 * that PS can use.
313 */
314 if (lds_per_wave)
315 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
316
317 fprintf(file, "\n%s:\n",
318 radv_get_shader_name(var, i));
319 if (i == MESA_SHADER_FRAGMENT) {
320 fprintf(file, "*** SHADER CONFIG ***\n"
321 "SPI_PS_INPUT_ADDR = 0x%04x\n"
322 "SPI_PS_INPUT_ENA = 0x%04x\n",
323 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
324 }
325 fprintf(file, "*** SHADER STATS ***\n"
326 "SGPRS: %d\n"
327 "VGPRS: %d\n"
328 "Spilled SGPRs: %d\n"
329 "Spilled VGPRs: %d\n"
330 "Code Size: %d bytes\n"
331 "LDS: %d blocks\n"
332 "Scratch: %d bytes per wave\n"
333 "Max Waves: %d\n"
334 "********************\n\n\n",
335 conf->num_sgprs, conf->num_vgprs,
336 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
337 conf->lds_size, conf->scratch_bytes_per_wave,
338 max_simd_waves);
339 }
340 }
341
342 void radv_shader_variant_destroy(struct radv_device *device,
343 struct radv_shader_variant *variant)
344 {
345 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
346 return;
347
348 device->ws->buffer_destroy(variant->bo);
349 free(variant);
350 }
351
352 static void radv_fill_shader_variant(struct radv_device *device,
353 struct radv_shader_variant *variant,
354 struct ac_shader_binary *binary,
355 gl_shader_stage stage)
356 {
357 variant->code_size = binary->code_size;
358 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
359 unsigned vgpr_comp_cnt = 0;
360
361 if (scratch_enabled)
362 radv_finishme("shader scratch space");
363
364 switch (stage) {
365 case MESA_SHADER_VERTEX:
366 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
367 S_00B12C_SCRATCH_EN(scratch_enabled);
368 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
369 break;
370 case MESA_SHADER_FRAGMENT:
371 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
372 S_00B12C_SCRATCH_EN(scratch_enabled);
373 break;
374 case MESA_SHADER_COMPUTE:
375 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
376 S_00B84C_SCRATCH_EN(scratch_enabled) |
377 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
378 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
379 S_00B84C_TG_SIZE_EN(1) |
380 S_00B84C_LDS_SIZE(variant->config.lds_size);
381 break;
382 default:
383 unreachable("unsupported shader type");
384 break;
385 }
386
387 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
388 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
389 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
390 S_00B848_DX10_CLAMP(1) |
391 S_00B848_FLOAT_MODE(variant->config.float_mode);
392
393 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
394 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
395
396 void *ptr = device->ws->buffer_map(variant->bo);
397 memcpy(ptr, binary->code, binary->code_size);
398 device->ws->buffer_unmap(variant->bo);
399
400
401 }
402
403 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
404 struct nir_shader *shader,
405 struct radv_pipeline_layout *layout,
406 const union ac_shader_variant_key *key,
407 void** code_out,
408 unsigned *code_size_out,
409 bool dump)
410 {
411 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
412 enum radeon_family chip_family = device->physical_device->rad_info.family;
413 LLVMTargetMachineRef tm;
414 if (!variant)
415 return NULL;
416
417 struct ac_nir_compiler_options options = {0};
418 options.layout = layout;
419 if (key)
420 options.key = *key;
421
422 struct ac_shader_binary binary;
423
424 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
425 options.family = chip_family;
426 options.chip_class = device->physical_device->rad_info.chip_class;
427 options.supports_spill = false;
428 tm = ac_create_target_machine(chip_family, false);
429 ac_compile_nir_shader(tm, &binary, &variant->config,
430 &variant->info, shader, &options, dump);
431 LLVMDisposeTargetMachine(tm);
432
433 radv_fill_shader_variant(device, variant, &binary, shader->stage);
434
435 if (code_out) {
436 *code_out = binary.code;
437 *code_size_out = binary.code_size;
438 } else
439 free(binary.code);
440 free(binary.config);
441 free(binary.rodata);
442 free(binary.global_symbol_offsets);
443 free(binary.relocs);
444 free(binary.disasm_string);
445 variant->ref_count = 1;
446 return variant;
447 }
448
449
450 static struct radv_shader_variant *
451 radv_pipeline_compile(struct radv_pipeline *pipeline,
452 struct radv_pipeline_cache *cache,
453 struct radv_shader_module *module,
454 const char *entrypoint,
455 gl_shader_stage stage,
456 const VkSpecializationInfo *spec_info,
457 struct radv_pipeline_layout *layout,
458 const union ac_shader_variant_key *key)
459 {
460 unsigned char sha1[20];
461 struct radv_shader_variant *variant;
462 nir_shader *nir;
463 void *code = NULL;
464 unsigned code_size = 0;
465 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
466
467 if (module->nir)
468 _mesa_sha1_compute(module->nir->info->name,
469 strlen(module->nir->info->name),
470 module->sha1);
471
472 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
473
474 if (cache) {
475 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
476 cache,
477 sha1);
478 if (variant)
479 return variant;
480 }
481
482 nir = radv_shader_compile_to_nir(pipeline->device,
483 module, entrypoint, stage,
484 spec_info, dump);
485 if (nir == NULL)
486 return NULL;
487
488 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
489 &code, &code_size, dump);
490 if (!module->nir)
491 ralloc_free(nir);
492
493 if (variant && cache)
494 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
495 code, code_size);
496
497 if (code)
498 free(code);
499 return variant;
500 }
501
502 static uint32_t si_translate_blend_function(VkBlendOp op)
503 {
504 switch (op) {
505 case VK_BLEND_OP_ADD:
506 return V_028780_COMB_DST_PLUS_SRC;
507 case VK_BLEND_OP_SUBTRACT:
508 return V_028780_COMB_SRC_MINUS_DST;
509 case VK_BLEND_OP_REVERSE_SUBTRACT:
510 return V_028780_COMB_DST_MINUS_SRC;
511 case VK_BLEND_OP_MIN:
512 return V_028780_COMB_MIN_DST_SRC;
513 case VK_BLEND_OP_MAX:
514 return V_028780_COMB_MAX_DST_SRC;
515 default:
516 return 0;
517 }
518 }
519
520 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
521 {
522 switch (factor) {
523 case VK_BLEND_FACTOR_ZERO:
524 return V_028780_BLEND_ZERO;
525 case VK_BLEND_FACTOR_ONE:
526 return V_028780_BLEND_ONE;
527 case VK_BLEND_FACTOR_SRC_COLOR:
528 return V_028780_BLEND_SRC_COLOR;
529 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
530 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
531 case VK_BLEND_FACTOR_DST_COLOR:
532 return V_028780_BLEND_DST_COLOR;
533 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
534 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
535 case VK_BLEND_FACTOR_SRC_ALPHA:
536 return V_028780_BLEND_SRC_ALPHA;
537 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
538 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
539 case VK_BLEND_FACTOR_DST_ALPHA:
540 return V_028780_BLEND_DST_ALPHA;
541 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
542 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
543 case VK_BLEND_FACTOR_CONSTANT_COLOR:
544 return V_028780_BLEND_CONSTANT_COLOR;
545 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
546 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
547 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
548 return V_028780_BLEND_CONSTANT_ALPHA;
549 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
550 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
551 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
552 return V_028780_BLEND_SRC_ALPHA_SATURATE;
553 case VK_BLEND_FACTOR_SRC1_COLOR:
554 return V_028780_BLEND_SRC1_COLOR;
555 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
556 return V_028780_BLEND_INV_SRC1_COLOR;
557 case VK_BLEND_FACTOR_SRC1_ALPHA:
558 return V_028780_BLEND_SRC1_ALPHA;
559 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
560 return V_028780_BLEND_INV_SRC1_ALPHA;
561 default:
562 return 0;
563 }
564 }
565
566 static bool is_dual_src(VkBlendFactor factor)
567 {
568 switch (factor) {
569 case VK_BLEND_FACTOR_SRC1_COLOR:
570 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
571 case VK_BLEND_FACTOR_SRC1_ALPHA:
572 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
573 return true;
574 default:
575 return false;
576 }
577 }
578
579 static unsigned si_choose_spi_color_format(VkFormat vk_format,
580 bool blend_enable,
581 bool blend_need_alpha)
582 {
583 const struct vk_format_description *desc = vk_format_description(vk_format);
584 unsigned format, ntype, swap;
585
586 /* Alpha is needed for alpha-to-coverage.
587 * Blending may be with or without alpha.
588 */
589 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
590 unsigned alpha = 0; /* exports alpha, but may not support blending */
591 unsigned blend = 0; /* supports blending, but may not export alpha */
592 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
593
594 format = radv_translate_colorformat(vk_format);
595 ntype = radv_translate_color_numformat(vk_format, desc,
596 vk_format_get_first_non_void_channel(vk_format));
597 swap = radv_translate_colorswap(vk_format, false);
598
599 /* Choose the SPI color formats. These are required values for Stoney/RB+.
600 * Other chips have multiple choices, though they are not necessarily better.
601 */
602 switch (format) {
603 case V_028C70_COLOR_5_6_5:
604 case V_028C70_COLOR_1_5_5_5:
605 case V_028C70_COLOR_5_5_5_1:
606 case V_028C70_COLOR_4_4_4_4:
607 case V_028C70_COLOR_10_11_11:
608 case V_028C70_COLOR_11_11_10:
609 case V_028C70_COLOR_8:
610 case V_028C70_COLOR_8_8:
611 case V_028C70_COLOR_8_8_8_8:
612 case V_028C70_COLOR_10_10_10_2:
613 case V_028C70_COLOR_2_10_10_10:
614 if (ntype == V_028C70_NUMBER_UINT)
615 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
616 else if (ntype == V_028C70_NUMBER_SINT)
617 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
618 else
619 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
620 break;
621
622 case V_028C70_COLOR_16:
623 case V_028C70_COLOR_16_16:
624 case V_028C70_COLOR_16_16_16_16:
625 if (ntype == V_028C70_NUMBER_UNORM ||
626 ntype == V_028C70_NUMBER_SNORM) {
627 /* UNORM16 and SNORM16 don't support blending */
628 if (ntype == V_028C70_NUMBER_UNORM)
629 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
630 else
631 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
632
633 /* Use 32 bits per channel for blending. */
634 if (format == V_028C70_COLOR_16) {
635 if (swap == V_028C70_SWAP_STD) { /* R */
636 blend = V_028714_SPI_SHADER_32_R;
637 blend_alpha = V_028714_SPI_SHADER_32_AR;
638 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
639 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
640 else
641 assert(0);
642 } else if (format == V_028C70_COLOR_16_16) {
643 if (swap == V_028C70_SWAP_STD) { /* RG */
644 blend = V_028714_SPI_SHADER_32_GR;
645 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
646 } else if (swap == V_028C70_SWAP_ALT) /* RA */
647 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
648 else
649 assert(0);
650 } else /* 16_16_16_16 */
651 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
652 } else if (ntype == V_028C70_NUMBER_UINT)
653 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
654 else if (ntype == V_028C70_NUMBER_SINT)
655 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
656 else if (ntype == V_028C70_NUMBER_FLOAT)
657 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
658 else
659 assert(0);
660 break;
661
662 case V_028C70_COLOR_32:
663 if (swap == V_028C70_SWAP_STD) { /* R */
664 blend = normal = V_028714_SPI_SHADER_32_R;
665 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
666 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
667 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
668 else
669 assert(0);
670 break;
671
672 case V_028C70_COLOR_32_32:
673 if (swap == V_028C70_SWAP_STD) { /* RG */
674 blend = normal = V_028714_SPI_SHADER_32_GR;
675 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
676 } else if (swap == V_028C70_SWAP_ALT) /* RA */
677 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
678 else
679 assert(0);
680 break;
681
682 case V_028C70_COLOR_32_32_32_32:
683 case V_028C70_COLOR_8_24:
684 case V_028C70_COLOR_24_8:
685 case V_028C70_COLOR_X24_8_32_FLOAT:
686 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
687 break;
688
689 default:
690 unreachable("unhandled blend format");
691 }
692
693 if (blend_enable && blend_need_alpha)
694 return blend_alpha;
695 else if(blend_need_alpha)
696 return alpha;
697 else if(blend_enable)
698 return blend;
699 else
700 return normal;
701 }
702
703 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
704 {
705 unsigned i, cb_shader_mask = 0;
706
707 for (i = 0; i < 8; i++) {
708 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
709 case V_028714_SPI_SHADER_ZERO:
710 break;
711 case V_028714_SPI_SHADER_32_R:
712 cb_shader_mask |= 0x1 << (i * 4);
713 break;
714 case V_028714_SPI_SHADER_32_GR:
715 cb_shader_mask |= 0x3 << (i * 4);
716 break;
717 case V_028714_SPI_SHADER_32_AR:
718 cb_shader_mask |= 0x9 << (i * 4);
719 break;
720 case V_028714_SPI_SHADER_FP16_ABGR:
721 case V_028714_SPI_SHADER_UNORM16_ABGR:
722 case V_028714_SPI_SHADER_SNORM16_ABGR:
723 case V_028714_SPI_SHADER_UINT16_ABGR:
724 case V_028714_SPI_SHADER_SINT16_ABGR:
725 case V_028714_SPI_SHADER_32_ABGR:
726 cb_shader_mask |= 0xf << (i * 4);
727 break;
728 default:
729 assert(0);
730 }
731 }
732 return cb_shader_mask;
733 }
734
735 static void
736 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
737 const VkGraphicsPipelineCreateInfo *pCreateInfo,
738 uint32_t blend_enable,
739 uint32_t blend_need_alpha,
740 bool single_cb_enable,
741 bool blend_mrt0_is_dual_src)
742 {
743 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
744 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
745 struct radv_blend_state *blend = &pipeline->graphics.blend;
746 unsigned col_format = 0;
747
748 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
749 struct radv_render_pass_attachment *attachment;
750 unsigned cf;
751
752 attachment = pass->attachments + subpass->color_attachments[i].attachment;
753
754 cf = si_choose_spi_color_format(attachment->format,
755 blend_enable & (1 << i),
756 blend_need_alpha & (1 << i));
757
758 col_format |= cf << (4 * i);
759 }
760
761 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
762
763 if (blend_mrt0_is_dual_src)
764 col_format |= (col_format & 0xf) << 4;
765 if (!col_format)
766 col_format |= V_028714_SPI_SHADER_32_R;
767 blend->spi_shader_col_format = col_format;
768 }
769
770 static bool
771 format_is_int8(VkFormat format)
772 {
773 const struct vk_format_description *desc = vk_format_description(format);
774 int channel = vk_format_get_first_non_void_channel(format);
775
776 return channel >= 0 && desc->channel[channel].pure_integer &&
777 desc->channel[channel].size == 8;
778 }
779
780 unsigned radv_format_meta_fs_key(VkFormat format)
781 {
782 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
783 bool is_int8 = format_is_int8(format);
784
785 return col_format + (is_int8 ? 3 : 0);
786 }
787
788 static unsigned
789 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
790 {
791 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
792 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
793 unsigned is_int8 = 0;
794
795 for (unsigned i = 0; i < subpass->color_count; ++i) {
796 struct radv_render_pass_attachment *attachment;
797
798 attachment = pass->attachments + subpass->color_attachments[i].attachment;
799
800 if (format_is_int8(attachment->format))
801 is_int8 |= 1 << i;
802 }
803
804 return is_int8;
805 }
806
807 static void
808 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
809 const VkGraphicsPipelineCreateInfo *pCreateInfo,
810 const struct radv_graphics_pipeline_create_info *extra)
811 {
812 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
813 struct radv_blend_state *blend = &pipeline->graphics.blend;
814 unsigned mode = V_028808_CB_NORMAL;
815 uint32_t blend_enable = 0, blend_need_alpha = 0;
816 bool blend_mrt0_is_dual_src = false;
817 int i;
818 bool single_cb_enable = false;
819
820 if (!vkblend)
821 return;
822
823 if (extra && extra->custom_blend_mode) {
824 single_cb_enable = true;
825 mode = extra->custom_blend_mode;
826 }
827 blend->cb_color_control = 0;
828 if (vkblend->logicOpEnable)
829 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
830 else
831 blend->cb_color_control |= S_028808_ROP3(0xcc);
832
833 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
834 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
835 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
836 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
837
838 blend->cb_target_mask = 0;
839 for (i = 0; i < vkblend->attachmentCount; i++) {
840 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
841 unsigned blend_cntl = 0;
842 VkBlendOp eqRGB = att->colorBlendOp;
843 VkBlendFactor srcRGB = att->srcColorBlendFactor;
844 VkBlendFactor dstRGB = att->dstColorBlendFactor;
845 VkBlendOp eqA = att->alphaBlendOp;
846 VkBlendFactor srcA = att->srcAlphaBlendFactor;
847 VkBlendFactor dstA = att->dstAlphaBlendFactor;
848
849 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
850
851 if (!att->colorWriteMask)
852 continue;
853
854 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
855 if (!att->blendEnable) {
856 blend->cb_blend_control[i] = blend_cntl;
857 continue;
858 }
859
860 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
861 if (i == 0)
862 blend_mrt0_is_dual_src = true;
863
864 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
865 srcRGB = VK_BLEND_FACTOR_ONE;
866 dstRGB = VK_BLEND_FACTOR_ONE;
867 }
868 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
869 srcA = VK_BLEND_FACTOR_ONE;
870 dstA = VK_BLEND_FACTOR_ONE;
871 }
872
873 blend_cntl |= S_028780_ENABLE(1);
874
875 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
876 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
877 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
878 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
879 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
880 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
881 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
882 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
883 }
884 blend->cb_blend_control[i] = blend_cntl;
885
886 blend_enable |= 1 << i;
887
888 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
889 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
890 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
891 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
892 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
893 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
894 blend_need_alpha |= 1 << i;
895 }
896 for (i = vkblend->attachmentCount; i < 8; i++)
897 blend->cb_blend_control[i] = 0;
898
899 if (blend->cb_target_mask)
900 blend->cb_color_control |= S_028808_MODE(mode);
901 else
902 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
903
904 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
905 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
906 }
907
908 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
909 {
910 switch (op) {
911 case VK_STENCIL_OP_KEEP:
912 return V_02842C_STENCIL_KEEP;
913 case VK_STENCIL_OP_ZERO:
914 return V_02842C_STENCIL_ZERO;
915 case VK_STENCIL_OP_REPLACE:
916 return V_02842C_STENCIL_REPLACE_TEST;
917 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
918 return V_02842C_STENCIL_ADD_CLAMP;
919 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
920 return V_02842C_STENCIL_SUB_CLAMP;
921 case VK_STENCIL_OP_INVERT:
922 return V_02842C_STENCIL_INVERT;
923 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
924 return V_02842C_STENCIL_ADD_WRAP;
925 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
926 return V_02842C_STENCIL_SUB_WRAP;
927 default:
928 return 0;
929 }
930 }
931 static void
932 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
933 const VkGraphicsPipelineCreateInfo *pCreateInfo,
934 const struct radv_graphics_pipeline_create_info *extra)
935 {
936 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
937 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
938
939 memset(ds, 0, sizeof(*ds));
940 if (!vkds)
941 return;
942 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
943 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
944 S_028800_ZFUNC(vkds->depthCompareOp) |
945 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
946
947 if (vkds->stencilTestEnable) {
948 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
949 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
950 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
951 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
952 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
953
954 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
955 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
956 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
957 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
958 }
959
960 if (extra) {
961
962 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
963 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
964
965 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
966 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
967 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
968 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
969 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
970 }
971 }
972
973 static uint32_t si_translate_fill(VkPolygonMode func)
974 {
975 switch(func) {
976 case VK_POLYGON_MODE_FILL:
977 return V_028814_X_DRAW_TRIANGLES;
978 case VK_POLYGON_MODE_LINE:
979 return V_028814_X_DRAW_LINES;
980 case VK_POLYGON_MODE_POINT:
981 return V_028814_X_DRAW_POINTS;
982 default:
983 assert(0);
984 return V_028814_X_DRAW_POINTS;
985 }
986 }
987 static void
988 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
989 const VkGraphicsPipelineCreateInfo *pCreateInfo)
990 {
991 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
992 struct radv_raster_state *raster = &pipeline->graphics.raster;
993
994 memset(raster, 0, sizeof(*raster));
995
996 raster->spi_interp_control =
997 S_0286D4_FLAT_SHADE_ENA(1) |
998 S_0286D4_PNT_SPRITE_ENA(1) |
999 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1000 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1001 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1002 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1003 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1004
1005 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1006 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1007 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1008 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1009 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1010 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1011 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1012
1013 raster->pa_su_vtx_cntl =
1014 S_028BE4_PIX_CENTER(1) | // TODO verify
1015 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1016 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1017
1018 raster->pa_su_sc_mode_cntl =
1019 S_028814_FACE(vkraster->frontFace) |
1020 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1021 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1022 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1023 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1024 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1025 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1026 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1027 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1028
1029 }
1030
1031 static void
1032 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1033 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1034 {
1035 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1036 struct radv_blend_state *blend = &pipeline->graphics.blend;
1037 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1038 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1039 int ps_iter_samples = 1;
1040 uint32_t mask = 0xffff;
1041
1042 ms->num_samples = vkms->rasterizationSamples;
1043
1044 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1045 ps_iter_samples = vkms->rasterizationSamples;
1046 }
1047
1048 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1049 ms->pa_sc_aa_config = 0;
1050 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1051 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1052 ms->pa_sc_mode_cntl_1 =
1053 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1054 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1055 /* always 1: */
1056 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1057 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1058 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1059 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1060 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1061 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1062
1063 if (vkms->rasterizationSamples > 1) {
1064 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1065 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1066 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1067 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1068 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1069 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1070 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1071 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1072 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1073 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1074 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1075 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1076 }
1077
1078 if (vkms->alphaToCoverageEnable)
1079 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1080
1081 if (vkms->pSampleMask) {
1082 mask = vkms->pSampleMask[0] & 0xffff;
1083 }
1084
1085 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1086 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1087 }
1088
1089 static uint32_t
1090 si_translate_prim(enum VkPrimitiveTopology topology)
1091 {
1092 switch (topology) {
1093 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1094 return V_008958_DI_PT_POINTLIST;
1095 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1096 return V_008958_DI_PT_LINELIST;
1097 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1098 return V_008958_DI_PT_LINESTRIP;
1099 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1100 return V_008958_DI_PT_TRILIST;
1101 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1102 return V_008958_DI_PT_TRISTRIP;
1103 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1104 return V_008958_DI_PT_TRIFAN;
1105 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1106 return V_008958_DI_PT_LINELIST_ADJ;
1107 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1108 return V_008958_DI_PT_LINESTRIP_ADJ;
1109 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1110 return V_008958_DI_PT_TRILIST_ADJ;
1111 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1112 return V_008958_DI_PT_TRISTRIP_ADJ;
1113 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1114 return V_008958_DI_PT_PATCH;
1115 default:
1116 assert(0);
1117 return 0;
1118 }
1119 }
1120
1121 static uint32_t
1122 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1123 {
1124 switch (topology) {
1125 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1126 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1127 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1128 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1129 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1130 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1131 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1132 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1133 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1134 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1135 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1136 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1137 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1138 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1139 default:
1140 assert(0);
1141 return 0;
1142 }
1143 }
1144
1145 static unsigned si_map_swizzle(unsigned swizzle)
1146 {
1147 switch (swizzle) {
1148 case VK_SWIZZLE_Y:
1149 return V_008F0C_SQ_SEL_Y;
1150 case VK_SWIZZLE_Z:
1151 return V_008F0C_SQ_SEL_Z;
1152 case VK_SWIZZLE_W:
1153 return V_008F0C_SQ_SEL_W;
1154 case VK_SWIZZLE_0:
1155 return V_008F0C_SQ_SEL_0;
1156 case VK_SWIZZLE_1:
1157 return V_008F0C_SQ_SEL_1;
1158 default: /* VK_SWIZZLE_X */
1159 return V_008F0C_SQ_SEL_X;
1160 }
1161 }
1162
1163 static void
1164 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1165 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1166 {
1167 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1168 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1169 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1170
1171 pipeline->dynamic_state = default_dynamic_state;
1172
1173 if (pCreateInfo->pDynamicState) {
1174 /* Remove all of the states that are marked as dynamic */
1175 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1176 for (uint32_t s = 0; s < count; s++)
1177 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1178 }
1179
1180 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1181
1182 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1183 *
1184 * pViewportState is [...] NULL if the pipeline
1185 * has rasterization disabled.
1186 */
1187 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1188 assert(pCreateInfo->pViewportState);
1189
1190 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1191 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1192 typed_memcpy(dynamic->viewport.viewports,
1193 pCreateInfo->pViewportState->pViewports,
1194 pCreateInfo->pViewportState->viewportCount);
1195 }
1196
1197 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1198 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1199 typed_memcpy(dynamic->scissor.scissors,
1200 pCreateInfo->pViewportState->pScissors,
1201 pCreateInfo->pViewportState->scissorCount);
1202 }
1203 }
1204
1205 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1206 assert(pCreateInfo->pRasterizationState);
1207 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1208 }
1209
1210 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1211 assert(pCreateInfo->pRasterizationState);
1212 dynamic->depth_bias.bias =
1213 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1214 dynamic->depth_bias.clamp =
1215 pCreateInfo->pRasterizationState->depthBiasClamp;
1216 dynamic->depth_bias.slope =
1217 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1218 }
1219
1220 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1221 *
1222 * pColorBlendState is [...] NULL if the pipeline has rasterization
1223 * disabled or if the subpass of the render pass the pipeline is
1224 * created against does not use any color attachments.
1225 */
1226 bool uses_color_att = false;
1227 for (unsigned i = 0; i < subpass->color_count; ++i) {
1228 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1229 uses_color_att = true;
1230 break;
1231 }
1232 }
1233
1234 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1235 assert(pCreateInfo->pColorBlendState);
1236 typed_memcpy(dynamic->blend_constants,
1237 pCreateInfo->pColorBlendState->blendConstants, 4);
1238 }
1239
1240 /* If there is no depthstencil attachment, then don't read
1241 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1242 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1243 * no need to override the depthstencil defaults in
1244 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1245 *
1246 * Section 9.2 of the Vulkan 1.0.15 spec says:
1247 *
1248 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1249 * disabled or if the subpass of the render pass the pipeline is created
1250 * against does not use a depth/stencil attachment.
1251 */
1252 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1253 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1254 assert(pCreateInfo->pDepthStencilState);
1255
1256 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1257 dynamic->depth_bounds.min =
1258 pCreateInfo->pDepthStencilState->minDepthBounds;
1259 dynamic->depth_bounds.max =
1260 pCreateInfo->pDepthStencilState->maxDepthBounds;
1261 }
1262
1263 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1264 dynamic->stencil_compare_mask.front =
1265 pCreateInfo->pDepthStencilState->front.compareMask;
1266 dynamic->stencil_compare_mask.back =
1267 pCreateInfo->pDepthStencilState->back.compareMask;
1268 }
1269
1270 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1271 dynamic->stencil_write_mask.front =
1272 pCreateInfo->pDepthStencilState->front.writeMask;
1273 dynamic->stencil_write_mask.back =
1274 pCreateInfo->pDepthStencilState->back.writeMask;
1275 }
1276
1277 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1278 dynamic->stencil_reference.front =
1279 pCreateInfo->pDepthStencilState->front.reference;
1280 dynamic->stencil_reference.back =
1281 pCreateInfo->pDepthStencilState->back.reference;
1282 }
1283 }
1284
1285 pipeline->dynamic_state_mask = states;
1286 }
1287
1288 static union ac_shader_variant_key
1289 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1290 {
1291 union ac_shader_variant_key key;
1292 const VkPipelineVertexInputStateCreateInfo *input_state =
1293 pCreateInfo->pVertexInputState;
1294
1295 memset(&key, 0, sizeof(key));
1296 key.vs.instance_rate_inputs = 0;
1297
1298 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1299 unsigned binding;
1300 binding = input_state->pVertexAttributeDescriptions[i].binding;
1301 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1302 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1303 }
1304 return key;
1305 }
1306
1307 VkResult
1308 radv_pipeline_init(struct radv_pipeline *pipeline,
1309 struct radv_device *device,
1310 struct radv_pipeline_cache *cache,
1311 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1312 const struct radv_graphics_pipeline_create_info *extra,
1313 const VkAllocationCallbacks *alloc)
1314 {
1315 struct radv_shader_module fs_m = {0};
1316
1317 if (alloc == NULL)
1318 alloc = &device->alloc;
1319
1320 pipeline->device = device;
1321 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1322
1323 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1324 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1325 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1326 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1327 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1328 pStages[stage] = &pCreateInfo->pStages[i];
1329 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1330 }
1331
1332 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1333
1334 /* */
1335 if (modules[MESA_SHADER_VERTEX]) {
1336 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1337
1338 pipeline->shaders[MESA_SHADER_VERTEX] =
1339 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1340 pStages[MESA_SHADER_VERTEX]->pName,
1341 MESA_SHADER_VERTEX,
1342 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1343 pipeline->layout, &key);
1344
1345 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1346 }
1347
1348 if (!modules[MESA_SHADER_FRAGMENT]) {
1349 nir_builder fs_b;
1350 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1351 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1352 fs_m.nir = fs_b.shader;
1353 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1354 }
1355
1356 if (modules[MESA_SHADER_FRAGMENT]) {
1357 union ac_shader_variant_key key;
1358 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1359 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1360
1361 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1362
1363 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1364 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1365 stage ? stage->pName : "main",
1366 MESA_SHADER_FRAGMENT,
1367 stage ? stage->pSpecializationInfo : NULL,
1368 pipeline->layout, &key);
1369 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1370 }
1371
1372 if (fs_m.nir)
1373 ralloc_free(fs_m.nir);
1374
1375 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1376 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1377 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1378 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1379 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1380 if (extra && extra->use_rectlist) {
1381 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1382 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1383 }
1384 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1385
1386 const VkPipelineVertexInputStateCreateInfo *vi_info =
1387 pCreateInfo->pVertexInputState;
1388 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1389 const VkVertexInputAttributeDescription *desc =
1390 &vi_info->pVertexAttributeDescriptions[i];
1391 unsigned loc = desc->location;
1392 const struct vk_format_description *format_desc;
1393 int first_non_void;
1394 uint32_t num_format, data_format;
1395 format_desc = vk_format_description(desc->format);
1396 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1397
1398 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1399 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1400
1401 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1402 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1403 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1404 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1405 S_008F0C_NUM_FORMAT(num_format) |
1406 S_008F0C_DATA_FORMAT(data_format);
1407 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1408 pipeline->va_offset[loc] = desc->offset;
1409 pipeline->va_binding[loc] = desc->binding;
1410 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1411 }
1412
1413 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1414 const VkVertexInputBindingDescription *desc =
1415 &vi_info->pVertexBindingDescriptions[i];
1416
1417 pipeline->binding_stride[desc->binding] = desc->stride;
1418 }
1419
1420 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1421 radv_dump_pipeline_stats(device, pipeline);
1422 }
1423
1424 return VK_SUCCESS;
1425 }
1426
1427 VkResult
1428 radv_graphics_pipeline_create(
1429 VkDevice _device,
1430 VkPipelineCache _cache,
1431 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1432 const struct radv_graphics_pipeline_create_info *extra,
1433 const VkAllocationCallbacks *pAllocator,
1434 VkPipeline *pPipeline)
1435 {
1436 RADV_FROM_HANDLE(radv_device, device, _device);
1437 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1438 struct radv_pipeline *pipeline;
1439 VkResult result;
1440
1441 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1442 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1443 if (pipeline == NULL)
1444 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1445
1446 memset(pipeline, 0, sizeof(*pipeline));
1447 result = radv_pipeline_init(pipeline, device, cache,
1448 pCreateInfo, extra, pAllocator);
1449 if (result != VK_SUCCESS) {
1450 vk_free2(&device->alloc, pAllocator, pipeline);
1451 return result;
1452 }
1453
1454 *pPipeline = radv_pipeline_to_handle(pipeline);
1455
1456 return VK_SUCCESS;
1457 }
1458
1459 VkResult radv_CreateGraphicsPipelines(
1460 VkDevice _device,
1461 VkPipelineCache pipelineCache,
1462 uint32_t count,
1463 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1464 const VkAllocationCallbacks* pAllocator,
1465 VkPipeline* pPipelines)
1466 {
1467 VkResult result = VK_SUCCESS;
1468 unsigned i = 0;
1469
1470 for (; i < count; i++) {
1471 VkResult r;
1472 r = radv_graphics_pipeline_create(_device,
1473 pipelineCache,
1474 &pCreateInfos[i],
1475 NULL, pAllocator, &pPipelines[i]);
1476 if (r != VK_SUCCESS) {
1477 result = r;
1478 pPipelines[i] = VK_NULL_HANDLE;
1479 }
1480 }
1481
1482 return result;
1483 }
1484
1485 static VkResult radv_compute_pipeline_create(
1486 VkDevice _device,
1487 VkPipelineCache _cache,
1488 const VkComputePipelineCreateInfo* pCreateInfo,
1489 const VkAllocationCallbacks* pAllocator,
1490 VkPipeline* pPipeline)
1491 {
1492 RADV_FROM_HANDLE(radv_device, device, _device);
1493 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1494 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1495 struct radv_pipeline *pipeline;
1496
1497 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1498 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1499 if (pipeline == NULL)
1500 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1501
1502 memset(pipeline, 0, sizeof(*pipeline));
1503 pipeline->device = device;
1504 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1505
1506 pipeline->shaders[MESA_SHADER_COMPUTE] =
1507 radv_pipeline_compile(pipeline, cache, module,
1508 pCreateInfo->stage.pName,
1509 MESA_SHADER_COMPUTE,
1510 pCreateInfo->stage.pSpecializationInfo,
1511 pipeline->layout, NULL);
1512
1513 *pPipeline = radv_pipeline_to_handle(pipeline);
1514
1515 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1516 radv_dump_pipeline_stats(device, pipeline);
1517 }
1518 return VK_SUCCESS;
1519 }
1520 VkResult radv_CreateComputePipelines(
1521 VkDevice _device,
1522 VkPipelineCache pipelineCache,
1523 uint32_t count,
1524 const VkComputePipelineCreateInfo* pCreateInfos,
1525 const VkAllocationCallbacks* pAllocator,
1526 VkPipeline* pPipelines)
1527 {
1528 VkResult result = VK_SUCCESS;
1529
1530 unsigned i = 0;
1531 for (; i < count; i++) {
1532 VkResult r;
1533 r = radv_compute_pipeline_create(_device, pipelineCache,
1534 &pCreateInfos[i],
1535 pAllocator, &pPipelines[i]);
1536 if (r != VK_SUCCESS) {
1537 result = r;
1538 pPipelines[i] = VK_NULL_HANDLE;
1539 }
1540 }
1541
1542 return result;
1543 }