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radv: enable lower_sub to fix loop unrolling.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 #include "ac_exp_param.h"
45
46 void radv_shader_variant_destroy(struct radv_device *device,
47 struct radv_shader_variant *variant);
48
49 static const struct nir_shader_compiler_options nir_options = {
50 .vertex_id_zero_based = true,
51 .lower_scmp = true,
52 .lower_flrp32 = true,
53 .lower_fsat = true,
54 .lower_fdiv = true,
55 .lower_sub = true,
56 .lower_pack_snorm_2x16 = true,
57 .lower_pack_snorm_4x8 = true,
58 .lower_pack_unorm_2x16 = true,
59 .lower_pack_unorm_4x8 = true,
60 .lower_unpack_snorm_2x16 = true,
61 .lower_unpack_snorm_4x8 = true,
62 .lower_unpack_unorm_2x16 = true,
63 .lower_unpack_unorm_4x8 = true,
64 .lower_extract_byte = true,
65 .lower_extract_word = true,
66 .max_unroll_iterations = 32
67 };
68
69 VkResult radv_CreateShaderModule(
70 VkDevice _device,
71 const VkShaderModuleCreateInfo* pCreateInfo,
72 const VkAllocationCallbacks* pAllocator,
73 VkShaderModule* pShaderModule)
74 {
75 RADV_FROM_HANDLE(radv_device, device, _device);
76 struct radv_shader_module *module;
77
78 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
79 assert(pCreateInfo->flags == 0);
80
81 module = vk_alloc2(&device->alloc, pAllocator,
82 sizeof(*module) + pCreateInfo->codeSize, 8,
83 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
84 if (module == NULL)
85 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
86
87 module->nir = NULL;
88 module->size = pCreateInfo->codeSize;
89 memcpy(module->data, pCreateInfo->pCode, module->size);
90
91 _mesa_sha1_compute(module->data, module->size, module->sha1);
92
93 *pShaderModule = radv_shader_module_to_handle(module);
94
95 return VK_SUCCESS;
96 }
97
98 void radv_DestroyShaderModule(
99 VkDevice _device,
100 VkShaderModule _module,
101 const VkAllocationCallbacks* pAllocator)
102 {
103 RADV_FROM_HANDLE(radv_device, device, _device);
104 RADV_FROM_HANDLE(radv_shader_module, module, _module);
105
106 if (!module)
107 return;
108
109 vk_free2(&device->alloc, pAllocator, module);
110 }
111
112
113 static void
114 radv_pipeline_destroy(struct radv_device *device,
115 struct radv_pipeline *pipeline,
116 const VkAllocationCallbacks* allocator)
117 {
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 if (pipeline->gs_copy_shader)
123 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
124
125 vk_free2(&device->alloc, allocator, pipeline);
126 }
127
128 void radv_DestroyPipeline(
129 VkDevice _device,
130 VkPipeline _pipeline,
131 const VkAllocationCallbacks* pAllocator)
132 {
133 RADV_FROM_HANDLE(radv_device, device, _device);
134 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
135
136 if (!_pipeline)
137 return;
138
139 radv_pipeline_destroy(device, pipeline, pAllocator);
140 }
141
142
143 static void
144 radv_optimize_nir(struct nir_shader *shader)
145 {
146 bool progress;
147
148 do {
149 progress = false;
150
151 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
152 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
153 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
154
155 NIR_PASS(progress, shader, nir_copy_prop);
156 NIR_PASS(progress, shader, nir_opt_remove_phis);
157 NIR_PASS(progress, shader, nir_opt_dce);
158 if (nir_opt_trivial_continues(shader)) {
159 progress = true;
160 NIR_PASS(progress, shader, nir_copy_prop);
161 NIR_PASS(progress, shader, nir_opt_dce);
162 }
163 NIR_PASS(progress, shader, nir_opt_if);
164 NIR_PASS(progress, shader, nir_opt_dead_cf);
165 NIR_PASS(progress, shader, nir_opt_cse);
166 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
167 NIR_PASS(progress, shader, nir_opt_algebraic);
168 NIR_PASS(progress, shader, nir_opt_constant_folding);
169 NIR_PASS(progress, shader, nir_opt_undef);
170 NIR_PASS(progress, shader, nir_opt_conditional_discard);
171 if (shader->options->max_unroll_iterations) {
172 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
173 }
174 } while (progress);
175 }
176
177 static nir_shader *
178 radv_shader_compile_to_nir(struct radv_device *device,
179 struct radv_shader_module *module,
180 const char *entrypoint_name,
181 gl_shader_stage stage,
182 const VkSpecializationInfo *spec_info,
183 bool dump)
184 {
185 if (strcmp(entrypoint_name, "main") != 0) {
186 radv_finishme("Multiple shaders per module not really supported");
187 }
188
189 nir_shader *nir;
190 nir_function *entry_point;
191 if (module->nir) {
192 /* Some things such as our meta clear/blit code will give us a NIR
193 * shader directly. In that case, we just ignore the SPIR-V entirely
194 * and just use the NIR shader */
195 nir = module->nir;
196 nir->options = &nir_options;
197 nir_validate_shader(nir);
198
199 assert(exec_list_length(&nir->functions) == 1);
200 struct exec_node *node = exec_list_get_head(&nir->functions);
201 entry_point = exec_node_data(nir_function, node, node);
202 } else {
203 uint32_t *spirv = (uint32_t *) module->data;
204 assert(module->size % 4 == 0);
205
206 uint32_t num_spec_entries = 0;
207 struct nir_spirv_specialization *spec_entries = NULL;
208 if (spec_info && spec_info->mapEntryCount > 0) {
209 num_spec_entries = spec_info->mapEntryCount;
210 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
211 for (uint32_t i = 0; i < num_spec_entries; i++) {
212 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
213 const void *data = spec_info->pData + entry.offset;
214 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
215
216 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
217 if (spec_info->dataSize == 8)
218 spec_entries[i].data64 = *(const uint64_t *)data;
219 else
220 spec_entries[i].data32 = *(const uint32_t *)data;
221 }
222 }
223 const struct nir_spirv_supported_extensions supported_ext = {
224 .draw_parameters = true,
225 .float64 = true,
226 .image_read_without_format = true,
227 .image_write_without_format = true,
228 .tessellation = true,
229 };
230 entry_point = spirv_to_nir(spirv, module->size / 4,
231 spec_entries, num_spec_entries,
232 stage, entrypoint_name, &supported_ext, &nir_options);
233 nir = entry_point->shader;
234 assert(nir->stage == stage);
235 nir_validate_shader(nir);
236
237 free(spec_entries);
238
239 /* We have to lower away local constant initializers right before we
240 * inline functions. That way they get properly initialized at the top
241 * of the function and not at the top of its caller.
242 */
243 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
244 NIR_PASS_V(nir, nir_lower_returns);
245 NIR_PASS_V(nir, nir_inline_functions);
246
247 /* Pick off the single entrypoint that we want */
248 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
249 if (func != entry_point)
250 exec_node_remove(&func->node);
251 }
252 assert(exec_list_length(&nir->functions) == 1);
253 entry_point->name = ralloc_strdup(entry_point, "main");
254
255 NIR_PASS_V(nir, nir_remove_dead_variables,
256 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
257
258 /* Now that we've deleted all but the main function, we can go ahead and
259 * lower the rest of the constant initializers.
260 */
261 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
262 NIR_PASS_V(nir, nir_lower_system_values);
263 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
264 }
265
266 /* Vulkan uses the separate-shader linking model */
267 nir->info->separate_shader = true;
268
269 nir_shader_gather_info(nir, entry_point->impl);
270
271 nir_variable_mode indirect_mask = 0;
272 indirect_mask |= nir_var_shader_in;
273 indirect_mask |= nir_var_local;
274
275 nir_lower_indirect_derefs(nir, indirect_mask);
276
277 static const nir_lower_tex_options tex_options = {
278 .lower_txp = ~0,
279 };
280
281 nir_lower_tex(nir, &tex_options);
282
283 nir_lower_vars_to_ssa(nir);
284 nir_lower_var_copies(nir);
285 nir_lower_global_vars_to_local(nir);
286 nir_remove_dead_variables(nir, nir_var_local);
287 radv_optimize_nir(nir);
288
289 if (dump)
290 nir_print_shader(nir, stderr);
291
292 return nir;
293 }
294
295 static const char *radv_get_shader_name(struct radv_shader_variant *var,
296 gl_shader_stage stage)
297 {
298 switch (stage) {
299 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
300 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
301 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
302 case MESA_SHADER_COMPUTE: return "Compute Shader";
303 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
304 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
305 default:
306 return "Unknown shader";
307 };
308
309 }
310 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
311 {
312 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
313 struct radv_shader_variant *var;
314 struct ac_shader_config *conf;
315 int i;
316 FILE *file = stderr;
317 unsigned max_simd_waves = 10;
318 unsigned lds_per_wave = 0;
319
320 for (i = 0; i < MESA_SHADER_STAGES; i++) {
321 if (!pipeline->shaders[i])
322 continue;
323 var = pipeline->shaders[i];
324
325 conf = &var->config;
326
327 if (i == MESA_SHADER_FRAGMENT) {
328 lds_per_wave = conf->lds_size * lds_increment +
329 align(var->info.fs.num_interp * 48, lds_increment);
330 }
331
332 if (conf->num_sgprs) {
333 if (device->physical_device->rad_info.chip_class >= VI)
334 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
335 else
336 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
337 }
338
339 if (conf->num_vgprs)
340 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
341
342 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
343 * that PS can use.
344 */
345 if (lds_per_wave)
346 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
347
348 fprintf(file, "\n%s:\n",
349 radv_get_shader_name(var, i));
350 if (i == MESA_SHADER_FRAGMENT) {
351 fprintf(file, "*** SHADER CONFIG ***\n"
352 "SPI_PS_INPUT_ADDR = 0x%04x\n"
353 "SPI_PS_INPUT_ENA = 0x%04x\n",
354 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
355 }
356 fprintf(file, "*** SHADER STATS ***\n"
357 "SGPRS: %d\n"
358 "VGPRS: %d\n"
359 "Spilled SGPRs: %d\n"
360 "Spilled VGPRs: %d\n"
361 "Code Size: %d bytes\n"
362 "LDS: %d blocks\n"
363 "Scratch: %d bytes per wave\n"
364 "Max Waves: %d\n"
365 "********************\n\n\n",
366 conf->num_sgprs, conf->num_vgprs,
367 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
368 conf->lds_size, conf->scratch_bytes_per_wave,
369 max_simd_waves);
370 }
371 }
372
373 void radv_shader_variant_destroy(struct radv_device *device,
374 struct radv_shader_variant *variant)
375 {
376 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
377 return;
378
379 device->ws->buffer_destroy(variant->bo);
380 free(variant);
381 }
382
383 static void radv_fill_shader_variant(struct radv_device *device,
384 struct radv_shader_variant *variant,
385 struct ac_shader_binary *binary,
386 gl_shader_stage stage)
387 {
388 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
389 unsigned vgpr_comp_cnt = 0;
390
391 if (scratch_enabled && !device->llvm_supports_spill)
392 radv_finishme("shader scratch support only available with LLVM 4.0");
393
394 variant->code_size = binary->code_size;
395 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
396 S_00B12C_SCRATCH_EN(scratch_enabled);
397
398 switch (stage) {
399 case MESA_SHADER_TESS_EVAL:
400 vgpr_comp_cnt = 3;
401 /* fallthrough */
402 case MESA_SHADER_TESS_CTRL:
403 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
404 break;
405 case MESA_SHADER_VERTEX:
406 case MESA_SHADER_GEOMETRY:
407 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
408 break;
409 case MESA_SHADER_FRAGMENT:
410 break;
411 case MESA_SHADER_COMPUTE:
412 variant->rsrc2 |=
413 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
414 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
415 S_00B84C_TG_SIZE_EN(1) |
416 S_00B84C_LDS_SIZE(variant->config.lds_size);
417 break;
418 default:
419 unreachable("unsupported shader type");
420 break;
421 }
422
423 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
424 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
425 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
426 S_00B848_DX10_CLAMP(1) |
427 S_00B848_FLOAT_MODE(variant->config.float_mode);
428
429 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
430 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
431
432 void *ptr = device->ws->buffer_map(variant->bo);
433 memcpy(ptr, binary->code, binary->code_size);
434 device->ws->buffer_unmap(variant->bo);
435
436
437 }
438
439 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
440 struct nir_shader *shader,
441 struct radv_pipeline_layout *layout,
442 const union ac_shader_variant_key *key,
443 void** code_out,
444 unsigned *code_size_out,
445 bool dump)
446 {
447 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
448 enum radeon_family chip_family = device->physical_device->rad_info.family;
449 LLVMTargetMachineRef tm;
450 if (!variant)
451 return NULL;
452
453 struct ac_nir_compiler_options options = {0};
454 options.layout = layout;
455 if (key)
456 options.key = *key;
457
458 struct ac_shader_binary binary;
459
460 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
461 options.family = chip_family;
462 options.chip_class = device->physical_device->rad_info.chip_class;
463 options.supports_spill = device->llvm_supports_spill;
464 tm = ac_create_target_machine(chip_family, options.supports_spill);
465 ac_compile_nir_shader(tm, &binary, &variant->config,
466 &variant->info, shader, &options, dump);
467 LLVMDisposeTargetMachine(tm);
468
469 radv_fill_shader_variant(device, variant, &binary, shader->stage);
470
471 if (code_out) {
472 *code_out = binary.code;
473 *code_size_out = binary.code_size;
474 } else
475 free(binary.code);
476 free(binary.config);
477 free(binary.rodata);
478 free(binary.global_symbol_offsets);
479 free(binary.relocs);
480 free(binary.disasm_string);
481 variant->ref_count = 1;
482 return variant;
483 }
484
485 static struct radv_shader_variant *
486 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
487 struct nir_shader *nir,
488 void** code_out,
489 unsigned *code_size_out,
490 bool dump_shader)
491 {
492 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
493 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
494 LLVMTargetMachineRef tm;
495 if (!variant)
496 return NULL;
497
498 struct ac_nir_compiler_options options = {0};
499 struct ac_shader_binary binary;
500 options.family = chip_family;
501 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
502 options.supports_spill = pipeline->device->llvm_supports_spill;
503 tm = ac_create_target_machine(chip_family, options.supports_spill);
504 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
505 LLVMDisposeTargetMachine(tm);
506
507 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
508
509 if (code_out) {
510 *code_out = binary.code;
511 *code_size_out = binary.code_size;
512 } else
513 free(binary.code);
514 free(binary.config);
515 free(binary.rodata);
516 free(binary.global_symbol_offsets);
517 free(binary.relocs);
518 free(binary.disasm_string);
519 variant->ref_count = 1;
520 return variant;
521 }
522
523 static struct radv_shader_variant *
524 radv_pipeline_compile(struct radv_pipeline *pipeline,
525 struct radv_pipeline_cache *cache,
526 struct radv_shader_module *module,
527 const char *entrypoint,
528 gl_shader_stage stage,
529 const VkSpecializationInfo *spec_info,
530 struct radv_pipeline_layout *layout,
531 const union ac_shader_variant_key *key)
532 {
533 unsigned char sha1[20];
534 unsigned char gs_copy_sha1[20];
535 struct radv_shader_variant *variant;
536 nir_shader *nir;
537 void *code = NULL;
538 unsigned code_size = 0;
539 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
540
541 if (module->nir)
542 _mesa_sha1_compute(module->nir->info->name,
543 strlen(module->nir->info->name),
544 module->sha1);
545
546 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
547 if (stage == MESA_SHADER_GEOMETRY)
548 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
549 layout, key, 1);
550
551 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
552 cache,
553 sha1);
554
555 if (stage == MESA_SHADER_GEOMETRY) {
556 pipeline->gs_copy_shader =
557 radv_create_shader_variant_from_pipeline_cache(
558 pipeline->device,
559 cache,
560 gs_copy_sha1);
561 }
562
563 if (variant &&
564 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
565 return variant;
566
567 nir = radv_shader_compile_to_nir(pipeline->device,
568 module, entrypoint, stage,
569 spec_info, dump);
570 if (nir == NULL)
571 return NULL;
572
573 if (!variant) {
574 variant = radv_shader_variant_create(pipeline->device, nir,
575 layout, key, &code,
576 &code_size, dump);
577 }
578
579 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
580 void *gs_copy_code = NULL;
581 unsigned gs_copy_code_size = 0;
582 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
583 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
584
585 if (pipeline->gs_copy_shader) {
586 pipeline->gs_copy_shader =
587 radv_pipeline_cache_insert_shader(cache,
588 gs_copy_sha1,
589 pipeline->gs_copy_shader,
590 gs_copy_code,
591 gs_copy_code_size);
592 }
593 }
594 if (!module->nir)
595 ralloc_free(nir);
596
597 if (variant)
598 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
599 code, code_size);
600
601 if (code)
602 free(code);
603 return variant;
604 }
605
606 static union ac_shader_variant_key
607 radv_compute_tes_key(bool as_es)
608 {
609 union ac_shader_variant_key key;
610 memset(&key, 0, sizeof(key));
611 key.tes.as_es = as_es;
612 return key;
613 }
614
615 static union ac_shader_variant_key
616 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
617 {
618 union ac_shader_variant_key key;
619 memset(&key, 0, sizeof(key));
620 key.tcs.primitive_mode = primitive_mode;
621 key.tcs.input_vertices = input_vertices;
622 return key;
623 }
624
625 static void
626 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
627 struct radv_pipeline_cache *cache,
628 struct radv_shader_module *tcs_module,
629 struct radv_shader_module *tes_module,
630 const char *tcs_entrypoint,
631 const char *tes_entrypoint,
632 const VkSpecializationInfo *tcs_spec_info,
633 const VkSpecializationInfo *tes_spec_info,
634 struct radv_pipeline_layout *layout,
635 unsigned input_vertices)
636 {
637 unsigned char tcs_sha1[20], tes_sha1[20];
638 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
639 nir_shader *tes_nir, *tcs_nir;
640 void *tes_code = NULL, *tcs_code = NULL;
641 unsigned tes_code_size = 0, tcs_code_size = 0;
642 union ac_shader_variant_key tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline));
643 union ac_shader_variant_key tcs_key;
644 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
645
646 if (tes_module->nir)
647 _mesa_sha1_compute(tes_module->nir->info->name,
648 strlen(tes_module->nir->info->name),
649 tes_module->sha1);
650 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
651
652 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
653 cache,
654 tes_sha1);
655
656 if (tes_variant) {
657 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
658
659 if (tcs_module->nir)
660 _mesa_sha1_compute(tcs_module->nir->info->name,
661 strlen(tcs_module->nir->info->name),
662 tcs_module->sha1);
663
664 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
665
666 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
667 cache,
668 tcs_sha1);
669 }
670
671 if (tcs_variant && tes_variant) {
672 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
673 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
674 return;
675 }
676
677 tes_nir = radv_shader_compile_to_nir(pipeline->device,
678 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
679 tes_spec_info, dump);
680 if (tes_nir == NULL)
681 return;
682
683 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
684 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
685 tcs_spec_info, dump);
686 if (tcs_nir == NULL)
687 return;
688
689 nir_lower_tes_patch_vertices(tes_nir,
690 tcs_nir->info->tess.tcs_vertices_out);
691
692 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
693 layout, &tes_key, &tes_code,
694 &tes_code_size, dump);
695
696 tcs_key = radv_compute_tcs_key(tes_nir->info->tess.primitive_mode, input_vertices);
697 if (tcs_module->nir)
698 _mesa_sha1_compute(tcs_module->nir->info->name,
699 strlen(tcs_module->nir->info->name),
700 tcs_module->sha1);
701
702 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
703
704 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
705 layout, &tcs_key, &tcs_code,
706 &tcs_code_size, dump);
707
708 if (!tes_module->nir)
709 ralloc_free(tes_nir);
710
711 if (!tcs_module->nir)
712 ralloc_free(tcs_nir);
713
714 if (tes_variant)
715 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
716 tes_code, tes_code_size);
717
718 if (tcs_variant)
719 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
720 tcs_code, tcs_code_size);
721
722 if (tes_code)
723 free(tes_code);
724 if (tcs_code)
725 free(tcs_code);
726 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
727 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
728 return;
729 }
730
731 static VkResult
732 radv_pipeline_scratch_init(struct radv_device *device,
733 struct radv_pipeline *pipeline)
734 {
735 unsigned scratch_bytes_per_wave = 0;
736 unsigned max_waves = 0;
737 unsigned min_waves = 1;
738
739 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
740 if (pipeline->shaders[i]) {
741 unsigned max_stage_waves = device->scratch_waves;
742
743 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
744 pipeline->shaders[i]->config.scratch_bytes_per_wave);
745
746 max_stage_waves = MIN2(max_stage_waves,
747 4 * device->physical_device->rad_info.num_good_compute_units *
748 (256 / pipeline->shaders[i]->config.num_vgprs));
749 max_waves = MAX2(max_waves, max_stage_waves);
750 }
751 }
752
753 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
754 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
755 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
756 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
757 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
758 }
759
760 if (scratch_bytes_per_wave)
761 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
762
763 if (scratch_bytes_per_wave && max_waves < min_waves) {
764 /* Not really true at this moment, but will be true on first
765 * execution. Avoid having hanging shaders. */
766 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
767 }
768 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
769 pipeline->max_waves = max_waves;
770 return VK_SUCCESS;
771 }
772
773 static uint32_t si_translate_blend_function(VkBlendOp op)
774 {
775 switch (op) {
776 case VK_BLEND_OP_ADD:
777 return V_028780_COMB_DST_PLUS_SRC;
778 case VK_BLEND_OP_SUBTRACT:
779 return V_028780_COMB_SRC_MINUS_DST;
780 case VK_BLEND_OP_REVERSE_SUBTRACT:
781 return V_028780_COMB_DST_MINUS_SRC;
782 case VK_BLEND_OP_MIN:
783 return V_028780_COMB_MIN_DST_SRC;
784 case VK_BLEND_OP_MAX:
785 return V_028780_COMB_MAX_DST_SRC;
786 default:
787 return 0;
788 }
789 }
790
791 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
792 {
793 switch (factor) {
794 case VK_BLEND_FACTOR_ZERO:
795 return V_028780_BLEND_ZERO;
796 case VK_BLEND_FACTOR_ONE:
797 return V_028780_BLEND_ONE;
798 case VK_BLEND_FACTOR_SRC_COLOR:
799 return V_028780_BLEND_SRC_COLOR;
800 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
801 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
802 case VK_BLEND_FACTOR_DST_COLOR:
803 return V_028780_BLEND_DST_COLOR;
804 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
805 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
806 case VK_BLEND_FACTOR_SRC_ALPHA:
807 return V_028780_BLEND_SRC_ALPHA;
808 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
809 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
810 case VK_BLEND_FACTOR_DST_ALPHA:
811 return V_028780_BLEND_DST_ALPHA;
812 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
813 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
814 case VK_BLEND_FACTOR_CONSTANT_COLOR:
815 return V_028780_BLEND_CONSTANT_COLOR;
816 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
817 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
818 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
819 return V_028780_BLEND_CONSTANT_ALPHA;
820 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
821 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
822 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
823 return V_028780_BLEND_SRC_ALPHA_SATURATE;
824 case VK_BLEND_FACTOR_SRC1_COLOR:
825 return V_028780_BLEND_SRC1_COLOR;
826 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
827 return V_028780_BLEND_INV_SRC1_COLOR;
828 case VK_BLEND_FACTOR_SRC1_ALPHA:
829 return V_028780_BLEND_SRC1_ALPHA;
830 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
831 return V_028780_BLEND_INV_SRC1_ALPHA;
832 default:
833 return 0;
834 }
835 }
836
837 static bool is_dual_src(VkBlendFactor factor)
838 {
839 switch (factor) {
840 case VK_BLEND_FACTOR_SRC1_COLOR:
841 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
842 case VK_BLEND_FACTOR_SRC1_ALPHA:
843 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
844 return true;
845 default:
846 return false;
847 }
848 }
849
850 static unsigned si_choose_spi_color_format(VkFormat vk_format,
851 bool blend_enable,
852 bool blend_need_alpha)
853 {
854 const struct vk_format_description *desc = vk_format_description(vk_format);
855 unsigned format, ntype, swap;
856
857 /* Alpha is needed for alpha-to-coverage.
858 * Blending may be with or without alpha.
859 */
860 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
861 unsigned alpha = 0; /* exports alpha, but may not support blending */
862 unsigned blend = 0; /* supports blending, but may not export alpha */
863 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
864
865 format = radv_translate_colorformat(vk_format);
866 ntype = radv_translate_color_numformat(vk_format, desc,
867 vk_format_get_first_non_void_channel(vk_format));
868 swap = radv_translate_colorswap(vk_format, false);
869
870 /* Choose the SPI color formats. These are required values for Stoney/RB+.
871 * Other chips have multiple choices, though they are not necessarily better.
872 */
873 switch (format) {
874 case V_028C70_COLOR_5_6_5:
875 case V_028C70_COLOR_1_5_5_5:
876 case V_028C70_COLOR_5_5_5_1:
877 case V_028C70_COLOR_4_4_4_4:
878 case V_028C70_COLOR_10_11_11:
879 case V_028C70_COLOR_11_11_10:
880 case V_028C70_COLOR_8:
881 case V_028C70_COLOR_8_8:
882 case V_028C70_COLOR_8_8_8_8:
883 case V_028C70_COLOR_10_10_10_2:
884 case V_028C70_COLOR_2_10_10_10:
885 if (ntype == V_028C70_NUMBER_UINT)
886 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
887 else if (ntype == V_028C70_NUMBER_SINT)
888 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
889 else
890 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
891 break;
892
893 case V_028C70_COLOR_16:
894 case V_028C70_COLOR_16_16:
895 case V_028C70_COLOR_16_16_16_16:
896 if (ntype == V_028C70_NUMBER_UNORM ||
897 ntype == V_028C70_NUMBER_SNORM) {
898 /* UNORM16 and SNORM16 don't support blending */
899 if (ntype == V_028C70_NUMBER_UNORM)
900 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
901 else
902 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
903
904 /* Use 32 bits per channel for blending. */
905 if (format == V_028C70_COLOR_16) {
906 if (swap == V_028C70_SWAP_STD) { /* R */
907 blend = V_028714_SPI_SHADER_32_R;
908 blend_alpha = V_028714_SPI_SHADER_32_AR;
909 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
910 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
911 else
912 assert(0);
913 } else if (format == V_028C70_COLOR_16_16) {
914 if (swap == V_028C70_SWAP_STD) { /* RG */
915 blend = V_028714_SPI_SHADER_32_GR;
916 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
917 } else if (swap == V_028C70_SWAP_ALT) /* RA */
918 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
919 else
920 assert(0);
921 } else /* 16_16_16_16 */
922 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
923 } else if (ntype == V_028C70_NUMBER_UINT)
924 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
925 else if (ntype == V_028C70_NUMBER_SINT)
926 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
927 else if (ntype == V_028C70_NUMBER_FLOAT)
928 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
929 else
930 assert(0);
931 break;
932
933 case V_028C70_COLOR_32:
934 if (swap == V_028C70_SWAP_STD) { /* R */
935 blend = normal = V_028714_SPI_SHADER_32_R;
936 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
937 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
938 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
939 else
940 assert(0);
941 break;
942
943 case V_028C70_COLOR_32_32:
944 if (swap == V_028C70_SWAP_STD) { /* RG */
945 blend = normal = V_028714_SPI_SHADER_32_GR;
946 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
947 } else if (swap == V_028C70_SWAP_ALT) /* RA */
948 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
949 else
950 assert(0);
951 break;
952
953 case V_028C70_COLOR_32_32_32_32:
954 case V_028C70_COLOR_8_24:
955 case V_028C70_COLOR_24_8:
956 case V_028C70_COLOR_X24_8_32_FLOAT:
957 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
958 break;
959
960 default:
961 unreachable("unhandled blend format");
962 }
963
964 if (blend_enable && blend_need_alpha)
965 return blend_alpha;
966 else if(blend_need_alpha)
967 return alpha;
968 else if(blend_enable)
969 return blend;
970 else
971 return normal;
972 }
973
974 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
975 {
976 unsigned i, cb_shader_mask = 0;
977
978 for (i = 0; i < 8; i++) {
979 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
980 case V_028714_SPI_SHADER_ZERO:
981 break;
982 case V_028714_SPI_SHADER_32_R:
983 cb_shader_mask |= 0x1 << (i * 4);
984 break;
985 case V_028714_SPI_SHADER_32_GR:
986 cb_shader_mask |= 0x3 << (i * 4);
987 break;
988 case V_028714_SPI_SHADER_32_AR:
989 cb_shader_mask |= 0x9 << (i * 4);
990 break;
991 case V_028714_SPI_SHADER_FP16_ABGR:
992 case V_028714_SPI_SHADER_UNORM16_ABGR:
993 case V_028714_SPI_SHADER_SNORM16_ABGR:
994 case V_028714_SPI_SHADER_UINT16_ABGR:
995 case V_028714_SPI_SHADER_SINT16_ABGR:
996 case V_028714_SPI_SHADER_32_ABGR:
997 cb_shader_mask |= 0xf << (i * 4);
998 break;
999 default:
1000 assert(0);
1001 }
1002 }
1003 return cb_shader_mask;
1004 }
1005
1006 static void
1007 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1008 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1009 uint32_t blend_enable,
1010 uint32_t blend_need_alpha,
1011 bool single_cb_enable,
1012 bool blend_mrt0_is_dual_src)
1013 {
1014 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1015 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1016 struct radv_blend_state *blend = &pipeline->graphics.blend;
1017 unsigned col_format = 0;
1018
1019 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1020 struct radv_render_pass_attachment *attachment;
1021 unsigned cf;
1022
1023 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1024
1025 cf = si_choose_spi_color_format(attachment->format,
1026 blend_enable & (1 << i),
1027 blend_need_alpha & (1 << i));
1028
1029 col_format |= cf << (4 * i);
1030 }
1031
1032 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1033
1034 if (blend_mrt0_is_dual_src)
1035 col_format |= (col_format & 0xf) << 4;
1036 blend->spi_shader_col_format = col_format;
1037 }
1038
1039 static bool
1040 format_is_int8(VkFormat format)
1041 {
1042 const struct vk_format_description *desc = vk_format_description(format);
1043 int channel = vk_format_get_first_non_void_channel(format);
1044
1045 return channel >= 0 && desc->channel[channel].pure_integer &&
1046 desc->channel[channel].size == 8;
1047 }
1048
1049 unsigned radv_format_meta_fs_key(VkFormat format)
1050 {
1051 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1052 bool is_int8 = format_is_int8(format);
1053
1054 return col_format + (is_int8 ? 3 : 0);
1055 }
1056
1057 static unsigned
1058 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1059 {
1060 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1061 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1062 unsigned is_int8 = 0;
1063
1064 for (unsigned i = 0; i < subpass->color_count; ++i) {
1065 struct radv_render_pass_attachment *attachment;
1066
1067 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1068
1069 if (format_is_int8(attachment->format))
1070 is_int8 |= 1 << i;
1071 }
1072
1073 return is_int8;
1074 }
1075
1076 static void
1077 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1078 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1079 const struct radv_graphics_pipeline_create_info *extra)
1080 {
1081 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1082 struct radv_blend_state *blend = &pipeline->graphics.blend;
1083 unsigned mode = V_028808_CB_NORMAL;
1084 uint32_t blend_enable = 0, blend_need_alpha = 0;
1085 bool blend_mrt0_is_dual_src = false;
1086 int i;
1087 bool single_cb_enable = false;
1088
1089 if (!vkblend)
1090 return;
1091
1092 if (extra && extra->custom_blend_mode) {
1093 single_cb_enable = true;
1094 mode = extra->custom_blend_mode;
1095 }
1096 blend->cb_color_control = 0;
1097 if (vkblend->logicOpEnable)
1098 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1099 else
1100 blend->cb_color_control |= S_028808_ROP3(0xcc);
1101
1102 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1103 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1104 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1105 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1106
1107 blend->cb_target_mask = 0;
1108 for (i = 0; i < vkblend->attachmentCount; i++) {
1109 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1110 unsigned blend_cntl = 0;
1111 VkBlendOp eqRGB = att->colorBlendOp;
1112 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1113 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1114 VkBlendOp eqA = att->alphaBlendOp;
1115 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1116 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1117
1118 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1119
1120 if (!att->colorWriteMask)
1121 continue;
1122
1123 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1124 if (!att->blendEnable) {
1125 blend->cb_blend_control[i] = blend_cntl;
1126 continue;
1127 }
1128
1129 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1130 if (i == 0)
1131 blend_mrt0_is_dual_src = true;
1132
1133 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1134 srcRGB = VK_BLEND_FACTOR_ONE;
1135 dstRGB = VK_BLEND_FACTOR_ONE;
1136 }
1137 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1138 srcA = VK_BLEND_FACTOR_ONE;
1139 dstA = VK_BLEND_FACTOR_ONE;
1140 }
1141
1142 blend_cntl |= S_028780_ENABLE(1);
1143
1144 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1145 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1146 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1147 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1148 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1149 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1150 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1151 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1152 }
1153 blend->cb_blend_control[i] = blend_cntl;
1154
1155 blend_enable |= 1 << i;
1156
1157 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1158 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1159 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1160 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1161 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1162 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1163 blend_need_alpha |= 1 << i;
1164 }
1165 for (i = vkblend->attachmentCount; i < 8; i++)
1166 blend->cb_blend_control[i] = 0;
1167
1168 if (blend->cb_target_mask)
1169 blend->cb_color_control |= S_028808_MODE(mode);
1170 else
1171 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1172
1173 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1174 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1175 }
1176
1177 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1178 {
1179 switch (op) {
1180 case VK_STENCIL_OP_KEEP:
1181 return V_02842C_STENCIL_KEEP;
1182 case VK_STENCIL_OP_ZERO:
1183 return V_02842C_STENCIL_ZERO;
1184 case VK_STENCIL_OP_REPLACE:
1185 return V_02842C_STENCIL_REPLACE_TEST;
1186 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1187 return V_02842C_STENCIL_ADD_CLAMP;
1188 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1189 return V_02842C_STENCIL_SUB_CLAMP;
1190 case VK_STENCIL_OP_INVERT:
1191 return V_02842C_STENCIL_INVERT;
1192 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1193 return V_02842C_STENCIL_ADD_WRAP;
1194 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1195 return V_02842C_STENCIL_SUB_WRAP;
1196 default:
1197 return 0;
1198 }
1199 }
1200 static void
1201 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1202 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1203 const struct radv_graphics_pipeline_create_info *extra)
1204 {
1205 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1206 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1207
1208 memset(ds, 0, sizeof(*ds));
1209 if (!vkds)
1210 return;
1211 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1212 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1213 S_028800_ZFUNC(vkds->depthCompareOp) |
1214 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1215
1216 if (vkds->stencilTestEnable) {
1217 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1218 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1219 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1220 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1221 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1222
1223 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1224 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1225 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1226 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1227 }
1228
1229 if (extra) {
1230
1231 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1232 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1233
1234 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1235 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1236 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1237 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1238 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1239 }
1240 }
1241
1242 static uint32_t si_translate_fill(VkPolygonMode func)
1243 {
1244 switch(func) {
1245 case VK_POLYGON_MODE_FILL:
1246 return V_028814_X_DRAW_TRIANGLES;
1247 case VK_POLYGON_MODE_LINE:
1248 return V_028814_X_DRAW_LINES;
1249 case VK_POLYGON_MODE_POINT:
1250 return V_028814_X_DRAW_POINTS;
1251 default:
1252 assert(0);
1253 return V_028814_X_DRAW_POINTS;
1254 }
1255 }
1256 static void
1257 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1258 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1259 {
1260 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1261 struct radv_raster_state *raster = &pipeline->graphics.raster;
1262
1263 memset(raster, 0, sizeof(*raster));
1264
1265 raster->spi_interp_control =
1266 S_0286D4_FLAT_SHADE_ENA(1) |
1267 S_0286D4_PNT_SPRITE_ENA(1) |
1268 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1269 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1270 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1271 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1272 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1273
1274
1275 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1276 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1277 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1278 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1279 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1280 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1281
1282 raster->pa_su_vtx_cntl =
1283 S_028BE4_PIX_CENTER(1) | // TODO verify
1284 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1285 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1286
1287 raster->pa_su_sc_mode_cntl =
1288 S_028814_FACE(vkraster->frontFace) |
1289 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1290 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1291 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1292 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1293 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1294 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1295 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1296 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1297
1298 }
1299
1300 static void
1301 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1302 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1303 {
1304 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1305 struct radv_blend_state *blend = &pipeline->graphics.blend;
1306 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1307 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1308 int ps_iter_samples = 1;
1309 uint32_t mask = 0xffff;
1310
1311 if (vkms)
1312 ms->num_samples = vkms->rasterizationSamples;
1313 else
1314 ms->num_samples = 1;
1315
1316 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1317 ps_iter_samples = ms->num_samples;
1318 }
1319
1320 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1321 ms->pa_sc_aa_config = 0;
1322 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1323 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1324 ms->pa_sc_mode_cntl_1 =
1325 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1326 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1327 /* always 1: */
1328 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1329 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1330 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1331 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1332 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1333 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1334
1335 if (ms->num_samples > 1) {
1336 unsigned log_samples = util_logbase2(ms->num_samples);
1337 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1338 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1339 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1340 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1341 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1342 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1343 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1344 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1345 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1346 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1347 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1348 }
1349
1350 if (vkms) {
1351 if (vkms->alphaToCoverageEnable)
1352 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1353
1354 if (vkms->pSampleMask)
1355 mask = vkms->pSampleMask[0] & 0xffff;
1356 }
1357
1358 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1359 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1360 }
1361
1362 static bool
1363 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1364 {
1365 switch (topology) {
1366 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1367 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1368 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1369 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1370 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1371 return false;
1372 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1373 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1374 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1375 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1376 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1377 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1378 return true;
1379 default:
1380 unreachable("unhandled primitive type");
1381 }
1382 }
1383
1384 static uint32_t
1385 si_translate_prim(enum VkPrimitiveTopology topology)
1386 {
1387 switch (topology) {
1388 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1389 return V_008958_DI_PT_POINTLIST;
1390 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1391 return V_008958_DI_PT_LINELIST;
1392 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1393 return V_008958_DI_PT_LINESTRIP;
1394 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1395 return V_008958_DI_PT_TRILIST;
1396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1397 return V_008958_DI_PT_TRISTRIP;
1398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1399 return V_008958_DI_PT_TRIFAN;
1400 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1401 return V_008958_DI_PT_LINELIST_ADJ;
1402 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1403 return V_008958_DI_PT_LINESTRIP_ADJ;
1404 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1405 return V_008958_DI_PT_TRILIST_ADJ;
1406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1407 return V_008958_DI_PT_TRISTRIP_ADJ;
1408 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1409 return V_008958_DI_PT_PATCH;
1410 default:
1411 assert(0);
1412 return 0;
1413 }
1414 }
1415
1416 static uint32_t
1417 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1418 {
1419 switch (gl_prim) {
1420 case 0: /* GL_POINTS */
1421 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1422 case 1: /* GL_LINES */
1423 case 3: /* GL_LINE_STRIP */
1424 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1425 case 0x8E7A: /* GL_ISOLINES */
1426 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1427
1428 case 4: /* GL_TRIANGLES */
1429 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1430 case 5: /* GL_TRIANGLE_STRIP */
1431 case 7: /* GL_QUADS */
1432 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1433 default:
1434 assert(0);
1435 return 0;
1436 }
1437 }
1438
1439 static uint32_t
1440 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1441 {
1442 switch (topology) {
1443 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1444 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1445 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1446 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1447 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1448 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1449 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1450 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1451 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1452 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1453 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1454 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1455 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1456 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1457 default:
1458 assert(0);
1459 return 0;
1460 }
1461 }
1462
1463 static unsigned si_map_swizzle(unsigned swizzle)
1464 {
1465 switch (swizzle) {
1466 case VK_SWIZZLE_Y:
1467 return V_008F0C_SQ_SEL_Y;
1468 case VK_SWIZZLE_Z:
1469 return V_008F0C_SQ_SEL_Z;
1470 case VK_SWIZZLE_W:
1471 return V_008F0C_SQ_SEL_W;
1472 case VK_SWIZZLE_0:
1473 return V_008F0C_SQ_SEL_0;
1474 case VK_SWIZZLE_1:
1475 return V_008F0C_SQ_SEL_1;
1476 default: /* VK_SWIZZLE_X */
1477 return V_008F0C_SQ_SEL_X;
1478 }
1479 }
1480
1481 static void
1482 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1483 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1484 {
1485 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1486 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1487 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1488
1489 pipeline->dynamic_state = default_dynamic_state;
1490
1491 if (pCreateInfo->pDynamicState) {
1492 /* Remove all of the states that are marked as dynamic */
1493 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1494 for (uint32_t s = 0; s < count; s++)
1495 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1496 }
1497
1498 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1499
1500 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1501 *
1502 * pViewportState is [...] NULL if the pipeline
1503 * has rasterization disabled.
1504 */
1505 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1506 assert(pCreateInfo->pViewportState);
1507
1508 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1509 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1510 typed_memcpy(dynamic->viewport.viewports,
1511 pCreateInfo->pViewportState->pViewports,
1512 pCreateInfo->pViewportState->viewportCount);
1513 }
1514
1515 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1516 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1517 typed_memcpy(dynamic->scissor.scissors,
1518 pCreateInfo->pViewportState->pScissors,
1519 pCreateInfo->pViewportState->scissorCount);
1520 }
1521 }
1522
1523 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1524 assert(pCreateInfo->pRasterizationState);
1525 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1526 }
1527
1528 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1529 assert(pCreateInfo->pRasterizationState);
1530 dynamic->depth_bias.bias =
1531 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1532 dynamic->depth_bias.clamp =
1533 pCreateInfo->pRasterizationState->depthBiasClamp;
1534 dynamic->depth_bias.slope =
1535 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1536 }
1537
1538 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1539 *
1540 * pColorBlendState is [...] NULL if the pipeline has rasterization
1541 * disabled or if the subpass of the render pass the pipeline is
1542 * created against does not use any color attachments.
1543 */
1544 bool uses_color_att = false;
1545 for (unsigned i = 0; i < subpass->color_count; ++i) {
1546 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1547 uses_color_att = true;
1548 break;
1549 }
1550 }
1551
1552 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1553 assert(pCreateInfo->pColorBlendState);
1554 typed_memcpy(dynamic->blend_constants,
1555 pCreateInfo->pColorBlendState->blendConstants, 4);
1556 }
1557
1558 /* If there is no depthstencil attachment, then don't read
1559 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1560 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1561 * no need to override the depthstencil defaults in
1562 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1563 *
1564 * Section 9.2 of the Vulkan 1.0.15 spec says:
1565 *
1566 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1567 * disabled or if the subpass of the render pass the pipeline is created
1568 * against does not use a depth/stencil attachment.
1569 */
1570 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1571 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1572 assert(pCreateInfo->pDepthStencilState);
1573
1574 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1575 dynamic->depth_bounds.min =
1576 pCreateInfo->pDepthStencilState->minDepthBounds;
1577 dynamic->depth_bounds.max =
1578 pCreateInfo->pDepthStencilState->maxDepthBounds;
1579 }
1580
1581 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1582 dynamic->stencil_compare_mask.front =
1583 pCreateInfo->pDepthStencilState->front.compareMask;
1584 dynamic->stencil_compare_mask.back =
1585 pCreateInfo->pDepthStencilState->back.compareMask;
1586 }
1587
1588 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1589 dynamic->stencil_write_mask.front =
1590 pCreateInfo->pDepthStencilState->front.writeMask;
1591 dynamic->stencil_write_mask.back =
1592 pCreateInfo->pDepthStencilState->back.writeMask;
1593 }
1594
1595 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1596 dynamic->stencil_reference.front =
1597 pCreateInfo->pDepthStencilState->front.reference;
1598 dynamic->stencil_reference.back =
1599 pCreateInfo->pDepthStencilState->back.reference;
1600 }
1601 }
1602
1603 pipeline->dynamic_state_mask = states;
1604 }
1605
1606 static union ac_shader_variant_key
1607 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
1608 {
1609 union ac_shader_variant_key key;
1610 const VkPipelineVertexInputStateCreateInfo *input_state =
1611 pCreateInfo->pVertexInputState;
1612
1613 memset(&key, 0, sizeof(key));
1614 key.vs.instance_rate_inputs = 0;
1615 key.vs.as_es = as_es;
1616 key.vs.as_ls = as_ls;
1617
1618 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1619 unsigned binding;
1620 binding = input_state->pVertexAttributeDescriptions[i].binding;
1621 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1622 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1623 }
1624 return key;
1625 }
1626
1627 static void
1628 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1629 {
1630 struct radv_device *device = pipeline->device;
1631 unsigned num_se = device->physical_device->rad_info.max_se;
1632 unsigned wave_size = 64;
1633 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1634 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1635 unsigned alignment = 256 * num_se;
1636 /* The maximum size is 63.999 MB per SE. */
1637 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1638 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1639 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1640 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1641 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1642
1643 /* Calculate the minimum size. */
1644 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1645 wave_size, alignment);
1646 /* These are recommended sizes, not minimum sizes. */
1647 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1648 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1649 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1650 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1651
1652 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1653 esgs_ring_size = align(esgs_ring_size, alignment);
1654 gsvs_ring_size = align(gsvs_ring_size, alignment);
1655
1656 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1657 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1658 }
1659
1660 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1661 unsigned *lds_size)
1662 {
1663 /* SPI barrier management bug:
1664 * Make sure we have at least 4k of LDS in use to avoid the bug.
1665 * It applies to workgroup sizes of more than one wavefront.
1666 */
1667 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1668 device->physical_device->rad_info.family == CHIP_KABINI ||
1669 device->physical_device->rad_info.family == CHIP_MULLINS)
1670 *lds_size = MAX2(*lds_size, 8);
1671 }
1672
1673 static void
1674 calculate_tess_state(struct radv_pipeline *pipeline,
1675 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1676 {
1677 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1678 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1679 unsigned num_tcs_patch_outputs;
1680 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1681 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1682 unsigned lds_size, hardware_lds_size;
1683 unsigned perpatch_output_offset;
1684 unsigned num_patches;
1685 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1686
1687 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1688 * are laid out in LDS. */
1689 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1690
1691 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1692 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1693 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1694
1695 /* Ensure that we only need one wave per SIMD so we don't need to check
1696 * resource usage. Also ensures that the number of tcs in and out
1697 * vertices per threadgroup are at most 256.
1698 */
1699 input_vertex_size = num_tcs_inputs * 16;
1700 output_vertex_size = num_tcs_outputs * 16;
1701
1702 input_patch_size = num_tcs_input_cp * input_vertex_size;
1703
1704 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1705 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1706 /* Ensure that we only need one wave per SIMD so we don't need to check
1707 * resource usage. Also ensures that the number of tcs in and out
1708 * vertices per threadgroup are at most 256.
1709 */
1710 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1711
1712 /* Make sure that the data fits in LDS. This assumes the shaders only
1713 * use LDS for the inputs and outputs.
1714 */
1715 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1716 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1717
1718 /* Make sure the output data fits in the offchip buffer */
1719 num_patches = MIN2(num_patches,
1720 (pipeline->device->tess_offchip_block_dw_size * 4) /
1721 output_patch_size);
1722
1723 /* Not necessary for correctness, but improves performance. The
1724 * specific value is taken from the proprietary driver.
1725 */
1726 num_patches = MIN2(num_patches, 40);
1727
1728 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1729 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1730 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1731 num_patches = MIN2(num_patches, one_wave);
1732 }
1733
1734 output_patch0_offset = input_patch_size * num_patches;
1735 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1736
1737 lds_size = output_patch0_offset + output_patch_size * num_patches;
1738
1739 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1740 assert(lds_size <= 65536);
1741 lds_size = align(lds_size, 512) / 512;
1742 } else {
1743 assert(lds_size <= 32768);
1744 lds_size = align(lds_size, 256) / 256;
1745 }
1746 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1747
1748 tess->lds_size = lds_size;
1749
1750 tess->tcs_in_layout = (input_patch_size / 4) |
1751 ((input_vertex_size / 4) << 13);
1752 tess->tcs_out_layout = (output_patch_size / 4) |
1753 ((output_vertex_size / 4) << 13);
1754 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1755 ((perpatch_output_offset / 16) << 16);
1756 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1757 (num_tcs_output_cp << 9) | num_patches;
1758
1759 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1760 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1761 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1762 tess->num_patches = num_patches;
1763 tess->num_tcs_input_cp = num_tcs_input_cp;
1764
1765 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1766 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1767
1768 switch (tes->info.tes.primitive_mode) {
1769 case GL_TRIANGLES:
1770 type = V_028B6C_TESS_TRIANGLE;
1771 break;
1772 case GL_QUADS:
1773 type = V_028B6C_TESS_QUAD;
1774 break;
1775 case GL_ISOLINES:
1776 type = V_028B6C_TESS_ISOLINE;
1777 break;
1778 }
1779
1780 switch (tes->info.tes.spacing) {
1781 case TESS_SPACING_EQUAL:
1782 partitioning = V_028B6C_PART_INTEGER;
1783 break;
1784 case TESS_SPACING_FRACTIONAL_ODD:
1785 partitioning = V_028B6C_PART_FRAC_ODD;
1786 break;
1787 case TESS_SPACING_FRACTIONAL_EVEN:
1788 partitioning = V_028B6C_PART_FRAC_EVEN;
1789 break;
1790 default:
1791 break;
1792 }
1793
1794 if (tes->info.tes.point_mode)
1795 topology = V_028B6C_OUTPUT_POINT;
1796 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1797 topology = V_028B6C_OUTPUT_LINE;
1798 else if (tes->info.tes.ccw)
1799 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1800 else
1801 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1802
1803 if (pipeline->device->has_distributed_tess) {
1804 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1805 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1806 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1807 else
1808 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1809 } else
1810 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1811
1812 tess->tf_param = S_028B6C_TYPE(type) |
1813 S_028B6C_PARTITIONING(partitioning) |
1814 S_028B6C_TOPOLOGY(topology) |
1815 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1816 }
1817
1818 static const struct radv_prim_vertex_count prim_size_table[] = {
1819 [V_008958_DI_PT_NONE] = {0, 0},
1820 [V_008958_DI_PT_POINTLIST] = {1, 1},
1821 [V_008958_DI_PT_LINELIST] = {2, 2},
1822 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1823 [V_008958_DI_PT_TRILIST] = {3, 3},
1824 [V_008958_DI_PT_TRIFAN] = {3, 1},
1825 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1826 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1827 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1828 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1829 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1830 [V_008958_DI_PT_RECTLIST] = {3, 3},
1831 [V_008958_DI_PT_LINELOOP] = {2, 1},
1832 [V_008958_DI_PT_POLYGON] = {3, 1},
1833 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1834 };
1835
1836 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1837 {
1838 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1839 unsigned cut_mode;
1840
1841 if (gs_max_vert_out <= 128) {
1842 cut_mode = V_028A40_GS_CUT_128;
1843 } else if (gs_max_vert_out <= 256) {
1844 cut_mode = V_028A40_GS_CUT_256;
1845 } else if (gs_max_vert_out <= 512) {
1846 cut_mode = V_028A40_GS_CUT_512;
1847 } else {
1848 assert(gs_max_vert_out <= 1024);
1849 cut_mode = V_028A40_GS_CUT_1024;
1850 }
1851
1852 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1853 S_028A40_CUT_MODE(cut_mode)|
1854 S_028A40_ES_WRITE_OPTIMIZE(1) |
1855 S_028A40_GS_WRITE_OPTIMIZE(1);
1856 }
1857
1858 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1859 {
1860 struct radv_shader_variant *vs;
1861 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1862
1863 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1864
1865 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1866 clip_dist_mask = outinfo->clip_dist_mask;
1867 cull_dist_mask = outinfo->cull_dist_mask;
1868 total_mask = clip_dist_mask | cull_dist_mask;
1869
1870 bool misc_vec_ena = outinfo->writes_pointsize ||
1871 outinfo->writes_layer ||
1872 outinfo->writes_viewport_index;
1873 pipeline->graphics.pa_cl_vs_out_cntl =
1874 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1875 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1876 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1877 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1878 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1879 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1880 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1881 cull_dist_mask << 8 |
1882 clip_dist_mask;
1883
1884 }
1885
1886 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1887 {
1888 uint32_t ps_input_cntl;
1889 if (offset <= AC_EXP_PARAM_OFFSET_31)
1890 ps_input_cntl = S_028644_OFFSET(offset);
1891 else {
1892 /* The input is a DEFAULT_VAL constant. */
1893 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1894 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1895 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1896 ps_input_cntl = S_028644_OFFSET(0x20) |
1897 S_028644_DEFAULT_VAL(offset);
1898 }
1899 if (flat_shade)
1900 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1901 return ps_input_cntl;
1902 }
1903
1904 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1905 {
1906 struct radv_shader_variant *ps, *vs;
1907 struct ac_vs_output_info *outinfo;
1908
1909 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1910 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1911
1912 outinfo = &vs->info.vs.outinfo;
1913
1914 unsigned ps_offset = 0;
1915
1916 if (ps->info.fs.prim_id_input) {
1917 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1918 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1919 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1920 ++ps_offset;
1921 }
1922 }
1923
1924 if (ps->info.fs.layer_input) {
1925 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1926 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1927 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1928 ++ps_offset;
1929 }
1930 }
1931
1932 if (ps->info.fs.has_pcoord) {
1933 unsigned val;
1934 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1935 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1936 ps_offset++;
1937 }
1938
1939 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1940 unsigned vs_offset;
1941 bool flat_shade;
1942 if (!(ps->info.fs.input_mask & (1u << i)))
1943 continue;
1944
1945 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1946 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1947 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1948 ++ps_offset;
1949 continue;
1950 }
1951
1952 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1953
1954 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1955 ++ps_offset;
1956 }
1957
1958 pipeline->graphics.ps_input_cntl_num = ps_offset;
1959 }
1960
1961 VkResult
1962 radv_pipeline_init(struct radv_pipeline *pipeline,
1963 struct radv_device *device,
1964 struct radv_pipeline_cache *cache,
1965 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1966 const struct radv_graphics_pipeline_create_info *extra,
1967 const VkAllocationCallbacks *alloc)
1968 {
1969 struct radv_shader_module fs_m = {0};
1970 VkResult result;
1971
1972 if (alloc == NULL)
1973 alloc = &device->alloc;
1974
1975 pipeline->device = device;
1976 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1977
1978 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1979 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1980 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1981 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1982 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1983 pStages[stage] = &pCreateInfo->pStages[i];
1984 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1985 }
1986
1987 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1988
1989 if (modules[MESA_SHADER_VERTEX]) {
1990 bool as_es = false;
1991 bool as_ls = false;
1992 if (modules[MESA_SHADER_TESS_CTRL])
1993 as_ls = true;
1994 else if (modules[MESA_SHADER_GEOMETRY])
1995 as_es = true;
1996 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
1997
1998 pipeline->shaders[MESA_SHADER_VERTEX] =
1999 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2000 pStages[MESA_SHADER_VERTEX]->pName,
2001 MESA_SHADER_VERTEX,
2002 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2003 pipeline->layout, &key);
2004
2005 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2006 }
2007
2008 if (modules[MESA_SHADER_GEOMETRY]) {
2009 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false);
2010
2011 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2012 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2013 pStages[MESA_SHADER_GEOMETRY]->pName,
2014 MESA_SHADER_GEOMETRY,
2015 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2016 pipeline->layout, &key);
2017
2018 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2019
2020 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2021 } else
2022 pipeline->graphics.vgt_gs_mode = 0;
2023
2024 if (modules[MESA_SHADER_TESS_EVAL]) {
2025 assert(modules[MESA_SHADER_TESS_CTRL]);
2026
2027 radv_tess_pipeline_compile(pipeline,
2028 cache,
2029 modules[MESA_SHADER_TESS_CTRL],
2030 modules[MESA_SHADER_TESS_EVAL],
2031 pStages[MESA_SHADER_TESS_CTRL]->pName,
2032 pStages[MESA_SHADER_TESS_EVAL]->pName,
2033 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2034 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2035 pipeline->layout,
2036 pCreateInfo->pTessellationState->patchControlPoints);
2037 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2038 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2039 }
2040
2041 if (!modules[MESA_SHADER_FRAGMENT]) {
2042 nir_builder fs_b;
2043 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2044 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
2045 fs_m.nir = fs_b.shader;
2046 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2047 }
2048
2049 if (modules[MESA_SHADER_FRAGMENT]) {
2050 union ac_shader_variant_key key;
2051 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2052 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2053
2054 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2055
2056 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2057 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2058 stage ? stage->pName : "main",
2059 MESA_SHADER_FRAGMENT,
2060 stage ? stage->pSpecializationInfo : NULL,
2061 pipeline->layout, &key);
2062 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2063 }
2064
2065 if (fs_m.nir)
2066 ralloc_free(fs_m.nir);
2067
2068 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2069 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2070 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2071 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2072 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2073
2074 if (radv_pipeline_has_gs(pipeline)) {
2075 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2076 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2077 } else {
2078 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2079 }
2080 if (extra && extra->use_rectlist) {
2081 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2082 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2083 pipeline->graphics.can_use_guardband = true;
2084 }
2085 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2086 /* prim vertex count will need TESS changes */
2087 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2088
2089 /* Ensure that some export memory is always allocated, for two reasons:
2090 *
2091 * 1) Correctness: The hardware ignores the EXEC mask if no export
2092 * memory is allocated, so KILL and alpha test do not work correctly
2093 * without this.
2094 * 2) Performance: Every shader needs at least a NULL export, even when
2095 * it writes no color/depth output. The NULL export instruction
2096 * stalls without this setting.
2097 *
2098 * Don't add this to CB_SHADER_MASK.
2099 */
2100 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2101 if (!pipeline->graphics.blend.spi_shader_col_format) {
2102 if (!ps->info.fs.writes_z &&
2103 !ps->info.fs.writes_stencil &&
2104 !ps->info.fs.writes_sample_mask)
2105 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2106 }
2107
2108 unsigned z_order;
2109 pipeline->graphics.db_shader_control = 0;
2110 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2111 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2112 else
2113 z_order = V_02880C_LATE_Z;
2114
2115 pipeline->graphics.db_shader_control =
2116 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2117 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2118 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2119 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2120 S_02880C_Z_ORDER(z_order) |
2121 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2122 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2123 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2124
2125 pipeline->graphics.shader_z_format =
2126 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2127 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2128 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2129 V_028710_SPI_SHADER_ZERO;
2130
2131 calculate_pa_cl_vs_out_cntl(pipeline);
2132 calculate_ps_inputs(pipeline);
2133
2134 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2135 if (pipeline->shaders[i]) {
2136 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2137 }
2138 }
2139
2140 uint32_t stages = 0;
2141 if (radv_pipeline_has_tess(pipeline)) {
2142 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2143 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2144
2145 if (radv_pipeline_has_gs(pipeline))
2146 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2147 S_028B54_GS_EN(1) |
2148 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2149 else
2150 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2151 } else if (radv_pipeline_has_gs(pipeline))
2152 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2153 S_028B54_GS_EN(1) |
2154 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2155 pipeline->graphics.vgt_shader_stages_en = stages;
2156
2157 if (radv_pipeline_has_gs(pipeline))
2158 calculate_gs_ring_sizes(pipeline);
2159
2160 if (radv_pipeline_has_tess(pipeline)) {
2161 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2162 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2163 pipeline->graphics.prim_vertex_count.incr = 1;
2164 }
2165 calculate_tess_state(pipeline, pCreateInfo);
2166 }
2167
2168 const VkPipelineVertexInputStateCreateInfo *vi_info =
2169 pCreateInfo->pVertexInputState;
2170 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2171 const VkVertexInputAttributeDescription *desc =
2172 &vi_info->pVertexAttributeDescriptions[i];
2173 unsigned loc = desc->location;
2174 const struct vk_format_description *format_desc;
2175 int first_non_void;
2176 uint32_t num_format, data_format;
2177 format_desc = vk_format_description(desc->format);
2178 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2179
2180 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2181 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2182
2183 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2184 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2185 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2186 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2187 S_008F0C_NUM_FORMAT(num_format) |
2188 S_008F0C_DATA_FORMAT(data_format);
2189 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2190 pipeline->va_offset[loc] = desc->offset;
2191 pipeline->va_binding[loc] = desc->binding;
2192 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2193 }
2194
2195 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2196 const VkVertexInputBindingDescription *desc =
2197 &vi_info->pVertexBindingDescriptions[i];
2198
2199 pipeline->binding_stride[desc->binding] = desc->stride;
2200 }
2201
2202 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2203 radv_dump_pipeline_stats(device, pipeline);
2204 }
2205
2206 result = radv_pipeline_scratch_init(device, pipeline);
2207 return result;
2208 }
2209
2210 VkResult
2211 radv_graphics_pipeline_create(
2212 VkDevice _device,
2213 VkPipelineCache _cache,
2214 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2215 const struct radv_graphics_pipeline_create_info *extra,
2216 const VkAllocationCallbacks *pAllocator,
2217 VkPipeline *pPipeline)
2218 {
2219 RADV_FROM_HANDLE(radv_device, device, _device);
2220 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2221 struct radv_pipeline *pipeline;
2222 VkResult result;
2223
2224 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2225 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2226 if (pipeline == NULL)
2227 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2228
2229 memset(pipeline, 0, sizeof(*pipeline));
2230 result = radv_pipeline_init(pipeline, device, cache,
2231 pCreateInfo, extra, pAllocator);
2232 if (result != VK_SUCCESS) {
2233 radv_pipeline_destroy(device, pipeline, pAllocator);
2234 return result;
2235 }
2236
2237 *pPipeline = radv_pipeline_to_handle(pipeline);
2238
2239 return VK_SUCCESS;
2240 }
2241
2242 VkResult radv_CreateGraphicsPipelines(
2243 VkDevice _device,
2244 VkPipelineCache pipelineCache,
2245 uint32_t count,
2246 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2247 const VkAllocationCallbacks* pAllocator,
2248 VkPipeline* pPipelines)
2249 {
2250 VkResult result = VK_SUCCESS;
2251 unsigned i = 0;
2252
2253 for (; i < count; i++) {
2254 VkResult r;
2255 r = radv_graphics_pipeline_create(_device,
2256 pipelineCache,
2257 &pCreateInfos[i],
2258 NULL, pAllocator, &pPipelines[i]);
2259 if (r != VK_SUCCESS) {
2260 result = r;
2261 pPipelines[i] = VK_NULL_HANDLE;
2262 }
2263 }
2264
2265 return result;
2266 }
2267
2268 static VkResult radv_compute_pipeline_create(
2269 VkDevice _device,
2270 VkPipelineCache _cache,
2271 const VkComputePipelineCreateInfo* pCreateInfo,
2272 const VkAllocationCallbacks* pAllocator,
2273 VkPipeline* pPipeline)
2274 {
2275 RADV_FROM_HANDLE(radv_device, device, _device);
2276 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2277 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2278 struct radv_pipeline *pipeline;
2279 VkResult result;
2280
2281 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2282 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2283 if (pipeline == NULL)
2284 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2285
2286 memset(pipeline, 0, sizeof(*pipeline));
2287 pipeline->device = device;
2288 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2289
2290 pipeline->shaders[MESA_SHADER_COMPUTE] =
2291 radv_pipeline_compile(pipeline, cache, module,
2292 pCreateInfo->stage.pName,
2293 MESA_SHADER_COMPUTE,
2294 pCreateInfo->stage.pSpecializationInfo,
2295 pipeline->layout, NULL);
2296
2297
2298 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2299 result = radv_pipeline_scratch_init(device, pipeline);
2300 if (result != VK_SUCCESS) {
2301 radv_pipeline_destroy(device, pipeline, pAllocator);
2302 return result;
2303 }
2304
2305 *pPipeline = radv_pipeline_to_handle(pipeline);
2306
2307 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2308 radv_dump_pipeline_stats(device, pipeline);
2309 }
2310 return VK_SUCCESS;
2311 }
2312 VkResult radv_CreateComputePipelines(
2313 VkDevice _device,
2314 VkPipelineCache pipelineCache,
2315 uint32_t count,
2316 const VkComputePipelineCreateInfo* pCreateInfos,
2317 const VkAllocationCallbacks* pAllocator,
2318 VkPipeline* pPipelines)
2319 {
2320 VkResult result = VK_SUCCESS;
2321
2322 unsigned i = 0;
2323 for (; i < count; i++) {
2324 VkResult r;
2325 r = radv_compute_pipeline_create(_device, pipelineCache,
2326 &pCreateInfos[i],
2327 pAllocator, &pPipelines[i]);
2328 if (r != VK_SUCCESS) {
2329 result = r;
2330 pPipelines[i] = VK_NULL_HANDLE;
2331 }
2332 }
2333
2334 return result;
2335 }