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radv: trivial tidy ups
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44
45 void radv_shader_variant_destroy(struct radv_device *device,
46 struct radv_shader_variant *variant);
47
48 static const struct nir_shader_compiler_options nir_options = {
49 .vertex_id_zero_based = true,
50 .lower_scmp = true,
51 .lower_flrp32 = true,
52 .lower_fsat = true,
53 .lower_pack_snorm_2x16 = true,
54 .lower_pack_snorm_4x8 = true,
55 .lower_pack_unorm_2x16 = true,
56 .lower_pack_unorm_4x8 = true,
57 .lower_unpack_snorm_2x16 = true,
58 .lower_unpack_snorm_4x8 = true,
59 .lower_unpack_unorm_2x16 = true,
60 .lower_unpack_unorm_4x8 = true,
61 .lower_extract_byte = true,
62 .lower_extract_word = true,
63 };
64
65 VkResult radv_CreateShaderModule(
66 VkDevice _device,
67 const VkShaderModuleCreateInfo* pCreateInfo,
68 const VkAllocationCallbacks* pAllocator,
69 VkShaderModule* pShaderModule)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 struct radv_shader_module *module;
73
74 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
75 assert(pCreateInfo->flags == 0);
76
77 module = vk_alloc2(&device->alloc, pAllocator,
78 sizeof(*module) + pCreateInfo->codeSize, 8,
79 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
80 if (module == NULL)
81 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
82
83 module->nir = NULL;
84 module->size = pCreateInfo->codeSize;
85 memcpy(module->data, pCreateInfo->pCode, module->size);
86
87 _mesa_sha1_compute(module->data, module->size, module->sha1);
88
89 *pShaderModule = radv_shader_module_to_handle(module);
90
91 return VK_SUCCESS;
92 }
93
94 void radv_DestroyShaderModule(
95 VkDevice _device,
96 VkShaderModule _module,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_shader_module, module, _module);
101
102 if (!module)
103 return;
104
105 vk_free2(&device->alloc, pAllocator, module);
106 }
107
108
109 static void
110 radv_pipeline_destroy(struct radv_device *device,
111 struct radv_pipeline *pipeline,
112 const VkAllocationCallbacks* allocator)
113 {
114 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
115 if (pipeline->shaders[i])
116 radv_shader_variant_destroy(device, pipeline->shaders[i]);
117
118 if (pipeline->gs_copy_shader)
119 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
120
121 vk_free2(&device->alloc, allocator, pipeline);
122 }
123
124 void radv_DestroyPipeline(
125 VkDevice _device,
126 VkPipeline _pipeline,
127 const VkAllocationCallbacks* pAllocator)
128 {
129 RADV_FROM_HANDLE(radv_device, device, _device);
130 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
131
132 if (!_pipeline)
133 return;
134
135 radv_pipeline_destroy(device, pipeline, pAllocator);
136 }
137
138
139 static void
140 radv_optimize_nir(struct nir_shader *shader)
141 {
142 bool progress;
143
144 do {
145 progress = false;
146
147 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
148 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
149 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
150
151 NIR_PASS(progress, shader, nir_copy_prop);
152 NIR_PASS(progress, shader, nir_opt_remove_phis);
153 NIR_PASS(progress, shader, nir_opt_dce);
154 NIR_PASS(progress, shader, nir_opt_dead_cf);
155 NIR_PASS(progress, shader, nir_opt_cse);
156 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
157 NIR_PASS(progress, shader, nir_opt_algebraic);
158 NIR_PASS(progress, shader, nir_opt_constant_folding);
159 NIR_PASS(progress, shader, nir_opt_undef);
160 NIR_PASS(progress, shader, nir_opt_conditional_discard);
161 } while (progress);
162 }
163
164 static nir_shader *
165 radv_shader_compile_to_nir(struct radv_device *device,
166 struct radv_shader_module *module,
167 const char *entrypoint_name,
168 gl_shader_stage stage,
169 const VkSpecializationInfo *spec_info,
170 bool dump)
171 {
172 if (strcmp(entrypoint_name, "main") != 0) {
173 radv_finishme("Multiple shaders per module not really supported");
174 }
175
176 nir_shader *nir;
177 nir_function *entry_point;
178 if (module->nir) {
179 /* Some things such as our meta clear/blit code will give us a NIR
180 * shader directly. In that case, we just ignore the SPIR-V entirely
181 * and just use the NIR shader */
182 nir = module->nir;
183 nir->options = &nir_options;
184 nir_validate_shader(nir);
185
186 assert(exec_list_length(&nir->functions) == 1);
187 struct exec_node *node = exec_list_get_head(&nir->functions);
188 entry_point = exec_node_data(nir_function, node, node);
189 } else {
190 uint32_t *spirv = (uint32_t *) module->data;
191 assert(module->size % 4 == 0);
192
193 uint32_t num_spec_entries = 0;
194 struct nir_spirv_specialization *spec_entries = NULL;
195 if (spec_info && spec_info->mapEntryCount > 0) {
196 num_spec_entries = spec_info->mapEntryCount;
197 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
198 for (uint32_t i = 0; i < num_spec_entries; i++) {
199 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
200 const void *data = spec_info->pData + entry.offset;
201 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
202
203 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
204 if (spec_info->dataSize == 8)
205 spec_entries[i].data64 = *(const uint64_t *)data;
206 else
207 spec_entries[i].data32 = *(const uint32_t *)data;
208 }
209 }
210 const struct nir_spirv_supported_extensions supported_ext = {
211 .draw_parameters = true,
212 .float64 = true,
213 .image_read_without_format = true,
214 .image_write_without_format = true,
215 };
216 entry_point = spirv_to_nir(spirv, module->size / 4,
217 spec_entries, num_spec_entries,
218 stage, entrypoint_name, &supported_ext, &nir_options);
219 nir = entry_point->shader;
220 assert(nir->stage == stage);
221 nir_validate_shader(nir);
222
223 free(spec_entries);
224
225 /* We have to lower away local constant initializers right before we
226 * inline functions. That way they get properly initialized at the top
227 * of the function and not at the top of its caller.
228 */
229 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
230 NIR_PASS_V(nir, nir_lower_returns);
231 NIR_PASS_V(nir, nir_inline_functions);
232
233 /* Pick off the single entrypoint that we want */
234 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
235 if (func != entry_point)
236 exec_node_remove(&func->node);
237 }
238 assert(exec_list_length(&nir->functions) == 1);
239 entry_point->name = ralloc_strdup(entry_point, "main");
240
241 NIR_PASS_V(nir, nir_remove_dead_variables,
242 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
243
244 /* Now that we've deleted all but the main function, we can go ahead and
245 * lower the rest of the constant initializers.
246 */
247 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
248 NIR_PASS_V(nir, nir_lower_system_values);
249 }
250
251 /* Vulkan uses the separate-shader linking model */
252 nir->info->separate_shader = true;
253
254 nir_shader_gather_info(nir, entry_point->impl);
255
256 nir_variable_mode indirect_mask = 0;
257 indirect_mask |= nir_var_shader_in;
258 indirect_mask |= nir_var_local;
259
260 nir_lower_indirect_derefs(nir, indirect_mask);
261
262 static const nir_lower_tex_options tex_options = {
263 .lower_txp = ~0,
264 };
265
266 nir_lower_tex(nir, &tex_options);
267
268 nir_lower_vars_to_ssa(nir);
269 nir_lower_var_copies(nir);
270 nir_lower_global_vars_to_local(nir);
271 nir_remove_dead_variables(nir, nir_var_local);
272 radv_optimize_nir(nir);
273
274 if (dump)
275 nir_print_shader(nir, stderr);
276
277 return nir;
278 }
279
280 static const char *radv_get_shader_name(struct radv_shader_variant *var,
281 gl_shader_stage stage)
282 {
283 switch (stage) {
284 case MESA_SHADER_VERTEX: return var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
285 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
286 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
287 case MESA_SHADER_COMPUTE: return "Compute Shader";
288 default:
289 return "Unknown shader";
290 };
291
292 }
293 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
294 {
295 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
296 struct radv_shader_variant *var;
297 struct ac_shader_config *conf;
298 int i;
299 FILE *file = stderr;
300 unsigned max_simd_waves = 10;
301 unsigned lds_per_wave = 0;
302
303 for (i = 0; i < MESA_SHADER_STAGES; i++) {
304 if (!pipeline->shaders[i])
305 continue;
306 var = pipeline->shaders[i];
307
308 conf = &var->config;
309
310 if (i == MESA_SHADER_FRAGMENT) {
311 lds_per_wave = conf->lds_size * lds_increment +
312 align(var->info.fs.num_interp * 48, lds_increment);
313 }
314
315 if (conf->num_sgprs) {
316 if (device->physical_device->rad_info.chip_class >= VI)
317 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
318 else
319 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
320 }
321
322 if (conf->num_vgprs)
323 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
324
325 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
326 * that PS can use.
327 */
328 if (lds_per_wave)
329 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
330
331 fprintf(file, "\n%s:\n",
332 radv_get_shader_name(var, i));
333 if (i == MESA_SHADER_FRAGMENT) {
334 fprintf(file, "*** SHADER CONFIG ***\n"
335 "SPI_PS_INPUT_ADDR = 0x%04x\n"
336 "SPI_PS_INPUT_ENA = 0x%04x\n",
337 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
338 }
339 fprintf(file, "*** SHADER STATS ***\n"
340 "SGPRS: %d\n"
341 "VGPRS: %d\n"
342 "Spilled SGPRs: %d\n"
343 "Spilled VGPRs: %d\n"
344 "Code Size: %d bytes\n"
345 "LDS: %d blocks\n"
346 "Scratch: %d bytes per wave\n"
347 "Max Waves: %d\n"
348 "********************\n\n\n",
349 conf->num_sgprs, conf->num_vgprs,
350 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
351 conf->lds_size, conf->scratch_bytes_per_wave,
352 max_simd_waves);
353 }
354 }
355
356 void radv_shader_variant_destroy(struct radv_device *device,
357 struct radv_shader_variant *variant)
358 {
359 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
360 return;
361
362 device->ws->buffer_destroy(variant->bo);
363 free(variant);
364 }
365
366 static void radv_fill_shader_variant(struct radv_device *device,
367 struct radv_shader_variant *variant,
368 struct ac_shader_binary *binary,
369 gl_shader_stage stage)
370 {
371 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
372 unsigned vgpr_comp_cnt = 0;
373
374 if (scratch_enabled && !device->llvm_supports_spill)
375 radv_finishme("shader scratch support only available with LLVM 4.0");
376
377 variant->code_size = binary->code_size;
378
379 switch (stage) {
380 case MESA_SHADER_VERTEX:
381 case MESA_SHADER_GEOMETRY:
382 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
383 S_00B12C_SCRATCH_EN(scratch_enabled);
384 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
385 break;
386 case MESA_SHADER_FRAGMENT:
387 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
388 S_00B12C_SCRATCH_EN(scratch_enabled);
389 break;
390 case MESA_SHADER_COMPUTE:
391 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
392 S_00B84C_SCRATCH_EN(scratch_enabled) |
393 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
394 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
395 S_00B84C_TG_SIZE_EN(1) |
396 S_00B84C_LDS_SIZE(variant->config.lds_size);
397 break;
398 default:
399 unreachable("unsupported shader type");
400 break;
401 }
402
403 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
404 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
405 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
406 S_00B848_DX10_CLAMP(1) |
407 S_00B848_FLOAT_MODE(variant->config.float_mode);
408
409 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
410 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
411
412 void *ptr = device->ws->buffer_map(variant->bo);
413 memcpy(ptr, binary->code, binary->code_size);
414 device->ws->buffer_unmap(variant->bo);
415
416
417 }
418
419 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
420 struct nir_shader *shader,
421 struct radv_pipeline_layout *layout,
422 const union ac_shader_variant_key *key,
423 void** code_out,
424 unsigned *code_size_out,
425 bool dump)
426 {
427 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
428 enum radeon_family chip_family = device->physical_device->rad_info.family;
429 LLVMTargetMachineRef tm;
430 if (!variant)
431 return NULL;
432
433 struct ac_nir_compiler_options options = {0};
434 options.layout = layout;
435 if (key)
436 options.key = *key;
437
438 struct ac_shader_binary binary;
439
440 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
441 options.family = chip_family;
442 options.chip_class = device->physical_device->rad_info.chip_class;
443 options.supports_spill = device->llvm_supports_spill;
444 tm = ac_create_target_machine(chip_family, options.supports_spill);
445 ac_compile_nir_shader(tm, &binary, &variant->config,
446 &variant->info, shader, &options, dump);
447 LLVMDisposeTargetMachine(tm);
448
449 radv_fill_shader_variant(device, variant, &binary, shader->stage);
450
451 if (code_out) {
452 *code_out = binary.code;
453 *code_size_out = binary.code_size;
454 } else
455 free(binary.code);
456 free(binary.config);
457 free(binary.rodata);
458 free(binary.global_symbol_offsets);
459 free(binary.relocs);
460 free(binary.disasm_string);
461 variant->ref_count = 1;
462 return variant;
463 }
464
465 static struct radv_shader_variant *
466 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
467 struct nir_shader *nir,
468 void** code_out,
469 unsigned *code_size_out,
470 bool dump_shader)
471 {
472 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
473 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
474 LLVMTargetMachineRef tm;
475 if (!variant)
476 return NULL;
477
478 struct ac_nir_compiler_options options = {0};
479 struct ac_shader_binary binary;
480 options.family = chip_family;
481 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
482 options.supports_spill = pipeline->device->llvm_supports_spill;
483 tm = ac_create_target_machine(chip_family, options.supports_spill);
484 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
485 LLVMDisposeTargetMachine(tm);
486
487 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
488
489 if (code_out) {
490 *code_out = binary.code;
491 *code_size_out = binary.code_size;
492 } else
493 free(binary.code);
494 free(binary.config);
495 free(binary.rodata);
496 free(binary.global_symbol_offsets);
497 free(binary.relocs);
498 free(binary.disasm_string);
499 variant->ref_count = 1;
500 return variant;
501 }
502
503 static struct radv_shader_variant *
504 radv_pipeline_compile(struct radv_pipeline *pipeline,
505 struct radv_pipeline_cache *cache,
506 struct radv_shader_module *module,
507 const char *entrypoint,
508 gl_shader_stage stage,
509 const VkSpecializationInfo *spec_info,
510 struct radv_pipeline_layout *layout,
511 const union ac_shader_variant_key *key)
512 {
513 unsigned char sha1[20];
514 unsigned char gs_copy_sha1[20];
515 struct radv_shader_variant *variant;
516 nir_shader *nir;
517 void *code = NULL;
518 unsigned code_size = 0;
519 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
520
521 if (module->nir)
522 _mesa_sha1_compute(module->nir->info->name,
523 strlen(module->nir->info->name),
524 module->sha1);
525
526 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
527 if (stage == MESA_SHADER_GEOMETRY)
528 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
529 layout, key, 1);
530
531 if (cache) {
532 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
533 cache,
534 sha1);
535
536 if (stage == MESA_SHADER_GEOMETRY) {
537 pipeline->gs_copy_shader =
538 radv_create_shader_variant_from_pipeline_cache(
539 pipeline->device,
540 cache,
541 gs_copy_sha1);
542 }
543 if (variant)
544 return variant;
545 }
546
547 nir = radv_shader_compile_to_nir(pipeline->device,
548 module, entrypoint, stage,
549 spec_info, dump);
550 if (nir == NULL)
551 return NULL;
552
553 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
554 &code, &code_size, dump);
555
556 if (stage == MESA_SHADER_GEOMETRY) {
557 void *gs_copy_code = NULL;
558 unsigned gs_copy_code_size = 0;
559 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
560 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
561
562 if (pipeline->gs_copy_shader && cache) {
563 pipeline->gs_copy_shader =
564 radv_pipeline_cache_insert_shader(cache,
565 gs_copy_sha1,
566 pipeline->gs_copy_shader,
567 gs_copy_code,
568 gs_copy_code_size);
569 }
570 }
571 if (!module->nir)
572 ralloc_free(nir);
573
574 if (variant && cache)
575 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
576 code, code_size);
577
578 if (code)
579 free(code);
580 return variant;
581 }
582
583 static VkResult
584 radv_pipeline_scratch_init(struct radv_device *device,
585 struct radv_pipeline *pipeline)
586 {
587 unsigned scratch_bytes_per_wave = 0;
588 unsigned max_waves = 0;
589 unsigned min_waves = 1;
590
591 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
592 if (pipeline->shaders[i]) {
593 unsigned max_stage_waves = device->scratch_waves;
594
595 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
596 pipeline->shaders[i]->config.scratch_bytes_per_wave);
597
598 max_stage_waves = MIN2(max_stage_waves,
599 4 * device->physical_device->rad_info.num_good_compute_units *
600 (256 / pipeline->shaders[i]->config.num_vgprs));
601 max_waves = MAX2(max_waves, max_stage_waves);
602 }
603 }
604
605 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
606 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
607 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
608 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
609 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
610 }
611
612 if (scratch_bytes_per_wave)
613 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
614
615 if (scratch_bytes_per_wave && max_waves < min_waves) {
616 /* Not really true at this moment, but will be true on first
617 * execution. Avoid having hanging shaders. */
618 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
619 }
620 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
621 pipeline->max_waves = max_waves;
622 return VK_SUCCESS;
623 }
624
625 static uint32_t si_translate_blend_function(VkBlendOp op)
626 {
627 switch (op) {
628 case VK_BLEND_OP_ADD:
629 return V_028780_COMB_DST_PLUS_SRC;
630 case VK_BLEND_OP_SUBTRACT:
631 return V_028780_COMB_SRC_MINUS_DST;
632 case VK_BLEND_OP_REVERSE_SUBTRACT:
633 return V_028780_COMB_DST_MINUS_SRC;
634 case VK_BLEND_OP_MIN:
635 return V_028780_COMB_MIN_DST_SRC;
636 case VK_BLEND_OP_MAX:
637 return V_028780_COMB_MAX_DST_SRC;
638 default:
639 return 0;
640 }
641 }
642
643 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
644 {
645 switch (factor) {
646 case VK_BLEND_FACTOR_ZERO:
647 return V_028780_BLEND_ZERO;
648 case VK_BLEND_FACTOR_ONE:
649 return V_028780_BLEND_ONE;
650 case VK_BLEND_FACTOR_SRC_COLOR:
651 return V_028780_BLEND_SRC_COLOR;
652 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
653 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
654 case VK_BLEND_FACTOR_DST_COLOR:
655 return V_028780_BLEND_DST_COLOR;
656 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
657 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
658 case VK_BLEND_FACTOR_SRC_ALPHA:
659 return V_028780_BLEND_SRC_ALPHA;
660 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
661 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
662 case VK_BLEND_FACTOR_DST_ALPHA:
663 return V_028780_BLEND_DST_ALPHA;
664 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
665 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
666 case VK_BLEND_FACTOR_CONSTANT_COLOR:
667 return V_028780_BLEND_CONSTANT_COLOR;
668 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
669 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
670 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
671 return V_028780_BLEND_CONSTANT_ALPHA;
672 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
673 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
674 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
675 return V_028780_BLEND_SRC_ALPHA_SATURATE;
676 case VK_BLEND_FACTOR_SRC1_COLOR:
677 return V_028780_BLEND_SRC1_COLOR;
678 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
679 return V_028780_BLEND_INV_SRC1_COLOR;
680 case VK_BLEND_FACTOR_SRC1_ALPHA:
681 return V_028780_BLEND_SRC1_ALPHA;
682 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
683 return V_028780_BLEND_INV_SRC1_ALPHA;
684 default:
685 return 0;
686 }
687 }
688
689 static bool is_dual_src(VkBlendFactor factor)
690 {
691 switch (factor) {
692 case VK_BLEND_FACTOR_SRC1_COLOR:
693 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
694 case VK_BLEND_FACTOR_SRC1_ALPHA:
695 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
696 return true;
697 default:
698 return false;
699 }
700 }
701
702 static unsigned si_choose_spi_color_format(VkFormat vk_format,
703 bool blend_enable,
704 bool blend_need_alpha)
705 {
706 const struct vk_format_description *desc = vk_format_description(vk_format);
707 unsigned format, ntype, swap;
708
709 /* Alpha is needed for alpha-to-coverage.
710 * Blending may be with or without alpha.
711 */
712 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
713 unsigned alpha = 0; /* exports alpha, but may not support blending */
714 unsigned blend = 0; /* supports blending, but may not export alpha */
715 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
716
717 format = radv_translate_colorformat(vk_format);
718 ntype = radv_translate_color_numformat(vk_format, desc,
719 vk_format_get_first_non_void_channel(vk_format));
720 swap = radv_translate_colorswap(vk_format, false);
721
722 /* Choose the SPI color formats. These are required values for Stoney/RB+.
723 * Other chips have multiple choices, though they are not necessarily better.
724 */
725 switch (format) {
726 case V_028C70_COLOR_5_6_5:
727 case V_028C70_COLOR_1_5_5_5:
728 case V_028C70_COLOR_5_5_5_1:
729 case V_028C70_COLOR_4_4_4_4:
730 case V_028C70_COLOR_10_11_11:
731 case V_028C70_COLOR_11_11_10:
732 case V_028C70_COLOR_8:
733 case V_028C70_COLOR_8_8:
734 case V_028C70_COLOR_8_8_8_8:
735 case V_028C70_COLOR_10_10_10_2:
736 case V_028C70_COLOR_2_10_10_10:
737 if (ntype == V_028C70_NUMBER_UINT)
738 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
739 else if (ntype == V_028C70_NUMBER_SINT)
740 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
741 else
742 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
743 break;
744
745 case V_028C70_COLOR_16:
746 case V_028C70_COLOR_16_16:
747 case V_028C70_COLOR_16_16_16_16:
748 if (ntype == V_028C70_NUMBER_UNORM ||
749 ntype == V_028C70_NUMBER_SNORM) {
750 /* UNORM16 and SNORM16 don't support blending */
751 if (ntype == V_028C70_NUMBER_UNORM)
752 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
753 else
754 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
755
756 /* Use 32 bits per channel for blending. */
757 if (format == V_028C70_COLOR_16) {
758 if (swap == V_028C70_SWAP_STD) { /* R */
759 blend = V_028714_SPI_SHADER_32_R;
760 blend_alpha = V_028714_SPI_SHADER_32_AR;
761 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
762 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
763 else
764 assert(0);
765 } else if (format == V_028C70_COLOR_16_16) {
766 if (swap == V_028C70_SWAP_STD) { /* RG */
767 blend = V_028714_SPI_SHADER_32_GR;
768 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
769 } else if (swap == V_028C70_SWAP_ALT) /* RA */
770 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
771 else
772 assert(0);
773 } else /* 16_16_16_16 */
774 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
775 } else if (ntype == V_028C70_NUMBER_UINT)
776 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
777 else if (ntype == V_028C70_NUMBER_SINT)
778 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
779 else if (ntype == V_028C70_NUMBER_FLOAT)
780 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
781 else
782 assert(0);
783 break;
784
785 case V_028C70_COLOR_32:
786 if (swap == V_028C70_SWAP_STD) { /* R */
787 blend = normal = V_028714_SPI_SHADER_32_R;
788 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
789 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
790 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
791 else
792 assert(0);
793 break;
794
795 case V_028C70_COLOR_32_32:
796 if (swap == V_028C70_SWAP_STD) { /* RG */
797 blend = normal = V_028714_SPI_SHADER_32_GR;
798 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
799 } else if (swap == V_028C70_SWAP_ALT) /* RA */
800 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
801 else
802 assert(0);
803 break;
804
805 case V_028C70_COLOR_32_32_32_32:
806 case V_028C70_COLOR_8_24:
807 case V_028C70_COLOR_24_8:
808 case V_028C70_COLOR_X24_8_32_FLOAT:
809 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
810 break;
811
812 default:
813 unreachable("unhandled blend format");
814 }
815
816 if (blend_enable && blend_need_alpha)
817 return blend_alpha;
818 else if(blend_need_alpha)
819 return alpha;
820 else if(blend_enable)
821 return blend;
822 else
823 return normal;
824 }
825
826 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
827 {
828 unsigned i, cb_shader_mask = 0;
829
830 for (i = 0; i < 8; i++) {
831 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
832 case V_028714_SPI_SHADER_ZERO:
833 break;
834 case V_028714_SPI_SHADER_32_R:
835 cb_shader_mask |= 0x1 << (i * 4);
836 break;
837 case V_028714_SPI_SHADER_32_GR:
838 cb_shader_mask |= 0x3 << (i * 4);
839 break;
840 case V_028714_SPI_SHADER_32_AR:
841 cb_shader_mask |= 0x9 << (i * 4);
842 break;
843 case V_028714_SPI_SHADER_FP16_ABGR:
844 case V_028714_SPI_SHADER_UNORM16_ABGR:
845 case V_028714_SPI_SHADER_SNORM16_ABGR:
846 case V_028714_SPI_SHADER_UINT16_ABGR:
847 case V_028714_SPI_SHADER_SINT16_ABGR:
848 case V_028714_SPI_SHADER_32_ABGR:
849 cb_shader_mask |= 0xf << (i * 4);
850 break;
851 default:
852 assert(0);
853 }
854 }
855 return cb_shader_mask;
856 }
857
858 static void
859 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
860 const VkGraphicsPipelineCreateInfo *pCreateInfo,
861 uint32_t blend_enable,
862 uint32_t blend_need_alpha,
863 bool single_cb_enable,
864 bool blend_mrt0_is_dual_src)
865 {
866 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
867 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
868 struct radv_blend_state *blend = &pipeline->graphics.blend;
869 unsigned col_format = 0;
870
871 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
872 struct radv_render_pass_attachment *attachment;
873 unsigned cf;
874
875 attachment = pass->attachments + subpass->color_attachments[i].attachment;
876
877 cf = si_choose_spi_color_format(attachment->format,
878 blend_enable & (1 << i),
879 blend_need_alpha & (1 << i));
880
881 col_format |= cf << (4 * i);
882 }
883
884 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
885
886 if (blend_mrt0_is_dual_src)
887 col_format |= (col_format & 0xf) << 4;
888 if (!col_format)
889 col_format |= V_028714_SPI_SHADER_32_R;
890 blend->spi_shader_col_format = col_format;
891 }
892
893 static bool
894 format_is_int8(VkFormat format)
895 {
896 const struct vk_format_description *desc = vk_format_description(format);
897 int channel = vk_format_get_first_non_void_channel(format);
898
899 return channel >= 0 && desc->channel[channel].pure_integer &&
900 desc->channel[channel].size == 8;
901 }
902
903 unsigned radv_format_meta_fs_key(VkFormat format)
904 {
905 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
906 bool is_int8 = format_is_int8(format);
907
908 return col_format + (is_int8 ? 3 : 0);
909 }
910
911 static unsigned
912 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
913 {
914 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
915 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
916 unsigned is_int8 = 0;
917
918 for (unsigned i = 0; i < subpass->color_count; ++i) {
919 struct radv_render_pass_attachment *attachment;
920
921 attachment = pass->attachments + subpass->color_attachments[i].attachment;
922
923 if (format_is_int8(attachment->format))
924 is_int8 |= 1 << i;
925 }
926
927 return is_int8;
928 }
929
930 static void
931 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
932 const VkGraphicsPipelineCreateInfo *pCreateInfo,
933 const struct radv_graphics_pipeline_create_info *extra)
934 {
935 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
936 struct radv_blend_state *blend = &pipeline->graphics.blend;
937 unsigned mode = V_028808_CB_NORMAL;
938 uint32_t blend_enable = 0, blend_need_alpha = 0;
939 bool blend_mrt0_is_dual_src = false;
940 int i;
941 bool single_cb_enable = false;
942
943 if (!vkblend)
944 return;
945
946 if (extra && extra->custom_blend_mode) {
947 single_cb_enable = true;
948 mode = extra->custom_blend_mode;
949 }
950 blend->cb_color_control = 0;
951 if (vkblend->logicOpEnable)
952 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
953 else
954 blend->cb_color_control |= S_028808_ROP3(0xcc);
955
956 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
957 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
958 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
959 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
960
961 blend->cb_target_mask = 0;
962 for (i = 0; i < vkblend->attachmentCount; i++) {
963 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
964 unsigned blend_cntl = 0;
965 VkBlendOp eqRGB = att->colorBlendOp;
966 VkBlendFactor srcRGB = att->srcColorBlendFactor;
967 VkBlendFactor dstRGB = att->dstColorBlendFactor;
968 VkBlendOp eqA = att->alphaBlendOp;
969 VkBlendFactor srcA = att->srcAlphaBlendFactor;
970 VkBlendFactor dstA = att->dstAlphaBlendFactor;
971
972 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
973
974 if (!att->colorWriteMask)
975 continue;
976
977 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
978 if (!att->blendEnable) {
979 blend->cb_blend_control[i] = blend_cntl;
980 continue;
981 }
982
983 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
984 if (i == 0)
985 blend_mrt0_is_dual_src = true;
986
987 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
988 srcRGB = VK_BLEND_FACTOR_ONE;
989 dstRGB = VK_BLEND_FACTOR_ONE;
990 }
991 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
992 srcA = VK_BLEND_FACTOR_ONE;
993 dstA = VK_BLEND_FACTOR_ONE;
994 }
995
996 blend_cntl |= S_028780_ENABLE(1);
997
998 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
999 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1000 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1001 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1002 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1003 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1004 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1005 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1006 }
1007 blend->cb_blend_control[i] = blend_cntl;
1008
1009 blend_enable |= 1 << i;
1010
1011 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1012 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1013 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1014 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1015 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1016 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1017 blend_need_alpha |= 1 << i;
1018 }
1019 for (i = vkblend->attachmentCount; i < 8; i++)
1020 blend->cb_blend_control[i] = 0;
1021
1022 if (blend->cb_target_mask)
1023 blend->cb_color_control |= S_028808_MODE(mode);
1024 else
1025 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1026
1027 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1028 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1029 }
1030
1031 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1032 {
1033 switch (op) {
1034 case VK_STENCIL_OP_KEEP:
1035 return V_02842C_STENCIL_KEEP;
1036 case VK_STENCIL_OP_ZERO:
1037 return V_02842C_STENCIL_ZERO;
1038 case VK_STENCIL_OP_REPLACE:
1039 return V_02842C_STENCIL_REPLACE_TEST;
1040 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1041 return V_02842C_STENCIL_ADD_CLAMP;
1042 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1043 return V_02842C_STENCIL_SUB_CLAMP;
1044 case VK_STENCIL_OP_INVERT:
1045 return V_02842C_STENCIL_INVERT;
1046 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1047 return V_02842C_STENCIL_ADD_WRAP;
1048 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1049 return V_02842C_STENCIL_SUB_WRAP;
1050 default:
1051 return 0;
1052 }
1053 }
1054 static void
1055 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1056 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1057 const struct radv_graphics_pipeline_create_info *extra)
1058 {
1059 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1060 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1061
1062 memset(ds, 0, sizeof(*ds));
1063 if (!vkds)
1064 return;
1065 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1066 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1067 S_028800_ZFUNC(vkds->depthCompareOp) |
1068 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1069
1070 if (vkds->stencilTestEnable) {
1071 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1072 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1073 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1074 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1075 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1076
1077 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1078 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1079 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1080 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1081 }
1082
1083 if (extra) {
1084
1085 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1086 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1087
1088 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1089 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1090 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1091 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1092 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1093 }
1094 }
1095
1096 static uint32_t si_translate_fill(VkPolygonMode func)
1097 {
1098 switch(func) {
1099 case VK_POLYGON_MODE_FILL:
1100 return V_028814_X_DRAW_TRIANGLES;
1101 case VK_POLYGON_MODE_LINE:
1102 return V_028814_X_DRAW_LINES;
1103 case VK_POLYGON_MODE_POINT:
1104 return V_028814_X_DRAW_POINTS;
1105 default:
1106 assert(0);
1107 return V_028814_X_DRAW_POINTS;
1108 }
1109 }
1110 static void
1111 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1112 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1113 {
1114 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1115 struct radv_raster_state *raster = &pipeline->graphics.raster;
1116
1117 memset(raster, 0, sizeof(*raster));
1118
1119 raster->spi_interp_control =
1120 S_0286D4_FLAT_SHADE_ENA(1) |
1121 S_0286D4_PNT_SPRITE_ENA(1) |
1122 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1123 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1124 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1125 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1126 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1127
1128 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1129 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1130 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1131 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1132 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1133 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1134 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1135
1136 raster->pa_su_vtx_cntl =
1137 S_028BE4_PIX_CENTER(1) | // TODO verify
1138 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1139 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1140
1141 raster->pa_su_sc_mode_cntl =
1142 S_028814_FACE(vkraster->frontFace) |
1143 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1144 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1145 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1146 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1147 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1148 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1149 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1150 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1151
1152 }
1153
1154 static void
1155 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1156 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1157 {
1158 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1159 struct radv_blend_state *blend = &pipeline->graphics.blend;
1160 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1161 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1162 int ps_iter_samples = 1;
1163 uint32_t mask = 0xffff;
1164
1165 ms->num_samples = vkms->rasterizationSamples;
1166
1167 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1168 ps_iter_samples = vkms->rasterizationSamples;
1169 }
1170
1171 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1172 ms->pa_sc_aa_config = 0;
1173 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1174 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1175 ms->pa_sc_mode_cntl_1 =
1176 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1177 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1178 /* always 1: */
1179 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1180 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1181 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1182 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1183 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1184 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1185
1186 if (vkms->rasterizationSamples > 1) {
1187 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1188 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1189 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1190 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1191 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1192 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1193 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1194 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1195 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1196 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1197 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1198 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1199 }
1200
1201 if (vkms->alphaToCoverageEnable)
1202 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1203
1204 if (vkms->pSampleMask) {
1205 mask = vkms->pSampleMask[0] & 0xffff;
1206 }
1207
1208 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1209 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1210 }
1211
1212 static uint32_t
1213 si_translate_prim(enum VkPrimitiveTopology topology)
1214 {
1215 switch (topology) {
1216 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1217 return V_008958_DI_PT_POINTLIST;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1219 return V_008958_DI_PT_LINELIST;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1221 return V_008958_DI_PT_LINESTRIP;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1223 return V_008958_DI_PT_TRILIST;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1225 return V_008958_DI_PT_TRISTRIP;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1227 return V_008958_DI_PT_TRIFAN;
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1229 return V_008958_DI_PT_LINELIST_ADJ;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1231 return V_008958_DI_PT_LINESTRIP_ADJ;
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1233 return V_008958_DI_PT_TRILIST_ADJ;
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1235 return V_008958_DI_PT_TRISTRIP_ADJ;
1236 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1237 return V_008958_DI_PT_PATCH;
1238 default:
1239 assert(0);
1240 return 0;
1241 }
1242 }
1243
1244 static uint32_t
1245 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1246 {
1247 switch (gl_prim) {
1248 case 0: /* GL_POINTS */
1249 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1250 case 1: /* GL_LINES */
1251 case 3: /* GL_LINE_STRIP */
1252 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1253 case 0x8E7A: /* GL_ISOLINES */
1254 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1255
1256 case 4: /* GL_TRIANGLES */
1257 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1258 case 5: /* GL_TRIANGLE_STRIP */
1259 case 7: /* GL_QUADS */
1260 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1261 default:
1262 assert(0);
1263 return 0;
1264 }
1265 }
1266
1267 static uint32_t
1268 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1269 {
1270 switch (topology) {
1271 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1272 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1273 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1278 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1284 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1285 default:
1286 assert(0);
1287 return 0;
1288 }
1289 }
1290
1291 static unsigned si_map_swizzle(unsigned swizzle)
1292 {
1293 switch (swizzle) {
1294 case VK_SWIZZLE_Y:
1295 return V_008F0C_SQ_SEL_Y;
1296 case VK_SWIZZLE_Z:
1297 return V_008F0C_SQ_SEL_Z;
1298 case VK_SWIZZLE_W:
1299 return V_008F0C_SQ_SEL_W;
1300 case VK_SWIZZLE_0:
1301 return V_008F0C_SQ_SEL_0;
1302 case VK_SWIZZLE_1:
1303 return V_008F0C_SQ_SEL_1;
1304 default: /* VK_SWIZZLE_X */
1305 return V_008F0C_SQ_SEL_X;
1306 }
1307 }
1308
1309 static void
1310 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1311 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1312 {
1313 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1314 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1315 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1316
1317 pipeline->dynamic_state = default_dynamic_state;
1318
1319 if (pCreateInfo->pDynamicState) {
1320 /* Remove all of the states that are marked as dynamic */
1321 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1322 for (uint32_t s = 0; s < count; s++)
1323 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1324 }
1325
1326 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1327
1328 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1329 *
1330 * pViewportState is [...] NULL if the pipeline
1331 * has rasterization disabled.
1332 */
1333 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1334 assert(pCreateInfo->pViewportState);
1335
1336 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1337 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1338 typed_memcpy(dynamic->viewport.viewports,
1339 pCreateInfo->pViewportState->pViewports,
1340 pCreateInfo->pViewportState->viewportCount);
1341 }
1342
1343 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1344 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1345 typed_memcpy(dynamic->scissor.scissors,
1346 pCreateInfo->pViewportState->pScissors,
1347 pCreateInfo->pViewportState->scissorCount);
1348 }
1349 }
1350
1351 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1352 assert(pCreateInfo->pRasterizationState);
1353 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1354 }
1355
1356 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1357 assert(pCreateInfo->pRasterizationState);
1358 dynamic->depth_bias.bias =
1359 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1360 dynamic->depth_bias.clamp =
1361 pCreateInfo->pRasterizationState->depthBiasClamp;
1362 dynamic->depth_bias.slope =
1363 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1364 }
1365
1366 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1367 *
1368 * pColorBlendState is [...] NULL if the pipeline has rasterization
1369 * disabled or if the subpass of the render pass the pipeline is
1370 * created against does not use any color attachments.
1371 */
1372 bool uses_color_att = false;
1373 for (unsigned i = 0; i < subpass->color_count; ++i) {
1374 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1375 uses_color_att = true;
1376 break;
1377 }
1378 }
1379
1380 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1381 assert(pCreateInfo->pColorBlendState);
1382 typed_memcpy(dynamic->blend_constants,
1383 pCreateInfo->pColorBlendState->blendConstants, 4);
1384 }
1385
1386 /* If there is no depthstencil attachment, then don't read
1387 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1388 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1389 * no need to override the depthstencil defaults in
1390 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1391 *
1392 * Section 9.2 of the Vulkan 1.0.15 spec says:
1393 *
1394 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1395 * disabled or if the subpass of the render pass the pipeline is created
1396 * against does not use a depth/stencil attachment.
1397 */
1398 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1399 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1400 assert(pCreateInfo->pDepthStencilState);
1401
1402 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1403 dynamic->depth_bounds.min =
1404 pCreateInfo->pDepthStencilState->minDepthBounds;
1405 dynamic->depth_bounds.max =
1406 pCreateInfo->pDepthStencilState->maxDepthBounds;
1407 }
1408
1409 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1410 dynamic->stencil_compare_mask.front =
1411 pCreateInfo->pDepthStencilState->front.compareMask;
1412 dynamic->stencil_compare_mask.back =
1413 pCreateInfo->pDepthStencilState->back.compareMask;
1414 }
1415
1416 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1417 dynamic->stencil_write_mask.front =
1418 pCreateInfo->pDepthStencilState->front.writeMask;
1419 dynamic->stencil_write_mask.back =
1420 pCreateInfo->pDepthStencilState->back.writeMask;
1421 }
1422
1423 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1424 dynamic->stencil_reference.front =
1425 pCreateInfo->pDepthStencilState->front.reference;
1426 dynamic->stencil_reference.back =
1427 pCreateInfo->pDepthStencilState->back.reference;
1428 }
1429 }
1430
1431 pipeline->dynamic_state_mask = states;
1432 }
1433
1434 static union ac_shader_variant_key
1435 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
1436 {
1437 union ac_shader_variant_key key;
1438 const VkPipelineVertexInputStateCreateInfo *input_state =
1439 pCreateInfo->pVertexInputState;
1440
1441 memset(&key, 0, sizeof(key));
1442 key.vs.instance_rate_inputs = 0;
1443 key.vs.as_es = as_es;
1444
1445 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1446 unsigned binding;
1447 binding = input_state->pVertexAttributeDescriptions[i].binding;
1448 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1449 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1450 }
1451 return key;
1452 }
1453
1454 static void
1455 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1456 {
1457 struct radv_device *device = pipeline->device;
1458 unsigned num_se = device->physical_device->rad_info.max_se;
1459 unsigned wave_size = 64;
1460 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1461 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1462 unsigned alignment = 256 * num_se;
1463 /* The maximum size is 63.999 MB per SE. */
1464 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1465
1466 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1467 struct ac_shader_variant_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info;
1468 /* Calculate the minimum size. */
1469 unsigned min_esgs_ring_size = align(es_info->vs.esgs_itemsize * gs_vertex_reuse *
1470 wave_size, alignment);
1471 /* These are recommended sizes, not minimum sizes. */
1472 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1473 es_info->vs.esgs_itemsize * gs_info->gs.vertices_in;
1474 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1475 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1476
1477 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1478 esgs_ring_size = align(esgs_ring_size, alignment);
1479 gsvs_ring_size = align(gsvs_ring_size, alignment);
1480
1481 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1482 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1483 }
1484
1485 static const struct radv_prim_vertex_count prim_size_table[] = {
1486 [V_008958_DI_PT_NONE] = {0, 0},
1487 [V_008958_DI_PT_POINTLIST] = {1, 1},
1488 [V_008958_DI_PT_LINELIST] = {2, 2},
1489 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1490 [V_008958_DI_PT_TRILIST] = {3, 3},
1491 [V_008958_DI_PT_TRIFAN] = {3, 1},
1492 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1493 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1494 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1495 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1496 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1497 [V_008958_DI_PT_RECTLIST] = {3, 3},
1498 [V_008958_DI_PT_LINELOOP] = {2, 1},
1499 [V_008958_DI_PT_POLYGON] = {3, 1},
1500 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1501 };
1502
1503 VkResult
1504 radv_pipeline_init(struct radv_pipeline *pipeline,
1505 struct radv_device *device,
1506 struct radv_pipeline_cache *cache,
1507 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1508 const struct radv_graphics_pipeline_create_info *extra,
1509 const VkAllocationCallbacks *alloc)
1510 {
1511 struct radv_shader_module fs_m = {0};
1512 VkResult result;
1513
1514 if (alloc == NULL)
1515 alloc = &device->alloc;
1516
1517 pipeline->device = device;
1518 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1519
1520 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1521 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1522 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1523 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1524 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1525 pStages[stage] = &pCreateInfo->pStages[i];
1526 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1527 }
1528
1529 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1530
1531 if (modules[MESA_SHADER_VERTEX]) {
1532 bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
1533 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
1534
1535 pipeline->shaders[MESA_SHADER_VERTEX] =
1536 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1537 pStages[MESA_SHADER_VERTEX]->pName,
1538 MESA_SHADER_VERTEX,
1539 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1540 pipeline->layout, &key);
1541
1542 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1543 }
1544
1545 if (modules[MESA_SHADER_GEOMETRY]) {
1546 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false);
1547
1548 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1549 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1550 pStages[MESA_SHADER_GEOMETRY]->pName,
1551 MESA_SHADER_GEOMETRY,
1552 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1553 pipeline->layout, &key);
1554
1555 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1556 calculate_gs_ring_sizes(pipeline);
1557 }
1558
1559 if (!modules[MESA_SHADER_FRAGMENT]) {
1560 nir_builder fs_b;
1561 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1562 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1563 fs_m.nir = fs_b.shader;
1564 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1565 }
1566
1567 if (modules[MESA_SHADER_FRAGMENT]) {
1568 union ac_shader_variant_key key;
1569 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1570 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1571
1572 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1573
1574 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1575 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1576 stage ? stage->pName : "main",
1577 MESA_SHADER_FRAGMENT,
1578 stage ? stage->pSpecializationInfo : NULL,
1579 pipeline->layout, &key);
1580 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1581 }
1582
1583 if (fs_m.nir)
1584 ralloc_free(fs_m.nir);
1585
1586 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1587 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1588 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1589 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1590 if (radv_pipeline_has_gs(pipeline)) {
1591 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1592 } else {
1593 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1594 }
1595 if (extra && extra->use_rectlist) {
1596 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1597 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1598 }
1599 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1600 /* prim vertex count will need TESS changes */
1601 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1602
1603 const VkPipelineVertexInputStateCreateInfo *vi_info =
1604 pCreateInfo->pVertexInputState;
1605 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1606 const VkVertexInputAttributeDescription *desc =
1607 &vi_info->pVertexAttributeDescriptions[i];
1608 unsigned loc = desc->location;
1609 const struct vk_format_description *format_desc;
1610 int first_non_void;
1611 uint32_t num_format, data_format;
1612 format_desc = vk_format_description(desc->format);
1613 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1614
1615 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1616 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1617
1618 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1619 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1620 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1621 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1622 S_008F0C_NUM_FORMAT(num_format) |
1623 S_008F0C_DATA_FORMAT(data_format);
1624 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1625 pipeline->va_offset[loc] = desc->offset;
1626 pipeline->va_binding[loc] = desc->binding;
1627 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1628 }
1629
1630 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1631 const VkVertexInputBindingDescription *desc =
1632 &vi_info->pVertexBindingDescriptions[i];
1633
1634 pipeline->binding_stride[desc->binding] = desc->stride;
1635 }
1636
1637 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1638 radv_dump_pipeline_stats(device, pipeline);
1639 }
1640
1641 result = radv_pipeline_scratch_init(device, pipeline);
1642 return result;
1643 }
1644
1645 VkResult
1646 radv_graphics_pipeline_create(
1647 VkDevice _device,
1648 VkPipelineCache _cache,
1649 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1650 const struct radv_graphics_pipeline_create_info *extra,
1651 const VkAllocationCallbacks *pAllocator,
1652 VkPipeline *pPipeline)
1653 {
1654 RADV_FROM_HANDLE(radv_device, device, _device);
1655 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1656 struct radv_pipeline *pipeline;
1657 VkResult result;
1658
1659 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1660 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1661 if (pipeline == NULL)
1662 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1663
1664 memset(pipeline, 0, sizeof(*pipeline));
1665 result = radv_pipeline_init(pipeline, device, cache,
1666 pCreateInfo, extra, pAllocator);
1667 if (result != VK_SUCCESS) {
1668 radv_pipeline_destroy(device, pipeline, pAllocator);
1669 return result;
1670 }
1671
1672 *pPipeline = radv_pipeline_to_handle(pipeline);
1673
1674 return VK_SUCCESS;
1675 }
1676
1677 VkResult radv_CreateGraphicsPipelines(
1678 VkDevice _device,
1679 VkPipelineCache pipelineCache,
1680 uint32_t count,
1681 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1682 const VkAllocationCallbacks* pAllocator,
1683 VkPipeline* pPipelines)
1684 {
1685 VkResult result = VK_SUCCESS;
1686 unsigned i = 0;
1687
1688 for (; i < count; i++) {
1689 VkResult r;
1690 r = radv_graphics_pipeline_create(_device,
1691 pipelineCache,
1692 &pCreateInfos[i],
1693 NULL, pAllocator, &pPipelines[i]);
1694 if (r != VK_SUCCESS) {
1695 result = r;
1696 pPipelines[i] = VK_NULL_HANDLE;
1697 }
1698 }
1699
1700 return result;
1701 }
1702
1703 static VkResult radv_compute_pipeline_create(
1704 VkDevice _device,
1705 VkPipelineCache _cache,
1706 const VkComputePipelineCreateInfo* pCreateInfo,
1707 const VkAllocationCallbacks* pAllocator,
1708 VkPipeline* pPipeline)
1709 {
1710 RADV_FROM_HANDLE(radv_device, device, _device);
1711 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1712 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1713 struct radv_pipeline *pipeline;
1714 VkResult result;
1715
1716 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1717 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1718 if (pipeline == NULL)
1719 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1720
1721 memset(pipeline, 0, sizeof(*pipeline));
1722 pipeline->device = device;
1723 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1724
1725 pipeline->shaders[MESA_SHADER_COMPUTE] =
1726 radv_pipeline_compile(pipeline, cache, module,
1727 pCreateInfo->stage.pName,
1728 MESA_SHADER_COMPUTE,
1729 pCreateInfo->stage.pSpecializationInfo,
1730 pipeline->layout, NULL);
1731
1732
1733 result = radv_pipeline_scratch_init(device, pipeline);
1734 if (result != VK_SUCCESS) {
1735 radv_pipeline_destroy(device, pipeline, pAllocator);
1736 return result;
1737 }
1738
1739 *pPipeline = radv_pipeline_to_handle(pipeline);
1740
1741 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1742 radv_dump_pipeline_stats(device, pipeline);
1743 }
1744 return VK_SUCCESS;
1745 }
1746 VkResult radv_CreateComputePipelines(
1747 VkDevice _device,
1748 VkPipelineCache pipelineCache,
1749 uint32_t count,
1750 const VkComputePipelineCreateInfo* pCreateInfos,
1751 const VkAllocationCallbacks* pAllocator,
1752 VkPipeline* pPipelines)
1753 {
1754 VkResult result = VK_SUCCESS;
1755
1756 unsigned i = 0;
1757 for (; i < count; i++) {
1758 VkResult r;
1759 r = radv_compute_pipeline_create(_device, pipelineCache,
1760 &pCreateInfos[i],
1761 pAllocator, &pPipelines[i]);
1762 if (r != VK_SUCCESS) {
1763 result = r;
1764 pPipelines[i] = VK_NULL_HANDLE;
1765 }
1766 }
1767
1768 return result;
1769 }