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radv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 struct radv_ngg_state {
101 uint16_t ngg_emit_size; /* in dwords */
102 uint32_t hw_max_esverts;
103 uint32_t max_gsprims;
104 uint32_t max_out_verts;
105 uint32_t prim_amp_factor;
106 uint32_t vgt_esgs_ring_itemsize;
107 bool max_vert_out_per_gs_instance;
108 };
109
110 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
111 {
112 struct radv_shader_variant *variant = NULL;
113 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
114 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
115 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
116 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
117 else if (pipeline->shaders[MESA_SHADER_VERTEX])
118 variant = pipeline->shaders[MESA_SHADER_VERTEX];
119 else
120 return false;
121 return variant->info.is_ngg;
122 }
123
124 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
125 {
126 if (!radv_pipeline_has_gs(pipeline))
127 return false;
128
129 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
130 * On GFX10, it might be required in rare cases if it's not possible to
131 * enable NGG.
132 */
133 if (radv_pipeline_has_ngg(pipeline))
134 return false;
135
136 assert(pipeline->gs_copy_shader);
137 return true;
138 }
139
140 static void
141 radv_pipeline_destroy(struct radv_device *device,
142 struct radv_pipeline *pipeline,
143 const VkAllocationCallbacks* allocator)
144 {
145 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
146 if (pipeline->shaders[i])
147 radv_shader_variant_destroy(device, pipeline->shaders[i]);
148
149 if (pipeline->gs_copy_shader)
150 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
151
152 if(pipeline->cs.buf)
153 free(pipeline->cs.buf);
154 vk_free2(&device->alloc, allocator, pipeline);
155 }
156
157 void radv_DestroyPipeline(
158 VkDevice _device,
159 VkPipeline _pipeline,
160 const VkAllocationCallbacks* pAllocator)
161 {
162 RADV_FROM_HANDLE(radv_device, device, _device);
163 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
164
165 if (!_pipeline)
166 return;
167
168 radv_pipeline_destroy(device, pipeline, pAllocator);
169 }
170
171 static uint32_t get_hash_flags(struct radv_device *device)
172 {
173 uint32_t hash_flags = 0;
174
175 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
176 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
177 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
178 hash_flags |= RADV_HASH_SHADER_NO_NGG;
179 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
180 hash_flags |= RADV_HASH_SHADER_SISCHED;
181 if (device->physical_device->cs_wave_size == 32)
182 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
183 if (device->physical_device->ps_wave_size == 32)
184 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
185 if (device->physical_device->ge_wave_size == 32)
186 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
187 return hash_flags;
188 }
189
190 static VkResult
191 radv_pipeline_scratch_init(struct radv_device *device,
192 struct radv_pipeline *pipeline)
193 {
194 unsigned scratch_bytes_per_wave = 0;
195 unsigned max_waves = 0;
196 unsigned min_waves = 1;
197
198 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
199 if (pipeline->shaders[i]) {
200 unsigned max_stage_waves = device->scratch_waves;
201
202 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
203 pipeline->shaders[i]->config.scratch_bytes_per_wave);
204
205 max_stage_waves = MIN2(max_stage_waves,
206 4 * device->physical_device->rad_info.num_good_compute_units *
207 (256 / pipeline->shaders[i]->config.num_vgprs));
208 max_waves = MAX2(max_waves, max_stage_waves);
209 }
210 }
211
212 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
213 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
214 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
215 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
216 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
217 }
218
219 if (scratch_bytes_per_wave)
220 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
221
222 if (scratch_bytes_per_wave && max_waves < min_waves) {
223 /* Not really true at this moment, but will be true on first
224 * execution. Avoid having hanging shaders. */
225 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
226 }
227 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
228 pipeline->max_waves = max_waves;
229 return VK_SUCCESS;
230 }
231
232 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
233 {
234 switch (op) {
235 case VK_LOGIC_OP_CLEAR:
236 return V_028808_ROP3_CLEAR;
237 case VK_LOGIC_OP_AND:
238 return V_028808_ROP3_AND;
239 case VK_LOGIC_OP_AND_REVERSE:
240 return V_028808_ROP3_AND_REVERSE;
241 case VK_LOGIC_OP_COPY:
242 return V_028808_ROP3_COPY;
243 case VK_LOGIC_OP_AND_INVERTED:
244 return V_028808_ROP3_AND_INVERTED;
245 case VK_LOGIC_OP_NO_OP:
246 return V_028808_ROP3_NO_OP;
247 case VK_LOGIC_OP_XOR:
248 return V_028808_ROP3_XOR;
249 case VK_LOGIC_OP_OR:
250 return V_028808_ROP3_OR;
251 case VK_LOGIC_OP_NOR:
252 return V_028808_ROP3_NOR;
253 case VK_LOGIC_OP_EQUIVALENT:
254 return V_028808_ROP3_EQUIVALENT;
255 case VK_LOGIC_OP_INVERT:
256 return V_028808_ROP3_INVERT;
257 case VK_LOGIC_OP_OR_REVERSE:
258 return V_028808_ROP3_OR_REVERSE;
259 case VK_LOGIC_OP_COPY_INVERTED:
260 return V_028808_ROP3_COPY_INVERTED;
261 case VK_LOGIC_OP_OR_INVERTED:
262 return V_028808_ROP3_OR_INVERTED;
263 case VK_LOGIC_OP_NAND:
264 return V_028808_ROP3_NAND;
265 case VK_LOGIC_OP_SET:
266 return V_028808_ROP3_SET;
267 default:
268 unreachable("Unhandled logic op");
269 }
270 }
271
272
273 static uint32_t si_translate_blend_function(VkBlendOp op)
274 {
275 switch (op) {
276 case VK_BLEND_OP_ADD:
277 return V_028780_COMB_DST_PLUS_SRC;
278 case VK_BLEND_OP_SUBTRACT:
279 return V_028780_COMB_SRC_MINUS_DST;
280 case VK_BLEND_OP_REVERSE_SUBTRACT:
281 return V_028780_COMB_DST_MINUS_SRC;
282 case VK_BLEND_OP_MIN:
283 return V_028780_COMB_MIN_DST_SRC;
284 case VK_BLEND_OP_MAX:
285 return V_028780_COMB_MAX_DST_SRC;
286 default:
287 return 0;
288 }
289 }
290
291 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
292 {
293 switch (factor) {
294 case VK_BLEND_FACTOR_ZERO:
295 return V_028780_BLEND_ZERO;
296 case VK_BLEND_FACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case VK_BLEND_FACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
301 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
302 case VK_BLEND_FACTOR_DST_COLOR:
303 return V_028780_BLEND_DST_COLOR;
304 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
305 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
306 case VK_BLEND_FACTOR_SRC_ALPHA:
307 return V_028780_BLEND_SRC_ALPHA;
308 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
309 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
310 case VK_BLEND_FACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case VK_BLEND_FACTOR_CONSTANT_COLOR:
315 return V_028780_BLEND_CONSTANT_COLOR;
316 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case VK_BLEND_FACTOR_SRC1_COLOR:
325 return V_028780_BLEND_SRC1_COLOR;
326 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case VK_BLEND_FACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
331 return V_028780_BLEND_INV_SRC1_ALPHA;
332 default:
333 return 0;
334 }
335 }
336
337 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
338 {
339 switch (op) {
340 case VK_BLEND_OP_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case VK_BLEND_OP_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case VK_BLEND_OP_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case VK_BLEND_OP_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case VK_BLEND_OP_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
356 {
357 switch (factor) {
358 case VK_BLEND_FACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case VK_BLEND_FACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case VK_BLEND_FACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case VK_BLEND_FACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 /**
381 * Get rid of DST in the blend factors by commuting the operands:
382 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
383 */
384 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
385 unsigned *dst_factor, unsigned expected_dst,
386 unsigned replacement_src)
387 {
388 if (*src_factor == expected_dst &&
389 *dst_factor == VK_BLEND_FACTOR_ZERO) {
390 *src_factor = VK_BLEND_FACTOR_ZERO;
391 *dst_factor = replacement_src;
392
393 /* Commuting the operands requires reversing subtractions. */
394 if (*func == VK_BLEND_OP_SUBTRACT)
395 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
396 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
397 *func = VK_BLEND_OP_SUBTRACT;
398 }
399 }
400
401 static bool si_blend_factor_uses_dst(unsigned factor)
402 {
403 return factor == VK_BLEND_FACTOR_DST_COLOR ||
404 factor == VK_BLEND_FACTOR_DST_ALPHA ||
405 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
406 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
407 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
408 }
409
410 static bool is_dual_src(VkBlendFactor factor)
411 {
412 switch (factor) {
413 case VK_BLEND_FACTOR_SRC1_COLOR:
414 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
415 case VK_BLEND_FACTOR_SRC1_ALPHA:
416 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
417 return true;
418 default:
419 return false;
420 }
421 }
422
423 static unsigned si_choose_spi_color_format(VkFormat vk_format,
424 bool blend_enable,
425 bool blend_need_alpha)
426 {
427 const struct vk_format_description *desc = vk_format_description(vk_format);
428 unsigned format, ntype, swap;
429
430 /* Alpha is needed for alpha-to-coverage.
431 * Blending may be with or without alpha.
432 */
433 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
434 unsigned alpha = 0; /* exports alpha, but may not support blending */
435 unsigned blend = 0; /* supports blending, but may not export alpha */
436 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
437
438 format = radv_translate_colorformat(vk_format);
439 ntype = radv_translate_color_numformat(vk_format, desc,
440 vk_format_get_first_non_void_channel(vk_format));
441 swap = radv_translate_colorswap(vk_format, false);
442
443 /* Choose the SPI color formats. These are required values for Stoney/RB+.
444 * Other chips have multiple choices, though they are not necessarily better.
445 */
446 switch (format) {
447 case V_028C70_COLOR_5_6_5:
448 case V_028C70_COLOR_1_5_5_5:
449 case V_028C70_COLOR_5_5_5_1:
450 case V_028C70_COLOR_4_4_4_4:
451 case V_028C70_COLOR_10_11_11:
452 case V_028C70_COLOR_11_11_10:
453 case V_028C70_COLOR_8:
454 case V_028C70_COLOR_8_8:
455 case V_028C70_COLOR_8_8_8_8:
456 case V_028C70_COLOR_10_10_10_2:
457 case V_028C70_COLOR_2_10_10_10:
458 if (ntype == V_028C70_NUMBER_UINT)
459 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
460 else if (ntype == V_028C70_NUMBER_SINT)
461 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
462 else
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
464 break;
465
466 case V_028C70_COLOR_16:
467 case V_028C70_COLOR_16_16:
468 case V_028C70_COLOR_16_16_16_16:
469 if (ntype == V_028C70_NUMBER_UNORM ||
470 ntype == V_028C70_NUMBER_SNORM) {
471 /* UNORM16 and SNORM16 don't support blending */
472 if (ntype == V_028C70_NUMBER_UNORM)
473 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
474 else
475 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
476
477 /* Use 32 bits per channel for blending. */
478 if (format == V_028C70_COLOR_16) {
479 if (swap == V_028C70_SWAP_STD) { /* R */
480 blend = V_028714_SPI_SHADER_32_R;
481 blend_alpha = V_028714_SPI_SHADER_32_AR;
482 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
483 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
484 else
485 assert(0);
486 } else if (format == V_028C70_COLOR_16_16) {
487 if (swap == V_028C70_SWAP_STD) { /* RG */
488 blend = V_028714_SPI_SHADER_32_GR;
489 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
490 } else if (swap == V_028C70_SWAP_ALT) /* RA */
491 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
492 else
493 assert(0);
494 } else /* 16_16_16_16 */
495 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
496 } else if (ntype == V_028C70_NUMBER_UINT)
497 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
498 else if (ntype == V_028C70_NUMBER_SINT)
499 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
500 else if (ntype == V_028C70_NUMBER_FLOAT)
501 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
502 else
503 assert(0);
504 break;
505
506 case V_028C70_COLOR_32:
507 if (swap == V_028C70_SWAP_STD) { /* R */
508 blend = normal = V_028714_SPI_SHADER_32_R;
509 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
510 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
511 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
512 else
513 assert(0);
514 break;
515
516 case V_028C70_COLOR_32_32:
517 if (swap == V_028C70_SWAP_STD) { /* RG */
518 blend = normal = V_028714_SPI_SHADER_32_GR;
519 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
520 } else if (swap == V_028C70_SWAP_ALT) /* RA */
521 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
522 else
523 assert(0);
524 break;
525
526 case V_028C70_COLOR_32_32_32_32:
527 case V_028C70_COLOR_8_24:
528 case V_028C70_COLOR_24_8:
529 case V_028C70_COLOR_X24_8_32_FLOAT:
530 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
531 break;
532
533 default:
534 unreachable("unhandled blend format");
535 }
536
537 if (blend_enable && blend_need_alpha)
538 return blend_alpha;
539 else if(blend_need_alpha)
540 return alpha;
541 else if(blend_enable)
542 return blend;
543 else
544 return normal;
545 }
546
547 static void
548 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
549 const VkGraphicsPipelineCreateInfo *pCreateInfo,
550 struct radv_blend_state *blend)
551 {
552 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
553 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
554 unsigned col_format = 0;
555 unsigned num_targets;
556
557 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
558 unsigned cf;
559
560 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
561 cf = V_028714_SPI_SHADER_ZERO;
562 } else {
563 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
564 bool blend_enable =
565 blend->blend_enable_4bit & (0xfu << (i * 4));
566
567 cf = si_choose_spi_color_format(attachment->format,
568 blend_enable,
569 blend->need_src_alpha & (1 << i));
570 }
571
572 col_format |= cf << (4 * i);
573 }
574
575 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
576 /* When a subpass doesn't have any color attachments, write the
577 * alpha channel of MRT0 when alpha coverage is enabled because
578 * the depth attachment needs it.
579 */
580 col_format |= V_028714_SPI_SHADER_32_AR;
581 }
582
583 /* If the i-th target format is set, all previous target formats must
584 * be non-zero to avoid hangs.
585 */
586 num_targets = (util_last_bit(col_format) + 3) / 4;
587 for (unsigned i = 0; i < num_targets; i++) {
588 if (!(col_format & (0xf << (i * 4)))) {
589 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
590 }
591 }
592
593 /* The output for dual source blending should have the same format as
594 * the first output.
595 */
596 if (blend->mrt0_is_dual_src)
597 col_format |= (col_format & 0xf) << 4;
598
599 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
600 blend->spi_shader_col_format = col_format;
601 }
602
603 static bool
604 format_is_int8(VkFormat format)
605 {
606 const struct vk_format_description *desc = vk_format_description(format);
607 int channel = vk_format_get_first_non_void_channel(format);
608
609 return channel >= 0 && desc->channel[channel].pure_integer &&
610 desc->channel[channel].size == 8;
611 }
612
613 static bool
614 format_is_int10(VkFormat format)
615 {
616 const struct vk_format_description *desc = vk_format_description(format);
617
618 if (desc->nr_channels != 4)
619 return false;
620 for (unsigned i = 0; i < 4; i++) {
621 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
622 return true;
623 }
624 return false;
625 }
626
627 /*
628 * Ordered so that for each i,
629 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
630 */
631 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
632 VK_FORMAT_R32_SFLOAT,
633 VK_FORMAT_R32G32_SFLOAT,
634 VK_FORMAT_R8G8B8A8_UNORM,
635 VK_FORMAT_R16G16B16A16_UNORM,
636 VK_FORMAT_R16G16B16A16_SNORM,
637 VK_FORMAT_R16G16B16A16_UINT,
638 VK_FORMAT_R16G16B16A16_SINT,
639 VK_FORMAT_R32G32B32A32_SFLOAT,
640 VK_FORMAT_R8G8B8A8_UINT,
641 VK_FORMAT_R8G8B8A8_SINT,
642 VK_FORMAT_A2R10G10B10_UINT_PACK32,
643 VK_FORMAT_A2R10G10B10_SINT_PACK32,
644 };
645
646 unsigned radv_format_meta_fs_key(VkFormat format)
647 {
648 unsigned col_format = si_choose_spi_color_format(format, false, false);
649
650 assert(col_format != V_028714_SPI_SHADER_32_AR);
651 if (col_format >= V_028714_SPI_SHADER_32_AR)
652 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
653
654 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
655 bool is_int8 = format_is_int8(format);
656 bool is_int10 = format_is_int10(format);
657
658 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
659 }
660
661 static void
662 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
663 unsigned *is_int8, unsigned *is_int10)
664 {
665 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
666 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
667 *is_int8 = 0;
668 *is_int10 = 0;
669
670 for (unsigned i = 0; i < subpass->color_count; ++i) {
671 struct radv_render_pass_attachment *attachment;
672
673 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
674 continue;
675
676 attachment = pass->attachments + subpass->color_attachments[i].attachment;
677
678 if (format_is_int8(attachment->format))
679 *is_int8 |= 1 << i;
680 if (format_is_int10(attachment->format))
681 *is_int10 |= 1 << i;
682 }
683 }
684
685 static void
686 radv_blend_check_commutativity(struct radv_blend_state *blend,
687 VkBlendOp op, VkBlendFactor src,
688 VkBlendFactor dst, unsigned chanmask)
689 {
690 /* Src factor is allowed when it does not depend on Dst. */
691 static const uint32_t src_allowed =
692 (1u << VK_BLEND_FACTOR_ONE) |
693 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
694 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
695 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
696 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
697 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
698 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
699 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
700 (1u << VK_BLEND_FACTOR_ZERO) |
701 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
702 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
703 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
704 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
705 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
706 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
707
708 if (dst == VK_BLEND_FACTOR_ONE &&
709 (src_allowed & (1u << src))) {
710 /* Addition is commutative, but floating point addition isn't
711 * associative: subtle changes can be introduced via different
712 * rounding. Be conservative, only enable for min and max.
713 */
714 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
715 blend->commutative_4bit |= chanmask;
716 }
717 }
718
719 static struct radv_blend_state
720 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
721 const VkGraphicsPipelineCreateInfo *pCreateInfo,
722 const struct radv_graphics_pipeline_create_info *extra)
723 {
724 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
725 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
726 struct radv_blend_state blend = {0};
727 unsigned mode = V_028808_CB_NORMAL;
728 int i;
729
730 if (!vkblend)
731 return blend;
732
733 if (extra && extra->custom_blend_mode) {
734 blend.single_cb_enable = true;
735 mode = extra->custom_blend_mode;
736 }
737 blend.cb_color_control = 0;
738 if (vkblend->logicOpEnable)
739 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
740 else
741 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
742
743 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
744 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
745 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
746 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
747 S_028B70_OFFSET_ROUND(1);
748
749 if (vkms && vkms->alphaToCoverageEnable) {
750 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
751 blend.need_src_alpha |= 0x1;
752 }
753
754 blend.cb_target_mask = 0;
755 for (i = 0; i < vkblend->attachmentCount; i++) {
756 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
757 unsigned blend_cntl = 0;
758 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
759 VkBlendOp eqRGB = att->colorBlendOp;
760 VkBlendFactor srcRGB = att->srcColorBlendFactor;
761 VkBlendFactor dstRGB = att->dstColorBlendFactor;
762 VkBlendOp eqA = att->alphaBlendOp;
763 VkBlendFactor srcA = att->srcAlphaBlendFactor;
764 VkBlendFactor dstA = att->dstAlphaBlendFactor;
765
766 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
767
768 if (!att->colorWriteMask)
769 continue;
770
771 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
772 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
773 if (!att->blendEnable) {
774 blend.cb_blend_control[i] = blend_cntl;
775 continue;
776 }
777
778 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
779 if (i == 0)
780 blend.mrt0_is_dual_src = true;
781
782 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
783 srcRGB = VK_BLEND_FACTOR_ONE;
784 dstRGB = VK_BLEND_FACTOR_ONE;
785 }
786 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
787 srcA = VK_BLEND_FACTOR_ONE;
788 dstA = VK_BLEND_FACTOR_ONE;
789 }
790
791 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
792 0x7 << (4 * i));
793 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
794 0x8 << (4 * i));
795
796 /* Blending optimizations for RB+.
797 * These transformations don't change the behavior.
798 *
799 * First, get rid of DST in the blend factors:
800 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
801 */
802 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
803 VK_BLEND_FACTOR_DST_COLOR,
804 VK_BLEND_FACTOR_SRC_COLOR);
805
806 si_blend_remove_dst(&eqA, &srcA, &dstA,
807 VK_BLEND_FACTOR_DST_COLOR,
808 VK_BLEND_FACTOR_SRC_COLOR);
809
810 si_blend_remove_dst(&eqA, &srcA, &dstA,
811 VK_BLEND_FACTOR_DST_ALPHA,
812 VK_BLEND_FACTOR_SRC_ALPHA);
813
814 /* Look up the ideal settings from tables. */
815 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
816 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
817 srcA_opt = si_translate_blend_opt_factor(srcA, true);
818 dstA_opt = si_translate_blend_opt_factor(dstA, true);
819
820 /* Handle interdependencies. */
821 if (si_blend_factor_uses_dst(srcRGB))
822 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
823 if (si_blend_factor_uses_dst(srcA))
824 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
825
826 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
827 (dstRGB == VK_BLEND_FACTOR_ZERO ||
828 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
829 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
830 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
831
832 /* Set the final value. */
833 blend.sx_mrt_blend_opt[i] =
834 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
835 S_028760_COLOR_DST_OPT(dstRGB_opt) |
836 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
837 S_028760_ALPHA_SRC_OPT(srcA_opt) |
838 S_028760_ALPHA_DST_OPT(dstA_opt) |
839 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
840 blend_cntl |= S_028780_ENABLE(1);
841
842 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
843 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
844 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
845 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
846 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
847 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
848 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
849 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
850 }
851 blend.cb_blend_control[i] = blend_cntl;
852
853 blend.blend_enable_4bit |= 0xfu << (i * 4);
854
855 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
856 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
857 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
858 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
859 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
860 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
861 blend.need_src_alpha |= 1 << i;
862 }
863 for (i = vkblend->attachmentCount; i < 8; i++) {
864 blend.cb_blend_control[i] = 0;
865 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
866 }
867
868 if (pipeline->device->physical_device->has_rbplus) {
869 /* Disable RB+ blend optimizations for dual source blending. */
870 if (blend.mrt0_is_dual_src) {
871 for (i = 0; i < 8; i++) {
872 blend.sx_mrt_blend_opt[i] =
873 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
874 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
875 }
876 }
877
878 /* RB+ doesn't work with dual source blending, logic op and
879 * RESOLVE.
880 */
881 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
882 mode == V_028808_CB_RESOLVE)
883 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
884 }
885
886 if (blend.cb_target_mask)
887 blend.cb_color_control |= S_028808_MODE(mode);
888 else
889 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
890
891 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
892 return blend;
893 }
894
895 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
896 {
897 switch (op) {
898 case VK_STENCIL_OP_KEEP:
899 return V_02842C_STENCIL_KEEP;
900 case VK_STENCIL_OP_ZERO:
901 return V_02842C_STENCIL_ZERO;
902 case VK_STENCIL_OP_REPLACE:
903 return V_02842C_STENCIL_REPLACE_TEST;
904 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
905 return V_02842C_STENCIL_ADD_CLAMP;
906 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
907 return V_02842C_STENCIL_SUB_CLAMP;
908 case VK_STENCIL_OP_INVERT:
909 return V_02842C_STENCIL_INVERT;
910 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
911 return V_02842C_STENCIL_ADD_WRAP;
912 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
913 return V_02842C_STENCIL_SUB_WRAP;
914 default:
915 return 0;
916 }
917 }
918
919 static uint32_t si_translate_fill(VkPolygonMode func)
920 {
921 switch(func) {
922 case VK_POLYGON_MODE_FILL:
923 return V_028814_X_DRAW_TRIANGLES;
924 case VK_POLYGON_MODE_LINE:
925 return V_028814_X_DRAW_LINES;
926 case VK_POLYGON_MODE_POINT:
927 return V_028814_X_DRAW_POINTS;
928 default:
929 assert(0);
930 return V_028814_X_DRAW_POINTS;
931 }
932 }
933
934 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
935 {
936 uint32_t num_samples = vkms->rasterizationSamples;
937 uint32_t ps_iter_samples = 1;
938
939 if (vkms->sampleShadingEnable) {
940 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
941 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
942 }
943 return ps_iter_samples;
944 }
945
946 static bool
947 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
948 {
949 return pCreateInfo->depthTestEnable &&
950 pCreateInfo->depthWriteEnable &&
951 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
952 }
953
954 static bool
955 radv_writes_stencil(const VkStencilOpState *state)
956 {
957 return state->writeMask &&
958 (state->failOp != VK_STENCIL_OP_KEEP ||
959 state->passOp != VK_STENCIL_OP_KEEP ||
960 state->depthFailOp != VK_STENCIL_OP_KEEP);
961 }
962
963 static bool
964 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
965 {
966 return pCreateInfo->stencilTestEnable &&
967 (radv_writes_stencil(&pCreateInfo->front) ||
968 radv_writes_stencil(&pCreateInfo->back));
969 }
970
971 static bool
972 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
973 {
974 return radv_is_depth_write_enabled(pCreateInfo) ||
975 radv_is_stencil_write_enabled(pCreateInfo);
976 }
977
978 static bool
979 radv_order_invariant_stencil_op(VkStencilOp op)
980 {
981 /* REPLACE is normally order invariant, except when the stencil
982 * reference value is written by the fragment shader. Tracking this
983 * interaction does not seem worth the effort, so be conservative.
984 */
985 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
986 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
987 op != VK_STENCIL_OP_REPLACE;
988 }
989
990 static bool
991 radv_order_invariant_stencil_state(const VkStencilOpState *state)
992 {
993 /* Compute whether, assuming Z writes are disabled, this stencil state
994 * is order invariant in the sense that the set of passing fragments as
995 * well as the final stencil buffer result does not depend on the order
996 * of fragments.
997 */
998 return !state->writeMask ||
999 /* The following assumes that Z writes are disabled. */
1000 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
1001 radv_order_invariant_stencil_op(state->passOp) &&
1002 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1003 (state->compareOp == VK_COMPARE_OP_NEVER &&
1004 radv_order_invariant_stencil_op(state->failOp));
1005 }
1006
1007 static bool
1008 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1009 struct radv_blend_state *blend,
1010 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1011 {
1012 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1013 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1014 unsigned colormask = blend->cb_target_enabled_4bit;
1015
1016 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1017 return false;
1018
1019 /* Be conservative if a logic operation is enabled with color buffers. */
1020 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1021 return false;
1022
1023 /* Default depth/stencil invariance when no attachment is bound. */
1024 struct radv_dsa_order_invariance dsa_order_invariant = {
1025 .zs = true, .pass_set = true
1026 };
1027
1028 if (pCreateInfo->pDepthStencilState &&
1029 subpass->depth_stencil_attachment) {
1030 const VkPipelineDepthStencilStateCreateInfo *vkds =
1031 pCreateInfo->pDepthStencilState;
1032 struct radv_render_pass_attachment *attachment =
1033 pass->attachments + subpass->depth_stencil_attachment->attachment;
1034 bool has_stencil = vk_format_is_stencil(attachment->format);
1035 struct radv_dsa_order_invariance order_invariance[2];
1036 struct radv_shader_variant *ps =
1037 pipeline->shaders[MESA_SHADER_FRAGMENT];
1038
1039 /* Compute depth/stencil order invariance in order to know if
1040 * it's safe to enable out-of-order.
1041 */
1042 bool zfunc_is_ordered =
1043 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1044 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1045 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1046 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1047 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1048
1049 bool nozwrite_and_order_invariant_stencil =
1050 !radv_is_ds_write_enabled(vkds) ||
1051 (!radv_is_depth_write_enabled(vkds) &&
1052 radv_order_invariant_stencil_state(&vkds->front) &&
1053 radv_order_invariant_stencil_state(&vkds->back));
1054
1055 order_invariance[1].zs =
1056 nozwrite_and_order_invariant_stencil ||
1057 (!radv_is_stencil_write_enabled(vkds) &&
1058 zfunc_is_ordered);
1059 order_invariance[0].zs =
1060 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1061
1062 order_invariance[1].pass_set =
1063 nozwrite_and_order_invariant_stencil ||
1064 (!radv_is_stencil_write_enabled(vkds) &&
1065 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1066 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1067 order_invariance[0].pass_set =
1068 !radv_is_depth_write_enabled(vkds) ||
1069 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1070 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1071
1072 dsa_order_invariant = order_invariance[has_stencil];
1073 if (!dsa_order_invariant.zs)
1074 return false;
1075
1076 /* The set of PS invocations is always order invariant,
1077 * except when early Z/S tests are requested.
1078 */
1079 if (ps &&
1080 ps->info.info.ps.writes_memory &&
1081 ps->info.fs.early_fragment_test &&
1082 !dsa_order_invariant.pass_set)
1083 return false;
1084
1085 /* Determine if out-of-order rasterization should be disabled
1086 * when occlusion queries are used.
1087 */
1088 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1089 !dsa_order_invariant.pass_set;
1090 }
1091
1092 /* No color buffers are enabled for writing. */
1093 if (!colormask)
1094 return true;
1095
1096 unsigned blendmask = colormask & blend->blend_enable_4bit;
1097
1098 if (blendmask) {
1099 /* Only commutative blending. */
1100 if (blendmask & ~blend->commutative_4bit)
1101 return false;
1102
1103 if (!dsa_order_invariant.pass_set)
1104 return false;
1105 }
1106
1107 if (colormask & ~blendmask)
1108 return false;
1109
1110 return true;
1111 }
1112
1113 static void
1114 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1115 struct radv_blend_state *blend,
1116 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1117 {
1118 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1119 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1120 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1121 bool out_of_order_rast = false;
1122 int ps_iter_samples = 1;
1123 uint32_t mask = 0xffff;
1124
1125 if (vkms)
1126 ms->num_samples = vkms->rasterizationSamples;
1127 else
1128 ms->num_samples = 1;
1129
1130 if (vkms)
1131 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1132 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1133 ps_iter_samples = ms->num_samples;
1134 }
1135
1136 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1137 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1138 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1139 /* Out-of-order rasterization is explicitly enabled by the
1140 * application.
1141 */
1142 out_of_order_rast = true;
1143 } else {
1144 /* Determine if the driver can enable out-of-order
1145 * rasterization internally.
1146 */
1147 out_of_order_rast =
1148 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1149 }
1150
1151 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1152 ms->pa_sc_aa_config = 0;
1153 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1154 S_028804_INCOHERENT_EQAA_READS(1) |
1155 S_028804_INTERPOLATE_COMP_Z(1) |
1156 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1157 ms->pa_sc_mode_cntl_1 =
1158 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1159 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1160 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1161 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1162 /* always 1: */
1163 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1164 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1165 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1166 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1167 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1168 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1169 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1170 S_028A48_VPORT_SCISSOR_ENABLE(1);
1171
1172 if (ms->num_samples > 1) {
1173 unsigned log_samples = util_logbase2(ms->num_samples);
1174 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1175 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1176 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1177 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1178 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1179 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1180 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1181 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1182 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1183 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1184 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1185 if (ps_iter_samples > 1)
1186 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1187 }
1188
1189 if (vkms && vkms->pSampleMask) {
1190 mask = vkms->pSampleMask[0] & 0xffff;
1191 }
1192
1193 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1194 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1195 }
1196
1197 static bool
1198 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1199 {
1200 switch (topology) {
1201 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1204 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1206 return false;
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1208 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1209 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1210 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1211 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1212 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1213 return true;
1214 default:
1215 unreachable("unhandled primitive type");
1216 }
1217 }
1218
1219 static uint32_t
1220 si_translate_prim(enum VkPrimitiveTopology topology)
1221 {
1222 switch (topology) {
1223 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1224 return V_008958_DI_PT_POINTLIST;
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1226 return V_008958_DI_PT_LINELIST;
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1228 return V_008958_DI_PT_LINESTRIP;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1230 return V_008958_DI_PT_TRILIST;
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1232 return V_008958_DI_PT_TRISTRIP;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1234 return V_008958_DI_PT_TRIFAN;
1235 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1236 return V_008958_DI_PT_LINELIST_ADJ;
1237 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1238 return V_008958_DI_PT_LINESTRIP_ADJ;
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1240 return V_008958_DI_PT_TRILIST_ADJ;
1241 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1242 return V_008958_DI_PT_TRISTRIP_ADJ;
1243 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1244 return V_008958_DI_PT_PATCH;
1245 default:
1246 assert(0);
1247 return 0;
1248 }
1249 }
1250
1251 static uint32_t
1252 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1253 {
1254 switch (gl_prim) {
1255 case 0: /* GL_POINTS */
1256 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1257 case 1: /* GL_LINES */
1258 case 3: /* GL_LINE_STRIP */
1259 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1260 case 0x8E7A: /* GL_ISOLINES */
1261 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1262
1263 case 4: /* GL_TRIANGLES */
1264 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1265 case 5: /* GL_TRIANGLE_STRIP */
1266 case 7: /* GL_QUADS */
1267 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1268 default:
1269 assert(0);
1270 return 0;
1271 }
1272 }
1273
1274 static uint32_t
1275 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1276 {
1277 switch (topology) {
1278 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1279 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1280 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1281 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1282 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1283 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1284 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1285 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1286 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1287 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1288 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1289 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1290 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1291 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1292 default:
1293 assert(0);
1294 return 0;
1295 }
1296 }
1297
1298 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1299 {
1300 switch(state) {
1301 case VK_DYNAMIC_STATE_VIEWPORT:
1302 return RADV_DYNAMIC_VIEWPORT;
1303 case VK_DYNAMIC_STATE_SCISSOR:
1304 return RADV_DYNAMIC_SCISSOR;
1305 case VK_DYNAMIC_STATE_LINE_WIDTH:
1306 return RADV_DYNAMIC_LINE_WIDTH;
1307 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1308 return RADV_DYNAMIC_DEPTH_BIAS;
1309 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1310 return RADV_DYNAMIC_BLEND_CONSTANTS;
1311 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1312 return RADV_DYNAMIC_DEPTH_BOUNDS;
1313 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1314 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1315 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1316 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1317 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1318 return RADV_DYNAMIC_STENCIL_REFERENCE;
1319 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1320 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1321 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1322 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1323 default:
1324 unreachable("Unhandled dynamic state");
1325 }
1326 }
1327
1328 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1329 {
1330 uint32_t states = RADV_DYNAMIC_ALL;
1331
1332 /* If rasterization is disabled we do not care about any of the dynamic states,
1333 * since they are all rasterization related only. */
1334 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1335 return 0;
1336
1337 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1338 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1339
1340 if (!pCreateInfo->pDepthStencilState ||
1341 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1342 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1343
1344 if (!pCreateInfo->pDepthStencilState ||
1345 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1346 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1347 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1348 RADV_DYNAMIC_STENCIL_REFERENCE);
1349
1350 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1351 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1352
1353 if (!pCreateInfo->pMultisampleState ||
1354 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1355 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1356 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1357
1358 /* TODO: blend constants & line width. */
1359
1360 return states;
1361 }
1362
1363
1364 static void
1365 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1366 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1367 {
1368 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1369 uint32_t states = needed_states;
1370 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1371 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1372
1373 pipeline->dynamic_state = default_dynamic_state;
1374 pipeline->graphics.needed_dynamic_state = needed_states;
1375
1376 if (pCreateInfo->pDynamicState) {
1377 /* Remove all of the states that are marked as dynamic */
1378 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1379 for (uint32_t s = 0; s < count; s++)
1380 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1381 }
1382
1383 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1384
1385 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1386 assert(pCreateInfo->pViewportState);
1387
1388 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1389 if (states & RADV_DYNAMIC_VIEWPORT) {
1390 typed_memcpy(dynamic->viewport.viewports,
1391 pCreateInfo->pViewportState->pViewports,
1392 pCreateInfo->pViewportState->viewportCount);
1393 }
1394 }
1395
1396 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1397 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1398 if (states & RADV_DYNAMIC_SCISSOR) {
1399 typed_memcpy(dynamic->scissor.scissors,
1400 pCreateInfo->pViewportState->pScissors,
1401 pCreateInfo->pViewportState->scissorCount);
1402 }
1403 }
1404
1405 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1406 assert(pCreateInfo->pRasterizationState);
1407 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1408 }
1409
1410 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1411 assert(pCreateInfo->pRasterizationState);
1412 dynamic->depth_bias.bias =
1413 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1414 dynamic->depth_bias.clamp =
1415 pCreateInfo->pRasterizationState->depthBiasClamp;
1416 dynamic->depth_bias.slope =
1417 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1418 }
1419
1420 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1421 *
1422 * pColorBlendState is [...] NULL if the pipeline has rasterization
1423 * disabled or if the subpass of the render pass the pipeline is
1424 * created against does not use any color attachments.
1425 */
1426 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1427 assert(pCreateInfo->pColorBlendState);
1428 typed_memcpy(dynamic->blend_constants,
1429 pCreateInfo->pColorBlendState->blendConstants, 4);
1430 }
1431
1432 /* If there is no depthstencil attachment, then don't read
1433 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1434 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1435 * no need to override the depthstencil defaults in
1436 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1437 *
1438 * Section 9.2 of the Vulkan 1.0.15 spec says:
1439 *
1440 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1441 * disabled or if the subpass of the render pass the pipeline is created
1442 * against does not use a depth/stencil attachment.
1443 */
1444 if (needed_states && subpass->depth_stencil_attachment) {
1445 assert(pCreateInfo->pDepthStencilState);
1446
1447 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1448 dynamic->depth_bounds.min =
1449 pCreateInfo->pDepthStencilState->minDepthBounds;
1450 dynamic->depth_bounds.max =
1451 pCreateInfo->pDepthStencilState->maxDepthBounds;
1452 }
1453
1454 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1455 dynamic->stencil_compare_mask.front =
1456 pCreateInfo->pDepthStencilState->front.compareMask;
1457 dynamic->stencil_compare_mask.back =
1458 pCreateInfo->pDepthStencilState->back.compareMask;
1459 }
1460
1461 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1462 dynamic->stencil_write_mask.front =
1463 pCreateInfo->pDepthStencilState->front.writeMask;
1464 dynamic->stencil_write_mask.back =
1465 pCreateInfo->pDepthStencilState->back.writeMask;
1466 }
1467
1468 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1469 dynamic->stencil_reference.front =
1470 pCreateInfo->pDepthStencilState->front.reference;
1471 dynamic->stencil_reference.back =
1472 pCreateInfo->pDepthStencilState->back.reference;
1473 }
1474 }
1475
1476 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1477 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1478 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1479 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1480 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1481 typed_memcpy(dynamic->discard_rectangle.rectangles,
1482 discard_rectangle_info->pDiscardRectangles,
1483 discard_rectangle_info->discardRectangleCount);
1484 }
1485 }
1486
1487 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1488 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1489 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1490 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1491 /* If sampleLocationsEnable is VK_FALSE, the default sample
1492 * locations are used and the values specified in
1493 * sampleLocationsInfo are ignored.
1494 */
1495 if (sample_location_info->sampleLocationsEnable) {
1496 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1497 &sample_location_info->sampleLocationsInfo;
1498
1499 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1500
1501 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1502 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1503 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1504 typed_memcpy(&dynamic->sample_location.locations[0],
1505 pSampleLocationsInfo->pSampleLocations,
1506 pSampleLocationsInfo->sampleLocationsCount);
1507 }
1508 }
1509
1510 pipeline->dynamic_state.mask = states;
1511 }
1512
1513 static struct radv_gs_state
1514 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1515 const struct radv_pipeline *pipeline)
1516 {
1517 struct radv_gs_state gs = {0};
1518 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1519 struct radv_es_output_info *es_info;
1520 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1521 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1522 else
1523 es_info = radv_pipeline_has_tess(pipeline) ?
1524 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1525 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1526
1527 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1528 bool uses_adjacency;
1529 switch(pCreateInfo->pInputAssemblyState->topology) {
1530 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1531 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1532 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1533 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1534 uses_adjacency = true;
1535 break;
1536 default:
1537 uses_adjacency = false;
1538 break;
1539 }
1540
1541 /* All these are in dwords: */
1542 /* We can't allow using the whole LDS, because GS waves compete with
1543 * other shader stages for LDS space. */
1544 const unsigned max_lds_size = 8 * 1024;
1545 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1546 unsigned esgs_lds_size;
1547
1548 /* All these are per subgroup: */
1549 const unsigned max_out_prims = 32 * 1024;
1550 const unsigned max_es_verts = 255;
1551 const unsigned ideal_gs_prims = 64;
1552 unsigned max_gs_prims, gs_prims;
1553 unsigned min_es_verts, es_verts, worst_case_es_verts;
1554
1555 if (uses_adjacency || gs_num_invocations > 1)
1556 max_gs_prims = 127 / gs_num_invocations;
1557 else
1558 max_gs_prims = 255;
1559
1560 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1561 * Make sure we don't go over the maximum value.
1562 */
1563 if (gs_info->gs.vertices_out > 0) {
1564 max_gs_prims = MIN2(max_gs_prims,
1565 max_out_prims /
1566 (gs_info->gs.vertices_out * gs_num_invocations));
1567 }
1568 assert(max_gs_prims > 0);
1569
1570 /* If the primitive has adjacency, halve the number of vertices
1571 * that will be reused in multiple primitives.
1572 */
1573 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1574
1575 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1576 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1577
1578 /* Compute ESGS LDS size based on the worst case number of ES vertices
1579 * needed to create the target number of GS prims per subgroup.
1580 */
1581 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1582
1583 /* If total LDS usage is too big, refactor partitions based on ratio
1584 * of ESGS item sizes.
1585 */
1586 if (esgs_lds_size > max_lds_size) {
1587 /* Our target GS Prims Per Subgroup was too large. Calculate
1588 * the maximum number of GS Prims Per Subgroup that will fit
1589 * into LDS, capped by the maximum that the hardware can support.
1590 */
1591 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1592 max_gs_prims);
1593 assert(gs_prims > 0);
1594 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1595 max_es_verts);
1596
1597 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1598 assert(esgs_lds_size <= max_lds_size);
1599 }
1600
1601 /* Now calculate remaining ESGS information. */
1602 if (esgs_lds_size)
1603 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1604 else
1605 es_verts = max_es_verts;
1606
1607 /* Vertices for adjacency primitives are not always reused, so restore
1608 * it for ES_VERTS_PER_SUBGRP.
1609 */
1610 min_es_verts = gs_info->gs.vertices_in;
1611
1612 /* For normal primitives, the VGT only checks if they are past the ES
1613 * verts per subgroup after allocating a full GS primitive and if they
1614 * are, kick off a new subgroup. But if those additional ES verts are
1615 * unique (e.g. not reused) we need to make sure there is enough LDS
1616 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1617 */
1618 es_verts -= min_es_verts - 1;
1619
1620 uint32_t es_verts_per_subgroup = es_verts;
1621 uint32_t gs_prims_per_subgroup = gs_prims;
1622 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1623 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1624 gs.lds_size = align(esgs_lds_size, 128) / 128;
1625 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1626 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1627 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1628 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1629 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1630 assert(max_prims_per_subgroup <= max_out_prims);
1631
1632 return gs;
1633 }
1634
1635 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1636 unsigned min_verts_per_prim, bool use_adjacency)
1637 {
1638 unsigned max_reuse = max_esverts - min_verts_per_prim;
1639 if (use_adjacency)
1640 max_reuse /= 2;
1641 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1642 }
1643
1644 static unsigned
1645 radv_get_num_input_vertices(struct radv_pipeline *pipeline)
1646 {
1647 if (radv_pipeline_has_gs(pipeline)) {
1648 struct radv_shader_variant *gs =
1649 radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
1650
1651 return gs->info.gs.vertices_in;
1652 }
1653
1654 if (radv_pipeline_has_tess(pipeline)) {
1655 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1656
1657 if (tes->info.tes.point_mode)
1658 return 1;
1659 if (tes->info.tes.primitive_mode == GL_ISOLINES)
1660 return 2;
1661 return 3;
1662 }
1663
1664 return 3;
1665 }
1666
1667 static struct radv_ngg_state
1668 calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1669 struct radv_pipeline *pipeline)
1670 {
1671 struct radv_ngg_state ngg = {0};
1672 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1673 struct radv_es_output_info *es_info =
1674 radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1675 unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1676 unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
1677 unsigned min_verts_per_prim =
1678 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1679 unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1;
1680 bool uses_adjacency;
1681 switch(pCreateInfo->pInputAssemblyState->topology) {
1682 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1683 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1684 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1685 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1686 uses_adjacency = true;
1687 break;
1688 default:
1689 uses_adjacency = false;
1690 break;
1691 }
1692
1693 /* All these are in dwords: */
1694 /* We can't allow using the whole LDS, because GS waves compete with
1695 * other shader stages for LDS space.
1696 *
1697 * Streamout can increase the ESGS buffer size later on, so be more
1698 * conservative with streamout and use 4K dwords. This may be suboptimal.
1699 *
1700 * Otherwise, use the limit of 7K dwords. The reason is that we need
1701 * to leave some headroom for the max_esverts increase at the end.
1702 *
1703 * TODO: We should really take the shader's internal LDS use into
1704 * account. The linker will fail if the size is greater than
1705 * 8K dwords.
1706 */
1707 const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1708 const unsigned target_lds_size = max_lds_size;
1709 unsigned esvert_lds_size = 0;
1710 unsigned gsprim_lds_size = 0;
1711
1712 /* All these are per subgroup: */
1713 bool max_vert_out_per_gs_instance = false;
1714 unsigned max_esverts_base = 256;
1715 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1716
1717 /* Hardware has the following non-natural restrictions on the value
1718 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1719 * the draw:
1720 * - at most 252 for any line input primitive type
1721 * - at most 251 for any quad input primitive type
1722 * - at most 251 for triangle strips with adjacency (this happens to
1723 * be the natural limit for triangle *lists* with adjacency)
1724 */
1725 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1726
1727 if (gs_type == MESA_SHADER_GEOMETRY) {
1728 unsigned max_out_verts_per_gsprim =
1729 gs_info->gs.vertices_out * gs_num_invocations;
1730
1731 if (max_out_verts_per_gsprim <= 256) {
1732 if (max_out_verts_per_gsprim) {
1733 max_gsprims_base = MIN2(max_gsprims_base,
1734 256 / max_out_verts_per_gsprim);
1735 }
1736 } else {
1737 /* Use special multi-cycling mode in which each GS
1738 * instance gets its own subgroup. Does not work with
1739 * tessellation. */
1740 max_vert_out_per_gs_instance = true;
1741 max_gsprims_base = 1;
1742 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1743 }
1744
1745 esvert_lds_size = es_info->esgs_itemsize / 4;
1746 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1747 } else {
1748 /* TODO: This needs to be adjusted once LDS use for compaction
1749 * after culling is implemented. */
1750 /*
1751 if (es_info->info.so.num_outputs)
1752 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1753 */
1754 }
1755
1756 unsigned max_gsprims = max_gsprims_base;
1757 unsigned max_esverts = max_esverts_base;
1758
1759 if (esvert_lds_size)
1760 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1761 if (gsprim_lds_size)
1762 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1763
1764 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1765 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1766 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1767
1768 if (esvert_lds_size || gsprim_lds_size) {
1769 /* Now that we have a rough proportionality between esverts
1770 * and gsprims based on the primitive type, scale both of them
1771 * down simultaneously based on required LDS space.
1772 *
1773 * We could be smarter about this if we knew how much vertex
1774 * reuse to expect.
1775 */
1776 unsigned lds_total = max_esverts * esvert_lds_size +
1777 max_gsprims * gsprim_lds_size;
1778 if (lds_total > target_lds_size) {
1779 max_esverts = max_esverts * target_lds_size / lds_total;
1780 max_gsprims = max_gsprims * target_lds_size / lds_total;
1781
1782 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1783 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1784 min_verts_per_prim, uses_adjacency);
1785 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1786 }
1787 }
1788
1789 /* Round up towards full wave sizes for better ALU utilization. */
1790 if (!max_vert_out_per_gs_instance) {
1791 const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
1792 unsigned orig_max_esverts;
1793 unsigned orig_max_gsprims;
1794 do {
1795 orig_max_esverts = max_esverts;
1796 orig_max_gsprims = max_gsprims;
1797
1798 max_esverts = align(max_esverts, wavesize);
1799 max_esverts = MIN2(max_esverts, max_esverts_base);
1800 if (esvert_lds_size)
1801 max_esverts = MIN2(max_esverts,
1802 (max_lds_size - max_gsprims * gsprim_lds_size) /
1803 esvert_lds_size);
1804 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1805
1806 max_gsprims = align(max_gsprims, wavesize);
1807 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1808 if (gsprim_lds_size)
1809 max_gsprims = MIN2(max_gsprims,
1810 (max_lds_size - max_esverts * esvert_lds_size) /
1811 gsprim_lds_size);
1812 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1813 min_verts_per_prim, uses_adjacency);
1814 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1815 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1816 }
1817
1818 /* Hardware restriction: minimum value of max_esverts */
1819 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1820
1821 unsigned max_out_vertices =
1822 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1823 gs_type == MESA_SHADER_GEOMETRY ?
1824 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1825 max_esverts;
1826 assert(max_out_vertices <= 256);
1827
1828 unsigned prim_amp_factor = 1;
1829 if (gs_type == MESA_SHADER_GEOMETRY) {
1830 /* Number of output primitives per GS input primitive after
1831 * GS instancing. */
1832 prim_amp_factor = gs_info->gs.vertices_out;
1833 }
1834
1835 /* The GE only checks against the maximum number of ES verts after
1836 * allocating a full GS primitive. So we need to ensure that whenever
1837 * this check passes, there is enough space for a full primitive without
1838 * vertex reuse.
1839 */
1840 ngg.hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1841 ngg.max_gsprims = max_gsprims;
1842 ngg.max_out_verts = max_out_vertices;
1843 ngg.prim_amp_factor = prim_amp_factor;
1844 ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1845 ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
1846
1847 if (gs_type == MESA_SHADER_GEOMETRY) {
1848 ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1849 } else {
1850 ngg.vgt_esgs_ring_itemsize = 1;
1851 }
1852
1853 pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1854
1855 assert(ngg.hw_max_esverts >= 24); /* HW limitation */
1856
1857 return ngg;
1858 }
1859
1860 static void
1861 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1862 {
1863 struct radv_device *device = pipeline->device;
1864 unsigned num_se = device->physical_device->rad_info.max_se;
1865 unsigned wave_size = 64;
1866 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1867 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1868 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1869 */
1870 unsigned gs_vertex_reuse =
1871 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1872 unsigned alignment = 256 * num_se;
1873 /* The maximum size is 63.999 MB per SE. */
1874 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1875 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1876
1877 /* Calculate the minimum size. */
1878 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1879 wave_size, alignment);
1880 /* These are recommended sizes, not minimum sizes. */
1881 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1882 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1883 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1884 gs_info->gs.max_gsvs_emit_size;
1885
1886 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1887 esgs_ring_size = align(esgs_ring_size, alignment);
1888 gsvs_ring_size = align(gsvs_ring_size, alignment);
1889
1890 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1891 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1892
1893 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1894 }
1895
1896 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1897 unsigned *lds_size)
1898 {
1899 /* If tessellation is all offchip and on-chip GS isn't used, this
1900 * workaround is not needed.
1901 */
1902 return;
1903
1904 /* SPI barrier management bug:
1905 * Make sure we have at least 4k of LDS in use to avoid the bug.
1906 * It applies to workgroup sizes of more than one wavefront.
1907 */
1908 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1909 device->physical_device->rad_info.family == CHIP_KABINI)
1910 *lds_size = MAX2(*lds_size, 8);
1911 }
1912
1913 struct radv_shader_variant *
1914 radv_get_shader(struct radv_pipeline *pipeline,
1915 gl_shader_stage stage)
1916 {
1917 if (stage == MESA_SHADER_VERTEX) {
1918 if (pipeline->shaders[MESA_SHADER_VERTEX])
1919 return pipeline->shaders[MESA_SHADER_VERTEX];
1920 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1921 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1922 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1923 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1924 } else if (stage == MESA_SHADER_TESS_EVAL) {
1925 if (!radv_pipeline_has_tess(pipeline))
1926 return NULL;
1927 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1928 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1929 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1930 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1931 }
1932 return pipeline->shaders[stage];
1933 }
1934
1935 static struct radv_tessellation_state
1936 calculate_tess_state(struct radv_pipeline *pipeline,
1937 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1938 {
1939 unsigned num_tcs_input_cp;
1940 unsigned num_tcs_output_cp;
1941 unsigned lds_size;
1942 unsigned num_patches;
1943 struct radv_tessellation_state tess = {0};
1944
1945 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1946 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1947 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1948
1949 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1950
1951 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1952 assert(lds_size <= 65536);
1953 lds_size = align(lds_size, 512) / 512;
1954 } else {
1955 assert(lds_size <= 32768);
1956 lds_size = align(lds_size, 256) / 256;
1957 }
1958 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1959
1960 tess.lds_size = lds_size;
1961
1962 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1963 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1964 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1965 tess.num_patches = num_patches;
1966
1967 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1968 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1969
1970 switch (tes->info.tes.primitive_mode) {
1971 case GL_TRIANGLES:
1972 type = V_028B6C_TESS_TRIANGLE;
1973 break;
1974 case GL_QUADS:
1975 type = V_028B6C_TESS_QUAD;
1976 break;
1977 case GL_ISOLINES:
1978 type = V_028B6C_TESS_ISOLINE;
1979 break;
1980 }
1981
1982 switch (tes->info.tes.spacing) {
1983 case TESS_SPACING_EQUAL:
1984 partitioning = V_028B6C_PART_INTEGER;
1985 break;
1986 case TESS_SPACING_FRACTIONAL_ODD:
1987 partitioning = V_028B6C_PART_FRAC_ODD;
1988 break;
1989 case TESS_SPACING_FRACTIONAL_EVEN:
1990 partitioning = V_028B6C_PART_FRAC_EVEN;
1991 break;
1992 default:
1993 break;
1994 }
1995
1996 bool ccw = tes->info.tes.ccw;
1997 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1998 vk_find_struct_const(pCreateInfo->pTessellationState,
1999 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2000
2001 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2002 ccw = !ccw;
2003
2004 if (tes->info.tes.point_mode)
2005 topology = V_028B6C_OUTPUT_POINT;
2006 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2007 topology = V_028B6C_OUTPUT_LINE;
2008 else if (ccw)
2009 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2010 else
2011 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2012
2013 if (pipeline->device->has_distributed_tess) {
2014 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2015 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2016 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2017 else
2018 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2019 } else
2020 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2021
2022 tess.tf_param = S_028B6C_TYPE(type) |
2023 S_028B6C_PARTITIONING(partitioning) |
2024 S_028B6C_TOPOLOGY(topology) |
2025 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2026
2027 return tess;
2028 }
2029
2030 static const struct radv_prim_vertex_count prim_size_table[] = {
2031 [V_008958_DI_PT_NONE] = {0, 0},
2032 [V_008958_DI_PT_POINTLIST] = {1, 1},
2033 [V_008958_DI_PT_LINELIST] = {2, 2},
2034 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2035 [V_008958_DI_PT_TRILIST] = {3, 3},
2036 [V_008958_DI_PT_TRIFAN] = {3, 1},
2037 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2038 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2039 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2040 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2041 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2042 [V_008958_DI_PT_RECTLIST] = {3, 3},
2043 [V_008958_DI_PT_LINELOOP] = {2, 1},
2044 [V_008958_DI_PT_POLYGON] = {3, 1},
2045 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2046 };
2047
2048 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2049 {
2050 if (radv_pipeline_has_gs(pipeline))
2051 if (radv_pipeline_has_ngg(pipeline))
2052 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2053 else
2054 return &pipeline->gs_copy_shader->info.vs.outinfo;
2055 else if (radv_pipeline_has_tess(pipeline))
2056 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2057 else
2058 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2059 }
2060
2061 static void
2062 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2063 {
2064 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2065 int shader_count = 0;
2066
2067 if(shaders[MESA_SHADER_FRAGMENT]) {
2068 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2069 }
2070 if(shaders[MESA_SHADER_GEOMETRY]) {
2071 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2072 }
2073 if(shaders[MESA_SHADER_TESS_EVAL]) {
2074 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2075 }
2076 if(shaders[MESA_SHADER_TESS_CTRL]) {
2077 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2078 }
2079 if(shaders[MESA_SHADER_VERTEX]) {
2080 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2081 }
2082
2083 if (shader_count > 1) {
2084 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2085 unsigned last = ordered_shaders[0]->info.stage;
2086
2087 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2088 ordered_shaders[1]->info.has_transform_feedback_varyings)
2089 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2090
2091 for (int i = 0; i < shader_count; ++i) {
2092 nir_variable_mode mask = 0;
2093
2094 if (ordered_shaders[i]->info.stage != first)
2095 mask = mask | nir_var_shader_in;
2096
2097 if (ordered_shaders[i]->info.stage != last)
2098 mask = mask | nir_var_shader_out;
2099
2100 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2101 radv_optimize_nir(ordered_shaders[i], false, false);
2102 }
2103 }
2104
2105 for (int i = 1; i < shader_count; ++i) {
2106 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2107 ordered_shaders[i - 1]);
2108
2109 if (nir_link_opt_varyings(ordered_shaders[i],
2110 ordered_shaders[i - 1]))
2111 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2112
2113 nir_remove_dead_variables(ordered_shaders[i],
2114 nir_var_shader_out);
2115 nir_remove_dead_variables(ordered_shaders[i - 1],
2116 nir_var_shader_in);
2117
2118 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2119 ordered_shaders[i - 1]);
2120
2121 nir_compact_varyings(ordered_shaders[i],
2122 ordered_shaders[i - 1], true);
2123
2124 if (progress) {
2125 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2126 ac_lower_indirect_derefs(ordered_shaders[i],
2127 pipeline->device->physical_device->rad_info.chip_class);
2128 }
2129 radv_optimize_nir(ordered_shaders[i], false, false);
2130
2131 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2132 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2133 pipeline->device->physical_device->rad_info.chip_class);
2134 }
2135 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2136 }
2137 }
2138 }
2139
2140 static uint32_t
2141 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2142 uint32_t attrib_binding)
2143 {
2144 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2145 const VkVertexInputBindingDescription *input_binding =
2146 &input_state->pVertexBindingDescriptions[i];
2147
2148 if (input_binding->binding == attrib_binding)
2149 return input_binding->stride;
2150 }
2151
2152 return 0;
2153 }
2154
2155 static struct radv_pipeline_key
2156 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2157 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2158 const struct radv_blend_state *blend,
2159 bool has_view_index)
2160 {
2161 const VkPipelineVertexInputStateCreateInfo *input_state =
2162 pCreateInfo->pVertexInputState;
2163 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2164 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2165
2166 struct radv_pipeline_key key;
2167 memset(&key, 0, sizeof(key));
2168
2169 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2170 key.optimisations_disabled = 1;
2171
2172 key.has_multiview_view_index = has_view_index;
2173
2174 uint32_t binding_input_rate = 0;
2175 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2176 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2177 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2178 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2179 binding_input_rate |= 1u << binding;
2180 instance_rate_divisors[binding] = 1;
2181 }
2182 }
2183 if (divisor_state) {
2184 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2185 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2186 divisor_state->pVertexBindingDivisors[i].divisor;
2187 }
2188 }
2189
2190 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2191 const VkVertexInputAttributeDescription *desc =
2192 &input_state->pVertexAttributeDescriptions[i];
2193 const struct vk_format_description *format_desc;
2194 unsigned location = desc->location;
2195 unsigned binding = desc->binding;
2196 unsigned num_format, data_format;
2197 int first_non_void;
2198
2199 if (binding_input_rate & (1u << binding)) {
2200 key.instance_rate_inputs |= 1u << location;
2201 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2202 }
2203
2204 format_desc = vk_format_description(desc->format);
2205 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2206
2207 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2208 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2209
2210 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2211 key.vertex_attribute_bindings[location] = desc->binding;
2212 key.vertex_attribute_offsets[location] = desc->offset;
2213 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2214
2215 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2216 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2217 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2218 uint64_t adjust;
2219 switch(format) {
2220 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2221 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2222 adjust = RADV_ALPHA_ADJUST_SNORM;
2223 break;
2224 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2225 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2226 adjust = RADV_ALPHA_ADJUST_SSCALED;
2227 break;
2228 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2229 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2230 adjust = RADV_ALPHA_ADJUST_SINT;
2231 break;
2232 default:
2233 adjust = 0;
2234 break;
2235 }
2236 key.vertex_alpha_adjust |= adjust << (2 * location);
2237 }
2238
2239 switch (desc->format) {
2240 case VK_FORMAT_B8G8R8A8_UNORM:
2241 case VK_FORMAT_B8G8R8A8_SNORM:
2242 case VK_FORMAT_B8G8R8A8_USCALED:
2243 case VK_FORMAT_B8G8R8A8_SSCALED:
2244 case VK_FORMAT_B8G8R8A8_UINT:
2245 case VK_FORMAT_B8G8R8A8_SINT:
2246 case VK_FORMAT_B8G8R8A8_SRGB:
2247 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2248 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2249 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2250 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2251 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2252 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2253 key.vertex_post_shuffle |= 1 << location;
2254 break;
2255 default:
2256 break;
2257 }
2258 }
2259
2260 if (pCreateInfo->pTessellationState)
2261 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2262
2263
2264 if (pCreateInfo->pMultisampleState &&
2265 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2266 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2267 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2268 key.num_samples = num_samples;
2269 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2270 }
2271
2272 key.col_format = blend->spi_shader_col_format;
2273 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2274 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2275
2276 return key;
2277 }
2278
2279 static bool
2280 radv_nir_stage_uses_xfb(const nir_shader *nir)
2281 {
2282 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2283 bool uses_xfb = !!xfb;
2284
2285 ralloc_free(xfb);
2286 return uses_xfb;
2287 }
2288
2289 static void
2290 radv_fill_shader_keys(struct radv_device *device,
2291 struct radv_shader_variant_key *keys,
2292 const struct radv_pipeline_key *key,
2293 nir_shader **nir)
2294 {
2295 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2296 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2297 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2298 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2299 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2300 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2301 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2302 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2303 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2304 }
2305
2306 if (nir[MESA_SHADER_TESS_CTRL]) {
2307 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2308 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2309 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2310 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2311
2312 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2313 }
2314
2315 if (nir[MESA_SHADER_GEOMETRY]) {
2316 if (nir[MESA_SHADER_TESS_CTRL])
2317 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2318 else
2319 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2320 }
2321
2322 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2323 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2324 if (nir[MESA_SHADER_TESS_CTRL]) {
2325 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2326 } else {
2327 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2328 }
2329
2330 if (nir[MESA_SHADER_TESS_CTRL] &&
2331 nir[MESA_SHADER_GEOMETRY] &&
2332 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2333 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2334 /* Fallback to the legacy path if tessellation is
2335 * enabled with extreme geometry because
2336 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2337 * might hang.
2338 */
2339 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2340 }
2341
2342 /* TODO: Implement streamout support for NGG. */
2343 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2344
2345 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2346 if (nir[i])
2347 last_xfb_stage = i;
2348 }
2349
2350 if (nir[last_xfb_stage] &&
2351 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2352 if (nir[MESA_SHADER_TESS_CTRL])
2353 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2354 else
2355 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2356 }
2357 }
2358
2359 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2360 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2361
2362 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2363 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2364 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2365 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2366 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2367 }
2368
2369 static void
2370 merge_tess_info(struct shader_info *tes_info,
2371 const struct shader_info *tcs_info)
2372 {
2373 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2374 *
2375 * "PointMode. Controls generation of points rather than triangles
2376 * or lines. This functionality defaults to disabled, and is
2377 * enabled if either shader stage includes the execution mode.
2378 *
2379 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2380 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2381 * and OutputVertices, it says:
2382 *
2383 * "One mode must be set in at least one of the tessellation
2384 * shader stages."
2385 *
2386 * So, the fields can be set in either the TCS or TES, but they must
2387 * agree if set in both. Our backend looks at TES, so bitwise-or in
2388 * the values from the TCS.
2389 */
2390 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2391 tes_info->tess.tcs_vertices_out == 0 ||
2392 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2393 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2394
2395 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2396 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2397 tcs_info->tess.spacing == tes_info->tess.spacing);
2398 tes_info->tess.spacing |= tcs_info->tess.spacing;
2399
2400 assert(tcs_info->tess.primitive_mode == 0 ||
2401 tes_info->tess.primitive_mode == 0 ||
2402 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2403 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2404 tes_info->tess.ccw |= tcs_info->tess.ccw;
2405 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2406 }
2407
2408 static
2409 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2410 {
2411 if (!ext)
2412 return;
2413
2414 if (ext->pPipelineCreationFeedback) {
2415 ext->pPipelineCreationFeedback->flags = 0;
2416 ext->pPipelineCreationFeedback->duration = 0;
2417 }
2418
2419 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2420 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2421 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2422 }
2423 }
2424
2425 static
2426 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2427 {
2428 if (!feedback)
2429 return;
2430
2431 feedback->duration -= radv_get_current_time();
2432 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2433 }
2434
2435 static
2436 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2437 {
2438 if (!feedback)
2439 return;
2440
2441 feedback->duration += radv_get_current_time();
2442 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2443 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2444 }
2445
2446 static
2447 void radv_create_shaders(struct radv_pipeline *pipeline,
2448 struct radv_device *device,
2449 struct radv_pipeline_cache *cache,
2450 const struct radv_pipeline_key *key,
2451 const VkPipelineShaderStageCreateInfo **pStages,
2452 const VkPipelineCreateFlags flags,
2453 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2454 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2455 {
2456 struct radv_shader_module fs_m = {0};
2457 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2458 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2459 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2460 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2461 unsigned char hash[20], gs_copy_hash[20];
2462 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2463
2464 radv_start_feedback(pipeline_feedback);
2465
2466 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2467 if (pStages[i]) {
2468 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2469 if (modules[i]->nir)
2470 _mesa_sha1_compute(modules[i]->nir->info.name,
2471 strlen(modules[i]->nir->info.name),
2472 modules[i]->sha1);
2473
2474 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2475 }
2476 }
2477
2478 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2479 memcpy(gs_copy_hash, hash, 20);
2480 gs_copy_hash[0] ^= 1;
2481
2482 bool found_in_application_cache = true;
2483 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2484 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2485 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2486 &found_in_application_cache);
2487 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2488 }
2489
2490 if (!keep_executable_info &&
2491 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2492 &found_in_application_cache) &&
2493 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2494 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2495 return;
2496 }
2497
2498 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2499 nir_builder fs_b;
2500 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2501 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2502 fs_m.nir = fs_b.shader;
2503 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2504 }
2505
2506 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2507 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2508
2509 if (!modules[i])
2510 continue;
2511
2512 radv_start_feedback(stage_feedbacks[i]);
2513
2514 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2515 stage ? stage->pName : "main", i,
2516 stage ? stage->pSpecializationInfo : NULL,
2517 flags, pipeline->layout);
2518
2519 /* We don't want to alter meta shaders IR directly so clone it
2520 * first.
2521 */
2522 if (nir[i]->info.name) {
2523 nir[i] = nir_shader_clone(NULL, nir[i]);
2524 }
2525
2526 radv_stop_feedback(stage_feedbacks[i], false);
2527 }
2528
2529 if (nir[MESA_SHADER_TESS_CTRL]) {
2530 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2531 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2532 }
2533
2534 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2535 radv_link_shaders(pipeline, nir);
2536
2537 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2538 if (nir[i]) {
2539 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2540 nir_lower_non_uniform_ubo_access |
2541 nir_lower_non_uniform_ssbo_access |
2542 nir_lower_non_uniform_texture_access |
2543 nir_lower_non_uniform_image_access);
2544 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2545 }
2546
2547 if (radv_can_dump_shader(device, modules[i], false))
2548 nir_print_shader(nir[i], stderr);
2549 }
2550
2551 radv_fill_shader_keys(device, keys, key, nir);
2552
2553 if (nir[MESA_SHADER_FRAGMENT]) {
2554 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2555 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2556
2557 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2558 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2559 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2560 keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
2561
2562 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2563 }
2564
2565 /* TODO: These are no longer used as keys we should refactor this */
2566 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2567 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2568 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2569 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2570 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2571 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2572 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2573 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2574 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2575 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2576 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2577 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2578 }
2579
2580 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2581 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2582 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2583 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2584 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2585
2586 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2587
2588 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2589 pipeline->layout,
2590 &key, keep_executable_info,
2591 &binaries[MESA_SHADER_TESS_CTRL]);
2592
2593 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2594 }
2595 modules[MESA_SHADER_VERTEX] = NULL;
2596 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2597 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2598 }
2599
2600 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2601 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2602 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2603 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2604
2605 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2606
2607 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2608 pipeline->layout,
2609 &keys[pre_stage], keep_executable_info,
2610 &binaries[MESA_SHADER_GEOMETRY]);
2611
2612 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2613 }
2614 modules[pre_stage] = NULL;
2615 }
2616
2617 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2618 if(modules[i] && !pipeline->shaders[i]) {
2619 if (i == MESA_SHADER_TESS_CTRL) {
2620 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2621 }
2622 if (i == MESA_SHADER_TESS_EVAL) {
2623 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2624 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2625 }
2626
2627 radv_start_feedback(stage_feedbacks[i]);
2628
2629 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2630 pipeline->layout,
2631 keys + i, keep_executable_info,
2632 &binaries[i]);
2633
2634 radv_stop_feedback(stage_feedbacks[i], false);
2635 }
2636 }
2637
2638 if(modules[MESA_SHADER_GEOMETRY]) {
2639 struct radv_shader_binary *gs_copy_binary = NULL;
2640 if (!pipeline->gs_copy_shader &&
2641 !radv_pipeline_has_ngg(pipeline)) {
2642 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2643 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
2644 keep_executable_info,
2645 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2646 }
2647
2648 if (!keep_executable_info && pipeline->gs_copy_shader) {
2649 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2650 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2651
2652 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2653 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2654
2655 radv_pipeline_cache_insert_shaders(device, cache,
2656 gs_copy_hash,
2657 variants,
2658 binaries);
2659 }
2660 free(gs_copy_binary);
2661 }
2662
2663 if (!keep_executable_info) {
2664 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2665 binaries);
2666 }
2667
2668 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2669 free(binaries[i]);
2670 if (nir[i]) {
2671 ralloc_free(nir[i]);
2672
2673 if (radv_can_dump_shader_stats(device, modules[i]))
2674 radv_shader_dump_stats(device,
2675 pipeline->shaders[i],
2676 i, stderr);
2677 }
2678 }
2679
2680 if (fs_m.nir)
2681 ralloc_free(fs_m.nir);
2682
2683 radv_stop_feedback(pipeline_feedback, false);
2684 }
2685
2686 static uint32_t
2687 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2688 gl_shader_stage stage, enum chip_class chip_class)
2689 {
2690 bool has_gs = radv_pipeline_has_gs(pipeline);
2691 bool has_tess = radv_pipeline_has_tess(pipeline);
2692 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2693
2694 switch (stage) {
2695 case MESA_SHADER_FRAGMENT:
2696 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2697 case MESA_SHADER_VERTEX:
2698 if (has_tess) {
2699 if (chip_class >= GFX10) {
2700 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2701 } else if (chip_class == GFX9) {
2702 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2703 } else {
2704 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2705 }
2706
2707 }
2708
2709 if (has_gs) {
2710 if (chip_class >= GFX10) {
2711 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2712 } else {
2713 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2714 }
2715 }
2716
2717 if (has_ngg)
2718 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2719
2720 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2721 case MESA_SHADER_GEOMETRY:
2722 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2723 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2724 case MESA_SHADER_COMPUTE:
2725 return R_00B900_COMPUTE_USER_DATA_0;
2726 case MESA_SHADER_TESS_CTRL:
2727 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2728 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2729 case MESA_SHADER_TESS_EVAL:
2730 if (has_gs) {
2731 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2732 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2733 } else if (has_ngg) {
2734 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2735 } else {
2736 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2737 }
2738 default:
2739 unreachable("unknown shader");
2740 }
2741 }
2742
2743 struct radv_bin_size_entry {
2744 unsigned bpp;
2745 VkExtent2D extent;
2746 };
2747
2748 static VkExtent2D
2749 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2750 {
2751 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2752 {
2753 /* One RB / SE */
2754 {
2755 /* One shader engine */
2756 { 0, {128, 128}},
2757 { 1, { 64, 128}},
2758 { 2, { 32, 128}},
2759 { 3, { 16, 128}},
2760 { 17, { 0, 0}},
2761 { UINT_MAX, { 0, 0}},
2762 },
2763 {
2764 /* Two shader engines */
2765 { 0, {128, 128}},
2766 { 2, { 64, 128}},
2767 { 3, { 32, 128}},
2768 { 5, { 16, 128}},
2769 { 17, { 0, 0}},
2770 { UINT_MAX, { 0, 0}},
2771 },
2772 {
2773 /* Four shader engines */
2774 { 0, {128, 128}},
2775 { 3, { 64, 128}},
2776 { 5, { 16, 128}},
2777 { 17, { 0, 0}},
2778 { UINT_MAX, { 0, 0}},
2779 },
2780 },
2781 {
2782 /* Two RB / SE */
2783 {
2784 /* One shader engine */
2785 { 0, {128, 128}},
2786 { 2, { 64, 128}},
2787 { 3, { 32, 128}},
2788 { 5, { 16, 128}},
2789 { 33, { 0, 0}},
2790 { UINT_MAX, { 0, 0}},
2791 },
2792 {
2793 /* Two shader engines */
2794 { 0, {128, 128}},
2795 { 3, { 64, 128}},
2796 { 5, { 32, 128}},
2797 { 9, { 16, 128}},
2798 { 33, { 0, 0}},
2799 { UINT_MAX, { 0, 0}},
2800 },
2801 {
2802 /* Four shader engines */
2803 { 0, {256, 256}},
2804 { 2, {128, 256}},
2805 { 3, {128, 128}},
2806 { 5, { 64, 128}},
2807 { 9, { 16, 128}},
2808 { 33, { 0, 0}},
2809 { UINT_MAX, { 0, 0}},
2810 },
2811 },
2812 {
2813 /* Four RB / SE */
2814 {
2815 /* One shader engine */
2816 { 0, {128, 256}},
2817 { 2, {128, 128}},
2818 { 3, { 64, 128}},
2819 { 5, { 32, 128}},
2820 { 9, { 16, 128}},
2821 { 33, { 0, 0}},
2822 { UINT_MAX, { 0, 0}},
2823 },
2824 {
2825 /* Two shader engines */
2826 { 0, {256, 256}},
2827 { 2, {128, 256}},
2828 { 3, {128, 128}},
2829 { 5, { 64, 128}},
2830 { 9, { 32, 128}},
2831 { 17, { 16, 128}},
2832 { 33, { 0, 0}},
2833 { UINT_MAX, { 0, 0}},
2834 },
2835 {
2836 /* Four shader engines */
2837 { 0, {256, 512}},
2838 { 2, {256, 256}},
2839 { 3, {128, 256}},
2840 { 5, {128, 128}},
2841 { 9, { 64, 128}},
2842 { 17, { 16, 128}},
2843 { 33, { 0, 0}},
2844 { UINT_MAX, { 0, 0}},
2845 },
2846 },
2847 };
2848 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2849 {
2850 // One RB / SE
2851 {
2852 // One shader engine
2853 { 0, {128, 256}},
2854 { 2, {128, 128}},
2855 { 4, { 64, 128}},
2856 { 7, { 32, 128}},
2857 { 13, { 16, 128}},
2858 { 49, { 0, 0}},
2859 { UINT_MAX, { 0, 0}},
2860 },
2861 {
2862 // Two shader engines
2863 { 0, {256, 256}},
2864 { 2, {128, 256}},
2865 { 4, {128, 128}},
2866 { 7, { 64, 128}},
2867 { 13, { 32, 128}},
2868 { 25, { 16, 128}},
2869 { 49, { 0, 0}},
2870 { UINT_MAX, { 0, 0}},
2871 },
2872 {
2873 // Four shader engines
2874 { 0, {256, 512}},
2875 { 2, {256, 256}},
2876 { 4, {128, 256}},
2877 { 7, {128, 128}},
2878 { 13, { 64, 128}},
2879 { 25, { 16, 128}},
2880 { 49, { 0, 0}},
2881 { UINT_MAX, { 0, 0}},
2882 },
2883 },
2884 {
2885 // Two RB / SE
2886 {
2887 // One shader engine
2888 { 0, {256, 256}},
2889 { 2, {128, 256}},
2890 { 4, {128, 128}},
2891 { 7, { 64, 128}},
2892 { 13, { 32, 128}},
2893 { 25, { 16, 128}},
2894 { 97, { 0, 0}},
2895 { UINT_MAX, { 0, 0}},
2896 },
2897 {
2898 // Two shader engines
2899 { 0, {256, 512}},
2900 { 2, {256, 256}},
2901 { 4, {128, 256}},
2902 { 7, {128, 128}},
2903 { 13, { 64, 128}},
2904 { 25, { 32, 128}},
2905 { 49, { 16, 128}},
2906 { 97, { 0, 0}},
2907 { UINT_MAX, { 0, 0}},
2908 },
2909 {
2910 // Four shader engines
2911 { 0, {512, 512}},
2912 { 2, {256, 512}},
2913 { 4, {256, 256}},
2914 { 7, {128, 256}},
2915 { 13, {128, 128}},
2916 { 25, { 64, 128}},
2917 { 49, { 16, 128}},
2918 { 97, { 0, 0}},
2919 { UINT_MAX, { 0, 0}},
2920 },
2921 },
2922 {
2923 // Four RB / SE
2924 {
2925 // One shader engine
2926 { 0, {256, 512}},
2927 { 2, {256, 256}},
2928 { 4, {128, 256}},
2929 { 7, {128, 128}},
2930 { 13, { 64, 128}},
2931 { 25, { 32, 128}},
2932 { 49, { 16, 128}},
2933 { UINT_MAX, { 0, 0}},
2934 },
2935 {
2936 // Two shader engines
2937 { 0, {512, 512}},
2938 { 2, {256, 512}},
2939 { 4, {256, 256}},
2940 { 7, {128, 256}},
2941 { 13, {128, 128}},
2942 { 25, { 64, 128}},
2943 { 49, { 32, 128}},
2944 { 97, { 16, 128}},
2945 { UINT_MAX, { 0, 0}},
2946 },
2947 {
2948 // Four shader engines
2949 { 0, {512, 512}},
2950 { 4, {256, 512}},
2951 { 7, {256, 256}},
2952 { 13, {128, 256}},
2953 { 25, {128, 128}},
2954 { 49, { 64, 128}},
2955 { 97, { 16, 128}},
2956 { UINT_MAX, { 0, 0}},
2957 },
2958 },
2959 };
2960
2961 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2962 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2963 VkExtent2D extent = {512, 512};
2964
2965 unsigned log_num_rb_per_se =
2966 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2967 pipeline->device->physical_device->rad_info.max_se);
2968 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2969
2970 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
2971 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2972 unsigned effective_samples = total_samples;
2973 unsigned color_bytes_per_pixel = 0;
2974
2975 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2976 if (vkblend) {
2977 for (unsigned i = 0; i < subpass->color_count; i++) {
2978 if (!vkblend->pAttachments[i].colorWriteMask)
2979 continue;
2980
2981 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2982 continue;
2983
2984 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2985 color_bytes_per_pixel += vk_format_get_blocksize(format);
2986 }
2987
2988 /* MSAA images typically don't use all samples all the time. */
2989 if (effective_samples >= 2 && ps_iter_samples <= 1)
2990 effective_samples = 2;
2991 color_bytes_per_pixel *= effective_samples;
2992 }
2993
2994 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2995 while(color_entry[1].bpp <= color_bytes_per_pixel)
2996 ++color_entry;
2997
2998 extent = color_entry->extent;
2999
3000 if (subpass->depth_stencil_attachment) {
3001 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3002
3003 /* Coefficients taken from AMDVLK */
3004 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3005 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3006 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3007
3008 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3009 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3010 ++ds_entry;
3011
3012 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3013 extent = ds_entry->extent;
3014 }
3015
3016 return extent;
3017 }
3018
3019 static VkExtent2D
3020 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3021 {
3022 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3023 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3024 VkExtent2D extent = {512, 512};
3025
3026 unsigned sdp_interface_count;
3027
3028 switch(pipeline->device->physical_device->rad_info.family) {
3029 case CHIP_NAVI10:
3030 case CHIP_NAVI12:
3031 sdp_interface_count = 16;
3032 break;
3033 case CHIP_NAVI14:
3034 sdp_interface_count = 8;
3035 break;
3036 default:
3037 unreachable("Unhandled GFX10 chip");
3038 }
3039
3040 const unsigned db_tag_size = 64;
3041 const unsigned db_tag_count = 312;
3042 const unsigned color_tag_size = 1024;
3043 const unsigned color_tag_count = 31;
3044 const unsigned fmask_tag_size = 256;
3045 const unsigned fmask_tag_count = 44;
3046
3047 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3048 const unsigned pipe_count = MAX2(rb_count, sdp_interface_count);
3049
3050 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3051 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3052 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3053
3054 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3055 const unsigned samples_log = util_logbase2_ceil(total_samples);
3056
3057 unsigned color_bytes_per_pixel = 0;
3058 unsigned fmask_bytes_per_pixel = 0;
3059
3060 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3061 if (vkblend) {
3062 for (unsigned i = 0; i < subpass->color_count; i++) {
3063 if (!vkblend->pAttachments[i].colorWriteMask)
3064 continue;
3065
3066 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3067 continue;
3068
3069 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3070 color_bytes_per_pixel += vk_format_get_blocksize(format);
3071
3072 if (total_samples > 1) {
3073 const unsigned fmask_array[] = {0, 1, 1, 4};
3074 fmask_bytes_per_pixel += fmask_array[samples_log];
3075 }
3076 }
3077
3078 color_bytes_per_pixel *= total_samples;
3079 }
3080 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3081
3082 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3083 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3084 extent.height = 1ull << (color_pixel_count_log / 2);
3085
3086 if (fmask_bytes_per_pixel) {
3087 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3088
3089 const VkExtent2D fmask_extent = (VkExtent2D){
3090 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3091 .height = 1ull << (color_pixel_count_log / 2)
3092 };
3093
3094 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3095 extent = fmask_extent;
3096 }
3097
3098 if (subpass->depth_stencil_attachment) {
3099 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3100
3101 /* Coefficients taken from AMDVLK */
3102 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3103 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3104 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3105
3106 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3107
3108 const VkExtent2D db_extent = (VkExtent2D){
3109 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3110 .height = 1ull << (color_pixel_count_log / 2)
3111 };
3112
3113 if (db_extent.width * db_extent.height < extent.width * extent.height)
3114 extent = db_extent;
3115 }
3116
3117 extent.width = MAX2(extent.width, 128);
3118 extent.height = MAX2(extent.width, 64);
3119
3120 return extent;
3121 }
3122
3123 static void
3124 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3125 struct radv_pipeline *pipeline,
3126 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3127 {
3128 uint32_t pa_sc_binner_cntl_0 =
3129 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3130 S_028C44_DISABLE_START_OF_PRIM(1);
3131 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3132
3133 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3134 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3135 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3136 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3137 unsigned min_bytes_per_pixel = 0;
3138
3139 if (vkblend) {
3140 for (unsigned i = 0; i < subpass->color_count; i++) {
3141 if (!vkblend->pAttachments[i].colorWriteMask)
3142 continue;
3143
3144 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3145 continue;
3146
3147 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3148 unsigned bytes = vk_format_get_blocksize(format);
3149 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3150 min_bytes_per_pixel = bytes;
3151 }
3152 }
3153
3154 pa_sc_binner_cntl_0 =
3155 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3156 S_028C44_BIN_SIZE_X(0) |
3157 S_028C44_BIN_SIZE_Y(0) |
3158 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3159 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3160 S_028C44_DISABLE_START_OF_PRIM(1);
3161 }
3162
3163 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3164 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3165 }
3166
3167 static void
3168 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3169 struct radv_pipeline *pipeline,
3170 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3171 {
3172 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3173 return;
3174
3175 VkExtent2D bin_size;
3176 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3177 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3178 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3179 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3180 } else
3181 unreachable("Unhandled generation for binning bin size calculation");
3182
3183 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3184 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3185 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3186 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3187
3188 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3189 context_states_per_bin = 1;
3190 persistent_states_per_bin = 1;
3191 fpovs_per_batch = 63;
3192 } else {
3193 /* The context states are affected by the scissor bug. */
3194 context_states_per_bin = pipeline->device->physical_device->has_scissor_bug ? 1 : 6;
3195 /* 32 causes hangs for RAVEN. */
3196 persistent_states_per_bin = 16;
3197 fpovs_per_batch = 63;
3198 }
3199
3200 const uint32_t pa_sc_binner_cntl_0 =
3201 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3202 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3203 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3204 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3205 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3206 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3207 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3208 S_028C44_DISABLE_START_OF_PRIM(1) |
3209 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3210 S_028C44_OPTIMAL_BIN_SELECTION(1);
3211
3212 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3213
3214 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3215 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3216 } else
3217 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3218 }
3219
3220
3221 static void
3222 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3223 struct radv_pipeline *pipeline,
3224 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3225 const struct radv_graphics_pipeline_create_info *extra)
3226 {
3227 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3228 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3229 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3230 struct radv_render_pass_attachment *attachment = NULL;
3231 uint32_t db_depth_control = 0, db_stencil_control = 0;
3232 uint32_t db_render_control = 0, db_render_override2 = 0;
3233 uint32_t db_render_override = 0;
3234
3235 if (subpass->depth_stencil_attachment)
3236 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3237
3238 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3239 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3240
3241 if (vkds && has_depth_attachment) {
3242 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3243 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3244 S_028800_ZFUNC(vkds->depthCompareOp) |
3245 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3246
3247 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3248 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3249 }
3250
3251 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3252 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3253 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3254 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3255 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3256 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3257
3258 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3259 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3260 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3261 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3262 }
3263
3264 if (attachment && extra) {
3265 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3266 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3267
3268 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3269 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3270 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3271 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3272 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3273 }
3274
3275 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3276 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3277
3278 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3279 /* From VK_EXT_depth_range_unrestricted spec:
3280 *
3281 * "The behavior described in Primitive Clipping still applies.
3282 * If depth clamping is disabled the depth values are still
3283 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3284 * depth clamping is enabled the above equation is ignored and
3285 * the depth values are instead clamped to the VkViewport
3286 * minDepth and maxDepth values, which in the case of this
3287 * extension can be outside of the 0.0 to 1.0 range."
3288 */
3289 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3290 }
3291
3292 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3293 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3294
3295 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3296 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3297 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3298 }
3299
3300 static void
3301 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3302 struct radv_pipeline *pipeline,
3303 const struct radv_blend_state *blend)
3304 {
3305 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3306 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3307 8);
3308 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3309 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3310
3311 if (pipeline->device->physical_device->has_rbplus) {
3312
3313 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3314 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3315 }
3316
3317 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3318
3319 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3320 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3321
3322 pipeline->graphics.col_format = blend->spi_shader_col_format;
3323 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3324 }
3325
3326 static const VkConservativeRasterizationModeEXT
3327 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3328 {
3329 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3330 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3331
3332 if (!conservative_raster)
3333 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3334 return conservative_raster->conservativeRasterizationMode;
3335 }
3336
3337 static void
3338 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3339 struct radv_pipeline *pipeline,
3340 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3341 {
3342 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3343 const VkConservativeRasterizationModeEXT mode =
3344 radv_get_conservative_raster_mode(vkraster);
3345 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3346 bool depth_clip_disable = vkraster->depthClampEnable;
3347
3348 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3349 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3350 if (depth_clip_state) {
3351 depth_clip_disable = !depth_clip_state->depthClipEnable;
3352 }
3353
3354 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3355 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3356 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3357 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3358 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3359 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3360
3361 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3362 S_0286D4_FLAT_SHADE_ENA(1) |
3363 S_0286D4_PNT_SPRITE_ENA(1) |
3364 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3365 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3366 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3367 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3368 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3369
3370 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3371 S_028BE4_PIX_CENTER(1) | // TODO verify
3372 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3373 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3374
3375 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3376 S_028814_FACE(vkraster->frontFace) |
3377 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3378 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3379 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3380 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3381 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3382 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3383 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3384 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3385
3386 /* Conservative rasterization. */
3387 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3388 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3389
3390 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3391 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3392 S_028804_OVERRASTERIZATION_AMOUNT(4);
3393
3394 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3395 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3396 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3397
3398 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3399 pa_sc_conservative_rast |=
3400 S_028C4C_OVER_RAST_ENABLE(1) |
3401 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3402 S_028C4C_UNDER_RAST_ENABLE(0) |
3403 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3404 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3405 } else {
3406 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3407 pa_sc_conservative_rast |=
3408 S_028C4C_OVER_RAST_ENABLE(0) |
3409 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3410 S_028C4C_UNDER_RAST_ENABLE(1) |
3411 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3412 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3413 }
3414 }
3415
3416 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3417 pa_sc_conservative_rast);
3418 }
3419
3420
3421 static void
3422 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3423 struct radv_pipeline *pipeline)
3424 {
3425 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3426
3427 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3428 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3429 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3430
3431 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3432 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3433
3434 /* The exclusion bits can be set to improve rasterization efficiency
3435 * if no sample lies on the pixel boundary (-8 sample offset). It's
3436 * currently always TRUE because the driver doesn't support 16 samples.
3437 */
3438 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3439 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3440 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3441 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3442 }
3443
3444 static void
3445 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3446 struct radv_pipeline *pipeline)
3447 {
3448 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3449 const struct radv_shader_variant *vs =
3450 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3451 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3452 pipeline->shaders[MESA_SHADER_VERTEX];
3453 unsigned vgt_primitiveid_en = 0;
3454 uint32_t vgt_gs_mode = 0;
3455
3456 if (radv_pipeline_has_ngg(pipeline))
3457 return;
3458
3459 if (radv_pipeline_has_gs(pipeline)) {
3460 const struct radv_shader_variant *gs =
3461 pipeline->shaders[MESA_SHADER_GEOMETRY];
3462
3463 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3464 pipeline->device->physical_device->rad_info.chip_class);
3465 } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
3466 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3467 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3468 }
3469
3470 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3471 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3472 }
3473
3474 static void
3475 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3476 struct radeon_cmdbuf *cs,
3477 struct radv_pipeline *pipeline,
3478 struct radv_shader_variant *shader)
3479 {
3480 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3481
3482 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3483 radeon_emit(cs, va >> 8);
3484 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3485 radeon_emit(cs, shader->config.rsrc1);
3486 radeon_emit(cs, shader->config.rsrc2);
3487
3488 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3489 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3490 clip_dist_mask = outinfo->clip_dist_mask;
3491 cull_dist_mask = outinfo->cull_dist_mask;
3492 total_mask = clip_dist_mask | cull_dist_mask;
3493 bool misc_vec_ena = outinfo->writes_pointsize ||
3494 outinfo->writes_layer ||
3495 outinfo->writes_viewport_index;
3496 unsigned spi_vs_out_config, nparams;
3497
3498 /* VS is required to export at least one param. */
3499 nparams = MAX2(outinfo->param_exports, 1);
3500 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3501
3502 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3503 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3504 }
3505
3506 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3507
3508 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3509 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3510 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3511 V_02870C_SPI_SHADER_4COMP :
3512 V_02870C_SPI_SHADER_NONE) |
3513 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3514 V_02870C_SPI_SHADER_4COMP :
3515 V_02870C_SPI_SHADER_NONE) |
3516 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3517 V_02870C_SPI_SHADER_4COMP :
3518 V_02870C_SPI_SHADER_NONE));
3519
3520 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3521 S_028818_VTX_W0_FMT(1) |
3522 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3523 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3524 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3525
3526 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3527 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3528 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3529 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3530 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3531 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3532 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3533 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3534 cull_dist_mask << 8 |
3535 clip_dist_mask);
3536
3537 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3538 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3539 outinfo->writes_viewport_index);
3540 }
3541
3542 static void
3543 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3544 struct radv_pipeline *pipeline,
3545 struct radv_shader_variant *shader)
3546 {
3547 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3548
3549 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3550 radeon_emit(cs, va >> 8);
3551 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3552 radeon_emit(cs, shader->config.rsrc1);
3553 radeon_emit(cs, shader->config.rsrc2);
3554 }
3555
3556 static void
3557 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3558 struct radv_pipeline *pipeline,
3559 struct radv_shader_variant *shader,
3560 const struct radv_tessellation_state *tess)
3561 {
3562 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3563 uint32_t rsrc2 = shader->config.rsrc2;
3564
3565 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3566 radeon_emit(cs, va >> 8);
3567 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3568
3569 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3570 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3571 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3572 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3573
3574 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3575 radeon_emit(cs, shader->config.rsrc1);
3576 radeon_emit(cs, rsrc2);
3577 }
3578
3579 static void
3580 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3581 struct radeon_cmdbuf *cs,
3582 struct radv_pipeline *pipeline,
3583 struct radv_shader_variant *shader,
3584 const struct radv_ngg_state *ngg_state)
3585 {
3586 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3587 gl_shader_stage es_type =
3588 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3589 struct radv_shader_variant *es =
3590 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3591
3592 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3593 radeon_emit(cs, va >> 8);
3594 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3595 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3596 radeon_emit(cs, shader->config.rsrc1);
3597 radeon_emit(cs, shader->config.rsrc2);
3598
3599 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3600 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3601 clip_dist_mask = outinfo->clip_dist_mask;
3602 cull_dist_mask = outinfo->cull_dist_mask;
3603 total_mask = clip_dist_mask | cull_dist_mask;
3604 bool misc_vec_ena = outinfo->writes_pointsize ||
3605 outinfo->writes_layer ||
3606 outinfo->writes_viewport_index;
3607 bool es_enable_prim_id = outinfo->export_prim_id ||
3608 (es && es->info.info.uses_prim_id);
3609 bool break_wave_at_eoi = false;
3610 unsigned ge_cntl;
3611 unsigned nparams;
3612
3613 if (es_type == MESA_SHADER_TESS_EVAL) {
3614 struct radv_shader_variant *gs =
3615 pipeline->shaders[MESA_SHADER_GEOMETRY];
3616
3617 if (es_enable_prim_id || (gs && gs->info.info.uses_prim_id))
3618 break_wave_at_eoi = true;
3619 }
3620
3621 nparams = MAX2(outinfo->param_exports, 1);
3622 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3623 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3624 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3625
3626 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3627 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3628 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3629 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3630 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3631 V_02870C_SPI_SHADER_4COMP :
3632 V_02870C_SPI_SHADER_NONE) |
3633 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3634 V_02870C_SPI_SHADER_4COMP :
3635 V_02870C_SPI_SHADER_NONE) |
3636 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3637 V_02870C_SPI_SHADER_4COMP :
3638 V_02870C_SPI_SHADER_NONE));
3639
3640 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3641 S_028818_VTX_W0_FMT(1) |
3642 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3643 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3644 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3645 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3646 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3647 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3648 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3649 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3650 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3651 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3652 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3653 cull_dist_mask << 8 |
3654 clip_dist_mask);
3655
3656 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3657 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3658 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3659
3660 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3661 ngg_state->vgt_esgs_ring_itemsize);
3662
3663 /* NGG specific registers. */
3664 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3665 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3666
3667 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3668 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3669 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3670 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3671 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3672 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3673 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3674 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3675 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3676 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3677 S_028B90_CNT(gs_num_invocations) |
3678 S_028B90_ENABLE(gs_num_invocations > 1) |
3679 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3680
3681 /* User edge flags are set by the pos exports. If user edge flags are
3682 * not used, we must use hw-generated edge flags and pass them via
3683 * the prim export to prevent drawing lines on internal edges of
3684 * decomposed primitives (such as quads) with polygon mode = lines.
3685 *
3686 * TODO: We should combine hw-generated edge flags with user edge
3687 * flags in the shader.
3688 */
3689 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3690 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3691 !radv_pipeline_has_gs(pipeline)));
3692
3693 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3694 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3695 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3696
3697 /* Bug workaround for a possible hang with non-tessellation cases.
3698 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3699 *
3700 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3701 */
3702 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3703 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3704 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3705 !radv_pipeline_has_tess(pipeline) &&
3706 ngg_state->hw_max_esverts != 256) {
3707 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3708
3709 if (ngg_state->hw_max_esverts > 5) {
3710 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3711 }
3712 }
3713
3714 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3715 }
3716
3717 static void
3718 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3719 struct radv_pipeline *pipeline,
3720 struct radv_shader_variant *shader,
3721 const struct radv_tessellation_state *tess)
3722 {
3723 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3724
3725 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3726 unsigned hs_rsrc2 = shader->config.rsrc2;
3727
3728 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3729 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3730 } else {
3731 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3732 }
3733
3734 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3735 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3736 radeon_emit(cs, va >> 8);
3737 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3738 } else {
3739 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3740 radeon_emit(cs, va >> 8);
3741 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3742 }
3743
3744 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3745 radeon_emit(cs, shader->config.rsrc1);
3746 radeon_emit(cs, hs_rsrc2);
3747 } else {
3748 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3749 radeon_emit(cs, va >> 8);
3750 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3751 radeon_emit(cs, shader->config.rsrc1);
3752 radeon_emit(cs, shader->config.rsrc2);
3753 }
3754 }
3755
3756 static void
3757 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3758 struct radeon_cmdbuf *cs,
3759 struct radv_pipeline *pipeline,
3760 const struct radv_tessellation_state *tess,
3761 const struct radv_ngg_state *ngg)
3762 {
3763 struct radv_shader_variant *vs;
3764
3765 /* Skip shaders merged into HS/GS */
3766 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3767 if (!vs)
3768 return;
3769
3770 if (vs->info.vs.as_ls)
3771 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3772 else if (vs->info.vs.as_es)
3773 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3774 else if (vs->info.is_ngg)
3775 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs, ngg);
3776 else
3777 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3778 }
3779
3780 static void
3781 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3782 struct radeon_cmdbuf *cs,
3783 struct radv_pipeline *pipeline,
3784 const struct radv_tessellation_state *tess,
3785 const struct radv_ngg_state *ngg)
3786 {
3787 if (!radv_pipeline_has_tess(pipeline))
3788 return;
3789
3790 struct radv_shader_variant *tes, *tcs;
3791
3792 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3793 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3794
3795 if (tes) {
3796 if (tes->info.is_ngg) {
3797 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes, ngg);
3798 } else if (tes->info.tes.as_es)
3799 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3800 else
3801 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3802 }
3803
3804 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3805
3806 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3807 tess->tf_param);
3808
3809 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3810 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3811 tess->ls_hs_config);
3812 else
3813 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3814 tess->ls_hs_config);
3815 }
3816
3817 static void
3818 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3819 struct radeon_cmdbuf *cs,
3820 struct radv_pipeline *pipeline,
3821 struct radv_shader_variant *gs,
3822 const struct radv_gs_state *gs_state)
3823 {
3824 unsigned gs_max_out_vertices;
3825 uint8_t *num_components;
3826 uint8_t max_stream;
3827 unsigned offset;
3828 uint64_t va;
3829
3830 gs_max_out_vertices = gs->info.gs.vertices_out;
3831 max_stream = gs->info.info.gs.max_stream;
3832 num_components = gs->info.info.gs.num_stream_output_components;
3833
3834 offset = num_components[0] * gs_max_out_vertices;
3835
3836 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3837 radeon_emit(ctx_cs, offset);
3838 if (max_stream >= 1)
3839 offset += num_components[1] * gs_max_out_vertices;
3840 radeon_emit(ctx_cs, offset);
3841 if (max_stream >= 2)
3842 offset += num_components[2] * gs_max_out_vertices;
3843 radeon_emit(ctx_cs, offset);
3844 if (max_stream >= 3)
3845 offset += num_components[3] * gs_max_out_vertices;
3846 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3847
3848 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3849 radeon_emit(ctx_cs, num_components[0]);
3850 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3851 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3852 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3853
3854 uint32_t gs_num_invocations = gs->info.gs.invocations;
3855 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3856 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3857 S_028B90_ENABLE(gs_num_invocations > 0));
3858
3859 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3860 gs_state->vgt_esgs_ring_itemsize);
3861
3862 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3863
3864 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3865 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3866 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3867 radeon_emit(cs, va >> 8);
3868 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3869 } else {
3870 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3871 radeon_emit(cs, va >> 8);
3872 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3873 }
3874
3875 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3876 radeon_emit(cs, gs->config.rsrc1);
3877 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3878
3879 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3880 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3881 } else {
3882 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3883 radeon_emit(cs, va >> 8);
3884 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3885 radeon_emit(cs, gs->config.rsrc1);
3886 radeon_emit(cs, gs->config.rsrc2);
3887 }
3888
3889 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
3890 }
3891
3892 static void
3893 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
3894 struct radeon_cmdbuf *cs,
3895 struct radv_pipeline *pipeline,
3896 const struct radv_gs_state *gs_state,
3897 const struct radv_ngg_state *ngg_state)
3898 {
3899 struct radv_shader_variant *gs;
3900
3901 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3902 if (!gs)
3903 return;
3904
3905 if (gs->info.is_ngg)
3906 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state);
3907 else
3908 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
3909
3910 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
3911 gs->info.gs.vertices_out);
3912 }
3913
3914 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
3915 {
3916 uint32_t ps_input_cntl;
3917 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3918 ps_input_cntl = S_028644_OFFSET(offset);
3919 if (flat_shade)
3920 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3921 if (float16) {
3922 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
3923 S_028644_ATTR0_VALID(1);
3924 }
3925 } else {
3926 /* The input is a DEFAULT_VAL constant. */
3927 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3928 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3929 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3930 ps_input_cntl = S_028644_OFFSET(0x20) |
3931 S_028644_DEFAULT_VAL(offset);
3932 }
3933 return ps_input_cntl;
3934 }
3935
3936 static void
3937 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
3938 struct radv_pipeline *pipeline)
3939 {
3940 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3941 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3942 uint32_t ps_input_cntl[32];
3943
3944 unsigned ps_offset = 0;
3945
3946 if (ps->info.info.ps.prim_id_input) {
3947 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3948 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3949 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3950 ++ps_offset;
3951 }
3952 }
3953
3954 if (ps->info.info.ps.layer_input ||
3955 ps->info.info.needs_multiview_view_index) {
3956 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3957 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3958 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3959 else
3960 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
3961 ++ps_offset;
3962 }
3963
3964 if (ps->info.info.ps.has_pcoord) {
3965 unsigned val;
3966 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3967 ps_input_cntl[ps_offset] = val;
3968 ps_offset++;
3969 }
3970
3971 if (ps->info.info.ps.num_input_clips_culls) {
3972 unsigned vs_offset;
3973
3974 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3975 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3976 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3977 ++ps_offset;
3978 }
3979
3980 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3981 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
3982 ps->info.info.ps.num_input_clips_culls > 4) {
3983 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3984 ++ps_offset;
3985 }
3986 }
3987
3988 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3989 unsigned vs_offset;
3990 bool flat_shade;
3991 bool float16;
3992 if (!(ps->info.fs.input_mask & (1u << i)))
3993 continue;
3994
3995 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3996 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3997 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3998 ++ps_offset;
3999 continue;
4000 }
4001
4002 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
4003 float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset));
4004
4005 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4006 ++ps_offset;
4007 }
4008
4009 if (ps_offset) {
4010 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4011 for (unsigned i = 0; i < ps_offset; i++) {
4012 radeon_emit(ctx_cs, ps_input_cntl[i]);
4013 }
4014 }
4015 }
4016
4017 static uint32_t
4018 radv_compute_db_shader_control(const struct radv_device *device,
4019 const struct radv_pipeline *pipeline,
4020 const struct radv_shader_variant *ps)
4021 {
4022 unsigned z_order;
4023 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
4024 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4025 else
4026 z_order = V_02880C_LATE_Z;
4027
4028 bool disable_rbplus = device->physical_device->has_rbplus &&
4029 !device->physical_device->rbplus_allowed;
4030
4031 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4032 * but this appears to break Project Cars (DXVK). See
4033 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4034 */
4035 bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
4036
4037 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
4038 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
4039 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
4040 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4041 S_02880C_Z_ORDER(z_order) |
4042 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
4043 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
4044 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
4045 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
4046 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4047 }
4048
4049 static void
4050 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4051 struct radeon_cmdbuf *cs,
4052 struct radv_pipeline *pipeline)
4053 {
4054 struct radv_shader_variant *ps;
4055 uint64_t va;
4056 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4057
4058 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4059 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4060
4061 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4062 radeon_emit(cs, va >> 8);
4063 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4064 radeon_emit(cs, ps->config.rsrc1);
4065 radeon_emit(cs, ps->config.rsrc2);
4066
4067 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4068 radv_compute_db_shader_control(pipeline->device,
4069 pipeline, ps));
4070
4071 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4072 ps->config.spi_ps_input_ena);
4073
4074 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4075 ps->config.spi_ps_input_addr);
4076
4077 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4078 S_0286D8_NUM_INTERP(ps->info.fs.num_interp) |
4079 S_0286D8_PS_W32_EN(ps->info.info.wave_size == 32));
4080
4081 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4082
4083 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4084 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
4085 ps->info.info.ps.writes_stencil,
4086 ps->info.info.ps.writes_sample_mask));
4087
4088 if (pipeline->device->dfsm_allowed) {
4089 /* optimise this? */
4090 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4091 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4092 }
4093 }
4094
4095 static void
4096 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4097 struct radv_pipeline *pipeline)
4098 {
4099 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4100 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4101 return;
4102
4103 unsigned vtx_reuse_depth = 30;
4104 if (radv_pipeline_has_tess(pipeline) &&
4105 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4106 vtx_reuse_depth = 14;
4107 }
4108 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4109 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4110 }
4111
4112 static uint32_t
4113 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4114 {
4115 uint32_t stages = 0;
4116 if (radv_pipeline_has_tess(pipeline)) {
4117 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4118 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4119
4120 if (radv_pipeline_has_gs(pipeline))
4121 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4122 S_028B54_GS_EN(1);
4123 else if (radv_pipeline_has_ngg(pipeline))
4124 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4125 else
4126 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4127 } else if (radv_pipeline_has_gs(pipeline)) {
4128 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4129 S_028B54_GS_EN(1);
4130 } else if (radv_pipeline_has_ngg(pipeline)) {
4131 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4132 }
4133
4134 if (radv_pipeline_has_ngg(pipeline)) {
4135 stages |= S_028B54_PRIMGEN_EN(1);
4136 } else if (radv_pipeline_has_gs(pipeline)) {
4137 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4138 }
4139
4140 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4141 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4142
4143 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4144 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4145
4146 if (radv_pipeline_has_tess(pipeline))
4147 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.wave_size;
4148
4149 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4150 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.wave_size;
4151 if (pipeline->gs_copy_shader)
4152 vs_size = pipeline->gs_copy_shader->info.info.wave_size;
4153 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4154 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.info.wave_size;
4155 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4156 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.info.wave_size;
4157
4158 if (radv_pipeline_has_ngg(pipeline))
4159 gs_size = vs_size;
4160
4161 /* legacy GS only supports Wave64 */
4162 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4163 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4164 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4165 }
4166
4167 return stages;
4168 }
4169
4170 static uint32_t
4171 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4172 {
4173 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4174 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4175
4176 if (!discard_rectangle_info)
4177 return 0xffff;
4178
4179 unsigned mask = 0;
4180
4181 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4182 /* Interpret i as a bitmask, and then set the bit in the mask if
4183 * that combination of rectangles in which the pixel is contained
4184 * should pass the cliprect test. */
4185 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4186
4187 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4188 !relevant_subset)
4189 continue;
4190
4191 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4192 relevant_subset)
4193 continue;
4194
4195 mask |= 1u << i;
4196 }
4197
4198 return mask;
4199 }
4200
4201 static void
4202 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4203 struct radv_pipeline *pipeline,
4204 const struct radv_tessellation_state *tess,
4205 const struct radv_gs_state *gs_state)
4206 {
4207 bool break_wave_at_eoi = false;
4208 unsigned primgroup_size;
4209 unsigned vertgroup_size;
4210
4211 if (radv_pipeline_has_tess(pipeline)) {
4212 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4213 vertgroup_size = 0;
4214 } else if (radv_pipeline_has_gs(pipeline)) {
4215 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4216 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4217 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4218 } else {
4219 primgroup_size = 128; /* recommended without a GS and tess */
4220 vertgroup_size = 0;
4221 }
4222
4223 if (radv_pipeline_has_tess(pipeline)) {
4224 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4225 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4226 break_wave_at_eoi = true;
4227 }
4228
4229 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4230 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4231 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4232 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4233 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4234 }
4235
4236 static void
4237 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4238 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4239 const struct radv_graphics_pipeline_create_info *extra,
4240 const struct radv_blend_state *blend,
4241 const struct radv_tessellation_state *tess,
4242 const struct radv_gs_state *gs,
4243 const struct radv_ngg_state *ngg,
4244 unsigned prim, unsigned gs_out)
4245 {
4246 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4247 struct radeon_cmdbuf *cs = &pipeline->cs;
4248
4249 cs->max_dw = 64;
4250 ctx_cs->max_dw = 256;
4251 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4252 ctx_cs->buf = cs->buf + cs->max_dw;
4253
4254 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4255 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4256 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4257 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4258 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4259 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
4260 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
4261 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);
4262 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4263 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4264 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4265 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4266
4267 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4268 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
4269
4270 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4271 S_0286E8_WAVES(pipeline->max_waves) |
4272 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4273
4274 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4275
4276 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4277 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4278 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4279 } else {
4280 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4281 }
4282 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4283
4284 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4285
4286 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4287
4288 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4289 assert(cs->cdw <= cs->max_dw);
4290 }
4291
4292 static struct radv_ia_multi_vgt_param_helpers
4293 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4294 const struct radv_tessellation_state *tess,
4295 uint32_t prim)
4296 {
4297 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4298 const struct radv_device *device = pipeline->device;
4299
4300 if (radv_pipeline_has_tess(pipeline))
4301 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4302 else if (radv_pipeline_has_gs(pipeline))
4303 ia_multi_vgt_param.primgroup_size = 64;
4304 else
4305 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4306
4307 /* GS requirement. */
4308 ia_multi_vgt_param.partial_es_wave = false;
4309 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4310 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4311 ia_multi_vgt_param.partial_es_wave = true;
4312
4313 ia_multi_vgt_param.wd_switch_on_eop = false;
4314 if (device->physical_device->rad_info.chip_class >= GFX7) {
4315 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4316 * 4 shader engines. Set 1 to pass the assertion below.
4317 * The other cases are hardware requirements. */
4318 if (device->physical_device->rad_info.max_se < 4 ||
4319 prim == V_008958_DI_PT_POLYGON ||
4320 prim == V_008958_DI_PT_LINELOOP ||
4321 prim == V_008958_DI_PT_TRIFAN ||
4322 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4323 (pipeline->graphics.prim_restart_enable &&
4324 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4325 (prim != V_008958_DI_PT_POINTLIST &&
4326 prim != V_008958_DI_PT_LINESTRIP))))
4327 ia_multi_vgt_param.wd_switch_on_eop = true;
4328 }
4329
4330 ia_multi_vgt_param.ia_switch_on_eoi = false;
4331 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
4332 ia_multi_vgt_param.ia_switch_on_eoi = true;
4333 if (radv_pipeline_has_gs(pipeline) &&
4334 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
4335 ia_multi_vgt_param.ia_switch_on_eoi = true;
4336 if (radv_pipeline_has_tess(pipeline)) {
4337 /* SWITCH_ON_EOI must be set if PrimID is used. */
4338 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4339 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4340 ia_multi_vgt_param.ia_switch_on_eoi = true;
4341 }
4342
4343 ia_multi_vgt_param.partial_vs_wave = false;
4344 if (radv_pipeline_has_tess(pipeline)) {
4345 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4346 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4347 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4348 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4349 radv_pipeline_has_gs(pipeline))
4350 ia_multi_vgt_param.partial_vs_wave = true;
4351 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4352 if (device->has_distributed_tess) {
4353 if (radv_pipeline_has_gs(pipeline)) {
4354 if (device->physical_device->rad_info.chip_class <= GFX8)
4355 ia_multi_vgt_param.partial_es_wave = true;
4356 } else {
4357 ia_multi_vgt_param.partial_vs_wave = true;
4358 }
4359 }
4360 }
4361
4362 /* Workaround for a VGT hang when strip primitive types are used with
4363 * primitive restart.
4364 */
4365 if (pipeline->graphics.prim_restart_enable &&
4366 (prim == V_008958_DI_PT_LINESTRIP ||
4367 prim == V_008958_DI_PT_TRISTRIP ||
4368 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4369 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4370 ia_multi_vgt_param.partial_vs_wave = true;
4371 }
4372
4373 if (radv_pipeline_has_gs(pipeline)) {
4374 /* On these chips there is the possibility of a hang if the
4375 * pipeline uses a GS and partial_vs_wave is not set.
4376 *
4377 * This mostly does not hit 4-SE chips, as those typically set
4378 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4379 * with GS due to another workaround.
4380 *
4381 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4382 */
4383 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4384 device->physical_device->rad_info.family == CHIP_FIJI ||
4385 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4386 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4387 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4388 device->physical_device->rad_info.family == CHIP_VEGAM) {
4389 ia_multi_vgt_param.partial_vs_wave = true;
4390 }
4391 }
4392
4393 ia_multi_vgt_param.base =
4394 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4395 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4396 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4397 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4398 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4399
4400 return ia_multi_vgt_param;
4401 }
4402
4403
4404 static void
4405 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4406 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4407 {
4408 const VkPipelineVertexInputStateCreateInfo *vi_info =
4409 pCreateInfo->pVertexInputState;
4410 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4411
4412 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4413 const VkVertexInputAttributeDescription *desc =
4414 &vi_info->pVertexAttributeDescriptions[i];
4415 unsigned loc = desc->location;
4416 const struct vk_format_description *format_desc;
4417
4418 format_desc = vk_format_description(desc->format);
4419
4420 velems->format_size[loc] = format_desc->block.bits / 8;
4421 }
4422
4423 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4424 const VkVertexInputBindingDescription *desc =
4425 &vi_info->pVertexBindingDescriptions[i];
4426
4427 pipeline->binding_stride[desc->binding] = desc->stride;
4428 pipeline->num_vertex_bindings =
4429 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4430 }
4431 }
4432
4433 static struct radv_shader_variant *
4434 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4435 {
4436 int i;
4437
4438 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4439 struct radv_shader_variant *shader =
4440 radv_get_shader(pipeline, i);
4441
4442 if (shader && shader->info.info.so.num_outputs > 0)
4443 return shader;
4444 }
4445
4446 return NULL;
4447 }
4448
4449 static VkResult
4450 radv_pipeline_init(struct radv_pipeline *pipeline,
4451 struct radv_device *device,
4452 struct radv_pipeline_cache *cache,
4453 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4454 const struct radv_graphics_pipeline_create_info *extra)
4455 {
4456 VkResult result;
4457 bool has_view_index = false;
4458
4459 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4460 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4461 if (subpass->view_mask)
4462 has_view_index = true;
4463
4464 pipeline->device = device;
4465 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4466 assert(pipeline->layout);
4467
4468 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4469
4470 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4471 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4472 radv_init_feedback(creation_feedback);
4473
4474 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4475
4476 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4477 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4478 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4479 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4480 pStages[stage] = &pCreateInfo->pStages[i];
4481 if(creation_feedback)
4482 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4483 }
4484
4485 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4486 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4487
4488 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4489 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4490 uint32_t gs_out;
4491 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4492
4493 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4494
4495 if (radv_pipeline_has_gs(pipeline)) {
4496 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4497 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4498 } else if (radv_pipeline_has_tess(pipeline)) {
4499 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4500 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4501 else
4502 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4503 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4504 } else {
4505 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4506 }
4507 if (extra && extra->use_rectlist) {
4508 prim = V_008958_DI_PT_RECTLIST;
4509 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4510 pipeline->graphics.can_use_guardband = true;
4511 if (radv_pipeline_has_ngg(pipeline))
4512 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4513 }
4514 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4515 /* prim vertex count will need TESS changes */
4516 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4517
4518 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4519
4520 /* Ensure that some export memory is always allocated, for two reasons:
4521 *
4522 * 1) Correctness: The hardware ignores the EXEC mask if no export
4523 * memory is allocated, so KILL and alpha test do not work correctly
4524 * without this.
4525 * 2) Performance: Every shader needs at least a NULL export, even when
4526 * it writes no color/depth output. The NULL export instruction
4527 * stalls without this setting.
4528 *
4529 * Don't add this to CB_SHADER_MASK.
4530 *
4531 * GFX10 supports pixel shaders without exports by setting both the
4532 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4533 * instructions if any are present.
4534 */
4535 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4536 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4537 ps->info.fs.can_discard) &&
4538 !blend.spi_shader_col_format) {
4539 if (!ps->info.info.ps.writes_z &&
4540 !ps->info.info.ps.writes_stencil &&
4541 !ps->info.info.ps.writes_sample_mask)
4542 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4543 }
4544
4545 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4546 if (pipeline->shaders[i]) {
4547 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4548 }
4549 }
4550
4551 struct radv_ngg_state ngg = {0};
4552 struct radv_gs_state gs = {0};
4553
4554 if (radv_pipeline_has_ngg(pipeline)) {
4555 ngg = calculate_ngg_info(pCreateInfo, pipeline);
4556 } else if (radv_pipeline_has_gs(pipeline)) {
4557 gs = calculate_gs_info(pCreateInfo, pipeline);
4558 calculate_gs_ring_sizes(pipeline, &gs);
4559 }
4560
4561 struct radv_tessellation_state tess = {0};
4562 if (radv_pipeline_has_tess(pipeline)) {
4563 if (prim == V_008958_DI_PT_PATCH) {
4564 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4565 pipeline->graphics.prim_vertex_count.incr = 1;
4566 }
4567 tess = calculate_tess_state(pipeline, pCreateInfo);
4568 }
4569
4570 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4571
4572 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4573
4574 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4575 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4576
4577 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4578 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4579 if (loc->sgpr_idx != -1) {
4580 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4581 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4582 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
4583 pipeline->graphics.vtx_emit_num = 3;
4584 else
4585 pipeline->graphics.vtx_emit_num = 2;
4586 }
4587
4588 /* Find the last vertex shader stage that eventually uses streamout. */
4589 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4590
4591 result = radv_pipeline_scratch_init(device, pipeline);
4592 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, &ngg, prim, gs_out);
4593
4594 return result;
4595 }
4596
4597 VkResult
4598 radv_graphics_pipeline_create(
4599 VkDevice _device,
4600 VkPipelineCache _cache,
4601 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4602 const struct radv_graphics_pipeline_create_info *extra,
4603 const VkAllocationCallbacks *pAllocator,
4604 VkPipeline *pPipeline)
4605 {
4606 RADV_FROM_HANDLE(radv_device, device, _device);
4607 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4608 struct radv_pipeline *pipeline;
4609 VkResult result;
4610
4611 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4612 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4613 if (pipeline == NULL)
4614 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4615
4616 result = radv_pipeline_init(pipeline, device, cache,
4617 pCreateInfo, extra);
4618 if (result != VK_SUCCESS) {
4619 radv_pipeline_destroy(device, pipeline, pAllocator);
4620 return result;
4621 }
4622
4623 *pPipeline = radv_pipeline_to_handle(pipeline);
4624
4625 return VK_SUCCESS;
4626 }
4627
4628 VkResult radv_CreateGraphicsPipelines(
4629 VkDevice _device,
4630 VkPipelineCache pipelineCache,
4631 uint32_t count,
4632 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4633 const VkAllocationCallbacks* pAllocator,
4634 VkPipeline* pPipelines)
4635 {
4636 VkResult result = VK_SUCCESS;
4637 unsigned i = 0;
4638
4639 for (; i < count; i++) {
4640 VkResult r;
4641 r = radv_graphics_pipeline_create(_device,
4642 pipelineCache,
4643 &pCreateInfos[i],
4644 NULL, pAllocator, &pPipelines[i]);
4645 if (r != VK_SUCCESS) {
4646 result = r;
4647 pPipelines[i] = VK_NULL_HANDLE;
4648 }
4649 }
4650
4651 return result;
4652 }
4653
4654
4655 static void
4656 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4657 {
4658 struct radv_shader_variant *compute_shader;
4659 struct radv_device *device = pipeline->device;
4660 unsigned threads_per_threadgroup;
4661 unsigned threadgroups_per_cu = 1;
4662 unsigned waves_per_threadgroup;
4663 unsigned max_waves_per_sh = 0;
4664 uint64_t va;
4665
4666 pipeline->cs.buf = malloc(20 * 4);
4667 pipeline->cs.max_dw = 20;
4668
4669 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4670 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4671
4672 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4673 radeon_emit(&pipeline->cs, va >> 8);
4674 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4675
4676 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4677 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4678 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4679
4680 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4681 S_00B860_WAVES(pipeline->max_waves) |
4682 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4683
4684 /* Calculate best compute resource limits. */
4685 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4686 compute_shader->info.cs.block_size[1] *
4687 compute_shader->info.cs.block_size[2];
4688 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4689 device->physical_device->cs_wave_size);
4690
4691 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4692 waves_per_threadgroup == 1)
4693 threadgroups_per_cu = 2;
4694
4695 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4696 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4697 waves_per_threadgroup,
4698 max_waves_per_sh,
4699 threadgroups_per_cu));
4700
4701 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4702 radeon_emit(&pipeline->cs,
4703 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4704 radeon_emit(&pipeline->cs,
4705 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4706 radeon_emit(&pipeline->cs,
4707 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4708
4709 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4710 }
4711
4712 static VkResult radv_compute_pipeline_create(
4713 VkDevice _device,
4714 VkPipelineCache _cache,
4715 const VkComputePipelineCreateInfo* pCreateInfo,
4716 const VkAllocationCallbacks* pAllocator,
4717 VkPipeline* pPipeline)
4718 {
4719 RADV_FROM_HANDLE(radv_device, device, _device);
4720 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4721 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4722 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4723 struct radv_pipeline *pipeline;
4724 VkResult result;
4725
4726 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4727 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4728 if (pipeline == NULL)
4729 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4730
4731 pipeline->device = device;
4732 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4733 assert(pipeline->layout);
4734
4735 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4736 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4737 radv_init_feedback(creation_feedback);
4738
4739 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4740 if (creation_feedback)
4741 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4742
4743 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4744 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4745
4746 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4747 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4748 result = radv_pipeline_scratch_init(device, pipeline);
4749 if (result != VK_SUCCESS) {
4750 radv_pipeline_destroy(device, pipeline, pAllocator);
4751 return result;
4752 }
4753
4754 radv_compute_generate_pm4(pipeline);
4755
4756 *pPipeline = radv_pipeline_to_handle(pipeline);
4757
4758 return VK_SUCCESS;
4759 }
4760
4761 VkResult radv_CreateComputePipelines(
4762 VkDevice _device,
4763 VkPipelineCache pipelineCache,
4764 uint32_t count,
4765 const VkComputePipelineCreateInfo* pCreateInfos,
4766 const VkAllocationCallbacks* pAllocator,
4767 VkPipeline* pPipelines)
4768 {
4769 VkResult result = VK_SUCCESS;
4770
4771 unsigned i = 0;
4772 for (; i < count; i++) {
4773 VkResult r;
4774 r = radv_compute_pipeline_create(_device, pipelineCache,
4775 &pCreateInfos[i],
4776 pAllocator, &pPipelines[i]);
4777 if (r != VK_SUCCESS) {
4778 result = r;
4779 pPipelines[i] = VK_NULL_HANDLE;
4780 }
4781 }
4782
4783 return result;
4784 }
4785
4786
4787 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
4788 {
4789 uint32_t ret = 0;
4790 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4791 if (pipeline->shaders[i])
4792 ret += i == MESA_SHADER_GEOMETRY ? 2u : 1u;
4793
4794 }
4795 return ret;
4796 }
4797
4798 static struct radv_shader_variant *
4799 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
4800 {
4801 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4802 if (!pipeline->shaders[i])
4803 continue;
4804 if (!index) {
4805 *stage = i;
4806 return pipeline->shaders[i];
4807 }
4808
4809 --index;
4810
4811 if (i == MESA_SHADER_GEOMETRY) {
4812 if (!index) {
4813 *stage = i;
4814 return pipeline->gs_copy_shader;
4815 }
4816 --index;
4817 }
4818 }
4819
4820 *stage = -1;
4821 return NULL;
4822 }
4823
4824 /* Basically strlcpy (which does not exist on linux) specialized for
4825 * descriptions. */
4826 static void desc_copy(char *desc, const char *src) {
4827 int len = strlen(src);
4828 assert(len < VK_MAX_DESCRIPTION_SIZE);
4829 memcpy(desc, src, len);
4830 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
4831 }
4832
4833 VkResult radv_GetPipelineExecutablePropertiesKHR(
4834 VkDevice _device,
4835 const VkPipelineInfoKHR* pPipelineInfo,
4836 uint32_t* pExecutableCount,
4837 VkPipelineExecutablePropertiesKHR* pProperties)
4838 {
4839 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
4840 const uint32_t total_count = radv_get_executable_count(pipeline);
4841
4842 if (!pProperties) {
4843 *pExecutableCount = total_count;
4844 return VK_SUCCESS;
4845 }
4846
4847 const uint32_t count = MIN2(total_count, *pExecutableCount);
4848 for (unsigned i = 0, executable_idx = 0;
4849 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
4850 if (!pipeline->shaders[i])
4851 continue;
4852 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
4853 const char *name = NULL;
4854 const char *description = NULL;
4855 switch(i) {
4856 case MESA_SHADER_VERTEX:
4857 name = "Vertex Shader";
4858 description = "Vulkan Vertex Shader";
4859 break;
4860 case MESA_SHADER_TESS_CTRL:
4861 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
4862 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
4863 name = "Vertex + Tessellation Control Shaders";
4864 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
4865 } else {
4866 name = "Tessellation Control Shader";
4867 description = "Vulkan Tessellation Control Shader";
4868 }
4869 break;
4870 case MESA_SHADER_TESS_EVAL:
4871 name = "Tessellation Evaluation Shader";
4872 description = "Vulkan Tessellation Evaluation Shader";
4873 break;
4874 case MESA_SHADER_GEOMETRY:
4875 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
4876 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
4877 name = "Tessellation Evaluation + Geometry Shaders";
4878 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
4879 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
4880 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
4881 name = "Vertex + Geometry Shader";
4882 description = "Combined Vulkan Vertex and Geometry Shaders";
4883 } else {
4884 name = "Geometry Shader";
4885 description = "Vulkan Geometry Shader";
4886 }
4887 break;
4888 case MESA_SHADER_FRAGMENT:
4889 name = "Fragment Shader";
4890 description = "Vulkan Fragment Shader";
4891 break;
4892 case MESA_SHADER_COMPUTE:
4893 name = "Compute Shader";
4894 description = "Vulkan Compute Shader";
4895 break;
4896 }
4897
4898 desc_copy(pProperties[executable_idx].name, name);
4899 desc_copy(pProperties[executable_idx].description, description);
4900
4901 ++executable_idx;
4902 if (i == MESA_SHADER_GEOMETRY) {
4903 assert(pipeline->gs_copy_shader);
4904 if (executable_idx >= count)
4905 break;
4906
4907 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
4908 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
4909 desc_copy(pProperties[executable_idx].description,
4910 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
4911
4912 ++executable_idx;
4913 }
4914 }
4915
4916 for (unsigned i = 0; i < count; ++i)
4917 pProperties[i].subgroupSize = 64;
4918
4919 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
4920 *pExecutableCount = count;
4921 return result;
4922 }
4923
4924 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
4925 {
4926 size_t total_size = strlen(src) + 1;
4927
4928 if (!data) {
4929 *data_size = total_size;
4930 return VK_SUCCESS;
4931 }
4932
4933 size_t size = MIN2(total_size, *data_size);
4934
4935 memcpy(data, src, size);
4936 if (size)
4937 *((char*)data + size - 1) = 0;
4938 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
4939 }
4940
4941 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
4942 VkDevice device,
4943 const VkPipelineExecutableInfoKHR* pExecutableInfo,
4944 uint32_t* pInternalRepresentationCount,
4945 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
4946 {
4947 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
4948 gl_shader_stage stage;
4949 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
4950
4951 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
4952 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
4953 VkResult result = VK_SUCCESS;
4954 /* optimized NIR */
4955 if (p < end) {
4956 p->isText = true;
4957 desc_copy(p->name, "NIR Shader(s)");
4958 desc_copy(p->description, "The optimized NIR shader(s)");
4959 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
4960 result = VK_INCOMPLETE;
4961 }
4962 ++p;
4963
4964 /* LLVM IR */
4965 if (p < end) {
4966 p->isText = true;
4967 desc_copy(p->name, "LLVM IR");
4968 desc_copy(p->description, "The LLVM IR after some optimizations");
4969 if (radv_copy_representation(p->pData, &p->dataSize, shader->llvm_ir_string) != VK_SUCCESS)
4970 result = VK_INCOMPLETE;
4971 }
4972 ++p;
4973
4974 /* Disassembler */
4975 if (p < end) {
4976 p->isText = true;
4977 desc_copy(p->name, "Assembly");
4978 desc_copy(p->description, "Final Assembly");
4979 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
4980 result = VK_INCOMPLETE;
4981 }
4982 ++p;
4983
4984 if (!pInternalRepresentations)
4985 *pInternalRepresentationCount = p - pInternalRepresentations;
4986 else if(p > end) {
4987 result = VK_INCOMPLETE;
4988 *pInternalRepresentationCount = end - pInternalRepresentations;
4989 } else {
4990 *pInternalRepresentationCount = p - pInternalRepresentations;
4991 }
4992
4993 return result;
4994 }