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aco,radv: rename record_llvm_ir/llvm_ir_string to record_ir/ir_string
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
94 {
95 struct radv_shader_variant *variant = NULL;
96 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
97 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
98 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
99 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
100 else if (pipeline->shaders[MESA_SHADER_VERTEX])
101 variant = pipeline->shaders[MESA_SHADER_VERTEX];
102 else
103 return false;
104 return variant->info.is_ngg;
105 }
106
107 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
108 {
109 if (!radv_pipeline_has_gs(pipeline))
110 return false;
111
112 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
113 * On GFX10, it might be required in rare cases if it's not possible to
114 * enable NGG.
115 */
116 if (radv_pipeline_has_ngg(pipeline))
117 return false;
118
119 assert(pipeline->gs_copy_shader);
120 return true;
121 }
122
123 static void
124 radv_pipeline_destroy(struct radv_device *device,
125 struct radv_pipeline *pipeline,
126 const VkAllocationCallbacks* allocator)
127 {
128 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
129 if (pipeline->shaders[i])
130 radv_shader_variant_destroy(device, pipeline->shaders[i]);
131
132 if (pipeline->gs_copy_shader)
133 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
134
135 if(pipeline->cs.buf)
136 free(pipeline->cs.buf);
137 vk_free2(&device->alloc, allocator, pipeline);
138 }
139
140 void radv_DestroyPipeline(
141 VkDevice _device,
142 VkPipeline _pipeline,
143 const VkAllocationCallbacks* pAllocator)
144 {
145 RADV_FROM_HANDLE(radv_device, device, _device);
146 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
147
148 if (!_pipeline)
149 return;
150
151 radv_pipeline_destroy(device, pipeline, pAllocator);
152 }
153
154 static uint32_t get_hash_flags(struct radv_device *device)
155 {
156 uint32_t hash_flags = 0;
157
158 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
159 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
160 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
161 hash_flags |= RADV_HASH_SHADER_NO_NGG;
162 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
163 hash_flags |= RADV_HASH_SHADER_SISCHED;
164 if (device->physical_device->cs_wave_size == 32)
165 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
166 if (device->physical_device->ps_wave_size == 32)
167 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
168 if (device->physical_device->ge_wave_size == 32)
169 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
170 if (device->physical_device->use_aco)
171 hash_flags |= RADV_HASH_SHADER_ACO;
172 return hash_flags;
173 }
174
175 static VkResult
176 radv_pipeline_scratch_init(struct radv_device *device,
177 struct radv_pipeline *pipeline)
178 {
179 unsigned scratch_bytes_per_wave = 0;
180 unsigned max_waves = 0;
181 unsigned min_waves = 1;
182
183 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
184 if (pipeline->shaders[i]) {
185 unsigned max_stage_waves = device->scratch_waves;
186
187 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
188 pipeline->shaders[i]->config.scratch_bytes_per_wave);
189
190 max_stage_waves = MIN2(max_stage_waves,
191 4 * device->physical_device->rad_info.num_good_compute_units *
192 (256 / pipeline->shaders[i]->config.num_vgprs));
193 max_waves = MAX2(max_waves, max_stage_waves);
194 }
195 }
196
197 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
198 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
199 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
200 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
201 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
202 }
203
204 if (scratch_bytes_per_wave)
205 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
206
207 if (scratch_bytes_per_wave && max_waves < min_waves) {
208 /* Not really true at this moment, but will be true on first
209 * execution. Avoid having hanging shaders. */
210 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
211 }
212 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
213 pipeline->max_waves = max_waves;
214 return VK_SUCCESS;
215 }
216
217 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
218 {
219 switch (op) {
220 case VK_LOGIC_OP_CLEAR:
221 return V_028808_ROP3_CLEAR;
222 case VK_LOGIC_OP_AND:
223 return V_028808_ROP3_AND;
224 case VK_LOGIC_OP_AND_REVERSE:
225 return V_028808_ROP3_AND_REVERSE;
226 case VK_LOGIC_OP_COPY:
227 return V_028808_ROP3_COPY;
228 case VK_LOGIC_OP_AND_INVERTED:
229 return V_028808_ROP3_AND_INVERTED;
230 case VK_LOGIC_OP_NO_OP:
231 return V_028808_ROP3_NO_OP;
232 case VK_LOGIC_OP_XOR:
233 return V_028808_ROP3_XOR;
234 case VK_LOGIC_OP_OR:
235 return V_028808_ROP3_OR;
236 case VK_LOGIC_OP_NOR:
237 return V_028808_ROP3_NOR;
238 case VK_LOGIC_OP_EQUIVALENT:
239 return V_028808_ROP3_EQUIVALENT;
240 case VK_LOGIC_OP_INVERT:
241 return V_028808_ROP3_INVERT;
242 case VK_LOGIC_OP_OR_REVERSE:
243 return V_028808_ROP3_OR_REVERSE;
244 case VK_LOGIC_OP_COPY_INVERTED:
245 return V_028808_ROP3_COPY_INVERTED;
246 case VK_LOGIC_OP_OR_INVERTED:
247 return V_028808_ROP3_OR_INVERTED;
248 case VK_LOGIC_OP_NAND:
249 return V_028808_ROP3_NAND;
250 case VK_LOGIC_OP_SET:
251 return V_028808_ROP3_SET;
252 default:
253 unreachable("Unhandled logic op");
254 }
255 }
256
257
258 static uint32_t si_translate_blend_function(VkBlendOp op)
259 {
260 switch (op) {
261 case VK_BLEND_OP_ADD:
262 return V_028780_COMB_DST_PLUS_SRC;
263 case VK_BLEND_OP_SUBTRACT:
264 return V_028780_COMB_SRC_MINUS_DST;
265 case VK_BLEND_OP_REVERSE_SUBTRACT:
266 return V_028780_COMB_DST_MINUS_SRC;
267 case VK_BLEND_OP_MIN:
268 return V_028780_COMB_MIN_DST_SRC;
269 case VK_BLEND_OP_MAX:
270 return V_028780_COMB_MAX_DST_SRC;
271 default:
272 return 0;
273 }
274 }
275
276 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
277 {
278 switch (factor) {
279 case VK_BLEND_FACTOR_ZERO:
280 return V_028780_BLEND_ZERO;
281 case VK_BLEND_FACTOR_ONE:
282 return V_028780_BLEND_ONE;
283 case VK_BLEND_FACTOR_SRC_COLOR:
284 return V_028780_BLEND_SRC_COLOR;
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
286 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
287 case VK_BLEND_FACTOR_DST_COLOR:
288 return V_028780_BLEND_DST_COLOR;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
290 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
291 case VK_BLEND_FACTOR_SRC_ALPHA:
292 return V_028780_BLEND_SRC_ALPHA;
293 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
294 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
295 case VK_BLEND_FACTOR_DST_ALPHA:
296 return V_028780_BLEND_DST_ALPHA;
297 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
298 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
299 case VK_BLEND_FACTOR_CONSTANT_COLOR:
300 return V_028780_BLEND_CONSTANT_COLOR;
301 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
302 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
303 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
304 return V_028780_BLEND_CONSTANT_ALPHA;
305 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
307 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
308 return V_028780_BLEND_SRC_ALPHA_SATURATE;
309 case VK_BLEND_FACTOR_SRC1_COLOR:
310 return V_028780_BLEND_SRC1_COLOR;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
312 return V_028780_BLEND_INV_SRC1_COLOR;
313 case VK_BLEND_FACTOR_SRC1_ALPHA:
314 return V_028780_BLEND_SRC1_ALPHA;
315 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
316 return V_028780_BLEND_INV_SRC1_ALPHA;
317 default:
318 return 0;
319 }
320 }
321
322 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
323 {
324 switch (op) {
325 case VK_BLEND_OP_ADD:
326 return V_028760_OPT_COMB_ADD;
327 case VK_BLEND_OP_SUBTRACT:
328 return V_028760_OPT_COMB_SUBTRACT;
329 case VK_BLEND_OP_REVERSE_SUBTRACT:
330 return V_028760_OPT_COMB_REVSUBTRACT;
331 case VK_BLEND_OP_MIN:
332 return V_028760_OPT_COMB_MIN;
333 case VK_BLEND_OP_MAX:
334 return V_028760_OPT_COMB_MAX;
335 default:
336 return V_028760_OPT_COMB_BLEND_DISABLED;
337 }
338 }
339
340 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
341 {
342 switch (factor) {
343 case VK_BLEND_FACTOR_ZERO:
344 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
345 case VK_BLEND_FACTOR_ONE:
346 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
347 case VK_BLEND_FACTOR_SRC_COLOR:
348 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
349 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
350 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
351 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
352 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
353 case VK_BLEND_FACTOR_SRC_ALPHA:
354 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
355 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
356 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
359 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
360 default:
361 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
362 }
363 }
364
365 /**
366 * Get rid of DST in the blend factors by commuting the operands:
367 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
368 */
369 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
370 unsigned *dst_factor, unsigned expected_dst,
371 unsigned replacement_src)
372 {
373 if (*src_factor == expected_dst &&
374 *dst_factor == VK_BLEND_FACTOR_ZERO) {
375 *src_factor = VK_BLEND_FACTOR_ZERO;
376 *dst_factor = replacement_src;
377
378 /* Commuting the operands requires reversing subtractions. */
379 if (*func == VK_BLEND_OP_SUBTRACT)
380 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
381 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
382 *func = VK_BLEND_OP_SUBTRACT;
383 }
384 }
385
386 static bool si_blend_factor_uses_dst(unsigned factor)
387 {
388 return factor == VK_BLEND_FACTOR_DST_COLOR ||
389 factor == VK_BLEND_FACTOR_DST_ALPHA ||
390 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
391 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
392 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
393 }
394
395 static bool is_dual_src(VkBlendFactor factor)
396 {
397 switch (factor) {
398 case VK_BLEND_FACTOR_SRC1_COLOR:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
400 case VK_BLEND_FACTOR_SRC1_ALPHA:
401 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
402 return true;
403 default:
404 return false;
405 }
406 }
407
408 static unsigned si_choose_spi_color_format(VkFormat vk_format,
409 bool blend_enable,
410 bool blend_need_alpha)
411 {
412 const struct vk_format_description *desc = vk_format_description(vk_format);
413 unsigned format, ntype, swap;
414
415 /* Alpha is needed for alpha-to-coverage.
416 * Blending may be with or without alpha.
417 */
418 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
419 unsigned alpha = 0; /* exports alpha, but may not support blending */
420 unsigned blend = 0; /* supports blending, but may not export alpha */
421 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
422
423 format = radv_translate_colorformat(vk_format);
424 ntype = radv_translate_color_numformat(vk_format, desc,
425 vk_format_get_first_non_void_channel(vk_format));
426 swap = radv_translate_colorswap(vk_format, false);
427
428 /* Choose the SPI color formats. These are required values for Stoney/RB+.
429 * Other chips have multiple choices, though they are not necessarily better.
430 */
431 switch (format) {
432 case V_028C70_COLOR_5_6_5:
433 case V_028C70_COLOR_1_5_5_5:
434 case V_028C70_COLOR_5_5_5_1:
435 case V_028C70_COLOR_4_4_4_4:
436 case V_028C70_COLOR_10_11_11:
437 case V_028C70_COLOR_11_11_10:
438 case V_028C70_COLOR_8:
439 case V_028C70_COLOR_8_8:
440 case V_028C70_COLOR_8_8_8_8:
441 case V_028C70_COLOR_10_10_10_2:
442 case V_028C70_COLOR_2_10_10_10:
443 if (ntype == V_028C70_NUMBER_UINT)
444 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
445 else if (ntype == V_028C70_NUMBER_SINT)
446 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
447 else
448 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
449 break;
450
451 case V_028C70_COLOR_16:
452 case V_028C70_COLOR_16_16:
453 case V_028C70_COLOR_16_16_16_16:
454 if (ntype == V_028C70_NUMBER_UNORM ||
455 ntype == V_028C70_NUMBER_SNORM) {
456 /* UNORM16 and SNORM16 don't support blending */
457 if (ntype == V_028C70_NUMBER_UNORM)
458 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
459 else
460 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
461
462 /* Use 32 bits per channel for blending. */
463 if (format == V_028C70_COLOR_16) {
464 if (swap == V_028C70_SWAP_STD) { /* R */
465 blend = V_028714_SPI_SHADER_32_R;
466 blend_alpha = V_028714_SPI_SHADER_32_AR;
467 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
468 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
469 else
470 assert(0);
471 } else if (format == V_028C70_COLOR_16_16) {
472 if (swap == V_028C70_SWAP_STD) { /* RG */
473 blend = V_028714_SPI_SHADER_32_GR;
474 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
475 } else if (swap == V_028C70_SWAP_ALT) /* RA */
476 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
477 else
478 assert(0);
479 } else /* 16_16_16_16 */
480 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
481 } else if (ntype == V_028C70_NUMBER_UINT)
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
483 else if (ntype == V_028C70_NUMBER_SINT)
484 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
485 else if (ntype == V_028C70_NUMBER_FLOAT)
486 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
487 else
488 assert(0);
489 break;
490
491 case V_028C70_COLOR_32:
492 if (swap == V_028C70_SWAP_STD) { /* R */
493 blend = normal = V_028714_SPI_SHADER_32_R;
494 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
495 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
496 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
497 else
498 assert(0);
499 break;
500
501 case V_028C70_COLOR_32_32:
502 if (swap == V_028C70_SWAP_STD) { /* RG */
503 blend = normal = V_028714_SPI_SHADER_32_GR;
504 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
505 } else if (swap == V_028C70_SWAP_ALT) /* RA */
506 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
507 else
508 assert(0);
509 break;
510
511 case V_028C70_COLOR_32_32_32_32:
512 case V_028C70_COLOR_8_24:
513 case V_028C70_COLOR_24_8:
514 case V_028C70_COLOR_X24_8_32_FLOAT:
515 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
516 break;
517
518 default:
519 unreachable("unhandled blend format");
520 }
521
522 if (blend_enable && blend_need_alpha)
523 return blend_alpha;
524 else if(blend_need_alpha)
525 return alpha;
526 else if(blend_enable)
527 return blend;
528 else
529 return normal;
530 }
531
532 static void
533 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
534 const VkGraphicsPipelineCreateInfo *pCreateInfo,
535 struct radv_blend_state *blend)
536 {
537 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
538 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
539 unsigned col_format = 0;
540 unsigned num_targets;
541
542 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
543 unsigned cf;
544
545 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
546 cf = V_028714_SPI_SHADER_ZERO;
547 } else {
548 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
549 bool blend_enable =
550 blend->blend_enable_4bit & (0xfu << (i * 4));
551
552 cf = si_choose_spi_color_format(attachment->format,
553 blend_enable,
554 blend->need_src_alpha & (1 << i));
555 }
556
557 col_format |= cf << (4 * i);
558 }
559
560 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
561 /* When a subpass doesn't have any color attachments, write the
562 * alpha channel of MRT0 when alpha coverage is enabled because
563 * the depth attachment needs it.
564 */
565 col_format |= V_028714_SPI_SHADER_32_AR;
566 }
567
568 /* If the i-th target format is set, all previous target formats must
569 * be non-zero to avoid hangs.
570 */
571 num_targets = (util_last_bit(col_format) + 3) / 4;
572 for (unsigned i = 0; i < num_targets; i++) {
573 if (!(col_format & (0xf << (i * 4)))) {
574 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
575 }
576 }
577
578 /* The output for dual source blending should have the same format as
579 * the first output.
580 */
581 if (blend->mrt0_is_dual_src)
582 col_format |= (col_format & 0xf) << 4;
583
584 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
585 blend->spi_shader_col_format = col_format;
586 }
587
588 static bool
589 format_is_int8(VkFormat format)
590 {
591 const struct vk_format_description *desc = vk_format_description(format);
592 int channel = vk_format_get_first_non_void_channel(format);
593
594 return channel >= 0 && desc->channel[channel].pure_integer &&
595 desc->channel[channel].size == 8;
596 }
597
598 static bool
599 format_is_int10(VkFormat format)
600 {
601 const struct vk_format_description *desc = vk_format_description(format);
602
603 if (desc->nr_channels != 4)
604 return false;
605 for (unsigned i = 0; i < 4; i++) {
606 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
607 return true;
608 }
609 return false;
610 }
611
612 /*
613 * Ordered so that for each i,
614 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
615 */
616 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
617 VK_FORMAT_R32_SFLOAT,
618 VK_FORMAT_R32G32_SFLOAT,
619 VK_FORMAT_R8G8B8A8_UNORM,
620 VK_FORMAT_R16G16B16A16_UNORM,
621 VK_FORMAT_R16G16B16A16_SNORM,
622 VK_FORMAT_R16G16B16A16_UINT,
623 VK_FORMAT_R16G16B16A16_SINT,
624 VK_FORMAT_R32G32B32A32_SFLOAT,
625 VK_FORMAT_R8G8B8A8_UINT,
626 VK_FORMAT_R8G8B8A8_SINT,
627 VK_FORMAT_A2R10G10B10_UINT_PACK32,
628 VK_FORMAT_A2R10G10B10_SINT_PACK32,
629 };
630
631 unsigned radv_format_meta_fs_key(VkFormat format)
632 {
633 unsigned col_format = si_choose_spi_color_format(format, false, false);
634
635 assert(col_format != V_028714_SPI_SHADER_32_AR);
636 if (col_format >= V_028714_SPI_SHADER_32_AR)
637 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
638
639 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
640 bool is_int8 = format_is_int8(format);
641 bool is_int10 = format_is_int10(format);
642
643 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
644 }
645
646 static void
647 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
648 unsigned *is_int8, unsigned *is_int10)
649 {
650 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
651 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
652 *is_int8 = 0;
653 *is_int10 = 0;
654
655 for (unsigned i = 0; i < subpass->color_count; ++i) {
656 struct radv_render_pass_attachment *attachment;
657
658 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
659 continue;
660
661 attachment = pass->attachments + subpass->color_attachments[i].attachment;
662
663 if (format_is_int8(attachment->format))
664 *is_int8 |= 1 << i;
665 if (format_is_int10(attachment->format))
666 *is_int10 |= 1 << i;
667 }
668 }
669
670 static void
671 radv_blend_check_commutativity(struct radv_blend_state *blend,
672 VkBlendOp op, VkBlendFactor src,
673 VkBlendFactor dst, unsigned chanmask)
674 {
675 /* Src factor is allowed when it does not depend on Dst. */
676 static const uint32_t src_allowed =
677 (1u << VK_BLEND_FACTOR_ONE) |
678 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
679 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
680 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
681 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
682 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
683 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
684 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
685 (1u << VK_BLEND_FACTOR_ZERO) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
690 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
691 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
692
693 if (dst == VK_BLEND_FACTOR_ONE &&
694 (src_allowed & (1u << src))) {
695 /* Addition is commutative, but floating point addition isn't
696 * associative: subtle changes can be introduced via different
697 * rounding. Be conservative, only enable for min and max.
698 */
699 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
700 blend->commutative_4bit |= chanmask;
701 }
702 }
703
704 static struct radv_blend_state
705 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
706 const VkGraphicsPipelineCreateInfo *pCreateInfo,
707 const struct radv_graphics_pipeline_create_info *extra)
708 {
709 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
710 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
711 struct radv_blend_state blend = {0};
712 unsigned mode = V_028808_CB_NORMAL;
713 int i;
714
715 if (!vkblend)
716 return blend;
717
718 if (extra && extra->custom_blend_mode) {
719 blend.single_cb_enable = true;
720 mode = extra->custom_blend_mode;
721 }
722 blend.cb_color_control = 0;
723 if (vkblend->logicOpEnable)
724 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
725 else
726 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
727
728 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
729 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
730 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
731 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
732 S_028B70_OFFSET_ROUND(1);
733
734 if (vkms && vkms->alphaToCoverageEnable) {
735 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
736 blend.need_src_alpha |= 0x1;
737 }
738
739 blend.cb_target_mask = 0;
740 for (i = 0; i < vkblend->attachmentCount; i++) {
741 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
742 unsigned blend_cntl = 0;
743 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
744 VkBlendOp eqRGB = att->colorBlendOp;
745 VkBlendFactor srcRGB = att->srcColorBlendFactor;
746 VkBlendFactor dstRGB = att->dstColorBlendFactor;
747 VkBlendOp eqA = att->alphaBlendOp;
748 VkBlendFactor srcA = att->srcAlphaBlendFactor;
749 VkBlendFactor dstA = att->dstAlphaBlendFactor;
750
751 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
752
753 if (!att->colorWriteMask)
754 continue;
755
756 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
757 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
758 if (!att->blendEnable) {
759 blend.cb_blend_control[i] = blend_cntl;
760 continue;
761 }
762
763 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
764 if (i == 0)
765 blend.mrt0_is_dual_src = true;
766
767 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
768 srcRGB = VK_BLEND_FACTOR_ONE;
769 dstRGB = VK_BLEND_FACTOR_ONE;
770 }
771 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
772 srcA = VK_BLEND_FACTOR_ONE;
773 dstA = VK_BLEND_FACTOR_ONE;
774 }
775
776 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
777 0x7 << (4 * i));
778 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
779 0x8 << (4 * i));
780
781 /* Blending optimizations for RB+.
782 * These transformations don't change the behavior.
783 *
784 * First, get rid of DST in the blend factors:
785 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
786 */
787 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
788 VK_BLEND_FACTOR_DST_COLOR,
789 VK_BLEND_FACTOR_SRC_COLOR);
790
791 si_blend_remove_dst(&eqA, &srcA, &dstA,
792 VK_BLEND_FACTOR_DST_COLOR,
793 VK_BLEND_FACTOR_SRC_COLOR);
794
795 si_blend_remove_dst(&eqA, &srcA, &dstA,
796 VK_BLEND_FACTOR_DST_ALPHA,
797 VK_BLEND_FACTOR_SRC_ALPHA);
798
799 /* Look up the ideal settings from tables. */
800 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
801 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
802 srcA_opt = si_translate_blend_opt_factor(srcA, true);
803 dstA_opt = si_translate_blend_opt_factor(dstA, true);
804
805 /* Handle interdependencies. */
806 if (si_blend_factor_uses_dst(srcRGB))
807 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
808 if (si_blend_factor_uses_dst(srcA))
809 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
810
811 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
812 (dstRGB == VK_BLEND_FACTOR_ZERO ||
813 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
814 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
815 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
816
817 /* Set the final value. */
818 blend.sx_mrt_blend_opt[i] =
819 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
820 S_028760_COLOR_DST_OPT(dstRGB_opt) |
821 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
822 S_028760_ALPHA_SRC_OPT(srcA_opt) |
823 S_028760_ALPHA_DST_OPT(dstA_opt) |
824 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
825 blend_cntl |= S_028780_ENABLE(1);
826
827 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
828 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
829 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
830 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
831 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
832 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
833 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
834 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
835 }
836 blend.cb_blend_control[i] = blend_cntl;
837
838 blend.blend_enable_4bit |= 0xfu << (i * 4);
839
840 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
841 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
842 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
843 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
844 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
845 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
846 blend.need_src_alpha |= 1 << i;
847 }
848 for (i = vkblend->attachmentCount; i < 8; i++) {
849 blend.cb_blend_control[i] = 0;
850 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
851 }
852
853 if (pipeline->device->physical_device->rad_info.has_rbplus) {
854 /* Disable RB+ blend optimizations for dual source blending. */
855 if (blend.mrt0_is_dual_src) {
856 for (i = 0; i < 8; i++) {
857 blend.sx_mrt_blend_opt[i] =
858 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
859 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
860 }
861 }
862
863 /* RB+ doesn't work with dual source blending, logic op and
864 * RESOLVE.
865 */
866 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
867 mode == V_028808_CB_RESOLVE)
868 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
869 }
870
871 if (blend.cb_target_mask)
872 blend.cb_color_control |= S_028808_MODE(mode);
873 else
874 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
875
876 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
877 return blend;
878 }
879
880 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
881 {
882 switch (op) {
883 case VK_STENCIL_OP_KEEP:
884 return V_02842C_STENCIL_KEEP;
885 case VK_STENCIL_OP_ZERO:
886 return V_02842C_STENCIL_ZERO;
887 case VK_STENCIL_OP_REPLACE:
888 return V_02842C_STENCIL_REPLACE_TEST;
889 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
890 return V_02842C_STENCIL_ADD_CLAMP;
891 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
892 return V_02842C_STENCIL_SUB_CLAMP;
893 case VK_STENCIL_OP_INVERT:
894 return V_02842C_STENCIL_INVERT;
895 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
896 return V_02842C_STENCIL_ADD_WRAP;
897 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
898 return V_02842C_STENCIL_SUB_WRAP;
899 default:
900 return 0;
901 }
902 }
903
904 static uint32_t si_translate_fill(VkPolygonMode func)
905 {
906 switch(func) {
907 case VK_POLYGON_MODE_FILL:
908 return V_028814_X_DRAW_TRIANGLES;
909 case VK_POLYGON_MODE_LINE:
910 return V_028814_X_DRAW_LINES;
911 case VK_POLYGON_MODE_POINT:
912 return V_028814_X_DRAW_POINTS;
913 default:
914 assert(0);
915 return V_028814_X_DRAW_POINTS;
916 }
917 }
918
919 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
920 {
921 uint32_t num_samples = vkms->rasterizationSamples;
922 uint32_t ps_iter_samples = 1;
923
924 if (vkms->sampleShadingEnable) {
925 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
926 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
927 }
928 return ps_iter_samples;
929 }
930
931 static bool
932 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
933 {
934 return pCreateInfo->depthTestEnable &&
935 pCreateInfo->depthWriteEnable &&
936 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
937 }
938
939 static bool
940 radv_writes_stencil(const VkStencilOpState *state)
941 {
942 return state->writeMask &&
943 (state->failOp != VK_STENCIL_OP_KEEP ||
944 state->passOp != VK_STENCIL_OP_KEEP ||
945 state->depthFailOp != VK_STENCIL_OP_KEEP);
946 }
947
948 static bool
949 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
950 {
951 return pCreateInfo->stencilTestEnable &&
952 (radv_writes_stencil(&pCreateInfo->front) ||
953 radv_writes_stencil(&pCreateInfo->back));
954 }
955
956 static bool
957 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
958 {
959 return radv_is_depth_write_enabled(pCreateInfo) ||
960 radv_is_stencil_write_enabled(pCreateInfo);
961 }
962
963 static bool
964 radv_order_invariant_stencil_op(VkStencilOp op)
965 {
966 /* REPLACE is normally order invariant, except when the stencil
967 * reference value is written by the fragment shader. Tracking this
968 * interaction does not seem worth the effort, so be conservative.
969 */
970 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
971 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
972 op != VK_STENCIL_OP_REPLACE;
973 }
974
975 static bool
976 radv_order_invariant_stencil_state(const VkStencilOpState *state)
977 {
978 /* Compute whether, assuming Z writes are disabled, this stencil state
979 * is order invariant in the sense that the set of passing fragments as
980 * well as the final stencil buffer result does not depend on the order
981 * of fragments.
982 */
983 return !state->writeMask ||
984 /* The following assumes that Z writes are disabled. */
985 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
986 radv_order_invariant_stencil_op(state->passOp) &&
987 radv_order_invariant_stencil_op(state->depthFailOp)) ||
988 (state->compareOp == VK_COMPARE_OP_NEVER &&
989 radv_order_invariant_stencil_op(state->failOp));
990 }
991
992 static bool
993 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
994 struct radv_blend_state *blend,
995 const VkGraphicsPipelineCreateInfo *pCreateInfo)
996 {
997 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
998 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
999 unsigned colormask = blend->cb_target_enabled_4bit;
1000
1001 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1002 return false;
1003
1004 /* Be conservative if a logic operation is enabled with color buffers. */
1005 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1006 return false;
1007
1008 /* Default depth/stencil invariance when no attachment is bound. */
1009 struct radv_dsa_order_invariance dsa_order_invariant = {
1010 .zs = true, .pass_set = true
1011 };
1012
1013 if (pCreateInfo->pDepthStencilState &&
1014 subpass->depth_stencil_attachment) {
1015 const VkPipelineDepthStencilStateCreateInfo *vkds =
1016 pCreateInfo->pDepthStencilState;
1017 struct radv_render_pass_attachment *attachment =
1018 pass->attachments + subpass->depth_stencil_attachment->attachment;
1019 bool has_stencil = vk_format_is_stencil(attachment->format);
1020 struct radv_dsa_order_invariance order_invariance[2];
1021 struct radv_shader_variant *ps =
1022 pipeline->shaders[MESA_SHADER_FRAGMENT];
1023
1024 /* Compute depth/stencil order invariance in order to know if
1025 * it's safe to enable out-of-order.
1026 */
1027 bool zfunc_is_ordered =
1028 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1029 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1030 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1031 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1032 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1033
1034 bool nozwrite_and_order_invariant_stencil =
1035 !radv_is_ds_write_enabled(vkds) ||
1036 (!radv_is_depth_write_enabled(vkds) &&
1037 radv_order_invariant_stencil_state(&vkds->front) &&
1038 radv_order_invariant_stencil_state(&vkds->back));
1039
1040 order_invariance[1].zs =
1041 nozwrite_and_order_invariant_stencil ||
1042 (!radv_is_stencil_write_enabled(vkds) &&
1043 zfunc_is_ordered);
1044 order_invariance[0].zs =
1045 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1046
1047 order_invariance[1].pass_set =
1048 nozwrite_and_order_invariant_stencil ||
1049 (!radv_is_stencil_write_enabled(vkds) &&
1050 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1051 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1052 order_invariance[0].pass_set =
1053 !radv_is_depth_write_enabled(vkds) ||
1054 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1055 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1056
1057 dsa_order_invariant = order_invariance[has_stencil];
1058 if (!dsa_order_invariant.zs)
1059 return false;
1060
1061 /* The set of PS invocations is always order invariant,
1062 * except when early Z/S tests are requested.
1063 */
1064 if (ps &&
1065 ps->info.ps.writes_memory &&
1066 ps->info.ps.early_fragment_test &&
1067 !dsa_order_invariant.pass_set)
1068 return false;
1069
1070 /* Determine if out-of-order rasterization should be disabled
1071 * when occlusion queries are used.
1072 */
1073 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1074 !dsa_order_invariant.pass_set;
1075 }
1076
1077 /* No color buffers are enabled for writing. */
1078 if (!colormask)
1079 return true;
1080
1081 unsigned blendmask = colormask & blend->blend_enable_4bit;
1082
1083 if (blendmask) {
1084 /* Only commutative blending. */
1085 if (blendmask & ~blend->commutative_4bit)
1086 return false;
1087
1088 if (!dsa_order_invariant.pass_set)
1089 return false;
1090 }
1091
1092 if (colormask & ~blendmask)
1093 return false;
1094
1095 return true;
1096 }
1097
1098 static void
1099 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1100 struct radv_blend_state *blend,
1101 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1102 {
1103 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1104 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1105 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1106 bool out_of_order_rast = false;
1107 int ps_iter_samples = 1;
1108 uint32_t mask = 0xffff;
1109
1110 if (vkms)
1111 ms->num_samples = vkms->rasterizationSamples;
1112 else
1113 ms->num_samples = 1;
1114
1115 if (vkms)
1116 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1117 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1118 ps_iter_samples = ms->num_samples;
1119 }
1120
1121 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1122 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1123 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1124 /* Out-of-order rasterization is explicitly enabled by the
1125 * application.
1126 */
1127 out_of_order_rast = true;
1128 } else {
1129 /* Determine if the driver can enable out-of-order
1130 * rasterization internally.
1131 */
1132 out_of_order_rast =
1133 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1134 }
1135
1136 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1137 ms->pa_sc_aa_config = 0;
1138 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1139 S_028804_INCOHERENT_EQAA_READS(1) |
1140 S_028804_INTERPOLATE_COMP_Z(1) |
1141 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1142 ms->pa_sc_mode_cntl_1 =
1143 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1144 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1145 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1146 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1147 /* always 1: */
1148 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1149 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1150 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1151 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1152 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1153 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1154 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1155 S_028A48_VPORT_SCISSOR_ENABLE(1);
1156
1157 if (ms->num_samples > 1) {
1158 unsigned log_samples = util_logbase2(ms->num_samples);
1159 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1160 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1161 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1162 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1163 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1164 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1165 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1166 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1167 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1168 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1169 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1170 if (ps_iter_samples > 1)
1171 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1172 }
1173
1174 if (vkms && vkms->pSampleMask) {
1175 mask = vkms->pSampleMask[0] & 0xffff;
1176 }
1177
1178 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1179 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1180 }
1181
1182 static bool
1183 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1184 {
1185 switch (topology) {
1186 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1189 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1190 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1191 return false;
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1195 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1196 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1197 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1198 return true;
1199 default:
1200 unreachable("unhandled primitive type");
1201 }
1202 }
1203
1204 static uint32_t
1205 si_translate_prim(enum VkPrimitiveTopology topology)
1206 {
1207 switch (topology) {
1208 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1209 return V_008958_DI_PT_POINTLIST;
1210 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1211 return V_008958_DI_PT_LINELIST;
1212 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1213 return V_008958_DI_PT_LINESTRIP;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1215 return V_008958_DI_PT_TRILIST;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1217 return V_008958_DI_PT_TRISTRIP;
1218 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1219 return V_008958_DI_PT_TRIFAN;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1221 return V_008958_DI_PT_LINELIST_ADJ;
1222 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1223 return V_008958_DI_PT_LINESTRIP_ADJ;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1225 return V_008958_DI_PT_TRILIST_ADJ;
1226 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1227 return V_008958_DI_PT_TRISTRIP_ADJ;
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1229 return V_008958_DI_PT_PATCH;
1230 default:
1231 assert(0);
1232 return 0;
1233 }
1234 }
1235
1236 static uint32_t
1237 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1238 {
1239 switch (gl_prim) {
1240 case 0: /* GL_POINTS */
1241 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1242 case 1: /* GL_LINES */
1243 case 3: /* GL_LINE_STRIP */
1244 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1245 case 0x8E7A: /* GL_ISOLINES */
1246 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1247
1248 case 4: /* GL_TRIANGLES */
1249 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1250 case 5: /* GL_TRIANGLE_STRIP */
1251 case 7: /* GL_QUADS */
1252 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1253 default:
1254 assert(0);
1255 return 0;
1256 }
1257 }
1258
1259 static uint32_t
1260 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1261 {
1262 switch (topology) {
1263 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1264 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1265 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1268 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1269 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1270 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1274 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1275 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1276 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1277 default:
1278 assert(0);
1279 return 0;
1280 }
1281 }
1282
1283 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1284 {
1285 switch(state) {
1286 case VK_DYNAMIC_STATE_VIEWPORT:
1287 return RADV_DYNAMIC_VIEWPORT;
1288 case VK_DYNAMIC_STATE_SCISSOR:
1289 return RADV_DYNAMIC_SCISSOR;
1290 case VK_DYNAMIC_STATE_LINE_WIDTH:
1291 return RADV_DYNAMIC_LINE_WIDTH;
1292 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1293 return RADV_DYNAMIC_DEPTH_BIAS;
1294 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1295 return RADV_DYNAMIC_BLEND_CONSTANTS;
1296 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1297 return RADV_DYNAMIC_DEPTH_BOUNDS;
1298 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1299 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1300 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1301 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1302 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1303 return RADV_DYNAMIC_STENCIL_REFERENCE;
1304 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1305 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1306 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1307 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1308 default:
1309 unreachable("Unhandled dynamic state");
1310 }
1311 }
1312
1313 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1314 {
1315 uint32_t states = RADV_DYNAMIC_ALL;
1316
1317 /* If rasterization is disabled we do not care about any of the dynamic states,
1318 * since they are all rasterization related only. */
1319 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1320 return 0;
1321
1322 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1323 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1324
1325 if (!pCreateInfo->pDepthStencilState ||
1326 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1327 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1328
1329 if (!pCreateInfo->pDepthStencilState ||
1330 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1331 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1332 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1333 RADV_DYNAMIC_STENCIL_REFERENCE);
1334
1335 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1336 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1337
1338 if (!pCreateInfo->pMultisampleState ||
1339 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1340 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1341 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1342
1343 /* TODO: blend constants & line width. */
1344
1345 return states;
1346 }
1347
1348
1349 static void
1350 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1351 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1352 {
1353 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1354 uint32_t states = needed_states;
1355 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1356 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1357
1358 pipeline->dynamic_state = default_dynamic_state;
1359 pipeline->graphics.needed_dynamic_state = needed_states;
1360
1361 if (pCreateInfo->pDynamicState) {
1362 /* Remove all of the states that are marked as dynamic */
1363 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1364 for (uint32_t s = 0; s < count; s++)
1365 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1366 }
1367
1368 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1369
1370 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1371 assert(pCreateInfo->pViewportState);
1372
1373 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1374 if (states & RADV_DYNAMIC_VIEWPORT) {
1375 typed_memcpy(dynamic->viewport.viewports,
1376 pCreateInfo->pViewportState->pViewports,
1377 pCreateInfo->pViewportState->viewportCount);
1378 }
1379 }
1380
1381 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1382 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1383 if (states & RADV_DYNAMIC_SCISSOR) {
1384 typed_memcpy(dynamic->scissor.scissors,
1385 pCreateInfo->pViewportState->pScissors,
1386 pCreateInfo->pViewportState->scissorCount);
1387 }
1388 }
1389
1390 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1391 assert(pCreateInfo->pRasterizationState);
1392 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1393 }
1394
1395 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1396 assert(pCreateInfo->pRasterizationState);
1397 dynamic->depth_bias.bias =
1398 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1399 dynamic->depth_bias.clamp =
1400 pCreateInfo->pRasterizationState->depthBiasClamp;
1401 dynamic->depth_bias.slope =
1402 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1403 }
1404
1405 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1406 *
1407 * pColorBlendState is [...] NULL if the pipeline has rasterization
1408 * disabled or if the subpass of the render pass the pipeline is
1409 * created against does not use any color attachments.
1410 */
1411 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1412 assert(pCreateInfo->pColorBlendState);
1413 typed_memcpy(dynamic->blend_constants,
1414 pCreateInfo->pColorBlendState->blendConstants, 4);
1415 }
1416
1417 /* If there is no depthstencil attachment, then don't read
1418 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1419 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1420 * no need to override the depthstencil defaults in
1421 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1422 *
1423 * Section 9.2 of the Vulkan 1.0.15 spec says:
1424 *
1425 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1426 * disabled or if the subpass of the render pass the pipeline is created
1427 * against does not use a depth/stencil attachment.
1428 */
1429 if (needed_states && subpass->depth_stencil_attachment) {
1430 assert(pCreateInfo->pDepthStencilState);
1431
1432 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1433 dynamic->depth_bounds.min =
1434 pCreateInfo->pDepthStencilState->minDepthBounds;
1435 dynamic->depth_bounds.max =
1436 pCreateInfo->pDepthStencilState->maxDepthBounds;
1437 }
1438
1439 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1440 dynamic->stencil_compare_mask.front =
1441 pCreateInfo->pDepthStencilState->front.compareMask;
1442 dynamic->stencil_compare_mask.back =
1443 pCreateInfo->pDepthStencilState->back.compareMask;
1444 }
1445
1446 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1447 dynamic->stencil_write_mask.front =
1448 pCreateInfo->pDepthStencilState->front.writeMask;
1449 dynamic->stencil_write_mask.back =
1450 pCreateInfo->pDepthStencilState->back.writeMask;
1451 }
1452
1453 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1454 dynamic->stencil_reference.front =
1455 pCreateInfo->pDepthStencilState->front.reference;
1456 dynamic->stencil_reference.back =
1457 pCreateInfo->pDepthStencilState->back.reference;
1458 }
1459 }
1460
1461 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1462 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1463 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1465 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1466 typed_memcpy(dynamic->discard_rectangle.rectangles,
1467 discard_rectangle_info->pDiscardRectangles,
1468 discard_rectangle_info->discardRectangleCount);
1469 }
1470 }
1471
1472 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1473 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1474 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1475 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1476 /* If sampleLocationsEnable is VK_FALSE, the default sample
1477 * locations are used and the values specified in
1478 * sampleLocationsInfo are ignored.
1479 */
1480 if (sample_location_info->sampleLocationsEnable) {
1481 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1482 &sample_location_info->sampleLocationsInfo;
1483
1484 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1485
1486 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1487 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1488 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1489 typed_memcpy(&dynamic->sample_location.locations[0],
1490 pSampleLocationsInfo->pSampleLocations,
1491 pSampleLocationsInfo->sampleLocationsCount);
1492 }
1493 }
1494
1495 pipeline->dynamic_state.mask = states;
1496 }
1497
1498 static void
1499 gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1500 const struct radv_pipeline *pipeline,
1501 nir_shader **nir,
1502 struct radv_shader_info *infos,
1503 struct gfx9_gs_info *out)
1504 {
1505 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1506 struct radv_es_output_info *es_info;
1507 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1508 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1509 else
1510 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1511 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1512 &infos[MESA_SHADER_VERTEX].vs.es_info;
1513
1514 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1515 bool uses_adjacency;
1516 switch(pCreateInfo->pInputAssemblyState->topology) {
1517 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1518 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1519 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1520 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1521 uses_adjacency = true;
1522 break;
1523 default:
1524 uses_adjacency = false;
1525 break;
1526 }
1527
1528 /* All these are in dwords: */
1529 /* We can't allow using the whole LDS, because GS waves compete with
1530 * other shader stages for LDS space. */
1531 const unsigned max_lds_size = 8 * 1024;
1532 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1533 unsigned esgs_lds_size;
1534
1535 /* All these are per subgroup: */
1536 const unsigned max_out_prims = 32 * 1024;
1537 const unsigned max_es_verts = 255;
1538 const unsigned ideal_gs_prims = 64;
1539 unsigned max_gs_prims, gs_prims;
1540 unsigned min_es_verts, es_verts, worst_case_es_verts;
1541
1542 if (uses_adjacency || gs_num_invocations > 1)
1543 max_gs_prims = 127 / gs_num_invocations;
1544 else
1545 max_gs_prims = 255;
1546
1547 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1548 * Make sure we don't go over the maximum value.
1549 */
1550 if (gs_info->gs.vertices_out > 0) {
1551 max_gs_prims = MIN2(max_gs_prims,
1552 max_out_prims /
1553 (gs_info->gs.vertices_out * gs_num_invocations));
1554 }
1555 assert(max_gs_prims > 0);
1556
1557 /* If the primitive has adjacency, halve the number of vertices
1558 * that will be reused in multiple primitives.
1559 */
1560 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1561
1562 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1563 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1564
1565 /* Compute ESGS LDS size based on the worst case number of ES vertices
1566 * needed to create the target number of GS prims per subgroup.
1567 */
1568 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1569
1570 /* If total LDS usage is too big, refactor partitions based on ratio
1571 * of ESGS item sizes.
1572 */
1573 if (esgs_lds_size > max_lds_size) {
1574 /* Our target GS Prims Per Subgroup was too large. Calculate
1575 * the maximum number of GS Prims Per Subgroup that will fit
1576 * into LDS, capped by the maximum that the hardware can support.
1577 */
1578 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1579 max_gs_prims);
1580 assert(gs_prims > 0);
1581 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1582 max_es_verts);
1583
1584 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1585 assert(esgs_lds_size <= max_lds_size);
1586 }
1587
1588 /* Now calculate remaining ESGS information. */
1589 if (esgs_lds_size)
1590 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1591 else
1592 es_verts = max_es_verts;
1593
1594 /* Vertices for adjacency primitives are not always reused, so restore
1595 * it for ES_VERTS_PER_SUBGRP.
1596 */
1597 min_es_verts = gs_info->gs.vertices_in;
1598
1599 /* For normal primitives, the VGT only checks if they are past the ES
1600 * verts per subgroup after allocating a full GS primitive and if they
1601 * are, kick off a new subgroup. But if those additional ES verts are
1602 * unique (e.g. not reused) we need to make sure there is enough LDS
1603 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1604 */
1605 es_verts -= min_es_verts - 1;
1606
1607 uint32_t es_verts_per_subgroup = es_verts;
1608 uint32_t gs_prims_per_subgroup = gs_prims;
1609 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1610 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1611 out->lds_size = align(esgs_lds_size, 128) / 128;
1612 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1613 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1614 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1615 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1616 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1617 assert(max_prims_per_subgroup <= max_out_prims);
1618 }
1619
1620 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1621 unsigned min_verts_per_prim, bool use_adjacency)
1622 {
1623 unsigned max_reuse = max_esverts - min_verts_per_prim;
1624 if (use_adjacency)
1625 max_reuse /= 2;
1626 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1627 }
1628
1629 static unsigned
1630 radv_get_num_input_vertices(nir_shader **nir)
1631 {
1632 if (nir[MESA_SHADER_GEOMETRY]) {
1633 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1634
1635 return gs->info.gs.vertices_in;
1636 }
1637
1638 if (nir[MESA_SHADER_TESS_CTRL]) {
1639 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1640
1641 if (tes->info.tess.point_mode)
1642 return 1;
1643 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1644 return 2;
1645 return 3;
1646 }
1647
1648 return 3;
1649 }
1650
1651 static void
1652 gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1653 struct radv_pipeline *pipeline,
1654 nir_shader **nir,
1655 struct radv_shader_info *infos,
1656 struct gfx10_ngg_info *ngg)
1657 {
1658 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1659 struct radv_es_output_info *es_info =
1660 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1661 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1662 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1663 unsigned min_verts_per_prim =
1664 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1665 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1666 bool uses_adjacency;
1667 switch(pCreateInfo->pInputAssemblyState->topology) {
1668 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1669 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1670 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1671 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1672 uses_adjacency = true;
1673 break;
1674 default:
1675 uses_adjacency = false;
1676 break;
1677 }
1678
1679 /* All these are in dwords: */
1680 /* We can't allow using the whole LDS, because GS waves compete with
1681 * other shader stages for LDS space.
1682 *
1683 * TODO: We should really take the shader's internal LDS use into
1684 * account. The linker will fail if the size is greater than
1685 * 8K dwords.
1686 */
1687 const unsigned max_lds_size = 8 * 1024 - 768;
1688 const unsigned target_lds_size = max_lds_size;
1689 unsigned esvert_lds_size = 0;
1690 unsigned gsprim_lds_size = 0;
1691
1692 /* All these are per subgroup: */
1693 bool max_vert_out_per_gs_instance = false;
1694 unsigned max_esverts_base = 256;
1695 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1696
1697 /* Hardware has the following non-natural restrictions on the value
1698 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1699 * the draw:
1700 * - at most 252 for any line input primitive type
1701 * - at most 251 for any quad input primitive type
1702 * - at most 251 for triangle strips with adjacency (this happens to
1703 * be the natural limit for triangle *lists* with adjacency)
1704 */
1705 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1706
1707 if (gs_type == MESA_SHADER_GEOMETRY) {
1708 unsigned max_out_verts_per_gsprim =
1709 gs_info->gs.vertices_out * gs_num_invocations;
1710
1711 if (max_out_verts_per_gsprim <= 256) {
1712 if (max_out_verts_per_gsprim) {
1713 max_gsprims_base = MIN2(max_gsprims_base,
1714 256 / max_out_verts_per_gsprim);
1715 }
1716 } else {
1717 /* Use special multi-cycling mode in which each GS
1718 * instance gets its own subgroup. Does not work with
1719 * tessellation. */
1720 max_vert_out_per_gs_instance = true;
1721 max_gsprims_base = 1;
1722 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1723 }
1724
1725 esvert_lds_size = es_info->esgs_itemsize / 4;
1726 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1727 } else {
1728 /* VS and TES. */
1729 /* LDS size for passing data from GS to ES. */
1730 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1731 ? &infos[MESA_SHADER_TESS_EVAL].so
1732 : &infos[MESA_SHADER_VERTEX].so;
1733
1734 if (so_info->num_outputs)
1735 esvert_lds_size = 4 * so_info->num_outputs + 1;
1736
1737 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1738 * corresponding to the ES thread of the provoking vertex. All
1739 * ES threads load and export PrimitiveID for their thread.
1740 */
1741 if (!nir[MESA_SHADER_TESS_CTRL] &&
1742 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1743 esvert_lds_size = MAX2(esvert_lds_size, 1);
1744 }
1745
1746 unsigned max_gsprims = max_gsprims_base;
1747 unsigned max_esverts = max_esverts_base;
1748
1749 if (esvert_lds_size)
1750 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1751 if (gsprim_lds_size)
1752 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1753
1754 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1755 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1756 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1757
1758 if (esvert_lds_size || gsprim_lds_size) {
1759 /* Now that we have a rough proportionality between esverts
1760 * and gsprims based on the primitive type, scale both of them
1761 * down simultaneously based on required LDS space.
1762 *
1763 * We could be smarter about this if we knew how much vertex
1764 * reuse to expect.
1765 */
1766 unsigned lds_total = max_esverts * esvert_lds_size +
1767 max_gsprims * gsprim_lds_size;
1768 if (lds_total > target_lds_size) {
1769 max_esverts = max_esverts * target_lds_size / lds_total;
1770 max_gsprims = max_gsprims * target_lds_size / lds_total;
1771
1772 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1773 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1774 min_verts_per_prim, uses_adjacency);
1775 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1776 }
1777 }
1778
1779 /* Round up towards full wave sizes for better ALU utilization. */
1780 if (!max_vert_out_per_gs_instance) {
1781 const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
1782 unsigned orig_max_esverts;
1783 unsigned orig_max_gsprims;
1784 do {
1785 orig_max_esverts = max_esverts;
1786 orig_max_gsprims = max_gsprims;
1787
1788 max_esverts = align(max_esverts, wavesize);
1789 max_esverts = MIN2(max_esverts, max_esverts_base);
1790 if (esvert_lds_size)
1791 max_esverts = MIN2(max_esverts,
1792 (max_lds_size - max_gsprims * gsprim_lds_size) /
1793 esvert_lds_size);
1794 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1795
1796 max_gsprims = align(max_gsprims, wavesize);
1797 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1798 if (gsprim_lds_size)
1799 max_gsprims = MIN2(max_gsprims,
1800 (max_lds_size - max_esverts * esvert_lds_size) /
1801 gsprim_lds_size);
1802 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1803 min_verts_per_prim, uses_adjacency);
1804 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1805 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1806 }
1807
1808 /* Hardware restriction: minimum value of max_esverts */
1809 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1810
1811 unsigned max_out_vertices =
1812 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1813 gs_type == MESA_SHADER_GEOMETRY ?
1814 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1815 max_esverts;
1816 assert(max_out_vertices <= 256);
1817
1818 unsigned prim_amp_factor = 1;
1819 if (gs_type == MESA_SHADER_GEOMETRY) {
1820 /* Number of output primitives per GS input primitive after
1821 * GS instancing. */
1822 prim_amp_factor = gs_info->gs.vertices_out;
1823 }
1824
1825 /* The GE only checks against the maximum number of ES verts after
1826 * allocating a full GS primitive. So we need to ensure that whenever
1827 * this check passes, there is enough space for a full primitive without
1828 * vertex reuse.
1829 */
1830 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1831 ngg->max_gsprims = max_gsprims;
1832 ngg->max_out_verts = max_out_vertices;
1833 ngg->prim_amp_factor = prim_amp_factor;
1834 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1835 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1836 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1837
1838 if (gs_type == MESA_SHADER_GEOMETRY) {
1839 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1840 } else {
1841 ngg->vgt_esgs_ring_itemsize = 1;
1842 }
1843
1844 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1845
1846 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1847 }
1848
1849 static void
1850 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1851 const struct gfx9_gs_info *gs)
1852 {
1853 struct radv_device *device = pipeline->device;
1854 unsigned num_se = device->physical_device->rad_info.max_se;
1855 unsigned wave_size = 64;
1856 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1857 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1858 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1859 */
1860 unsigned gs_vertex_reuse =
1861 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1862 unsigned alignment = 256 * num_se;
1863 /* The maximum size is 63.999 MB per SE. */
1864 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1865 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1866
1867 /* Calculate the minimum size. */
1868 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1869 wave_size, alignment);
1870 /* These are recommended sizes, not minimum sizes. */
1871 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1872 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1873 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1874 gs_info->gs.max_gsvs_emit_size;
1875
1876 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1877 esgs_ring_size = align(esgs_ring_size, alignment);
1878 gsvs_ring_size = align(gsvs_ring_size, alignment);
1879
1880 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1881 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1882
1883 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1884 }
1885
1886 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1887 unsigned *lds_size)
1888 {
1889 /* If tessellation is all offchip and on-chip GS isn't used, this
1890 * workaround is not needed.
1891 */
1892 return;
1893
1894 /* SPI barrier management bug:
1895 * Make sure we have at least 4k of LDS in use to avoid the bug.
1896 * It applies to workgroup sizes of more than one wavefront.
1897 */
1898 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1899 device->physical_device->rad_info.family == CHIP_KABINI)
1900 *lds_size = MAX2(*lds_size, 8);
1901 }
1902
1903 struct radv_shader_variant *
1904 radv_get_shader(struct radv_pipeline *pipeline,
1905 gl_shader_stage stage)
1906 {
1907 if (stage == MESA_SHADER_VERTEX) {
1908 if (pipeline->shaders[MESA_SHADER_VERTEX])
1909 return pipeline->shaders[MESA_SHADER_VERTEX];
1910 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1911 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1912 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1913 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1914 } else if (stage == MESA_SHADER_TESS_EVAL) {
1915 if (!radv_pipeline_has_tess(pipeline))
1916 return NULL;
1917 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1918 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1919 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1920 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1921 }
1922 return pipeline->shaders[stage];
1923 }
1924
1925 static struct radv_tessellation_state
1926 calculate_tess_state(struct radv_pipeline *pipeline,
1927 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1928 {
1929 unsigned num_tcs_input_cp;
1930 unsigned num_tcs_output_cp;
1931 unsigned lds_size;
1932 unsigned num_patches;
1933 struct radv_tessellation_state tess = {0};
1934
1935 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1936 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1937 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1938
1939 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1940
1941 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1942 assert(lds_size <= 65536);
1943 lds_size = align(lds_size, 512) / 512;
1944 } else {
1945 assert(lds_size <= 32768);
1946 lds_size = align(lds_size, 256) / 256;
1947 }
1948 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1949
1950 tess.lds_size = lds_size;
1951
1952 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1953 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1954 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1955 tess.num_patches = num_patches;
1956
1957 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1958 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1959
1960 switch (tes->info.tes.primitive_mode) {
1961 case GL_TRIANGLES:
1962 type = V_028B6C_TESS_TRIANGLE;
1963 break;
1964 case GL_QUADS:
1965 type = V_028B6C_TESS_QUAD;
1966 break;
1967 case GL_ISOLINES:
1968 type = V_028B6C_TESS_ISOLINE;
1969 break;
1970 }
1971
1972 switch (tes->info.tes.spacing) {
1973 case TESS_SPACING_EQUAL:
1974 partitioning = V_028B6C_PART_INTEGER;
1975 break;
1976 case TESS_SPACING_FRACTIONAL_ODD:
1977 partitioning = V_028B6C_PART_FRAC_ODD;
1978 break;
1979 case TESS_SPACING_FRACTIONAL_EVEN:
1980 partitioning = V_028B6C_PART_FRAC_EVEN;
1981 break;
1982 default:
1983 break;
1984 }
1985
1986 bool ccw = tes->info.tes.ccw;
1987 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1988 vk_find_struct_const(pCreateInfo->pTessellationState,
1989 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1990
1991 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1992 ccw = !ccw;
1993
1994 if (tes->info.tes.point_mode)
1995 topology = V_028B6C_OUTPUT_POINT;
1996 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1997 topology = V_028B6C_OUTPUT_LINE;
1998 else if (ccw)
1999 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2000 else
2001 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2002
2003 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2004 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2005 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2006 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2007 else
2008 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2009 } else
2010 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2011
2012 tess.tf_param = S_028B6C_TYPE(type) |
2013 S_028B6C_PARTITIONING(partitioning) |
2014 S_028B6C_TOPOLOGY(topology) |
2015 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2016
2017 return tess;
2018 }
2019
2020 static const struct radv_prim_vertex_count prim_size_table[] = {
2021 [V_008958_DI_PT_NONE] = {0, 0},
2022 [V_008958_DI_PT_POINTLIST] = {1, 1},
2023 [V_008958_DI_PT_LINELIST] = {2, 2},
2024 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2025 [V_008958_DI_PT_TRILIST] = {3, 3},
2026 [V_008958_DI_PT_TRIFAN] = {3, 1},
2027 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2028 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2029 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2030 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2031 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2032 [V_008958_DI_PT_RECTLIST] = {3, 3},
2033 [V_008958_DI_PT_LINELOOP] = {2, 1},
2034 [V_008958_DI_PT_POLYGON] = {3, 1},
2035 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2036 };
2037
2038 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2039 {
2040 if (radv_pipeline_has_gs(pipeline))
2041 if (radv_pipeline_has_ngg(pipeline))
2042 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2043 else
2044 return &pipeline->gs_copy_shader->info.vs.outinfo;
2045 else if (radv_pipeline_has_tess(pipeline))
2046 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2047 else
2048 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2049 }
2050
2051 static void
2052 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2053 {
2054 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2055 int shader_count = 0;
2056
2057 if(shaders[MESA_SHADER_FRAGMENT]) {
2058 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2059 }
2060 if(shaders[MESA_SHADER_GEOMETRY]) {
2061 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2062 }
2063 if(shaders[MESA_SHADER_TESS_EVAL]) {
2064 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2065 }
2066 if(shaders[MESA_SHADER_TESS_CTRL]) {
2067 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2068 }
2069 if(shaders[MESA_SHADER_VERTEX]) {
2070 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2071 }
2072
2073 if (shader_count > 1) {
2074 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2075 unsigned last = ordered_shaders[0]->info.stage;
2076
2077 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2078 ordered_shaders[1]->info.has_transform_feedback_varyings)
2079 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2080
2081 for (int i = 0; i < shader_count; ++i) {
2082 nir_variable_mode mask = 0;
2083
2084 if (ordered_shaders[i]->info.stage != first)
2085 mask = mask | nir_var_shader_in;
2086
2087 if (ordered_shaders[i]->info.stage != last)
2088 mask = mask | nir_var_shader_out;
2089
2090 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2091 radv_optimize_nir(ordered_shaders[i], false, false);
2092 }
2093 }
2094
2095 for (int i = 1; i < shader_count; ++i) {
2096 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2097 ordered_shaders[i - 1]);
2098
2099 if (nir_link_opt_varyings(ordered_shaders[i],
2100 ordered_shaders[i - 1]))
2101 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2102
2103 nir_remove_dead_variables(ordered_shaders[i],
2104 nir_var_shader_out);
2105 nir_remove_dead_variables(ordered_shaders[i - 1],
2106 nir_var_shader_in);
2107
2108 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2109 ordered_shaders[i - 1]);
2110
2111 nir_compact_varyings(ordered_shaders[i],
2112 ordered_shaders[i - 1], true);
2113
2114 if (progress) {
2115 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2116 ac_lower_indirect_derefs(ordered_shaders[i],
2117 pipeline->device->physical_device->rad_info.chip_class);
2118 }
2119 radv_optimize_nir(ordered_shaders[i], false, false);
2120
2121 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2122 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2123 pipeline->device->physical_device->rad_info.chip_class);
2124 }
2125 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2126 }
2127 }
2128 }
2129
2130 static uint32_t
2131 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2132 uint32_t attrib_binding)
2133 {
2134 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2135 const VkVertexInputBindingDescription *input_binding =
2136 &input_state->pVertexBindingDescriptions[i];
2137
2138 if (input_binding->binding == attrib_binding)
2139 return input_binding->stride;
2140 }
2141
2142 return 0;
2143 }
2144
2145 static struct radv_pipeline_key
2146 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2147 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2148 const struct radv_blend_state *blend,
2149 bool has_view_index)
2150 {
2151 const VkPipelineVertexInputStateCreateInfo *input_state =
2152 pCreateInfo->pVertexInputState;
2153 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2154 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2155
2156 struct radv_pipeline_key key;
2157 memset(&key, 0, sizeof(key));
2158
2159 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2160 key.optimisations_disabled = 1;
2161
2162 key.has_multiview_view_index = has_view_index;
2163
2164 uint32_t binding_input_rate = 0;
2165 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2166 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2167 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2168 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2169 binding_input_rate |= 1u << binding;
2170 instance_rate_divisors[binding] = 1;
2171 }
2172 }
2173 if (divisor_state) {
2174 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2175 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2176 divisor_state->pVertexBindingDivisors[i].divisor;
2177 }
2178 }
2179
2180 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2181 const VkVertexInputAttributeDescription *desc =
2182 &input_state->pVertexAttributeDescriptions[i];
2183 const struct vk_format_description *format_desc;
2184 unsigned location = desc->location;
2185 unsigned binding = desc->binding;
2186 unsigned num_format, data_format;
2187 int first_non_void;
2188
2189 if (binding_input_rate & (1u << binding)) {
2190 key.instance_rate_inputs |= 1u << location;
2191 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2192 }
2193
2194 format_desc = vk_format_description(desc->format);
2195 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2196
2197 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2198 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2199
2200 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2201 key.vertex_attribute_bindings[location] = desc->binding;
2202 key.vertex_attribute_offsets[location] = desc->offset;
2203 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2204
2205 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2206 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2207 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2208 uint64_t adjust;
2209 switch(format) {
2210 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2211 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2212 adjust = RADV_ALPHA_ADJUST_SNORM;
2213 break;
2214 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2215 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2216 adjust = RADV_ALPHA_ADJUST_SSCALED;
2217 break;
2218 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2219 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2220 adjust = RADV_ALPHA_ADJUST_SINT;
2221 break;
2222 default:
2223 adjust = 0;
2224 break;
2225 }
2226 key.vertex_alpha_adjust |= adjust << (2 * location);
2227 }
2228
2229 switch (desc->format) {
2230 case VK_FORMAT_B8G8R8A8_UNORM:
2231 case VK_FORMAT_B8G8R8A8_SNORM:
2232 case VK_FORMAT_B8G8R8A8_USCALED:
2233 case VK_FORMAT_B8G8R8A8_SSCALED:
2234 case VK_FORMAT_B8G8R8A8_UINT:
2235 case VK_FORMAT_B8G8R8A8_SINT:
2236 case VK_FORMAT_B8G8R8A8_SRGB:
2237 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2238 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2239 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2240 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2241 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2242 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2243 key.vertex_post_shuffle |= 1 << location;
2244 break;
2245 default:
2246 break;
2247 }
2248 }
2249
2250 if (pCreateInfo->pTessellationState)
2251 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2252
2253
2254 if (pCreateInfo->pMultisampleState &&
2255 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2256 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2257 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2258 key.num_samples = num_samples;
2259 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2260 }
2261
2262 key.col_format = blend->spi_shader_col_format;
2263 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2264 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2265
2266 return key;
2267 }
2268
2269 static bool
2270 radv_nir_stage_uses_xfb(const nir_shader *nir)
2271 {
2272 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2273 bool uses_xfb = !!xfb;
2274
2275 ralloc_free(xfb);
2276 return uses_xfb;
2277 }
2278
2279 static void
2280 radv_fill_shader_keys(struct radv_device *device,
2281 struct radv_shader_variant_key *keys,
2282 const struct radv_pipeline_key *key,
2283 nir_shader **nir)
2284 {
2285 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2286 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2287 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2288 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2289 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2290 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2291 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2292 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2293 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2294 }
2295
2296 if (nir[MESA_SHADER_TESS_CTRL]) {
2297 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2298 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2299 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2300 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2301
2302 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2303 }
2304
2305 if (nir[MESA_SHADER_GEOMETRY]) {
2306 if (nir[MESA_SHADER_TESS_CTRL])
2307 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2308 else
2309 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2310 }
2311
2312 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2313 device->physical_device->rad_info.family != CHIP_NAVI14 &&
2314 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2315 if (nir[MESA_SHADER_TESS_CTRL]) {
2316 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2317 } else {
2318 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2319 }
2320
2321 if (nir[MESA_SHADER_TESS_CTRL] &&
2322 nir[MESA_SHADER_GEOMETRY] &&
2323 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2324 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2325 /* Fallback to the legacy path if tessellation is
2326 * enabled with extreme geometry because
2327 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2328 * might hang.
2329 */
2330 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2331 }
2332
2333 /*
2334 * Disable NGG with geometry shaders. There are a bunch of
2335 * issues still:
2336 * * GS primitives in pipeline statistic queries do not get
2337 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2338 * * General issues with the last primitive missing/corrupt:
2339 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2340 *
2341 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2342 */
2343 if (nir[MESA_SHADER_GEOMETRY]) {
2344 if (nir[MESA_SHADER_TESS_CTRL])
2345 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2346 else
2347 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2348 }
2349
2350 if (!device->physical_device->use_ngg_streamout) {
2351 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2352
2353 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2354 if (nir[i])
2355 last_xfb_stage = i;
2356 }
2357
2358 if (nir[last_xfb_stage] &&
2359 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2360 if (nir[MESA_SHADER_TESS_CTRL])
2361 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2362 else
2363 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2364 }
2365 }
2366 }
2367
2368 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2369 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2370
2371 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2372 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2373 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2374 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2375 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2376 }
2377
2378 static void
2379 radv_fill_shader_info(struct radv_pipeline *pipeline,
2380 struct radv_shader_variant_key *keys,
2381 struct radv_shader_info *infos,
2382 nir_shader **nir)
2383 {
2384 unsigned active_stages = 0;
2385 unsigned filled_stages = 0;
2386
2387 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2388 if (nir[i])
2389 active_stages |= (1 << i);
2390 }
2391
2392 if (nir[MESA_SHADER_FRAGMENT]) {
2393 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2394 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2395 pipeline->layout,
2396 &keys[MESA_SHADER_FRAGMENT],
2397 &infos[MESA_SHADER_FRAGMENT]);
2398
2399 /* TODO: These are no longer used as keys we should refactor this */
2400 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2401 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2402 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2403 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2404 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2405 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2406 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2407 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2408 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2409 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2410 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2411 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2412
2413 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2414 }
2415
2416 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2417 nir[MESA_SHADER_TESS_CTRL]) {
2418 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2419 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2420 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2421
2422 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2423
2424 for (int i = 0; i < 2; i++) {
2425 radv_nir_shader_info_pass(combined_nir[i],
2426 pipeline->layout, &key,
2427 &infos[MESA_SHADER_TESS_CTRL]);
2428 }
2429
2430 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2431 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2432 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2433 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2434
2435 filled_stages |= (1 << MESA_SHADER_VERTEX);
2436 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2437 }
2438
2439 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2440 nir[MESA_SHADER_GEOMETRY]) {
2441 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2442 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2443
2444 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2445
2446 for (int i = 0; i < 2; i++) {
2447 radv_nir_shader_info_pass(combined_nir[i],
2448 pipeline->layout,
2449 &keys[pre_stage],
2450 &infos[MESA_SHADER_GEOMETRY]);
2451 }
2452
2453 filled_stages |= (1 << pre_stage);
2454 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2455 }
2456
2457 active_stages ^= filled_stages;
2458 while (active_stages) {
2459 int i = u_bit_scan(&active_stages);
2460
2461 if (i == MESA_SHADER_TESS_CTRL) {
2462 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2463 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2464 }
2465
2466 if (i == MESA_SHADER_TESS_EVAL) {
2467 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2468 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2469 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2470 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2471 }
2472
2473 radv_nir_shader_info_init(&infos[i]);
2474 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2475 &keys[i], &infos[i]);
2476 }
2477 }
2478
2479 static void
2480 merge_tess_info(struct shader_info *tes_info,
2481 const struct shader_info *tcs_info)
2482 {
2483 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2484 *
2485 * "PointMode. Controls generation of points rather than triangles
2486 * or lines. This functionality defaults to disabled, and is
2487 * enabled if either shader stage includes the execution mode.
2488 *
2489 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2490 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2491 * and OutputVertices, it says:
2492 *
2493 * "One mode must be set in at least one of the tessellation
2494 * shader stages."
2495 *
2496 * So, the fields can be set in either the TCS or TES, but they must
2497 * agree if set in both. Our backend looks at TES, so bitwise-or in
2498 * the values from the TCS.
2499 */
2500 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2501 tes_info->tess.tcs_vertices_out == 0 ||
2502 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2503 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2504
2505 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2506 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2507 tcs_info->tess.spacing == tes_info->tess.spacing);
2508 tes_info->tess.spacing |= tcs_info->tess.spacing;
2509
2510 assert(tcs_info->tess.primitive_mode == 0 ||
2511 tes_info->tess.primitive_mode == 0 ||
2512 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2513 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2514 tes_info->tess.ccw |= tcs_info->tess.ccw;
2515 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2516 }
2517
2518 static
2519 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2520 {
2521 if (!ext)
2522 return;
2523
2524 if (ext->pPipelineCreationFeedback) {
2525 ext->pPipelineCreationFeedback->flags = 0;
2526 ext->pPipelineCreationFeedback->duration = 0;
2527 }
2528
2529 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2530 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2531 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2532 }
2533 }
2534
2535 static
2536 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2537 {
2538 if (!feedback)
2539 return;
2540
2541 feedback->duration -= radv_get_current_time();
2542 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2543 }
2544
2545 static
2546 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2547 {
2548 if (!feedback)
2549 return;
2550
2551 feedback->duration += radv_get_current_time();
2552 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2553 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2554 }
2555
2556 static
2557 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2558 {
2559 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2560 stage == MESA_SHADER_FRAGMENT ||
2561 stage == MESA_SHADER_COMPUTE;
2562 }
2563
2564 static
2565 void radv_create_shaders(struct radv_pipeline *pipeline,
2566 struct radv_device *device,
2567 struct radv_pipeline_cache *cache,
2568 const struct radv_pipeline_key *key,
2569 const VkPipelineShaderStageCreateInfo **pStages,
2570 const VkPipelineCreateFlags flags,
2571 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2572 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2573 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2574 {
2575 struct radv_shader_module fs_m = {0};
2576 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2577 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2578 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2579 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2580 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2581 unsigned char hash[20], gs_copy_hash[20];
2582 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2583
2584 radv_start_feedback(pipeline_feedback);
2585
2586 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2587 if (pStages[i]) {
2588 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2589 if (modules[i]->nir)
2590 _mesa_sha1_compute(modules[i]->nir->info.name,
2591 strlen(modules[i]->nir->info.name),
2592 modules[i]->sha1);
2593
2594 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2595 }
2596 }
2597
2598 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2599 memcpy(gs_copy_hash, hash, 20);
2600 gs_copy_hash[0] ^= 1;
2601
2602 bool found_in_application_cache = true;
2603 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2604 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2605 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2606 &found_in_application_cache);
2607 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2608 }
2609
2610 if (!keep_executable_info &&
2611 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2612 &found_in_application_cache) &&
2613 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2614 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2615 return;
2616 }
2617
2618 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2619 nir_builder fs_b;
2620 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2621 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2622 fs_m.nir = fs_b.shader;
2623 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2624 }
2625
2626 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2627 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2628 bool use_aco = device->physical_device->use_aco;
2629
2630 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2631 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2632
2633 if (!modules[i])
2634 continue;
2635
2636 radv_start_feedback(stage_feedbacks[i]);
2637
2638 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2639 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2640 stage ? stage->pName : "main", i,
2641 stage ? stage->pSpecializationInfo : NULL,
2642 flags, pipeline->layout, aco);
2643
2644 /* We don't want to alter meta shaders IR directly so clone it
2645 * first.
2646 */
2647 if (nir[i]->info.name) {
2648 nir[i] = nir_shader_clone(NULL, nir[i]);
2649 }
2650
2651 radv_stop_feedback(stage_feedbacks[i], false);
2652 }
2653
2654 if (nir[MESA_SHADER_TESS_CTRL]) {
2655 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2656 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2657 }
2658
2659 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2660 radv_link_shaders(pipeline, nir);
2661
2662 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2663 if (nir[i]) {
2664 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2665 nir_lower_non_uniform_ubo_access |
2666 nir_lower_non_uniform_ssbo_access |
2667 nir_lower_non_uniform_texture_access |
2668 nir_lower_non_uniform_image_access);
2669
2670 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2671 if (!aco)
2672 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2673 }
2674
2675 if (radv_can_dump_shader(device, modules[i], false))
2676 nir_print_shader(nir[i], stderr);
2677 }
2678
2679 if (nir[MESA_SHADER_FRAGMENT])
2680 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2681
2682 radv_fill_shader_keys(device, keys, key, nir);
2683
2684 radv_fill_shader_info(pipeline, keys, infos, nir);
2685
2686 if ((nir[MESA_SHADER_VERTEX] &&
2687 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2688 (nir[MESA_SHADER_TESS_EVAL] &&
2689 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2690 struct gfx10_ngg_info *ngg_info;
2691
2692 if (nir[MESA_SHADER_GEOMETRY])
2693 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2694 else if (nir[MESA_SHADER_TESS_CTRL])
2695 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2696 else
2697 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2698
2699 gfx10_get_ngg_info(pCreateInfo, pipeline, nir, infos, ngg_info);
2700 } else if (nir[MESA_SHADER_GEOMETRY]) {
2701 struct gfx9_gs_info *gs_info =
2702 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2703
2704 gfx9_get_gs_info(pCreateInfo, pipeline, nir, infos, gs_info);
2705 }
2706
2707 if (nir[MESA_SHADER_FRAGMENT]) {
2708 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2709 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2710
2711 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2712 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2713 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2714 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2715 infos + MESA_SHADER_FRAGMENT,
2716 keep_executable_info, aco,
2717 &binaries[MESA_SHADER_FRAGMENT]);
2718
2719 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2720 }
2721
2722 /* TODO: These are no longer used as keys we should refactor this */
2723 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2724 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2725 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2726 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2727 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2728 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2729 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2730 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2731 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2732 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2733 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2734 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2735 }
2736
2737 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2738 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2739 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2740 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2741 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2742
2743 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2744
2745 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2746 pipeline->layout,
2747 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2748 false, &binaries[MESA_SHADER_TESS_CTRL]);
2749
2750 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2751 }
2752 modules[MESA_SHADER_VERTEX] = NULL;
2753 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2754 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2755 }
2756
2757 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2758 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2759 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2760 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2761
2762 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2763
2764 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2765 pipeline->layout,
2766 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2767 false, &binaries[MESA_SHADER_GEOMETRY]);
2768
2769 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2770 }
2771 modules[pre_stage] = NULL;
2772 }
2773
2774 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2775 if(modules[i] && !pipeline->shaders[i]) {
2776 if (i == MESA_SHADER_TESS_CTRL) {
2777 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2778 }
2779 if (i == MESA_SHADER_TESS_EVAL) {
2780 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2781 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2782 }
2783
2784 radv_start_feedback(stage_feedbacks[i]);
2785
2786 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2787 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2788 pipeline->layout,
2789 keys + i, infos + i,keep_executable_info,
2790 aco, &binaries[i]);
2791
2792 radv_stop_feedback(stage_feedbacks[i], false);
2793 }
2794 }
2795
2796 if(modules[MESA_SHADER_GEOMETRY]) {
2797 struct radv_shader_binary *gs_copy_binary = NULL;
2798 if (!pipeline->gs_copy_shader &&
2799 !radv_pipeline_has_ngg(pipeline)) {
2800 struct radv_shader_info info = {};
2801 struct radv_shader_variant_key key = {};
2802
2803 key.has_multiview_view_index =
2804 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2805
2806 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2807 pipeline->layout, &key,
2808 &info);
2809
2810 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2811 device, nir[MESA_SHADER_GEOMETRY], &info,
2812 &gs_copy_binary, keep_executable_info,
2813 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2814 }
2815
2816 if (!keep_executable_info && pipeline->gs_copy_shader) {
2817 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2818 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2819
2820 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2821 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2822
2823 radv_pipeline_cache_insert_shaders(device, cache,
2824 gs_copy_hash,
2825 variants,
2826 binaries);
2827 }
2828 free(gs_copy_binary);
2829 }
2830
2831 if (!keep_executable_info) {
2832 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2833 binaries);
2834 }
2835
2836 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2837 free(binaries[i]);
2838 if (nir[i]) {
2839 ralloc_free(nir[i]);
2840
2841 if (radv_can_dump_shader_stats(device, modules[i]))
2842 radv_shader_dump_stats(device,
2843 pipeline->shaders[i],
2844 i, stderr);
2845 }
2846 }
2847
2848 if (fs_m.nir)
2849 ralloc_free(fs_m.nir);
2850
2851 radv_stop_feedback(pipeline_feedback, false);
2852 }
2853
2854 static uint32_t
2855 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2856 gl_shader_stage stage, enum chip_class chip_class)
2857 {
2858 bool has_gs = radv_pipeline_has_gs(pipeline);
2859 bool has_tess = radv_pipeline_has_tess(pipeline);
2860 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2861
2862 switch (stage) {
2863 case MESA_SHADER_FRAGMENT:
2864 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2865 case MESA_SHADER_VERTEX:
2866 if (has_tess) {
2867 if (chip_class >= GFX10) {
2868 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2869 } else if (chip_class == GFX9) {
2870 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2871 } else {
2872 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2873 }
2874
2875 }
2876
2877 if (has_gs) {
2878 if (chip_class >= GFX10) {
2879 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2880 } else {
2881 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2882 }
2883 }
2884
2885 if (has_ngg)
2886 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2887
2888 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2889 case MESA_SHADER_GEOMETRY:
2890 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2891 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2892 case MESA_SHADER_COMPUTE:
2893 return R_00B900_COMPUTE_USER_DATA_0;
2894 case MESA_SHADER_TESS_CTRL:
2895 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2896 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2897 case MESA_SHADER_TESS_EVAL:
2898 if (has_gs) {
2899 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2900 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2901 } else if (has_ngg) {
2902 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2903 } else {
2904 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2905 }
2906 default:
2907 unreachable("unknown shader");
2908 }
2909 }
2910
2911 struct radv_bin_size_entry {
2912 unsigned bpp;
2913 VkExtent2D extent;
2914 };
2915
2916 static VkExtent2D
2917 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2918 {
2919 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2920 {
2921 /* One RB / SE */
2922 {
2923 /* One shader engine */
2924 { 0, {128, 128}},
2925 { 1, { 64, 128}},
2926 { 2, { 32, 128}},
2927 { 3, { 16, 128}},
2928 { 17, { 0, 0}},
2929 { UINT_MAX, { 0, 0}},
2930 },
2931 {
2932 /* Two shader engines */
2933 { 0, {128, 128}},
2934 { 2, { 64, 128}},
2935 { 3, { 32, 128}},
2936 { 5, { 16, 128}},
2937 { 17, { 0, 0}},
2938 { UINT_MAX, { 0, 0}},
2939 },
2940 {
2941 /* Four shader engines */
2942 { 0, {128, 128}},
2943 { 3, { 64, 128}},
2944 { 5, { 16, 128}},
2945 { 17, { 0, 0}},
2946 { UINT_MAX, { 0, 0}},
2947 },
2948 },
2949 {
2950 /* Two RB / SE */
2951 {
2952 /* One shader engine */
2953 { 0, {128, 128}},
2954 { 2, { 64, 128}},
2955 { 3, { 32, 128}},
2956 { 5, { 16, 128}},
2957 { 33, { 0, 0}},
2958 { UINT_MAX, { 0, 0}},
2959 },
2960 {
2961 /* Two shader engines */
2962 { 0, {128, 128}},
2963 { 3, { 64, 128}},
2964 { 5, { 32, 128}},
2965 { 9, { 16, 128}},
2966 { 33, { 0, 0}},
2967 { UINT_MAX, { 0, 0}},
2968 },
2969 {
2970 /* Four shader engines */
2971 { 0, {256, 256}},
2972 { 2, {128, 256}},
2973 { 3, {128, 128}},
2974 { 5, { 64, 128}},
2975 { 9, { 16, 128}},
2976 { 33, { 0, 0}},
2977 { UINT_MAX, { 0, 0}},
2978 },
2979 },
2980 {
2981 /* Four RB / SE */
2982 {
2983 /* One shader engine */
2984 { 0, {128, 256}},
2985 { 2, {128, 128}},
2986 { 3, { 64, 128}},
2987 { 5, { 32, 128}},
2988 { 9, { 16, 128}},
2989 { 33, { 0, 0}},
2990 { UINT_MAX, { 0, 0}},
2991 },
2992 {
2993 /* Two shader engines */
2994 { 0, {256, 256}},
2995 { 2, {128, 256}},
2996 { 3, {128, 128}},
2997 { 5, { 64, 128}},
2998 { 9, { 32, 128}},
2999 { 17, { 16, 128}},
3000 { 33, { 0, 0}},
3001 { UINT_MAX, { 0, 0}},
3002 },
3003 {
3004 /* Four shader engines */
3005 { 0, {256, 512}},
3006 { 2, {256, 256}},
3007 { 3, {128, 256}},
3008 { 5, {128, 128}},
3009 { 9, { 64, 128}},
3010 { 17, { 16, 128}},
3011 { 33, { 0, 0}},
3012 { UINT_MAX, { 0, 0}},
3013 },
3014 },
3015 };
3016 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3017 {
3018 // One RB / SE
3019 {
3020 // One shader engine
3021 { 0, {128, 256}},
3022 { 2, {128, 128}},
3023 { 4, { 64, 128}},
3024 { 7, { 32, 128}},
3025 { 13, { 16, 128}},
3026 { 49, { 0, 0}},
3027 { UINT_MAX, { 0, 0}},
3028 },
3029 {
3030 // Two shader engines
3031 { 0, {256, 256}},
3032 { 2, {128, 256}},
3033 { 4, {128, 128}},
3034 { 7, { 64, 128}},
3035 { 13, { 32, 128}},
3036 { 25, { 16, 128}},
3037 { 49, { 0, 0}},
3038 { UINT_MAX, { 0, 0}},
3039 },
3040 {
3041 // Four shader engines
3042 { 0, {256, 512}},
3043 { 2, {256, 256}},
3044 { 4, {128, 256}},
3045 { 7, {128, 128}},
3046 { 13, { 64, 128}},
3047 { 25, { 16, 128}},
3048 { 49, { 0, 0}},
3049 { UINT_MAX, { 0, 0}},
3050 },
3051 },
3052 {
3053 // Two RB / SE
3054 {
3055 // One shader engine
3056 { 0, {256, 256}},
3057 { 2, {128, 256}},
3058 { 4, {128, 128}},
3059 { 7, { 64, 128}},
3060 { 13, { 32, 128}},
3061 { 25, { 16, 128}},
3062 { 97, { 0, 0}},
3063 { UINT_MAX, { 0, 0}},
3064 },
3065 {
3066 // Two shader engines
3067 { 0, {256, 512}},
3068 { 2, {256, 256}},
3069 { 4, {128, 256}},
3070 { 7, {128, 128}},
3071 { 13, { 64, 128}},
3072 { 25, { 32, 128}},
3073 { 49, { 16, 128}},
3074 { 97, { 0, 0}},
3075 { UINT_MAX, { 0, 0}},
3076 },
3077 {
3078 // Four shader engines
3079 { 0, {512, 512}},
3080 { 2, {256, 512}},
3081 { 4, {256, 256}},
3082 { 7, {128, 256}},
3083 { 13, {128, 128}},
3084 { 25, { 64, 128}},
3085 { 49, { 16, 128}},
3086 { 97, { 0, 0}},
3087 { UINT_MAX, { 0, 0}},
3088 },
3089 },
3090 {
3091 // Four RB / SE
3092 {
3093 // One shader engine
3094 { 0, {256, 512}},
3095 { 2, {256, 256}},
3096 { 4, {128, 256}},
3097 { 7, {128, 128}},
3098 { 13, { 64, 128}},
3099 { 25, { 32, 128}},
3100 { 49, { 16, 128}},
3101 { UINT_MAX, { 0, 0}},
3102 },
3103 {
3104 // Two shader engines
3105 { 0, {512, 512}},
3106 { 2, {256, 512}},
3107 { 4, {256, 256}},
3108 { 7, {128, 256}},
3109 { 13, {128, 128}},
3110 { 25, { 64, 128}},
3111 { 49, { 32, 128}},
3112 { 97, { 16, 128}},
3113 { UINT_MAX, { 0, 0}},
3114 },
3115 {
3116 // Four shader engines
3117 { 0, {512, 512}},
3118 { 4, {256, 512}},
3119 { 7, {256, 256}},
3120 { 13, {128, 256}},
3121 { 25, {128, 128}},
3122 { 49, { 64, 128}},
3123 { 97, { 16, 128}},
3124 { UINT_MAX, { 0, 0}},
3125 },
3126 },
3127 };
3128
3129 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3130 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3131 VkExtent2D extent = {512, 512};
3132
3133 unsigned log_num_rb_per_se =
3134 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3135 pipeline->device->physical_device->rad_info.max_se);
3136 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3137
3138 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3139 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3140 unsigned effective_samples = total_samples;
3141 unsigned color_bytes_per_pixel = 0;
3142
3143 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3144 if (vkblend) {
3145 for (unsigned i = 0; i < subpass->color_count; i++) {
3146 if (!vkblend->pAttachments[i].colorWriteMask)
3147 continue;
3148
3149 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3150 continue;
3151
3152 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3153 color_bytes_per_pixel += vk_format_get_blocksize(format);
3154 }
3155
3156 /* MSAA images typically don't use all samples all the time. */
3157 if (effective_samples >= 2 && ps_iter_samples <= 1)
3158 effective_samples = 2;
3159 color_bytes_per_pixel *= effective_samples;
3160 }
3161
3162 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3163 while(color_entry[1].bpp <= color_bytes_per_pixel)
3164 ++color_entry;
3165
3166 extent = color_entry->extent;
3167
3168 if (subpass->depth_stencil_attachment) {
3169 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3170
3171 /* Coefficients taken from AMDVLK */
3172 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3173 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3174 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3175
3176 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3177 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3178 ++ds_entry;
3179
3180 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3181 extent = ds_entry->extent;
3182 }
3183
3184 return extent;
3185 }
3186
3187 static VkExtent2D
3188 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3189 {
3190 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3191 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3192 VkExtent2D extent = {512, 512};
3193
3194 const unsigned db_tag_size = 64;
3195 const unsigned db_tag_count = 312;
3196 const unsigned color_tag_size = 1024;
3197 const unsigned color_tag_count = 31;
3198 const unsigned fmask_tag_size = 256;
3199 const unsigned fmask_tag_count = 44;
3200
3201 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3202 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3203
3204 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3205 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3206 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3207
3208 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3209 const unsigned samples_log = util_logbase2_ceil(total_samples);
3210
3211 unsigned color_bytes_per_pixel = 0;
3212 unsigned fmask_bytes_per_pixel = 0;
3213
3214 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3215 if (vkblend) {
3216 for (unsigned i = 0; i < subpass->color_count; i++) {
3217 if (!vkblend->pAttachments[i].colorWriteMask)
3218 continue;
3219
3220 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3221 continue;
3222
3223 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3224 color_bytes_per_pixel += vk_format_get_blocksize(format);
3225
3226 if (total_samples > 1) {
3227 const unsigned fmask_array[] = {0, 1, 1, 4};
3228 fmask_bytes_per_pixel += fmask_array[samples_log];
3229 }
3230 }
3231
3232 color_bytes_per_pixel *= total_samples;
3233 }
3234 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3235
3236 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3237 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3238 extent.height = 1ull << (color_pixel_count_log / 2);
3239
3240 if (fmask_bytes_per_pixel) {
3241 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3242
3243 const VkExtent2D fmask_extent = (VkExtent2D){
3244 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3245 .height = 1ull << (color_pixel_count_log / 2)
3246 };
3247
3248 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3249 extent = fmask_extent;
3250 }
3251
3252 if (subpass->depth_stencil_attachment) {
3253 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3254
3255 /* Coefficients taken from AMDVLK */
3256 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3257 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3258 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3259
3260 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3261
3262 const VkExtent2D db_extent = (VkExtent2D){
3263 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3264 .height = 1ull << (color_pixel_count_log / 2)
3265 };
3266
3267 if (db_extent.width * db_extent.height < extent.width * extent.height)
3268 extent = db_extent;
3269 }
3270
3271 extent.width = MAX2(extent.width, 128);
3272 extent.height = MAX2(extent.width, 64);
3273
3274 return extent;
3275 }
3276
3277 static void
3278 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3279 struct radv_pipeline *pipeline,
3280 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3281 {
3282 uint32_t pa_sc_binner_cntl_0 =
3283 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3284 S_028C44_DISABLE_START_OF_PRIM(1);
3285 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3286
3287 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3288 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3289 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3290 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3291 unsigned min_bytes_per_pixel = 0;
3292
3293 if (vkblend) {
3294 for (unsigned i = 0; i < subpass->color_count; i++) {
3295 if (!vkblend->pAttachments[i].colorWriteMask)
3296 continue;
3297
3298 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3299 continue;
3300
3301 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3302 unsigned bytes = vk_format_get_blocksize(format);
3303 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3304 min_bytes_per_pixel = bytes;
3305 }
3306 }
3307
3308 pa_sc_binner_cntl_0 =
3309 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3310 S_028C44_BIN_SIZE_X(0) |
3311 S_028C44_BIN_SIZE_Y(0) |
3312 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3313 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3314 S_028C44_DISABLE_START_OF_PRIM(1);
3315 }
3316
3317 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3318 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3319 }
3320
3321 static void
3322 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3323 struct radv_pipeline *pipeline,
3324 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3325 const struct radv_blend_state *blend)
3326 {
3327 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3328 return;
3329
3330 VkExtent2D bin_size;
3331 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3332 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3333 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3334 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3335 } else
3336 unreachable("Unhandled generation for binning bin size calculation");
3337
3338 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3339 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3340 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3341 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3342
3343 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3344 context_states_per_bin = 1;
3345 persistent_states_per_bin = 1;
3346 fpovs_per_batch = 63;
3347 } else {
3348 /* The context states are affected by the scissor bug. */
3349 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3350 /* 32 causes hangs for RAVEN. */
3351 persistent_states_per_bin = 16;
3352 fpovs_per_batch = 63;
3353 }
3354
3355 bool disable_start_of_prim = true;
3356 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3357
3358 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3359
3360 if (pipeline->device->dfsm_allowed && ps &&
3361 !ps->info.ps.can_discard &&
3362 !ps->info.ps.writes_memory &&
3363 blend->cb_target_enabled_4bit) {
3364 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3365 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3366 }
3367
3368 const uint32_t pa_sc_binner_cntl_0 =
3369 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3370 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3371 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3372 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3373 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3374 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3375 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3376 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3377 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3378 S_028C44_OPTIMAL_BIN_SELECTION(1);
3379
3380 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3381 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3382 } else
3383 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3384 }
3385
3386
3387 static void
3388 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3389 struct radv_pipeline *pipeline,
3390 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3391 const struct radv_graphics_pipeline_create_info *extra)
3392 {
3393 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3394 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3395 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3396 struct radv_render_pass_attachment *attachment = NULL;
3397 uint32_t db_depth_control = 0, db_stencil_control = 0;
3398 uint32_t db_render_control = 0, db_render_override2 = 0;
3399 uint32_t db_render_override = 0;
3400
3401 if (subpass->depth_stencil_attachment)
3402 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3403
3404 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3405 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3406
3407 if (vkds && has_depth_attachment) {
3408 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3409 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3410 S_028800_ZFUNC(vkds->depthCompareOp) |
3411 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3412
3413 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3414 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3415 }
3416
3417 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3418 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3419 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3420 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3421 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3422 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3423
3424 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3425 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3426 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3427 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3428 }
3429
3430 if (attachment && extra) {
3431 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3432 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3433
3434 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3435 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3436 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3437 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3438 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3439 }
3440
3441 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3442 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3443
3444 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3445 /* From VK_EXT_depth_range_unrestricted spec:
3446 *
3447 * "The behavior described in Primitive Clipping still applies.
3448 * If depth clamping is disabled the depth values are still
3449 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3450 * depth clamping is enabled the above equation is ignored and
3451 * the depth values are instead clamped to the VkViewport
3452 * minDepth and maxDepth values, which in the case of this
3453 * extension can be outside of the 0.0 to 1.0 range."
3454 */
3455 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3456 }
3457
3458 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3459 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3460
3461 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3462 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3463 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3464 }
3465
3466 static void
3467 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3468 struct radv_pipeline *pipeline,
3469 const struct radv_blend_state *blend)
3470 {
3471 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3472 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3473 8);
3474 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3475 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3476
3477 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3478
3479 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3480 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3481 }
3482
3483 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3484
3485 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3486 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3487
3488 pipeline->graphics.col_format = blend->spi_shader_col_format;
3489 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3490 }
3491
3492 static const VkConservativeRasterizationModeEXT
3493 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3494 {
3495 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3496 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3497
3498 if (!conservative_raster)
3499 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3500 return conservative_raster->conservativeRasterizationMode;
3501 }
3502
3503 static void
3504 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3505 struct radv_pipeline *pipeline,
3506 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3507 {
3508 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3509 const VkConservativeRasterizationModeEXT mode =
3510 radv_get_conservative_raster_mode(vkraster);
3511 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3512 bool depth_clip_disable = vkraster->depthClampEnable;
3513
3514 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3515 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3516 if (depth_clip_state) {
3517 depth_clip_disable = !depth_clip_state->depthClipEnable;
3518 }
3519
3520 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3521 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3522 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3523 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3524 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3525 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3526
3527 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3528 S_0286D4_FLAT_SHADE_ENA(1) |
3529 S_0286D4_PNT_SPRITE_ENA(1) |
3530 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3531 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3532 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3533 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3534 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3535
3536 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3537 S_028BE4_PIX_CENTER(1) | // TODO verify
3538 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3539 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3540
3541 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3542 S_028814_FACE(vkraster->frontFace) |
3543 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3544 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3545 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3546 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3547 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3548 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3549 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3550 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3551
3552 /* Conservative rasterization. */
3553 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3554 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3555
3556 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3557 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3558 S_028804_OVERRASTERIZATION_AMOUNT(4);
3559
3560 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3561 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3562 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3563
3564 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3565 pa_sc_conservative_rast |=
3566 S_028C4C_OVER_RAST_ENABLE(1) |
3567 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3568 S_028C4C_UNDER_RAST_ENABLE(0) |
3569 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3570 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3571 } else {
3572 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3573 pa_sc_conservative_rast |=
3574 S_028C4C_OVER_RAST_ENABLE(0) |
3575 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3576 S_028C4C_UNDER_RAST_ENABLE(1) |
3577 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3578 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3579 }
3580 }
3581
3582 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3583 pa_sc_conservative_rast);
3584 }
3585
3586
3587 static void
3588 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3589 struct radv_pipeline *pipeline)
3590 {
3591 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3592
3593 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3594 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3595 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3596
3597 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3598 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3599
3600 /* The exclusion bits can be set to improve rasterization efficiency
3601 * if no sample lies on the pixel boundary (-8 sample offset). It's
3602 * currently always TRUE because the driver doesn't support 16 samples.
3603 */
3604 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3605 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3606 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3607 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3608 }
3609
3610 static void
3611 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3612 struct radv_pipeline *pipeline)
3613 {
3614 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3615 const struct radv_shader_variant *vs =
3616 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3617 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3618 pipeline->shaders[MESA_SHADER_VERTEX];
3619 unsigned vgt_primitiveid_en = 0;
3620 uint32_t vgt_gs_mode = 0;
3621
3622 if (radv_pipeline_has_ngg(pipeline))
3623 return;
3624
3625 if (radv_pipeline_has_gs(pipeline)) {
3626 const struct radv_shader_variant *gs =
3627 pipeline->shaders[MESA_SHADER_GEOMETRY];
3628
3629 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3630 pipeline->device->physical_device->rad_info.chip_class);
3631 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3632 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3633 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3634 }
3635
3636 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3637 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3638 }
3639
3640 static void
3641 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3642 struct radeon_cmdbuf *cs,
3643 struct radv_pipeline *pipeline,
3644 struct radv_shader_variant *shader)
3645 {
3646 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3647
3648 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3649 radeon_emit(cs, va >> 8);
3650 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3651 radeon_emit(cs, shader->config.rsrc1);
3652 radeon_emit(cs, shader->config.rsrc2);
3653
3654 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3655 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3656 clip_dist_mask = outinfo->clip_dist_mask;
3657 cull_dist_mask = outinfo->cull_dist_mask;
3658 total_mask = clip_dist_mask | cull_dist_mask;
3659 bool misc_vec_ena = outinfo->writes_pointsize ||
3660 outinfo->writes_layer ||
3661 outinfo->writes_viewport_index;
3662 unsigned spi_vs_out_config, nparams;
3663
3664 /* VS is required to export at least one param. */
3665 nparams = MAX2(outinfo->param_exports, 1);
3666 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3667
3668 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3669 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3670 }
3671
3672 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3673
3674 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3675 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3676 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3677 V_02870C_SPI_SHADER_4COMP :
3678 V_02870C_SPI_SHADER_NONE) |
3679 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3680 V_02870C_SPI_SHADER_4COMP :
3681 V_02870C_SPI_SHADER_NONE) |
3682 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3683 V_02870C_SPI_SHADER_4COMP :
3684 V_02870C_SPI_SHADER_NONE));
3685
3686 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3687 S_028818_VTX_W0_FMT(1) |
3688 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3689 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3690 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3691
3692 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3693 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3694 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3695 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3696 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3697 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3698 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3699 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3700 cull_dist_mask << 8 |
3701 clip_dist_mask);
3702
3703 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3704 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3705 outinfo->writes_viewport_index);
3706 }
3707
3708 static void
3709 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3710 struct radv_pipeline *pipeline,
3711 struct radv_shader_variant *shader)
3712 {
3713 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3714
3715 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3716 radeon_emit(cs, va >> 8);
3717 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3718 radeon_emit(cs, shader->config.rsrc1);
3719 radeon_emit(cs, shader->config.rsrc2);
3720 }
3721
3722 static void
3723 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3724 struct radv_pipeline *pipeline,
3725 struct radv_shader_variant *shader,
3726 const struct radv_tessellation_state *tess)
3727 {
3728 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3729 uint32_t rsrc2 = shader->config.rsrc2;
3730
3731 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3732 radeon_emit(cs, va >> 8);
3733 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3734
3735 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3736 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3737 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3738 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3739
3740 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3741 radeon_emit(cs, shader->config.rsrc1);
3742 radeon_emit(cs, rsrc2);
3743 }
3744
3745 static void
3746 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3747 struct radeon_cmdbuf *cs,
3748 struct radv_pipeline *pipeline,
3749 struct radv_shader_variant *shader)
3750 {
3751 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3752 gl_shader_stage es_type =
3753 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3754 struct radv_shader_variant *es =
3755 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3756 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3757
3758 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3759 radeon_emit(cs, va >> 8);
3760 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3761 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3762 radeon_emit(cs, shader->config.rsrc1);
3763 radeon_emit(cs, shader->config.rsrc2);
3764
3765 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3766 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3767 clip_dist_mask = outinfo->clip_dist_mask;
3768 cull_dist_mask = outinfo->cull_dist_mask;
3769 total_mask = clip_dist_mask | cull_dist_mask;
3770 bool misc_vec_ena = outinfo->writes_pointsize ||
3771 outinfo->writes_layer ||
3772 outinfo->writes_viewport_index;
3773 bool es_enable_prim_id = outinfo->export_prim_id ||
3774 (es && es->info.uses_prim_id);
3775 bool break_wave_at_eoi = false;
3776 unsigned ge_cntl;
3777 unsigned nparams;
3778
3779 if (es_type == MESA_SHADER_TESS_EVAL) {
3780 struct radv_shader_variant *gs =
3781 pipeline->shaders[MESA_SHADER_GEOMETRY];
3782
3783 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3784 break_wave_at_eoi = true;
3785 }
3786
3787 nparams = MAX2(outinfo->param_exports, 1);
3788 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3789 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3790 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3791
3792 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3793 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3794 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3795 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3796 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3797 V_02870C_SPI_SHADER_4COMP :
3798 V_02870C_SPI_SHADER_NONE) |
3799 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3800 V_02870C_SPI_SHADER_4COMP :
3801 V_02870C_SPI_SHADER_NONE) |
3802 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3803 V_02870C_SPI_SHADER_4COMP :
3804 V_02870C_SPI_SHADER_NONE));
3805
3806 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3807 S_028818_VTX_W0_FMT(1) |
3808 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3809 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3810 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3811 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3812 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3813 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3814 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3815 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3816 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3817 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3818 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3819 cull_dist_mask << 8 |
3820 clip_dist_mask);
3821
3822 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3823 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3824 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3825
3826 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3827 ngg_state->vgt_esgs_ring_itemsize);
3828
3829 /* NGG specific registers. */
3830 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3831 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3832
3833 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3834 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3835 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3836 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3837 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3838 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3839 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3840 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3841 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3842 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3843 S_028B90_CNT(gs_num_invocations) |
3844 S_028B90_ENABLE(gs_num_invocations > 1) |
3845 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3846
3847 /* User edge flags are set by the pos exports. If user edge flags are
3848 * not used, we must use hw-generated edge flags and pass them via
3849 * the prim export to prevent drawing lines on internal edges of
3850 * decomposed primitives (such as quads) with polygon mode = lines.
3851 *
3852 * TODO: We should combine hw-generated edge flags with user edge
3853 * flags in the shader.
3854 */
3855 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3856 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3857 !radv_pipeline_has_gs(pipeline)));
3858
3859 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3860 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3861 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3862
3863 /* Bug workaround for a possible hang with non-tessellation cases.
3864 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3865 *
3866 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3867 */
3868 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3869 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3870 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3871 !radv_pipeline_has_tess(pipeline) &&
3872 ngg_state->hw_max_esverts != 256) {
3873 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3874
3875 if (ngg_state->hw_max_esverts > 5) {
3876 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3877 }
3878 }
3879
3880 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3881 }
3882
3883 static void
3884 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3885 struct radv_pipeline *pipeline,
3886 struct radv_shader_variant *shader,
3887 const struct radv_tessellation_state *tess)
3888 {
3889 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3890
3891 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3892 unsigned hs_rsrc2 = shader->config.rsrc2;
3893
3894 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3895 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3896 } else {
3897 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3898 }
3899
3900 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3901 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3902 radeon_emit(cs, va >> 8);
3903 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3904 } else {
3905 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3906 radeon_emit(cs, va >> 8);
3907 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3908 }
3909
3910 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3911 radeon_emit(cs, shader->config.rsrc1);
3912 radeon_emit(cs, hs_rsrc2);
3913 } else {
3914 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3915 radeon_emit(cs, va >> 8);
3916 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3917 radeon_emit(cs, shader->config.rsrc1);
3918 radeon_emit(cs, shader->config.rsrc2);
3919 }
3920 }
3921
3922 static void
3923 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3924 struct radeon_cmdbuf *cs,
3925 struct radv_pipeline *pipeline,
3926 const struct radv_tessellation_state *tess)
3927 {
3928 struct radv_shader_variant *vs;
3929
3930 /* Skip shaders merged into HS/GS */
3931 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3932 if (!vs)
3933 return;
3934
3935 if (vs->info.vs.as_ls)
3936 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3937 else if (vs->info.vs.as_es)
3938 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3939 else if (vs->info.is_ngg)
3940 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
3941 else
3942 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3943 }
3944
3945 static void
3946 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3947 struct radeon_cmdbuf *cs,
3948 struct radv_pipeline *pipeline,
3949 const struct radv_tessellation_state *tess)
3950 {
3951 if (!radv_pipeline_has_tess(pipeline))
3952 return;
3953
3954 struct radv_shader_variant *tes, *tcs;
3955
3956 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3957 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3958
3959 if (tes) {
3960 if (tes->info.is_ngg) {
3961 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
3962 } else if (tes->info.tes.as_es)
3963 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3964 else
3965 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3966 }
3967
3968 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3969
3970 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3971 tess->tf_param);
3972
3973 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3974 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3975 tess->ls_hs_config);
3976 else
3977 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3978 tess->ls_hs_config);
3979
3980 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
3981 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
3982 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3983 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3984 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3985 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3986 }
3987 }
3988
3989 static void
3990 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3991 struct radeon_cmdbuf *cs,
3992 struct radv_pipeline *pipeline,
3993 struct radv_shader_variant *gs)
3994 {
3995 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
3996 unsigned gs_max_out_vertices;
3997 uint8_t *num_components;
3998 uint8_t max_stream;
3999 unsigned offset;
4000 uint64_t va;
4001
4002 gs_max_out_vertices = gs->info.gs.vertices_out;
4003 max_stream = gs->info.gs.max_stream;
4004 num_components = gs->info.gs.num_stream_output_components;
4005
4006 offset = num_components[0] * gs_max_out_vertices;
4007
4008 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4009 radeon_emit(ctx_cs, offset);
4010 if (max_stream >= 1)
4011 offset += num_components[1] * gs_max_out_vertices;
4012 radeon_emit(ctx_cs, offset);
4013 if (max_stream >= 2)
4014 offset += num_components[2] * gs_max_out_vertices;
4015 radeon_emit(ctx_cs, offset);
4016 if (max_stream >= 3)
4017 offset += num_components[3] * gs_max_out_vertices;
4018 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4019
4020 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4021 radeon_emit(ctx_cs, num_components[0]);
4022 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4023 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4024 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4025
4026 uint32_t gs_num_invocations = gs->info.gs.invocations;
4027 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4028 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4029 S_028B90_ENABLE(gs_num_invocations > 0));
4030
4031 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4032 gs_state->vgt_esgs_ring_itemsize);
4033
4034 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4035
4036 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4037 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4038 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4039 radeon_emit(cs, va >> 8);
4040 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4041 } else {
4042 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4043 radeon_emit(cs, va >> 8);
4044 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4045 }
4046
4047 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4048 radeon_emit(cs, gs->config.rsrc1);
4049 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4050
4051 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4052 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4053 } else {
4054 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4055 radeon_emit(cs, va >> 8);
4056 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4057 radeon_emit(cs, gs->config.rsrc1);
4058 radeon_emit(cs, gs->config.rsrc2);
4059 }
4060
4061 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4062 }
4063
4064 static void
4065 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4066 struct radeon_cmdbuf *cs,
4067 struct radv_pipeline *pipeline)
4068 {
4069 struct radv_shader_variant *gs;
4070
4071 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4072 if (!gs)
4073 return;
4074
4075 if (gs->info.is_ngg)
4076 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4077 else
4078 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4079
4080 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4081 gs->info.gs.vertices_out);
4082 }
4083
4084 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4085 {
4086 uint32_t ps_input_cntl;
4087 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4088 ps_input_cntl = S_028644_OFFSET(offset);
4089 if (flat_shade)
4090 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4091 if (float16) {
4092 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4093 S_028644_ATTR0_VALID(1);
4094 }
4095 } else {
4096 /* The input is a DEFAULT_VAL constant. */
4097 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4098 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4099 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4100 ps_input_cntl = S_028644_OFFSET(0x20) |
4101 S_028644_DEFAULT_VAL(offset);
4102 }
4103 return ps_input_cntl;
4104 }
4105
4106 static void
4107 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4108 struct radv_pipeline *pipeline)
4109 {
4110 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4111 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4112 uint32_t ps_input_cntl[32];
4113
4114 unsigned ps_offset = 0;
4115
4116 if (ps->info.ps.prim_id_input) {
4117 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4118 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4119 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4120 ++ps_offset;
4121 }
4122 }
4123
4124 if (ps->info.ps.layer_input ||
4125 ps->info.needs_multiview_view_index) {
4126 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4127 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4128 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4129 else
4130 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4131 ++ps_offset;
4132 }
4133
4134 if (ps->info.ps.has_pcoord) {
4135 unsigned val;
4136 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4137 ps_input_cntl[ps_offset] = val;
4138 ps_offset++;
4139 }
4140
4141 if (ps->info.ps.num_input_clips_culls) {
4142 unsigned vs_offset;
4143
4144 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4145 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4146 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4147 ++ps_offset;
4148 }
4149
4150 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4151 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4152 ps->info.ps.num_input_clips_culls > 4) {
4153 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4154 ++ps_offset;
4155 }
4156 }
4157
4158 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4159 unsigned vs_offset;
4160 bool flat_shade;
4161 bool float16;
4162 if (!(ps->info.ps.input_mask & (1u << i)))
4163 continue;
4164
4165 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4166 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4167 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4168 ++ps_offset;
4169 continue;
4170 }
4171
4172 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4173 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4174
4175 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4176 ++ps_offset;
4177 }
4178
4179 if (ps_offset) {
4180 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4181 for (unsigned i = 0; i < ps_offset; i++) {
4182 radeon_emit(ctx_cs, ps_input_cntl[i]);
4183 }
4184 }
4185 }
4186
4187 static uint32_t
4188 radv_compute_db_shader_control(const struct radv_device *device,
4189 const struct radv_pipeline *pipeline,
4190 const struct radv_shader_variant *ps)
4191 {
4192 unsigned z_order;
4193 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4194 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4195 else
4196 z_order = V_02880C_LATE_Z;
4197
4198 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4199 !device->physical_device->rad_info.rbplus_allowed;
4200
4201 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4202 * but this appears to break Project Cars (DXVK). See
4203 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4204 */
4205 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4206
4207 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4208 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4209 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4210 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4211 S_02880C_Z_ORDER(z_order) |
4212 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4213 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4214 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4215 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4216 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4217 }
4218
4219 static void
4220 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4221 struct radeon_cmdbuf *cs,
4222 struct radv_pipeline *pipeline)
4223 {
4224 struct radv_shader_variant *ps;
4225 uint64_t va;
4226 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4227
4228 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4229 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4230
4231 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4232 radeon_emit(cs, va >> 8);
4233 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4234 radeon_emit(cs, ps->config.rsrc1);
4235 radeon_emit(cs, ps->config.rsrc2);
4236
4237 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4238 radv_compute_db_shader_control(pipeline->device,
4239 pipeline, ps));
4240
4241 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4242 ps->config.spi_ps_input_ena);
4243
4244 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4245 ps->config.spi_ps_input_addr);
4246
4247 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4248 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4249 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4250
4251 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4252
4253 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4254 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4255 ps->info.ps.writes_stencil,
4256 ps->info.ps.writes_sample_mask));
4257
4258 if (pipeline->device->dfsm_allowed) {
4259 /* optimise this? */
4260 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4261 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4262 }
4263 }
4264
4265 static void
4266 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4267 struct radv_pipeline *pipeline)
4268 {
4269 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4270 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4271 return;
4272
4273 unsigned vtx_reuse_depth = 30;
4274 if (radv_pipeline_has_tess(pipeline) &&
4275 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4276 vtx_reuse_depth = 14;
4277 }
4278 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4279 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4280 }
4281
4282 static uint32_t
4283 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4284 {
4285 uint32_t stages = 0;
4286 if (radv_pipeline_has_tess(pipeline)) {
4287 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4288 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4289
4290 if (radv_pipeline_has_gs(pipeline))
4291 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4292 S_028B54_GS_EN(1);
4293 else if (radv_pipeline_has_ngg(pipeline))
4294 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4295 else
4296 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4297 } else if (radv_pipeline_has_gs(pipeline)) {
4298 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4299 S_028B54_GS_EN(1);
4300 } else if (radv_pipeline_has_ngg(pipeline)) {
4301 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4302 }
4303
4304 if (radv_pipeline_has_ngg(pipeline)) {
4305 stages |= S_028B54_PRIMGEN_EN(1);
4306 if (pipeline->streamout_shader)
4307 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4308 } else if (radv_pipeline_has_gs(pipeline)) {
4309 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4310 }
4311
4312 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4313 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4314
4315 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4316 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4317
4318 if (radv_pipeline_has_tess(pipeline))
4319 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4320
4321 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4322 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4323 if (pipeline->gs_copy_shader)
4324 vs_size = pipeline->gs_copy_shader->info.wave_size;
4325 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4326 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4327 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4328 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4329
4330 if (radv_pipeline_has_ngg(pipeline))
4331 gs_size = vs_size;
4332
4333 /* legacy GS only supports Wave64 */
4334 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4335 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4336 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4337 }
4338
4339 return stages;
4340 }
4341
4342 static uint32_t
4343 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4344 {
4345 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4346 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4347
4348 if (!discard_rectangle_info)
4349 return 0xffff;
4350
4351 unsigned mask = 0;
4352
4353 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4354 /* Interpret i as a bitmask, and then set the bit in the mask if
4355 * that combination of rectangles in which the pixel is contained
4356 * should pass the cliprect test. */
4357 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4358
4359 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4360 !relevant_subset)
4361 continue;
4362
4363 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4364 relevant_subset)
4365 continue;
4366
4367 mask |= 1u << i;
4368 }
4369
4370 return mask;
4371 }
4372
4373 static void
4374 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4375 struct radv_pipeline *pipeline,
4376 const struct radv_tessellation_state *tess)
4377 {
4378 bool break_wave_at_eoi = false;
4379 unsigned primgroup_size;
4380 unsigned vertgroup_size;
4381
4382 if (radv_pipeline_has_tess(pipeline)) {
4383 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4384 vertgroup_size = 0;
4385 } else if (radv_pipeline_has_gs(pipeline)) {
4386 const struct gfx9_gs_info *gs_state =
4387 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4388 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4389 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4390 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4391 } else {
4392 primgroup_size = 128; /* recommended without a GS and tess */
4393 vertgroup_size = 0;
4394 }
4395
4396 if (radv_pipeline_has_tess(pipeline)) {
4397 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4398 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4399 break_wave_at_eoi = true;
4400 }
4401
4402 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4403 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4404 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4405 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4406 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4407 }
4408
4409 static void
4410 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4411 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4412 const struct radv_graphics_pipeline_create_info *extra,
4413 const struct radv_blend_state *blend,
4414 const struct radv_tessellation_state *tess,
4415 unsigned prim, unsigned gs_out)
4416 {
4417 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4418 struct radeon_cmdbuf *cs = &pipeline->cs;
4419
4420 cs->max_dw = 64;
4421 ctx_cs->max_dw = 256;
4422 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4423 ctx_cs->buf = cs->buf + cs->max_dw;
4424
4425 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4426 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4427 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4428 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4429 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4430 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4431 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4432 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4433 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4434 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4435 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4436 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4437
4438 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4439 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4440
4441 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4442 S_0286E8_WAVES(pipeline->max_waves) |
4443 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4444
4445 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4446
4447 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4448 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4449 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4450 } else {
4451 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4452 }
4453 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4454
4455 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4456
4457 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4458
4459 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4460 assert(cs->cdw <= cs->max_dw);
4461 }
4462
4463 static struct radv_ia_multi_vgt_param_helpers
4464 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4465 const struct radv_tessellation_state *tess,
4466 uint32_t prim)
4467 {
4468 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4469 const struct radv_device *device = pipeline->device;
4470
4471 if (radv_pipeline_has_tess(pipeline))
4472 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4473 else if (radv_pipeline_has_gs(pipeline))
4474 ia_multi_vgt_param.primgroup_size = 64;
4475 else
4476 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4477
4478 /* GS requirement. */
4479 ia_multi_vgt_param.partial_es_wave = false;
4480 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4481 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4482 ia_multi_vgt_param.partial_es_wave = true;
4483
4484 ia_multi_vgt_param.wd_switch_on_eop = false;
4485 if (device->physical_device->rad_info.chip_class >= GFX7) {
4486 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4487 * 4 shader engines. Set 1 to pass the assertion below.
4488 * The other cases are hardware requirements. */
4489 if (device->physical_device->rad_info.max_se < 4 ||
4490 prim == V_008958_DI_PT_POLYGON ||
4491 prim == V_008958_DI_PT_LINELOOP ||
4492 prim == V_008958_DI_PT_TRIFAN ||
4493 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4494 (pipeline->graphics.prim_restart_enable &&
4495 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4496 (prim != V_008958_DI_PT_POINTLIST &&
4497 prim != V_008958_DI_PT_LINESTRIP))))
4498 ia_multi_vgt_param.wd_switch_on_eop = true;
4499 }
4500
4501 ia_multi_vgt_param.ia_switch_on_eoi = false;
4502 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4503 ia_multi_vgt_param.ia_switch_on_eoi = true;
4504 if (radv_pipeline_has_gs(pipeline) &&
4505 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4506 ia_multi_vgt_param.ia_switch_on_eoi = true;
4507 if (radv_pipeline_has_tess(pipeline)) {
4508 /* SWITCH_ON_EOI must be set if PrimID is used. */
4509 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4510 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4511 ia_multi_vgt_param.ia_switch_on_eoi = true;
4512 }
4513
4514 ia_multi_vgt_param.partial_vs_wave = false;
4515 if (radv_pipeline_has_tess(pipeline)) {
4516 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4517 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4518 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4519 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4520 radv_pipeline_has_gs(pipeline))
4521 ia_multi_vgt_param.partial_vs_wave = true;
4522 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4523 if (device->physical_device->rad_info.has_distributed_tess) {
4524 if (radv_pipeline_has_gs(pipeline)) {
4525 if (device->physical_device->rad_info.chip_class <= GFX8)
4526 ia_multi_vgt_param.partial_es_wave = true;
4527 } else {
4528 ia_multi_vgt_param.partial_vs_wave = true;
4529 }
4530 }
4531 }
4532
4533 /* Workaround for a VGT hang when strip primitive types are used with
4534 * primitive restart.
4535 */
4536 if (pipeline->graphics.prim_restart_enable &&
4537 (prim == V_008958_DI_PT_LINESTRIP ||
4538 prim == V_008958_DI_PT_TRISTRIP ||
4539 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4540 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4541 ia_multi_vgt_param.partial_vs_wave = true;
4542 }
4543
4544 if (radv_pipeline_has_gs(pipeline)) {
4545 /* On these chips there is the possibility of a hang if the
4546 * pipeline uses a GS and partial_vs_wave is not set.
4547 *
4548 * This mostly does not hit 4-SE chips, as those typically set
4549 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4550 * with GS due to another workaround.
4551 *
4552 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4553 */
4554 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4555 device->physical_device->rad_info.family == CHIP_FIJI ||
4556 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4557 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4558 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4559 device->physical_device->rad_info.family == CHIP_VEGAM) {
4560 ia_multi_vgt_param.partial_vs_wave = true;
4561 }
4562 }
4563
4564 ia_multi_vgt_param.base =
4565 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4566 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4567 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4568 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4569 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4570
4571 return ia_multi_vgt_param;
4572 }
4573
4574
4575 static void
4576 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4577 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4578 {
4579 const VkPipelineVertexInputStateCreateInfo *vi_info =
4580 pCreateInfo->pVertexInputState;
4581 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4582
4583 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4584 const VkVertexInputAttributeDescription *desc =
4585 &vi_info->pVertexAttributeDescriptions[i];
4586 unsigned loc = desc->location;
4587 const struct vk_format_description *format_desc;
4588
4589 format_desc = vk_format_description(desc->format);
4590
4591 velems->format_size[loc] = format_desc->block.bits / 8;
4592 }
4593
4594 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4595 const VkVertexInputBindingDescription *desc =
4596 &vi_info->pVertexBindingDescriptions[i];
4597
4598 pipeline->binding_stride[desc->binding] = desc->stride;
4599 pipeline->num_vertex_bindings =
4600 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4601 }
4602 }
4603
4604 static struct radv_shader_variant *
4605 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4606 {
4607 int i;
4608
4609 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4610 struct radv_shader_variant *shader =
4611 radv_get_shader(pipeline, i);
4612
4613 if (shader && shader->info.so.num_outputs > 0)
4614 return shader;
4615 }
4616
4617 return NULL;
4618 }
4619
4620 static VkResult
4621 radv_pipeline_init(struct radv_pipeline *pipeline,
4622 struct radv_device *device,
4623 struct radv_pipeline_cache *cache,
4624 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4625 const struct radv_graphics_pipeline_create_info *extra)
4626 {
4627 VkResult result;
4628 bool has_view_index = false;
4629
4630 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4631 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4632 if (subpass->view_mask)
4633 has_view_index = true;
4634
4635 pipeline->device = device;
4636 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4637 assert(pipeline->layout);
4638
4639 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4640
4641 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4642 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4643 radv_init_feedback(creation_feedback);
4644
4645 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4646
4647 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4648 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4649 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4650 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4651 pStages[stage] = &pCreateInfo->pStages[i];
4652 if(creation_feedback)
4653 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4654 }
4655
4656 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4657 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pCreateInfo, pipeline_feedback, stage_feedbacks);
4658
4659 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4660 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4661 uint32_t gs_out;
4662 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4663
4664 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4665
4666 if (radv_pipeline_has_gs(pipeline)) {
4667 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4668 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4669 } else if (radv_pipeline_has_tess(pipeline)) {
4670 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4671 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4672 else
4673 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4674 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4675 } else {
4676 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4677 }
4678 if (extra && extra->use_rectlist) {
4679 prim = V_008958_DI_PT_RECTLIST;
4680 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4681 pipeline->graphics.can_use_guardband = true;
4682 if (radv_pipeline_has_ngg(pipeline))
4683 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4684 }
4685 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4686 /* prim vertex count will need TESS changes */
4687 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4688
4689 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4690
4691 /* Ensure that some export memory is always allocated, for two reasons:
4692 *
4693 * 1) Correctness: The hardware ignores the EXEC mask if no export
4694 * memory is allocated, so KILL and alpha test do not work correctly
4695 * without this.
4696 * 2) Performance: Every shader needs at least a NULL export, even when
4697 * it writes no color/depth output. The NULL export instruction
4698 * stalls without this setting.
4699 *
4700 * Don't add this to CB_SHADER_MASK.
4701 *
4702 * GFX10 supports pixel shaders without exports by setting both the
4703 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4704 * instructions if any are present.
4705 */
4706 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4707 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4708 ps->info.ps.can_discard) &&
4709 !blend.spi_shader_col_format) {
4710 if (!ps->info.ps.writes_z &&
4711 !ps->info.ps.writes_stencil &&
4712 !ps->info.ps.writes_sample_mask)
4713 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4714 }
4715
4716 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4717 if (pipeline->shaders[i]) {
4718 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4719 }
4720 }
4721
4722 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4723 struct radv_shader_variant *gs =
4724 pipeline->shaders[MESA_SHADER_GEOMETRY];
4725
4726 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4727 }
4728
4729 struct radv_tessellation_state tess = {0};
4730 if (radv_pipeline_has_tess(pipeline)) {
4731 if (prim == V_008958_DI_PT_PATCH) {
4732 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4733 pipeline->graphics.prim_vertex_count.incr = 1;
4734 }
4735 tess = calculate_tess_state(pipeline, pCreateInfo);
4736 }
4737
4738 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4739
4740 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4741
4742 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4743 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4744
4745 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4746 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4747 if (loc->sgpr_idx != -1) {
4748 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4749 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4750 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4751 pipeline->graphics.vtx_emit_num = 3;
4752 else
4753 pipeline->graphics.vtx_emit_num = 2;
4754 }
4755
4756 /* Find the last vertex shader stage that eventually uses streamout. */
4757 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4758
4759 result = radv_pipeline_scratch_init(device, pipeline);
4760 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
4761
4762 return result;
4763 }
4764
4765 VkResult
4766 radv_graphics_pipeline_create(
4767 VkDevice _device,
4768 VkPipelineCache _cache,
4769 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4770 const struct radv_graphics_pipeline_create_info *extra,
4771 const VkAllocationCallbacks *pAllocator,
4772 VkPipeline *pPipeline)
4773 {
4774 RADV_FROM_HANDLE(radv_device, device, _device);
4775 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4776 struct radv_pipeline *pipeline;
4777 VkResult result;
4778
4779 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4780 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4781 if (pipeline == NULL)
4782 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4783
4784 result = radv_pipeline_init(pipeline, device, cache,
4785 pCreateInfo, extra);
4786 if (result != VK_SUCCESS) {
4787 radv_pipeline_destroy(device, pipeline, pAllocator);
4788 return result;
4789 }
4790
4791 *pPipeline = radv_pipeline_to_handle(pipeline);
4792
4793 return VK_SUCCESS;
4794 }
4795
4796 VkResult radv_CreateGraphicsPipelines(
4797 VkDevice _device,
4798 VkPipelineCache pipelineCache,
4799 uint32_t count,
4800 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4801 const VkAllocationCallbacks* pAllocator,
4802 VkPipeline* pPipelines)
4803 {
4804 VkResult result = VK_SUCCESS;
4805 unsigned i = 0;
4806
4807 for (; i < count; i++) {
4808 VkResult r;
4809 r = radv_graphics_pipeline_create(_device,
4810 pipelineCache,
4811 &pCreateInfos[i],
4812 NULL, pAllocator, &pPipelines[i]);
4813 if (r != VK_SUCCESS) {
4814 result = r;
4815 pPipelines[i] = VK_NULL_HANDLE;
4816 }
4817 }
4818
4819 return result;
4820 }
4821
4822
4823 static void
4824 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4825 {
4826 struct radv_shader_variant *compute_shader;
4827 struct radv_device *device = pipeline->device;
4828 unsigned threads_per_threadgroup;
4829 unsigned threadgroups_per_cu = 1;
4830 unsigned waves_per_threadgroup;
4831 unsigned max_waves_per_sh = 0;
4832 uint64_t va;
4833
4834 pipeline->cs.buf = malloc(20 * 4);
4835 pipeline->cs.max_dw = 20;
4836
4837 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4838 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4839
4840 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4841 radeon_emit(&pipeline->cs, va >> 8);
4842 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4843
4844 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4845 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4846 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4847
4848 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4849 S_00B860_WAVES(pipeline->max_waves) |
4850 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4851
4852 /* Calculate best compute resource limits. */
4853 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4854 compute_shader->info.cs.block_size[1] *
4855 compute_shader->info.cs.block_size[2];
4856 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4857 device->physical_device->cs_wave_size);
4858
4859 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4860 waves_per_threadgroup == 1)
4861 threadgroups_per_cu = 2;
4862
4863 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4864 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4865 waves_per_threadgroup,
4866 max_waves_per_sh,
4867 threadgroups_per_cu));
4868
4869 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4870 radeon_emit(&pipeline->cs,
4871 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4872 radeon_emit(&pipeline->cs,
4873 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4874 radeon_emit(&pipeline->cs,
4875 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4876
4877 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4878 }
4879
4880 static VkResult radv_compute_pipeline_create(
4881 VkDevice _device,
4882 VkPipelineCache _cache,
4883 const VkComputePipelineCreateInfo* pCreateInfo,
4884 const VkAllocationCallbacks* pAllocator,
4885 VkPipeline* pPipeline)
4886 {
4887 RADV_FROM_HANDLE(radv_device, device, _device);
4888 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4889 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4890 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4891 struct radv_pipeline *pipeline;
4892 VkResult result;
4893
4894 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4895 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4896 if (pipeline == NULL)
4897 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4898
4899 pipeline->device = device;
4900 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4901 assert(pipeline->layout);
4902
4903 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4904 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4905 radv_init_feedback(creation_feedback);
4906
4907 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4908 if (creation_feedback)
4909 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4910
4911 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4912 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, NULL, pipeline_feedback, stage_feedbacks);
4913
4914 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4915 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4916 result = radv_pipeline_scratch_init(device, pipeline);
4917 if (result != VK_SUCCESS) {
4918 radv_pipeline_destroy(device, pipeline, pAllocator);
4919 return result;
4920 }
4921
4922 radv_compute_generate_pm4(pipeline);
4923
4924 *pPipeline = radv_pipeline_to_handle(pipeline);
4925
4926 return VK_SUCCESS;
4927 }
4928
4929 VkResult radv_CreateComputePipelines(
4930 VkDevice _device,
4931 VkPipelineCache pipelineCache,
4932 uint32_t count,
4933 const VkComputePipelineCreateInfo* pCreateInfos,
4934 const VkAllocationCallbacks* pAllocator,
4935 VkPipeline* pPipelines)
4936 {
4937 VkResult result = VK_SUCCESS;
4938
4939 unsigned i = 0;
4940 for (; i < count; i++) {
4941 VkResult r;
4942 r = radv_compute_pipeline_create(_device, pipelineCache,
4943 &pCreateInfos[i],
4944 pAllocator, &pPipelines[i]);
4945 if (r != VK_SUCCESS) {
4946 result = r;
4947 pPipelines[i] = VK_NULL_HANDLE;
4948 }
4949 }
4950
4951 return result;
4952 }
4953
4954
4955 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
4956 {
4957 uint32_t ret = 0;
4958 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4959 if (!pipeline->shaders[i])
4960 continue;
4961
4962 if (i == MESA_SHADER_GEOMETRY &&
4963 !radv_pipeline_has_ngg(pipeline)) {
4964 ret += 2u;
4965 } else {
4966 ret += 1u;
4967 }
4968
4969 }
4970 return ret;
4971 }
4972
4973 static struct radv_shader_variant *
4974 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
4975 {
4976 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4977 if (!pipeline->shaders[i])
4978 continue;
4979 if (!index) {
4980 *stage = i;
4981 return pipeline->shaders[i];
4982 }
4983
4984 --index;
4985
4986 if (i == MESA_SHADER_GEOMETRY &&
4987 !radv_pipeline_has_ngg(pipeline)) {
4988 if (!index) {
4989 *stage = i;
4990 return pipeline->gs_copy_shader;
4991 }
4992 --index;
4993 }
4994 }
4995
4996 *stage = -1;
4997 return NULL;
4998 }
4999
5000 /* Basically strlcpy (which does not exist on linux) specialized for
5001 * descriptions. */
5002 static void desc_copy(char *desc, const char *src) {
5003 int len = strlen(src);
5004 assert(len < VK_MAX_DESCRIPTION_SIZE);
5005 memcpy(desc, src, len);
5006 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5007 }
5008
5009 VkResult radv_GetPipelineExecutablePropertiesKHR(
5010 VkDevice _device,
5011 const VkPipelineInfoKHR* pPipelineInfo,
5012 uint32_t* pExecutableCount,
5013 VkPipelineExecutablePropertiesKHR* pProperties)
5014 {
5015 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5016 const uint32_t total_count = radv_get_executable_count(pipeline);
5017
5018 if (!pProperties) {
5019 *pExecutableCount = total_count;
5020 return VK_SUCCESS;
5021 }
5022
5023 const uint32_t count = MIN2(total_count, *pExecutableCount);
5024 for (unsigned i = 0, executable_idx = 0;
5025 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5026 if (!pipeline->shaders[i])
5027 continue;
5028 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5029 const char *name = NULL;
5030 const char *description = NULL;
5031 switch(i) {
5032 case MESA_SHADER_VERTEX:
5033 name = "Vertex Shader";
5034 description = "Vulkan Vertex Shader";
5035 break;
5036 case MESA_SHADER_TESS_CTRL:
5037 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5038 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5039 name = "Vertex + Tessellation Control Shaders";
5040 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5041 } else {
5042 name = "Tessellation Control Shader";
5043 description = "Vulkan Tessellation Control Shader";
5044 }
5045 break;
5046 case MESA_SHADER_TESS_EVAL:
5047 name = "Tessellation Evaluation Shader";
5048 description = "Vulkan Tessellation Evaluation Shader";
5049 break;
5050 case MESA_SHADER_GEOMETRY:
5051 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5052 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5053 name = "Tessellation Evaluation + Geometry Shaders";
5054 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5055 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5056 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5057 name = "Vertex + Geometry Shader";
5058 description = "Combined Vulkan Vertex and Geometry Shaders";
5059 } else {
5060 name = "Geometry Shader";
5061 description = "Vulkan Geometry Shader";
5062 }
5063 break;
5064 case MESA_SHADER_FRAGMENT:
5065 name = "Fragment Shader";
5066 description = "Vulkan Fragment Shader";
5067 break;
5068 case MESA_SHADER_COMPUTE:
5069 name = "Compute Shader";
5070 description = "Vulkan Compute Shader";
5071 break;
5072 }
5073
5074 desc_copy(pProperties[executable_idx].name, name);
5075 desc_copy(pProperties[executable_idx].description, description);
5076
5077 ++executable_idx;
5078 if (i == MESA_SHADER_GEOMETRY &&
5079 !radv_pipeline_has_ngg(pipeline)) {
5080 assert(pipeline->gs_copy_shader);
5081 if (executable_idx >= count)
5082 break;
5083
5084 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5085 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5086 desc_copy(pProperties[executable_idx].description,
5087 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5088
5089 ++executable_idx;
5090 }
5091 }
5092
5093 for (unsigned i = 0; i < count; ++i)
5094 pProperties[i].subgroupSize = 64;
5095
5096 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5097 *pExecutableCount = count;
5098 return result;
5099 }
5100
5101 VkResult radv_GetPipelineExecutableStatisticsKHR(
5102 VkDevice _device,
5103 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5104 uint32_t* pStatisticCount,
5105 VkPipelineExecutableStatisticKHR* pStatistics)
5106 {
5107 RADV_FROM_HANDLE(radv_device, device, _device);
5108 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5109 gl_shader_stage stage;
5110 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5111
5112 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5113 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5114 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5115
5116 VkPipelineExecutableStatisticKHR *s = pStatistics;
5117 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5118 VkResult result = VK_SUCCESS;
5119
5120 if (s < end) {
5121 desc_copy(s->name, "SGPRs");
5122 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5123 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5124 s->value.u64 = shader->config.num_sgprs;
5125 }
5126 ++s;
5127
5128 if (s < end) {
5129 desc_copy(s->name, "VGPRs");
5130 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5131 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5132 s->value.u64 = shader->config.num_vgprs;
5133 }
5134 ++s;
5135
5136 if (s < end) {
5137 desc_copy(s->name, "Spilled SGPRs");
5138 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5139 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5140 s->value.u64 = shader->config.spilled_sgprs;
5141 }
5142 ++s;
5143
5144 if (s < end) {
5145 desc_copy(s->name, "Spilled VGPRs");
5146 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5147 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5148 s->value.u64 = shader->config.spilled_vgprs;
5149 }
5150 ++s;
5151
5152 if (s < end) {
5153 desc_copy(s->name, "PrivMem VGPRs");
5154 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5155 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5156 s->value.u64 = shader->info.private_mem_vgprs;
5157 }
5158 ++s;
5159
5160 if (s < end) {
5161 desc_copy(s->name, "Code size");
5162 desc_copy(s->description, "Code size in bytes");
5163 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5164 s->value.u64 = shader->exec_size;
5165 }
5166 ++s;
5167
5168 if (s < end) {
5169 desc_copy(s->name, "LDS size");
5170 desc_copy(s->description, "LDS size in bytes per workgroup");
5171 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5172 s->value.u64 = shader->config.lds_size * lds_increment;
5173 }
5174 ++s;
5175
5176 if (s < end) {
5177 desc_copy(s->name, "Scratch size");
5178 desc_copy(s->description, "Private memory in bytes per subgroup");
5179 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5180 s->value.u64 = shader->config.scratch_bytes_per_wave;
5181 }
5182 ++s;
5183
5184 if (s < end) {
5185 desc_copy(s->name, "Subgroups per SIMD");
5186 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5187 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5188 s->value.u64 = max_waves;
5189 }
5190 ++s;
5191
5192 if (!pStatistics)
5193 *pStatisticCount = s - pStatistics;
5194 else if (s > end) {
5195 *pStatisticCount = end - pStatistics;
5196 result = VK_INCOMPLETE;
5197 } else {
5198 *pStatisticCount = s - pStatistics;
5199 }
5200
5201 return result;
5202 }
5203
5204 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5205 {
5206 size_t total_size = strlen(src) + 1;
5207
5208 if (!data) {
5209 *data_size = total_size;
5210 return VK_SUCCESS;
5211 }
5212
5213 size_t size = MIN2(total_size, *data_size);
5214
5215 memcpy(data, src, size);
5216 if (size)
5217 *((char*)data + size - 1) = 0;
5218 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5219 }
5220
5221 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5222 VkDevice device,
5223 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5224 uint32_t* pInternalRepresentationCount,
5225 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5226 {
5227 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5228 gl_shader_stage stage;
5229 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5230
5231 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5232 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5233 VkResult result = VK_SUCCESS;
5234 /* optimized NIR */
5235 if (p < end) {
5236 p->isText = true;
5237 desc_copy(p->name, "NIR Shader(s)");
5238 desc_copy(p->description, "The optimized NIR shader(s)");
5239 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5240 result = VK_INCOMPLETE;
5241 }
5242 ++p;
5243
5244 /* backend IR */
5245 if (p < end) {
5246 p->isText = true;
5247 if (shader->aco_used) {
5248 desc_copy(p->name, "ACO IR");
5249 desc_copy(p->description, "The ACO IR after some optimizations");
5250 } else {
5251 desc_copy(p->name, "LLVM IR");
5252 desc_copy(p->description, "The LLVM IR after some optimizations");
5253 }
5254 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5255 result = VK_INCOMPLETE;
5256 }
5257 ++p;
5258
5259 /* Disassembler */
5260 if (p < end) {
5261 p->isText = true;
5262 desc_copy(p->name, "Assembly");
5263 desc_copy(p->description, "Final Assembly");
5264 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5265 result = VK_INCOMPLETE;
5266 }
5267 ++p;
5268
5269 if (!pInternalRepresentations)
5270 *pInternalRepresentationCount = p - pInternalRepresentations;
5271 else if(p > end) {
5272 result = VK_INCOMPLETE;
5273 *pInternalRepresentationCount = end - pInternalRepresentations;
5274 } else {
5275 *pInternalRepresentationCount = p - pInternalRepresentations;
5276 }
5277
5278 return result;
5279 }