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radv: enable conditional discard optimisation on radv.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107 void radv_DestroyPipeline(
108 VkDevice _device,
109 VkPipeline _pipeline,
110 const VkAllocationCallbacks* pAllocator)
111 {
112 RADV_FROM_HANDLE(radv_device, device, _device);
113 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
114
115 if (!_pipeline)
116 return;
117
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 vk_free2(&device->alloc, pAllocator, pipeline);
123 }
124
125
126 static void
127 radv_optimize_nir(struct nir_shader *shader)
128 {
129 bool progress;
130
131 do {
132 progress = false;
133
134 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
135 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
136 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
137
138 NIR_PASS(progress, shader, nir_copy_prop);
139 NIR_PASS(progress, shader, nir_opt_remove_phis);
140 NIR_PASS(progress, shader, nir_opt_dce);
141 NIR_PASS(progress, shader, nir_opt_dead_cf);
142 NIR_PASS(progress, shader, nir_opt_cse);
143 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
144 NIR_PASS(progress, shader, nir_opt_algebraic);
145 NIR_PASS(progress, shader, nir_opt_constant_folding);
146 NIR_PASS(progress, shader, nir_opt_undef);
147 NIR_PASS(progress, shader, nir_opt_conditional_discard);
148 } while (progress);
149 }
150
151 static nir_shader *
152 radv_shader_compile_to_nir(struct radv_device *device,
153 struct radv_shader_module *module,
154 const char *entrypoint_name,
155 gl_shader_stage stage,
156 const VkSpecializationInfo *spec_info,
157 bool dump)
158 {
159 if (strcmp(entrypoint_name, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
161 }
162
163 nir_shader *nir;
164 nir_function *entry_point;
165 if (module->nir) {
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
169 nir = module->nir;
170 nir->options = &nir_options;
171 nir_validate_shader(nir);
172
173 assert(exec_list_length(&nir->functions) == 1);
174 struct exec_node *node = exec_list_get_head(&nir->functions);
175 entry_point = exec_node_data(nir_function, node, node);
176 } else {
177 uint32_t *spirv = (uint32_t *) module->data;
178 assert(module->size % 4 == 0);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 spec_entries[i].data = *(const uint32_t *)data;
192 }
193 }
194
195 entry_point = spirv_to_nir(spirv, module->size / 4,
196 spec_entries, num_spec_entries,
197 stage, entrypoint_name, &nir_options);
198 nir = entry_point->shader;
199 assert(nir->stage == stage);
200 nir_validate_shader(nir);
201
202 free(spec_entries);
203
204 nir_lower_returns(nir);
205 nir_validate_shader(nir);
206
207 nir_inline_functions(nir);
208 nir_validate_shader(nir);
209
210 /* Pick off the single entrypoint that we want */
211 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
212 if (func != entry_point)
213 exec_node_remove(&func->node);
214 }
215 assert(exec_list_length(&nir->functions) == 1);
216 entry_point->name = ralloc_strdup(entry_point, "main");
217
218 nir_remove_dead_variables(nir, nir_var_shader_in);
219 nir_remove_dead_variables(nir, nir_var_shader_out);
220 nir_remove_dead_variables(nir, nir_var_system_value);
221 nir_validate_shader(nir);
222
223 nir_lower_system_values(nir);
224 nir_validate_shader(nir);
225 }
226
227 /* Vulkan uses the separate-shader linking model */
228 nir->info->separate_shader = true;
229
230 // nir = brw_preprocess_nir(compiler, nir);
231
232 nir_shader_gather_info(nir, entry_point->impl);
233
234 nir_variable_mode indirect_mask = 0;
235 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
236 indirect_mask |= nir_var_shader_in;
237 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
238 indirect_mask |= nir_var_local;
239
240 nir_lower_indirect_derefs(nir, indirect_mask);
241
242 static const nir_lower_tex_options tex_options = {
243 .lower_txp = ~0,
244 };
245
246 nir_lower_tex(nir, &tex_options);
247
248 nir_lower_vars_to_ssa(nir);
249 nir_lower_var_copies(nir);
250 nir_lower_global_vars_to_local(nir);
251 nir_remove_dead_variables(nir, nir_var_local);
252 radv_optimize_nir(nir);
253
254 if (dump)
255 nir_print_shader(nir, stderr);
256
257 return nir;
258 }
259
260 void radv_shader_variant_destroy(struct radv_device *device,
261 struct radv_shader_variant *variant)
262 {
263 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
264 return;
265
266 device->ws->buffer_destroy(variant->bo);
267 free(variant);
268 }
269
270 static
271 struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
272 struct nir_shader *shader,
273 struct radv_pipeline_layout *layout,
274 const union ac_shader_variant_key *key,
275 void** code_out,
276 unsigned *code_size_out,
277 bool dump)
278 {
279 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
280 enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
281 LLVMTargetMachineRef tm;
282 if (!variant)
283 return NULL;
284
285 struct ac_nir_compiler_options options = {0};
286 options.layout = layout;
287 if (key)
288 options.key = *key;
289
290 struct ac_shader_binary binary;
291
292 options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false);
293 options.family = chip_family;
294 options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
295 tm = ac_create_target_machine(chip_family);
296 ac_compile_nir_shader(tm, &binary, &variant->config,
297 &variant->info, shader, &options, dump);
298 LLVMDisposeTargetMachine(tm);
299
300 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
301 unsigned vgpr_comp_cnt = 0;
302
303 if (scratch_enabled)
304 radv_finishme("shader scratch space");
305 switch (shader->stage) {
306 case MESA_SHADER_VERTEX:
307 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
308 S_00B12C_SCRATCH_EN(scratch_enabled);
309 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
310 break;
311 case MESA_SHADER_FRAGMENT:
312 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
313 S_00B12C_SCRATCH_EN(scratch_enabled);
314 break;
315 case MESA_SHADER_COMPUTE:
316 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
317 S_00B84C_SCRATCH_EN(scratch_enabled) |
318 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
319 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
320 S_00B84C_TG_SIZE_EN(1) |
321 S_00B84C_LDS_SIZE(variant->config.lds_size);
322 break;
323 default:
324 unreachable("unsupported shader type");
325 break;
326 }
327
328 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
329 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
330 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
331 S_00B848_DX10_CLAMP(1) |
332 S_00B848_FLOAT_MODE(variant->config.float_mode);
333
334 variant->bo = device->ws->buffer_create(device->ws, binary.code_size, 256,
335 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
336
337 void *ptr = device->ws->buffer_map(variant->bo);
338 memcpy(ptr, binary.code, binary.code_size);
339 device->ws->buffer_unmap(variant->bo);
340
341 if (code_out) {
342 *code_out = binary.code;
343 *code_size_out = binary.code_size;
344 } else
345 free(binary.code);
346 free(binary.config);
347 free(binary.rodata);
348 free(binary.global_symbol_offsets);
349 free(binary.relocs);
350 free(binary.disasm_string);
351 variant->ref_count = 1;
352 return variant;
353 }
354
355
356 static struct radv_shader_variant *
357 radv_pipeline_compile(struct radv_pipeline *pipeline,
358 struct radv_pipeline_cache *cache,
359 struct radv_shader_module *module,
360 const char *entrypoint,
361 gl_shader_stage stage,
362 const VkSpecializationInfo *spec_info,
363 struct radv_pipeline_layout *layout,
364 const union ac_shader_variant_key *key,
365 bool dump)
366 {
367 unsigned char sha1[20];
368 struct radv_shader_variant *variant;
369 nir_shader *nir;
370 void *code = NULL;
371 unsigned code_size = 0;
372
373 if (module->nir)
374 _mesa_sha1_compute(module->nir->info->name,
375 strlen(module->nir->info->name),
376 module->sha1);
377
378 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
379
380 if (cache) {
381 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
382 cache,
383 sha1);
384 if (variant)
385 return variant;
386 }
387
388 nir = radv_shader_compile_to_nir(pipeline->device,
389 module, entrypoint, stage,
390 spec_info, dump);
391 if (nir == NULL)
392 return NULL;
393
394 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
395 &code, &code_size, dump);
396 if (!module->nir)
397 ralloc_free(nir);
398
399 if (variant && cache)
400 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
401 code, code_size);
402
403 if (code)
404 free(code);
405 return variant;
406 }
407
408 static uint32_t si_translate_blend_function(VkBlendOp op)
409 {
410 switch (op) {
411 case VK_BLEND_OP_ADD:
412 return V_028780_COMB_DST_PLUS_SRC;
413 case VK_BLEND_OP_SUBTRACT:
414 return V_028780_COMB_SRC_MINUS_DST;
415 case VK_BLEND_OP_REVERSE_SUBTRACT:
416 return V_028780_COMB_DST_MINUS_SRC;
417 case VK_BLEND_OP_MIN:
418 return V_028780_COMB_MIN_DST_SRC;
419 case VK_BLEND_OP_MAX:
420 return V_028780_COMB_MAX_DST_SRC;
421 default:
422 return 0;
423 }
424 }
425
426 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
427 {
428 switch (factor) {
429 case VK_BLEND_FACTOR_ZERO:
430 return V_028780_BLEND_ZERO;
431 case VK_BLEND_FACTOR_ONE:
432 return V_028780_BLEND_ONE;
433 case VK_BLEND_FACTOR_SRC_COLOR:
434 return V_028780_BLEND_SRC_COLOR;
435 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
436 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
437 case VK_BLEND_FACTOR_DST_COLOR:
438 return V_028780_BLEND_DST_COLOR;
439 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
440 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
441 case VK_BLEND_FACTOR_SRC_ALPHA:
442 return V_028780_BLEND_SRC_ALPHA;
443 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
444 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
445 case VK_BLEND_FACTOR_DST_ALPHA:
446 return V_028780_BLEND_DST_ALPHA;
447 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
448 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
449 case VK_BLEND_FACTOR_CONSTANT_COLOR:
450 return V_028780_BLEND_CONSTANT_COLOR;
451 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
452 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
453 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
454 return V_028780_BLEND_CONSTANT_ALPHA;
455 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
456 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
457 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
458 return V_028780_BLEND_SRC_ALPHA_SATURATE;
459 case VK_BLEND_FACTOR_SRC1_COLOR:
460 return V_028780_BLEND_SRC1_COLOR;
461 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
462 return V_028780_BLEND_INV_SRC1_COLOR;
463 case VK_BLEND_FACTOR_SRC1_ALPHA:
464 return V_028780_BLEND_SRC1_ALPHA;
465 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
466 return V_028780_BLEND_INV_SRC1_ALPHA;
467 default:
468 return 0;
469 }
470 }
471
472 static bool is_dual_src(VkBlendFactor factor)
473 {
474 switch (factor) {
475 case VK_BLEND_FACTOR_SRC1_COLOR:
476 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
477 case VK_BLEND_FACTOR_SRC1_ALPHA:
478 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
479 return true;
480 default:
481 return false;
482 }
483 }
484
485 static unsigned si_choose_spi_color_format(VkFormat vk_format,
486 bool blend_enable,
487 bool blend_need_alpha)
488 {
489 const struct vk_format_description *desc = vk_format_description(vk_format);
490 unsigned format, ntype, swap;
491
492 /* Alpha is needed for alpha-to-coverage.
493 * Blending may be with or without alpha.
494 */
495 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
496 unsigned alpha = 0; /* exports alpha, but may not support blending */
497 unsigned blend = 0; /* supports blending, but may not export alpha */
498 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
499
500 format = radv_translate_colorformat(vk_format);
501 ntype = radv_translate_color_numformat(vk_format, desc,
502 vk_format_get_first_non_void_channel(vk_format));
503 swap = radv_translate_colorswap(vk_format, false);
504
505 /* Choose the SPI color formats. These are required values for Stoney/RB+.
506 * Other chips have multiple choices, though they are not necessarily better.
507 */
508 switch (format) {
509 case V_028C70_COLOR_5_6_5:
510 case V_028C70_COLOR_1_5_5_5:
511 case V_028C70_COLOR_5_5_5_1:
512 case V_028C70_COLOR_4_4_4_4:
513 case V_028C70_COLOR_10_11_11:
514 case V_028C70_COLOR_11_11_10:
515 case V_028C70_COLOR_8:
516 case V_028C70_COLOR_8_8:
517 case V_028C70_COLOR_8_8_8_8:
518 case V_028C70_COLOR_10_10_10_2:
519 case V_028C70_COLOR_2_10_10_10:
520 if (ntype == V_028C70_NUMBER_UINT)
521 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
522 else if (ntype == V_028C70_NUMBER_SINT)
523 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
524 else
525 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
526 break;
527
528 case V_028C70_COLOR_16:
529 case V_028C70_COLOR_16_16:
530 case V_028C70_COLOR_16_16_16_16:
531 if (ntype == V_028C70_NUMBER_UNORM ||
532 ntype == V_028C70_NUMBER_SNORM) {
533 /* UNORM16 and SNORM16 don't support blending */
534 if (ntype == V_028C70_NUMBER_UNORM)
535 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
536 else
537 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
538
539 /* Use 32 bits per channel for blending. */
540 if (format == V_028C70_COLOR_16) {
541 if (swap == V_028C70_SWAP_STD) { /* R */
542 blend = V_028714_SPI_SHADER_32_R;
543 blend_alpha = V_028714_SPI_SHADER_32_AR;
544 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
545 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
546 else
547 assert(0);
548 } else if (format == V_028C70_COLOR_16_16) {
549 if (swap == V_028C70_SWAP_STD) { /* RG */
550 blend = V_028714_SPI_SHADER_32_GR;
551 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
552 } else if (swap == V_028C70_SWAP_ALT) /* RA */
553 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
554 else
555 assert(0);
556 } else /* 16_16_16_16 */
557 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
558 } else if (ntype == V_028C70_NUMBER_UINT)
559 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
560 else if (ntype == V_028C70_NUMBER_SINT)
561 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
562 else if (ntype == V_028C70_NUMBER_FLOAT)
563 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
564 else
565 assert(0);
566 break;
567
568 case V_028C70_COLOR_32:
569 if (swap == V_028C70_SWAP_STD) { /* R */
570 blend = normal = V_028714_SPI_SHADER_32_R;
571 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
572 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
573 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
574 else
575 assert(0);
576 break;
577
578 case V_028C70_COLOR_32_32:
579 if (swap == V_028C70_SWAP_STD) { /* RG */
580 blend = normal = V_028714_SPI_SHADER_32_GR;
581 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
582 } else if (swap == V_028C70_SWAP_ALT) /* RA */
583 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
584 else
585 assert(0);
586 break;
587
588 case V_028C70_COLOR_32_32_32_32:
589 case V_028C70_COLOR_8_24:
590 case V_028C70_COLOR_24_8:
591 case V_028C70_COLOR_X24_8_32_FLOAT:
592 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
593 break;
594
595 default:
596 unreachable("unhandled blend format");
597 }
598
599 if (blend_enable && blend_need_alpha)
600 return blend_alpha;
601 else if(blend_need_alpha)
602 return alpha;
603 else if(blend_enable)
604 return blend;
605 else
606 return normal;
607 }
608
609 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
610 {
611 unsigned i, cb_shader_mask = 0;
612
613 for (i = 0; i < 8; i++) {
614 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
615 case V_028714_SPI_SHADER_ZERO:
616 break;
617 case V_028714_SPI_SHADER_32_R:
618 cb_shader_mask |= 0x1 << (i * 4);
619 break;
620 case V_028714_SPI_SHADER_32_GR:
621 cb_shader_mask |= 0x3 << (i * 4);
622 break;
623 case V_028714_SPI_SHADER_32_AR:
624 cb_shader_mask |= 0x9 << (i * 4);
625 break;
626 case V_028714_SPI_SHADER_FP16_ABGR:
627 case V_028714_SPI_SHADER_UNORM16_ABGR:
628 case V_028714_SPI_SHADER_SNORM16_ABGR:
629 case V_028714_SPI_SHADER_UINT16_ABGR:
630 case V_028714_SPI_SHADER_SINT16_ABGR:
631 case V_028714_SPI_SHADER_32_ABGR:
632 cb_shader_mask |= 0xf << (i * 4);
633 break;
634 default:
635 assert(0);
636 }
637 }
638 return cb_shader_mask;
639 }
640
641 static void
642 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
643 const VkGraphicsPipelineCreateInfo *pCreateInfo,
644 uint32_t blend_enable,
645 uint32_t blend_need_alpha,
646 bool single_cb_enable,
647 bool blend_mrt0_is_dual_src)
648 {
649 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
650 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
651 struct radv_blend_state *blend = &pipeline->graphics.blend;
652 unsigned col_format = 0;
653
654 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
655 struct radv_render_pass_attachment *attachment;
656 unsigned cf;
657
658 attachment = pass->attachments + subpass->color_attachments[i].attachment;
659
660 cf = si_choose_spi_color_format(attachment->format,
661 blend_enable & (1 << i),
662 blend_need_alpha & (1 << i));
663
664 col_format |= cf << (4 * i);
665 }
666
667 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
668
669 if (blend_mrt0_is_dual_src)
670 col_format |= (col_format & 0xf) << 4;
671 if (!col_format)
672 col_format |= V_028714_SPI_SHADER_32_R;
673 blend->spi_shader_col_format = col_format;
674 }
675
676 static bool
677 format_is_int8(VkFormat format)
678 {
679 const struct vk_format_description *desc = vk_format_description(format);
680 int channel = vk_format_get_first_non_void_channel(format);
681
682 return channel >= 0 && desc->channel[channel].pure_integer &&
683 desc->channel[channel].size == 8;
684 }
685
686 unsigned radv_format_meta_fs_key(VkFormat format)
687 {
688 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
689 bool is_int8 = format_is_int8(format);
690
691 return col_format + (is_int8 ? 3 : 0);
692 }
693
694 static unsigned
695 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
696 {
697 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
698 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
699 unsigned is_int8 = 0;
700
701 for (unsigned i = 0; i < subpass->color_count; ++i) {
702 struct radv_render_pass_attachment *attachment;
703
704 attachment = pass->attachments + subpass->color_attachments[i].attachment;
705
706 if (format_is_int8(attachment->format))
707 is_int8 |= 1 << i;
708 }
709
710 return is_int8;
711 }
712
713 static void
714 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
715 const VkGraphicsPipelineCreateInfo *pCreateInfo,
716 const struct radv_graphics_pipeline_create_info *extra)
717 {
718 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
719 struct radv_blend_state *blend = &pipeline->graphics.blend;
720 unsigned mode = V_028808_CB_NORMAL;
721 uint32_t blend_enable = 0, blend_need_alpha = 0;
722 bool blend_mrt0_is_dual_src = false;
723 int i;
724 bool single_cb_enable = false;
725 if (extra && extra->custom_blend_mode) {
726 single_cb_enable = true;
727 mode = extra->custom_blend_mode;
728 }
729 blend->cb_color_control = 0;
730 if (vkblend->logicOpEnable)
731 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
732 else
733 blend->cb_color_control |= S_028808_ROP3(0xcc);
734
735 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
736 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
737 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
738 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
739
740 blend->cb_target_mask = 0;
741 for (i = 0; i < vkblend->attachmentCount; i++) {
742 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
743 unsigned blend_cntl = 0;
744 VkBlendOp eqRGB = att->colorBlendOp;
745 VkBlendFactor srcRGB = att->srcColorBlendFactor;
746 VkBlendFactor dstRGB = att->dstColorBlendFactor;
747 VkBlendOp eqA = att->alphaBlendOp;
748 VkBlendFactor srcA = att->srcAlphaBlendFactor;
749 VkBlendFactor dstA = att->dstAlphaBlendFactor;
750
751 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
752
753 if (!att->colorWriteMask)
754 continue;
755
756 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
757 if (!att->blendEnable) {
758 blend->cb_blend_control[i] = blend_cntl;
759 continue;
760 }
761
762 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
763 if (i == 0)
764 blend_mrt0_is_dual_src = true;
765
766 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
767 srcRGB = VK_BLEND_FACTOR_ONE;
768 dstRGB = VK_BLEND_FACTOR_ONE;
769 }
770 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
771 srcA = VK_BLEND_FACTOR_ONE;
772 dstA = VK_BLEND_FACTOR_ONE;
773 }
774
775 blend_cntl |= S_028780_ENABLE(1);
776
777 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
778 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
779 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
780 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
781 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
782 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
783 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
784 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
785 }
786 blend->cb_blend_control[i] = blend_cntl;
787
788 blend_enable |= 1 << i;
789
790 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
791 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
792 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
793 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
794 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
795 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
796 blend_need_alpha |= 1 << i;
797 }
798 for (i = vkblend->attachmentCount; i < 8; i++)
799 blend->cb_blend_control[i] = 0;
800
801 if (blend->cb_target_mask)
802 blend->cb_color_control |= S_028808_MODE(mode);
803 else
804 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
805
806 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
807 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
808 }
809
810 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
811 {
812 switch (op) {
813 case VK_STENCIL_OP_KEEP:
814 return V_02842C_STENCIL_KEEP;
815 case VK_STENCIL_OP_ZERO:
816 return V_02842C_STENCIL_ZERO;
817 case VK_STENCIL_OP_REPLACE:
818 return V_02842C_STENCIL_REPLACE_TEST;
819 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
820 return V_02842C_STENCIL_ADD_CLAMP;
821 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
822 return V_02842C_STENCIL_SUB_CLAMP;
823 case VK_STENCIL_OP_INVERT:
824 return V_02842C_STENCIL_INVERT;
825 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
826 return V_02842C_STENCIL_ADD_WRAP;
827 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
828 return V_02842C_STENCIL_SUB_WRAP;
829 default:
830 return 0;
831 }
832 }
833 static void
834 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
835 const VkGraphicsPipelineCreateInfo *pCreateInfo,
836 const struct radv_graphics_pipeline_create_info *extra)
837 {
838 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
839 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
840
841 memset(ds, 0, sizeof(*ds));
842 if (!vkds)
843 return;
844 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
845 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
846 S_028800_ZFUNC(vkds->depthCompareOp) |
847 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
848
849 if (vkds->stencilTestEnable) {
850 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
851 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
852 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
853 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
854 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
855
856 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
857 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
858 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
859 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
860 }
861
862 if (extra) {
863
864 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
865 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
866
867 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
868 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
869 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
870 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
871 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
872 }
873 }
874
875 static uint32_t si_translate_fill(VkPolygonMode func)
876 {
877 switch(func) {
878 case VK_POLYGON_MODE_FILL:
879 return V_028814_X_DRAW_TRIANGLES;
880 case VK_POLYGON_MODE_LINE:
881 return V_028814_X_DRAW_LINES;
882 case VK_POLYGON_MODE_POINT:
883 return V_028814_X_DRAW_POINTS;
884 default:
885 assert(0);
886 return V_028814_X_DRAW_POINTS;
887 }
888 }
889 static void
890 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
891 const VkGraphicsPipelineCreateInfo *pCreateInfo)
892 {
893 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
894 struct radv_raster_state *raster = &pipeline->graphics.raster;
895
896 memset(raster, 0, sizeof(*raster));
897
898 raster->spi_interp_control =
899 S_0286D4_FLAT_SHADE_ENA(1) |
900 S_0286D4_PNT_SPRITE_ENA(1) |
901 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
902 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
903 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
904 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
905 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
906
907 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
908 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
909 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
910 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
911 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
912 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
913 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
914
915 raster->pa_su_vtx_cntl =
916 S_028BE4_PIX_CENTER(1) | // TODO verify
917 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
918 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
919
920 raster->pa_su_sc_mode_cntl =
921 S_028814_FACE(vkraster->frontFace) |
922 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
923 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
924 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
925 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
926 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
927 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
928 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
929 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
930
931 }
932
933 static void
934 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
935 const VkGraphicsPipelineCreateInfo *pCreateInfo)
936 {
937 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
938 struct radv_blend_state *blend = &pipeline->graphics.blend;
939 struct radv_multisample_state *ms = &pipeline->graphics.ms;
940 unsigned num_tile_pipes = pipeline->device->instance->physicalDevice.rad_info.num_tile_pipes;
941 int ps_iter_samples = 1;
942 uint32_t mask = 0xffff;
943
944 ms->num_samples = vkms->rasterizationSamples;
945 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
946 ms->pa_sc_aa_config = 0;
947 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
948 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
949 ms->pa_sc_mode_cntl_1 =
950 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
951 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
952 /* always 1: */
953 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
954 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
955 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
956 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
957 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
958 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
959
960 if (vkms->rasterizationSamples > 1) {
961 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
962 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
963 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
964 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
965 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
966 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
967 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
968 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
969 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
970 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
971 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
972 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
973 }
974
975 if (vkms->alphaToCoverageEnable)
976 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
977
978 if (vkms->pSampleMask) {
979 mask = vkms->pSampleMask[0] & 0xffff;
980 }
981
982 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
983 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
984 }
985
986 static uint32_t
987 si_translate_prim(enum VkPrimitiveTopology topology)
988 {
989 switch (topology) {
990 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
991 return V_008958_DI_PT_POINTLIST;
992 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
993 return V_008958_DI_PT_LINELIST;
994 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
995 return V_008958_DI_PT_LINESTRIP;
996 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
997 return V_008958_DI_PT_TRILIST;
998 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
999 return V_008958_DI_PT_TRISTRIP;
1000 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1001 return V_008958_DI_PT_TRIFAN;
1002 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1003 return V_008958_DI_PT_LINELIST_ADJ;
1004 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1005 return V_008958_DI_PT_LINESTRIP_ADJ;
1006 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1007 return V_008958_DI_PT_TRILIST_ADJ;
1008 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1009 return V_008958_DI_PT_TRISTRIP_ADJ;
1010 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1011 return V_008958_DI_PT_PATCH;
1012 default:
1013 assert(0);
1014 return 0;
1015 }
1016 }
1017
1018 static uint32_t
1019 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1020 {
1021 switch (topology) {
1022 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1023 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1024 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1025 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1026 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1027 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1028 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1029 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1030 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1031 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1032 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1033 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1034 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1035 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1036 default:
1037 assert(0);
1038 return 0;
1039 }
1040 }
1041
1042 static unsigned si_map_swizzle(unsigned swizzle)
1043 {
1044 switch (swizzle) {
1045 case VK_SWIZZLE_Y:
1046 return V_008F0C_SQ_SEL_Y;
1047 case VK_SWIZZLE_Z:
1048 return V_008F0C_SQ_SEL_Z;
1049 case VK_SWIZZLE_W:
1050 return V_008F0C_SQ_SEL_W;
1051 case VK_SWIZZLE_0:
1052 return V_008F0C_SQ_SEL_0;
1053 case VK_SWIZZLE_1:
1054 return V_008F0C_SQ_SEL_1;
1055 default: /* VK_SWIZZLE_X */
1056 return V_008F0C_SQ_SEL_X;
1057 }
1058 }
1059
1060 static void
1061 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1062 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1063 {
1064 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1065 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1066 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1067
1068 pipeline->dynamic_state = default_dynamic_state;
1069
1070 if (pCreateInfo->pDynamicState) {
1071 /* Remove all of the states that are marked as dynamic */
1072 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1073 for (uint32_t s = 0; s < count; s++)
1074 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1075 }
1076
1077 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1078
1079 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1080 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1081 typed_memcpy(dynamic->viewport.viewports,
1082 pCreateInfo->pViewportState->pViewports,
1083 pCreateInfo->pViewportState->viewportCount);
1084 }
1085
1086 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1087 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1088 typed_memcpy(dynamic->scissor.scissors,
1089 pCreateInfo->pViewportState->pScissors,
1090 pCreateInfo->pViewportState->scissorCount);
1091 }
1092
1093 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1094 assert(pCreateInfo->pRasterizationState);
1095 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1096 }
1097
1098 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1099 assert(pCreateInfo->pRasterizationState);
1100 dynamic->depth_bias.bias =
1101 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1102 dynamic->depth_bias.clamp =
1103 pCreateInfo->pRasterizationState->depthBiasClamp;
1104 dynamic->depth_bias.slope =
1105 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1106 }
1107
1108 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1109 assert(pCreateInfo->pColorBlendState);
1110 typed_memcpy(dynamic->blend_constants,
1111 pCreateInfo->pColorBlendState->blendConstants, 4);
1112 }
1113
1114 /* If there is no depthstencil attachment, then don't read
1115 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1116 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1117 * no need to override the depthstencil defaults in
1118 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1119 *
1120 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
1121 *
1122 * pDepthStencilState [...] may only be NULL if renderPass and subpass
1123 * specify a subpass that has no depth/stencil attachment.
1124 */
1125 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1126 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1127 assert(pCreateInfo->pDepthStencilState);
1128 dynamic->depth_bounds.min =
1129 pCreateInfo->pDepthStencilState->minDepthBounds;
1130 dynamic->depth_bounds.max =
1131 pCreateInfo->pDepthStencilState->maxDepthBounds;
1132 }
1133
1134 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1135 assert(pCreateInfo->pDepthStencilState);
1136 dynamic->stencil_compare_mask.front =
1137 pCreateInfo->pDepthStencilState->front.compareMask;
1138 dynamic->stencil_compare_mask.back =
1139 pCreateInfo->pDepthStencilState->back.compareMask;
1140 }
1141
1142 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1143 assert(pCreateInfo->pDepthStencilState);
1144 dynamic->stencil_write_mask.front =
1145 pCreateInfo->pDepthStencilState->front.writeMask;
1146 dynamic->stencil_write_mask.back =
1147 pCreateInfo->pDepthStencilState->back.writeMask;
1148 }
1149
1150 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1151 assert(pCreateInfo->pDepthStencilState);
1152 dynamic->stencil_reference.front =
1153 pCreateInfo->pDepthStencilState->front.reference;
1154 dynamic->stencil_reference.back =
1155 pCreateInfo->pDepthStencilState->back.reference;
1156 }
1157 }
1158
1159 pipeline->dynamic_state_mask = states;
1160 }
1161
1162 static union ac_shader_variant_key
1163 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1164 {
1165 union ac_shader_variant_key key;
1166 const VkPipelineVertexInputStateCreateInfo *input_state =
1167 pCreateInfo->pVertexInputState;
1168
1169 memset(&key, 0, sizeof(key));
1170 key.vs.instance_rate_inputs = 0;
1171
1172 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1173 unsigned binding;
1174 binding = input_state->pVertexAttributeDescriptions[i].binding;
1175 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1176 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1177 }
1178 return key;
1179 }
1180
1181 VkResult
1182 radv_pipeline_init(struct radv_pipeline *pipeline,
1183 struct radv_device *device,
1184 struct radv_pipeline_cache *cache,
1185 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1186 const struct radv_graphics_pipeline_create_info *extra,
1187 const VkAllocationCallbacks *alloc)
1188 {
1189 struct radv_shader_module fs_m = {0};
1190
1191 bool dump = getenv("RADV_DUMP_SHADERS");
1192 if (alloc == NULL)
1193 alloc = &device->alloc;
1194
1195 pipeline->device = device;
1196 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1197
1198 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1199 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1200 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1201 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1202 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1203 pStages[stage] = &pCreateInfo->pStages[i];
1204 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1205 }
1206
1207 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1208
1209 /* */
1210 if (modules[MESA_SHADER_VERTEX]) {
1211 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1212
1213 pipeline->shaders[MESA_SHADER_VERTEX] =
1214 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1215 pStages[MESA_SHADER_VERTEX]->pName,
1216 MESA_SHADER_VERTEX,
1217 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1218 pipeline->layout, &key, dump);
1219
1220 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1221 }
1222
1223 if (!modules[MESA_SHADER_FRAGMENT]) {
1224 nir_builder fs_b;
1225 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1226 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1227 fs_m.nir = fs_b.shader;
1228 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1229 }
1230
1231 if (modules[MESA_SHADER_FRAGMENT]) {
1232 union ac_shader_variant_key key;
1233 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1234 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1235
1236 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1237
1238 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1239 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1240 stage ? stage->pName : "main",
1241 MESA_SHADER_FRAGMENT,
1242 stage ? stage->pSpecializationInfo : NULL,
1243 pipeline->layout, &key, dump);
1244 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1245 }
1246
1247 if (fs_m.nir)
1248 ralloc_free(fs_m.nir);
1249
1250 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1251 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1252 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1253 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1254 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1255 if (extra && extra->use_rectlist) {
1256 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1257 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1258 }
1259 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1260
1261 const VkPipelineVertexInputStateCreateInfo *vi_info =
1262 pCreateInfo->pVertexInputState;
1263 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1264 const VkVertexInputAttributeDescription *desc =
1265 &vi_info->pVertexAttributeDescriptions[i];
1266 unsigned loc = desc->location;
1267 const struct vk_format_description *format_desc;
1268 int first_non_void;
1269 uint32_t num_format, data_format;
1270 format_desc = vk_format_description(desc->format);
1271 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1272
1273 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1274 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1275
1276 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1277 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1278 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1279 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1280 S_008F0C_NUM_FORMAT(num_format) |
1281 S_008F0C_DATA_FORMAT(data_format);
1282 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1283 pipeline->va_offset[loc] = desc->offset;
1284 pipeline->va_binding[loc] = desc->binding;
1285 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1286 }
1287
1288 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1289 const VkVertexInputBindingDescription *desc =
1290 &vi_info->pVertexBindingDescriptions[i];
1291
1292 pipeline->binding_stride[desc->binding] = desc->stride;
1293 }
1294
1295 return VK_SUCCESS;
1296 }
1297
1298 VkResult
1299 radv_graphics_pipeline_create(
1300 VkDevice _device,
1301 VkPipelineCache _cache,
1302 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1303 const struct radv_graphics_pipeline_create_info *extra,
1304 const VkAllocationCallbacks *pAllocator,
1305 VkPipeline *pPipeline)
1306 {
1307 RADV_FROM_HANDLE(radv_device, device, _device);
1308 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1309 struct radv_pipeline *pipeline;
1310 VkResult result;
1311
1312 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1313 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1314 if (pipeline == NULL)
1315 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1316
1317 memset(pipeline, 0, sizeof(*pipeline));
1318 result = radv_pipeline_init(pipeline, device, cache,
1319 pCreateInfo, extra, pAllocator);
1320 if (result != VK_SUCCESS) {
1321 vk_free2(&device->alloc, pAllocator, pipeline);
1322 return result;
1323 }
1324
1325 *pPipeline = radv_pipeline_to_handle(pipeline);
1326
1327 return VK_SUCCESS;
1328 }
1329
1330 VkResult radv_CreateGraphicsPipelines(
1331 VkDevice _device,
1332 VkPipelineCache pipelineCache,
1333 uint32_t count,
1334 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1335 const VkAllocationCallbacks* pAllocator,
1336 VkPipeline* pPipelines)
1337 {
1338 VkResult result = VK_SUCCESS;
1339 unsigned i = 0;
1340
1341 for (; i < count; i++) {
1342 result = radv_graphics_pipeline_create(_device,
1343 pipelineCache,
1344 &pCreateInfos[i],
1345 NULL, pAllocator, &pPipelines[i]);
1346 if (result != VK_SUCCESS) {
1347 for (unsigned j = 0; j < i; j++) {
1348 radv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1349 }
1350
1351 return result;
1352 }
1353 }
1354
1355 return VK_SUCCESS;
1356 }
1357
1358 static VkResult radv_compute_pipeline_create(
1359 VkDevice _device,
1360 VkPipelineCache _cache,
1361 const VkComputePipelineCreateInfo* pCreateInfo,
1362 const VkAllocationCallbacks* pAllocator,
1363 VkPipeline* pPipeline)
1364 {
1365 RADV_FROM_HANDLE(radv_device, device, _device);
1366 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1367 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1368 struct radv_pipeline *pipeline;
1369 bool dump = getenv("RADV_DUMP_SHADERS");
1370
1371 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1372 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1373 if (pipeline == NULL)
1374 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1375
1376 memset(pipeline, 0, sizeof(*pipeline));
1377 pipeline->device = device;
1378 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1379
1380 pipeline->shaders[MESA_SHADER_COMPUTE] =
1381 radv_pipeline_compile(pipeline, cache, module,
1382 pCreateInfo->stage.pName,
1383 MESA_SHADER_COMPUTE,
1384 pCreateInfo->stage.pSpecializationInfo,
1385 pipeline->layout, NULL, dump);
1386
1387 *pPipeline = radv_pipeline_to_handle(pipeline);
1388 return VK_SUCCESS;
1389 }
1390 VkResult radv_CreateComputePipelines(
1391 VkDevice _device,
1392 VkPipelineCache pipelineCache,
1393 uint32_t count,
1394 const VkComputePipelineCreateInfo* pCreateInfos,
1395 const VkAllocationCallbacks* pAllocator,
1396 VkPipeline* pPipelines)
1397 {
1398 VkResult result = VK_SUCCESS;
1399
1400 unsigned i = 0;
1401 for (; i < count; i++) {
1402 result = radv_compute_pipeline_create(_device, pipelineCache,
1403 &pCreateInfos[i],
1404 pAllocator, &pPipelines[i]);
1405 if (result != VK_SUCCESS) {
1406 for (unsigned j = 0; j < i; j++) {
1407 radv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1408 }
1409
1410 return result;
1411 }
1412 }
1413
1414 return VK_SUCCESS;
1415 }