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radv: compute prim_vertex_count at draw time
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 static const VkPipelineMultisampleStateCreateInfo *
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
94 {
95 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
96 return pCreateInfo->pMultisampleState;
97 return NULL;
98 }
99
100 static const VkPipelineTessellationStateCreateInfo *
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
102 {
103 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
104 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
105 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
106 return pCreateInfo->pTessellationState;
107 }
108 }
109 return NULL;
110 }
111
112 static const VkPipelineDepthStencilStateCreateInfo *
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
114 {
115 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
116 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
117
118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
119 subpass->depth_stencil_attachment)
120 return pCreateInfo->pDepthStencilState;
121 return NULL;
122 }
123
124 static const VkPipelineColorBlendStateCreateInfo *
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
126 {
127 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
128 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
129
130 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
131 subpass->has_color_att)
132 return pCreateInfo->pColorBlendState;
133 return NULL;
134 }
135
136 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
137 {
138 struct radv_shader_variant *variant = NULL;
139 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
140 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
141 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
142 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
143 else if (pipeline->shaders[MESA_SHADER_VERTEX])
144 variant = pipeline->shaders[MESA_SHADER_VERTEX];
145 else
146 return false;
147 return variant->info.is_ngg;
148 }
149
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
151 {
152 assert(radv_pipeline_has_ngg(pipeline));
153
154 struct radv_shader_variant *variant = NULL;
155 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
156 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
157 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
158 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
159 else if (pipeline->shaders[MESA_SHADER_VERTEX])
160 variant = pipeline->shaders[MESA_SHADER_VERTEX];
161 else
162 return false;
163 return variant->info.is_ngg_passthrough;
164 }
165
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
167 {
168 if (!radv_pipeline_has_gs(pipeline))
169 return false;
170
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
173 * enable NGG.
174 */
175 if (radv_pipeline_has_ngg(pipeline))
176 return false;
177
178 assert(pipeline->gs_copy_shader);
179 return true;
180 }
181
182 static void
183 radv_pipeline_destroy(struct radv_device *device,
184 struct radv_pipeline *pipeline,
185 const VkAllocationCallbacks* allocator)
186 {
187 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
188 if (pipeline->shaders[i])
189 radv_shader_variant_destroy(device, pipeline->shaders[i]);
190
191 if (pipeline->gs_copy_shader)
192 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
193
194 if(pipeline->cs.buf)
195 free(pipeline->cs.buf);
196
197 vk_object_base_finish(&pipeline->base);
198 vk_free2(&device->vk.alloc, allocator, pipeline);
199 }
200
201 void radv_DestroyPipeline(
202 VkDevice _device,
203 VkPipeline _pipeline,
204 const VkAllocationCallbacks* pAllocator)
205 {
206 RADV_FROM_HANDLE(radv_device, device, _device);
207 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
208
209 if (!_pipeline)
210 return;
211
212 radv_pipeline_destroy(device, pipeline, pAllocator);
213 }
214
215 static uint32_t get_hash_flags(struct radv_device *device)
216 {
217 uint32_t hash_flags = 0;
218
219 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
220 hash_flags |= RADV_HASH_SHADER_NO_NGG;
221 if (device->physical_device->cs_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
223 if (device->physical_device->ps_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
225 if (device->physical_device->ge_wave_size == 32)
226 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
227 if (device->physical_device->use_llvm)
228 hash_flags |= RADV_HASH_SHADER_LLVM;
229 return hash_flags;
230 }
231
232 static VkResult
233 radv_pipeline_scratch_init(struct radv_device *device,
234 struct radv_pipeline *pipeline)
235 {
236 unsigned scratch_bytes_per_wave = 0;
237 unsigned max_waves = 0;
238 unsigned min_waves = 1;
239
240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
241 if (pipeline->shaders[i] &&
242 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
243 unsigned max_stage_waves = device->scratch_waves;
244
245 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
246 pipeline->shaders[i]->config.scratch_bytes_per_wave);
247
248 max_stage_waves = MIN2(max_stage_waves,
249 4 * device->physical_device->rad_info.num_good_compute_units *
250 (256 / pipeline->shaders[i]->config.num_vgprs));
251 max_waves = MAX2(max_waves, max_stage_waves);
252 }
253 }
254
255 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
256 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
258 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
259 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
260 }
261
262 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
263 pipeline->max_waves = max_waves;
264 return VK_SUCCESS;
265 }
266
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
268 {
269 switch (op) {
270 case VK_LOGIC_OP_CLEAR:
271 return V_028808_ROP3_CLEAR;
272 case VK_LOGIC_OP_AND:
273 return V_028808_ROP3_AND;
274 case VK_LOGIC_OP_AND_REVERSE:
275 return V_028808_ROP3_AND_REVERSE;
276 case VK_LOGIC_OP_COPY:
277 return V_028808_ROP3_COPY;
278 case VK_LOGIC_OP_AND_INVERTED:
279 return V_028808_ROP3_AND_INVERTED;
280 case VK_LOGIC_OP_NO_OP:
281 return V_028808_ROP3_NO_OP;
282 case VK_LOGIC_OP_XOR:
283 return V_028808_ROP3_XOR;
284 case VK_LOGIC_OP_OR:
285 return V_028808_ROP3_OR;
286 case VK_LOGIC_OP_NOR:
287 return V_028808_ROP3_NOR;
288 case VK_LOGIC_OP_EQUIVALENT:
289 return V_028808_ROP3_EQUIVALENT;
290 case VK_LOGIC_OP_INVERT:
291 return V_028808_ROP3_INVERT;
292 case VK_LOGIC_OP_OR_REVERSE:
293 return V_028808_ROP3_OR_REVERSE;
294 case VK_LOGIC_OP_COPY_INVERTED:
295 return V_028808_ROP3_COPY_INVERTED;
296 case VK_LOGIC_OP_OR_INVERTED:
297 return V_028808_ROP3_OR_INVERTED;
298 case VK_LOGIC_OP_NAND:
299 return V_028808_ROP3_NAND;
300 case VK_LOGIC_OP_SET:
301 return V_028808_ROP3_SET;
302 default:
303 unreachable("Unhandled logic op");
304 }
305 }
306
307
308 static uint32_t si_translate_blend_function(VkBlendOp op)
309 {
310 switch (op) {
311 case VK_BLEND_OP_ADD:
312 return V_028780_COMB_DST_PLUS_SRC;
313 case VK_BLEND_OP_SUBTRACT:
314 return V_028780_COMB_SRC_MINUS_DST;
315 case VK_BLEND_OP_REVERSE_SUBTRACT:
316 return V_028780_COMB_DST_MINUS_SRC;
317 case VK_BLEND_OP_MIN:
318 return V_028780_COMB_MIN_DST_SRC;
319 case VK_BLEND_OP_MAX:
320 return V_028780_COMB_MAX_DST_SRC;
321 default:
322 return 0;
323 }
324 }
325
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
327 {
328 switch (factor) {
329 case VK_BLEND_FACTOR_ZERO:
330 return V_028780_BLEND_ZERO;
331 case VK_BLEND_FACTOR_ONE:
332 return V_028780_BLEND_ONE;
333 case VK_BLEND_FACTOR_SRC_COLOR:
334 return V_028780_BLEND_SRC_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
337 case VK_BLEND_FACTOR_DST_COLOR:
338 return V_028780_BLEND_DST_COLOR;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case VK_BLEND_FACTOR_SRC_ALPHA:
342 return V_028780_BLEND_SRC_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
345 case VK_BLEND_FACTOR_DST_ALPHA:
346 return V_028780_BLEND_DST_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR:
350 return V_028780_BLEND_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
354 return V_028780_BLEND_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE;
359 case VK_BLEND_FACTOR_SRC1_COLOR:
360 return V_028780_BLEND_SRC1_COLOR;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
362 return V_028780_BLEND_INV_SRC1_COLOR;
363 case VK_BLEND_FACTOR_SRC1_ALPHA:
364 return V_028780_BLEND_SRC1_ALPHA;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
366 return V_028780_BLEND_INV_SRC1_ALPHA;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
373 {
374 switch (op) {
375 case VK_BLEND_OP_ADD:
376 return V_028760_OPT_COMB_ADD;
377 case VK_BLEND_OP_SUBTRACT:
378 return V_028760_OPT_COMB_SUBTRACT;
379 case VK_BLEND_OP_REVERSE_SUBTRACT:
380 return V_028760_OPT_COMB_REVSUBTRACT;
381 case VK_BLEND_OP_MIN:
382 return V_028760_OPT_COMB_MIN;
383 case VK_BLEND_OP_MAX:
384 return V_028760_OPT_COMB_MAX;
385 default:
386 return V_028760_OPT_COMB_BLEND_DISABLED;
387 }
388 }
389
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
391 {
392 switch (factor) {
393 case VK_BLEND_FACTOR_ZERO:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
395 case VK_BLEND_FACTOR_ONE:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
397 case VK_BLEND_FACTOR_SRC_COLOR:
398 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
403 case VK_BLEND_FACTOR_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
408 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
410 default:
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == VK_BLEND_FACTOR_ZERO) {
425 *src_factor = VK_BLEND_FACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == VK_BLEND_OP_SUBTRACT)
430 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
431 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
432 *func = VK_BLEND_OP_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == VK_BLEND_FACTOR_DST_COLOR ||
439 factor == VK_BLEND_FACTOR_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
442 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
443 }
444
445 static bool is_dual_src(VkBlendFactor factor)
446 {
447 switch (factor) {
448 case VK_BLEND_FACTOR_SRC1_COLOR:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
450 case VK_BLEND_FACTOR_SRC1_ALPHA:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
452 return true;
453 default:
454 return false;
455 }
456 }
457
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
459 bool blend_enable,
460 bool blend_need_alpha)
461 {
462 const struct vk_format_description *desc = vk_format_description(vk_format);
463 struct ac_spi_color_formats formats = {};
464 unsigned format, ntype, swap;
465
466 format = radv_translate_colorformat(vk_format);
467 ntype = radv_translate_color_numformat(vk_format, desc,
468 vk_format_get_first_non_void_channel(vk_format));
469 swap = radv_translate_colorswap(vk_format, false);
470
471 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
472
473 if (blend_enable && blend_need_alpha)
474 return formats.blend_alpha;
475 else if(blend_need_alpha)
476 return formats.alpha;
477 else if(blend_enable)
478 return formats.blend;
479 else
480 return formats.normal;
481 }
482
483 static bool
484 format_is_int8(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487 int channel = vk_format_get_first_non_void_channel(format);
488
489 return channel >= 0 && desc->channel[channel].pure_integer &&
490 desc->channel[channel].size == 8;
491 }
492
493 static bool
494 format_is_int10(VkFormat format)
495 {
496 const struct vk_format_description *desc = vk_format_description(format);
497
498 if (desc->nr_channels != 4)
499 return false;
500 for (unsigned i = 0; i < 4; i++) {
501 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
502 return true;
503 }
504 return false;
505 }
506
507 static void
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 struct radv_blend_state *blend)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
515 unsigned num_targets;
516
517 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
518 unsigned cf;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
521 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
522 cf = V_028714_SPI_SHADER_ZERO;
523 } else {
524 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
525 bool blend_enable =
526 blend->blend_enable_4bit & (0xfu << (i * 4));
527
528 cf = radv_choose_spi_color_format(attachment->format,
529 blend_enable,
530 blend->need_src_alpha & (1 << i));
531
532 if (format_is_int8(attachment->format))
533 is_int8 |= 1 << i;
534 if (format_is_int10(attachment->format))
535 is_int10 |= 1 << i;
536 }
537
538 col_format |= cf << (4 * i);
539 }
540
541 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
545 */
546 col_format |= V_028714_SPI_SHADER_32_AR;
547 }
548
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
551 */
552 num_targets = (util_last_bit(col_format) + 3) / 4;
553 for (unsigned i = 0; i < num_targets; i++) {
554 if (!(col_format & (0xf << (i * 4)))) {
555 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
556 }
557 }
558
559 /* The output for dual source blending should have the same format as
560 * the first output.
561 */
562 if (blend->mrt0_is_dual_src)
563 col_format |= (col_format & 0xf) << 4;
564
565 blend->spi_shader_col_format = col_format;
566 blend->col_format_is_int8 = is_int8;
567 blend->col_format_is_int10 = is_int10;
568 }
569
570 /*
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 */
574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
575 VK_FORMAT_R32_SFLOAT,
576 VK_FORMAT_R32G32_SFLOAT,
577 VK_FORMAT_R8G8B8A8_UNORM,
578 VK_FORMAT_R16G16B16A16_UNORM,
579 VK_FORMAT_R16G16B16A16_SNORM,
580 VK_FORMAT_R16G16B16A16_UINT,
581 VK_FORMAT_R16G16B16A16_SINT,
582 VK_FORMAT_R32G32B32A32_SFLOAT,
583 VK_FORMAT_R8G8B8A8_UINT,
584 VK_FORMAT_R8G8B8A8_SINT,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32,
587 };
588
589 unsigned radv_format_meta_fs_key(VkFormat format)
590 {
591 unsigned col_format = radv_choose_spi_color_format(format, false, false);
592
593 assert(col_format != V_028714_SPI_SHADER_32_AR);
594 if (col_format >= V_028714_SPI_SHADER_32_AR)
595 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596
597 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8 = format_is_int8(format);
599 bool is_int10 = format_is_int10(format);
600
601 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
602 }
603
604 static void
605 radv_blend_check_commutativity(struct radv_blend_state *blend,
606 VkBlendOp op, VkBlendFactor src,
607 VkBlendFactor dst, unsigned chanmask)
608 {
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed =
611 (1u << VK_BLEND_FACTOR_ONE) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ZERO) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
626
627 if (dst == VK_BLEND_FACTOR_ONE &&
628 (src_allowed & (1u << src))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
632 */
633 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
634 blend->commutative_4bit |= chanmask;
635 }
636 }
637
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
640 const VkGraphicsPipelineCreateInfo *pCreateInfo,
641 const struct radv_graphics_pipeline_create_info *extra)
642 {
643 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
644 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
645 struct radv_blend_state blend = {0};
646 unsigned mode = V_028808_CB_NORMAL;
647 int i;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653
654 blend.cb_color_control = 0;
655 if (vkblend) {
656 if (vkblend->logicOpEnable)
657 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
658 else
659 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
660 }
661
662 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
667
668 if (vkms && vkms->alphaToCoverageEnable) {
669 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend.need_src_alpha |= 0x1;
671 }
672
673 blend.cb_target_mask = 0;
674 if (vkblend) {
675 for (i = 0; i < vkblend->attachmentCount; i++) {
676 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
677 unsigned blend_cntl = 0;
678 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
679 VkBlendOp eqRGB = att->colorBlendOp;
680 VkBlendFactor srcRGB = att->srcColorBlendFactor;
681 VkBlendFactor dstRGB = att->dstColorBlendFactor;
682 VkBlendOp eqA = att->alphaBlendOp;
683 VkBlendFactor srcA = att->srcAlphaBlendFactor;
684 VkBlendFactor dstA = att->dstAlphaBlendFactor;
685
686 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
687
688 if (!att->colorWriteMask)
689 continue;
690
691 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
692 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
693 if (!att->blendEnable) {
694 blend.cb_blend_control[i] = blend_cntl;
695 continue;
696 }
697
698 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
699 if (i == 0)
700 blend.mrt0_is_dual_src = true;
701
702 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
703 srcRGB = VK_BLEND_FACTOR_ONE;
704 dstRGB = VK_BLEND_FACTOR_ONE;
705 }
706 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
707 srcA = VK_BLEND_FACTOR_ONE;
708 dstA = VK_BLEND_FACTOR_ONE;
709 }
710
711 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
712 0x7 << (4 * i));
713 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
714 0x8 << (4 * i));
715
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
718 *
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 */
722 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
723 VK_BLEND_FACTOR_DST_COLOR,
724 VK_BLEND_FACTOR_SRC_COLOR);
725
726 si_blend_remove_dst(&eqA, &srcA, &dstA,
727 VK_BLEND_FACTOR_DST_COLOR,
728 VK_BLEND_FACTOR_SRC_COLOR);
729
730 si_blend_remove_dst(&eqA, &srcA, &dstA,
731 VK_BLEND_FACTOR_DST_ALPHA,
732 VK_BLEND_FACTOR_SRC_ALPHA);
733
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
736 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
737 srcA_opt = si_translate_blend_opt_factor(srcA, true);
738 dstA_opt = si_translate_blend_opt_factor(dstA, true);
739
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
743 if (si_blend_factor_uses_dst(srcA))
744 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
745
746 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
747 (dstRGB == VK_BLEND_FACTOR_ZERO ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
749 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
750 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
751
752 /* Set the final value. */
753 blend.sx_mrt_blend_opt[i] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt) |
758 S_028760_ALPHA_DST_OPT(dstA_opt) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
760 blend_cntl |= S_028780_ENABLE(1);
761
762 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
763 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
764 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
768 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
769 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
770 }
771 blend.cb_blend_control[i] = blend_cntl;
772
773 blend.blend_enable_4bit |= 0xfu << (i * 4);
774
775 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
777 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
779 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
781 blend.need_src_alpha |= 1 << i;
782 }
783 for (i = vkblend->attachmentCount; i < 8; i++) {
784 blend.cb_blend_control[i] = 0;
785 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
786 }
787 }
788
789 if (pipeline->device->physical_device->rad_info.has_rbplus) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend.mrt0_is_dual_src) {
792 for (i = 0; i < 8; i++) {
793 blend.sx_mrt_blend_opt[i] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
796 }
797 }
798
799 /* RB+ doesn't work with dual source blending, logic op and
800 * RESOLVE.
801 */
802 if (blend.mrt0_is_dual_src ||
803 (vkblend && vkblend->logicOpEnable) ||
804 mode == V_028808_CB_RESOLVE)
805 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
806 }
807
808 if (blend.cb_target_mask)
809 blend.cb_color_control |= S_028808_MODE(mode);
810 else
811 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
812
813 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
814 return blend;
815 }
816
817 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
818 {
819 switch (op) {
820 case VK_STENCIL_OP_KEEP:
821 return V_02842C_STENCIL_KEEP;
822 case VK_STENCIL_OP_ZERO:
823 return V_02842C_STENCIL_ZERO;
824 case VK_STENCIL_OP_REPLACE:
825 return V_02842C_STENCIL_REPLACE_TEST;
826 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
827 return V_02842C_STENCIL_ADD_CLAMP;
828 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
829 return V_02842C_STENCIL_SUB_CLAMP;
830 case VK_STENCIL_OP_INVERT:
831 return V_02842C_STENCIL_INVERT;
832 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
833 return V_02842C_STENCIL_ADD_WRAP;
834 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
835 return V_02842C_STENCIL_SUB_WRAP;
836 default:
837 return 0;
838 }
839 }
840
841 static uint32_t si_translate_fill(VkPolygonMode func)
842 {
843 switch(func) {
844 case VK_POLYGON_MODE_FILL:
845 return V_028814_X_DRAW_TRIANGLES;
846 case VK_POLYGON_MODE_LINE:
847 return V_028814_X_DRAW_LINES;
848 case VK_POLYGON_MODE_POINT:
849 return V_028814_X_DRAW_POINTS;
850 default:
851 assert(0);
852 return V_028814_X_DRAW_POINTS;
853 }
854 }
855
856 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
857 {
858 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
859 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
860 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
861 uint32_t ps_iter_samples = 1;
862 uint32_t num_samples;
863
864 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
865 *
866 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
867 * subpass uses color attachments, totalSamples is the number of
868 * samples of the color attachments. Otherwise, totalSamples is the
869 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
870 * specified at pipeline creation time."
871 */
872 if (subpass->has_color_att) {
873 num_samples = subpass->color_sample_count;
874 } else {
875 num_samples = vkms->rasterizationSamples;
876 }
877
878 if (vkms->sampleShadingEnable) {
879 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
880 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
881 }
882 return ps_iter_samples;
883 }
884
885 static bool
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return pCreateInfo->depthTestEnable &&
889 pCreateInfo->depthWriteEnable &&
890 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
891 }
892
893 static bool
894 radv_writes_stencil(const VkStencilOpState *state)
895 {
896 return state->writeMask &&
897 (state->failOp != VK_STENCIL_OP_KEEP ||
898 state->passOp != VK_STENCIL_OP_KEEP ||
899 state->depthFailOp != VK_STENCIL_OP_KEEP);
900 }
901
902 static bool
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
904 {
905 return pCreateInfo->stencilTestEnable &&
906 (radv_writes_stencil(&pCreateInfo->front) ||
907 radv_writes_stencil(&pCreateInfo->back));
908 }
909
910 static bool
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
912 {
913 return radv_is_depth_write_enabled(pCreateInfo) ||
914 radv_is_stencil_write_enabled(pCreateInfo);
915 }
916
917 static bool
918 radv_order_invariant_stencil_op(VkStencilOp op)
919 {
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
923 */
924 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
925 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
926 op != VK_STENCIL_OP_REPLACE;
927 }
928
929 static bool
930 radv_order_invariant_stencil_state(const VkStencilOpState *state)
931 {
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
935 * of fragments.
936 */
937 return !state->writeMask ||
938 /* The following assumes that Z writes are disabled. */
939 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
940 radv_order_invariant_stencil_op(state->passOp) &&
941 radv_order_invariant_stencil_op(state->depthFailOp)) ||
942 (state->compareOp == VK_COMPARE_OP_NEVER &&
943 radv_order_invariant_stencil_op(state->failOp));
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
954 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
955 unsigned colormask = blend->cb_target_enabled_4bit;
956
957 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
958 return false;
959
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask && vkblend && vkblend->logicOpEnable)
962 return false;
963
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant = {
966 .zs = true, .pass_set = true
967 };
968
969 if (vkds) {
970 struct radv_render_pass_attachment *attachment =
971 pass->attachments + subpass->depth_stencil_attachment->attachment;
972 bool has_stencil = vk_format_is_stencil(attachment->format);
973 struct radv_dsa_order_invariance order_invariance[2];
974 struct radv_shader_variant *ps =
975 pipeline->shaders[MESA_SHADER_FRAGMENT];
976
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
979 */
980 bool zfunc_is_ordered =
981 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
986
987 bool nozwrite_and_order_invariant_stencil =
988 !radv_is_ds_write_enabled(vkds) ||
989 (!radv_is_depth_write_enabled(vkds) &&
990 radv_order_invariant_stencil_state(&vkds->front) &&
991 radv_order_invariant_stencil_state(&vkds->back));
992
993 order_invariance[1].zs =
994 nozwrite_and_order_invariant_stencil ||
995 (!radv_is_stencil_write_enabled(vkds) &&
996 zfunc_is_ordered);
997 order_invariance[0].zs =
998 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
999
1000 order_invariance[1].pass_set =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1004 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1005 order_invariance[0].pass_set =
1006 !radv_is_depth_write_enabled(vkds) ||
1007 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1008 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1009
1010 dsa_order_invariant = order_invariance[has_stencil];
1011 if (!dsa_order_invariant.zs)
1012 return false;
1013
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1016 */
1017 if (ps &&
1018 ps->info.ps.writes_memory &&
1019 ps->info.ps.early_fragment_test &&
1020 !dsa_order_invariant.pass_set)
1021 return false;
1022
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1025 */
1026 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1027 !dsa_order_invariant.pass_set;
1028 }
1029
1030 /* No color buffers are enabled for writing. */
1031 if (!colormask)
1032 return true;
1033
1034 unsigned blendmask = colormask & blend->blend_enable_4bit;
1035
1036 if (blendmask) {
1037 /* Only commutative blending. */
1038 if (blendmask & ~blend->commutative_4bit)
1039 return false;
1040
1041 if (!dsa_order_invariant.pass_set)
1042 return false;
1043 }
1044
1045 if (colormask & ~blendmask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 static void
1052 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1053 struct radv_blend_state *blend,
1054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1055 {
1056 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1057 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1058 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1059 bool out_of_order_rast = false;
1060 int ps_iter_samples = 1;
1061 uint32_t mask = 0xffff;
1062
1063 if (vkms) {
1064 ms->num_samples = vkms->rasterizationSamples;
1065
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1067 *
1068 * "Sample shading is enabled for a graphics pipeline:
1069 *
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1079 *
1080 * Otherwise, sample shading is considered disabled."
1081 */
1082 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1083 ps_iter_samples = ms->num_samples;
1084 } else {
1085 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1086 }
1087 } else {
1088 ms->num_samples = 1;
1089 }
1090
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1092 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1093 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1095 * application.
1096 */
1097 out_of_order_rast = true;
1098 } else {
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1101 */
1102 out_of_order_rast =
1103 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1104 }
1105
1106 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1107 ms->pa_sc_aa_config = 0;
1108 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1109 S_028804_INCOHERENT_EQAA_READS(1) |
1110 S_028804_INTERPOLATE_COMP_Z(1) |
1111 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1112 ms->pa_sc_mode_cntl_1 =
1113 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1114 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1115 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1116 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1117 /* always 1: */
1118 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1119 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1121 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1123 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1124 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1125 S_028A48_VPORT_SCISSOR_ENABLE(1);
1126
1127 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1128 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1129 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1130 if (rast_line) {
1131 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1132 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1133 /* From the Vulkan spec 1.1.129:
1134 *
1135 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1136 * are being rasterized, sample locations may all be
1137 * treated as being at the pixel center (this may
1138 * affect attribute and depth interpolation)."
1139 */
1140 ms->num_samples = 1;
1141 }
1142 }
1143
1144 if (ms->num_samples > 1) {
1145 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1146 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1147 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1148 unsigned log_samples = util_logbase2(ms->num_samples);
1149 unsigned log_z_samples = util_logbase2(z_samples);
1150 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1152 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1153 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1154 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1155 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1156 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1157 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1158 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1159 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1160 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1161 if (ps_iter_samples > 1)
1162 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1163 }
1164
1165 if (vkms && vkms->pSampleMask) {
1166 mask = vkms->pSampleMask[0] & 0xffff;
1167 }
1168
1169 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1170 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1171 }
1172
1173 static bool
1174 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1175 {
1176 switch (topology) {
1177 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1182 return false;
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1189 return true;
1190 default:
1191 unreachable("unhandled primitive type");
1192 }
1193 }
1194
1195 static uint32_t
1196 si_translate_prim(enum VkPrimitiveTopology topology)
1197 {
1198 switch (topology) {
1199 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1200 return V_008958_DI_PT_POINTLIST;
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1202 return V_008958_DI_PT_LINELIST;
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1204 return V_008958_DI_PT_LINESTRIP;
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1206 return V_008958_DI_PT_TRILIST;
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1208 return V_008958_DI_PT_TRISTRIP;
1209 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1210 return V_008958_DI_PT_TRIFAN;
1211 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1212 return V_008958_DI_PT_LINELIST_ADJ;
1213 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1214 return V_008958_DI_PT_LINESTRIP_ADJ;
1215 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1216 return V_008958_DI_PT_TRILIST_ADJ;
1217 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1218 return V_008958_DI_PT_TRISTRIP_ADJ;
1219 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1220 return V_008958_DI_PT_PATCH;
1221 default:
1222 assert(0);
1223 return 0;
1224 }
1225 }
1226
1227 static uint32_t
1228 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1229 {
1230 switch (gl_prim) {
1231 case 0: /* GL_POINTS */
1232 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1233 case 1: /* GL_LINES */
1234 case 3: /* GL_LINE_STRIP */
1235 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1236 case 0x8E7A: /* GL_ISOLINES */
1237 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1238
1239 case 4: /* GL_TRIANGLES */
1240 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1241 case 5: /* GL_TRIANGLE_STRIP */
1242 case 7: /* GL_QUADS */
1243 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1244 default:
1245 assert(0);
1246 return 0;
1247 }
1248 }
1249
1250 static uint32_t
1251 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1252 {
1253 switch (topology) {
1254 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1255 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1256 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1257 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1258 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1259 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1260 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1261 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1262 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1263 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1264 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1266 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1267 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1268 default:
1269 assert(0);
1270 return 0;
1271 }
1272 }
1273
1274 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1275 {
1276 switch(state) {
1277 case VK_DYNAMIC_STATE_VIEWPORT:
1278 return RADV_DYNAMIC_VIEWPORT;
1279 case VK_DYNAMIC_STATE_SCISSOR:
1280 return RADV_DYNAMIC_SCISSOR;
1281 case VK_DYNAMIC_STATE_LINE_WIDTH:
1282 return RADV_DYNAMIC_LINE_WIDTH;
1283 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1284 return RADV_DYNAMIC_DEPTH_BIAS;
1285 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1286 return RADV_DYNAMIC_BLEND_CONSTANTS;
1287 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1288 return RADV_DYNAMIC_DEPTH_BOUNDS;
1289 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1290 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1291 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1292 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1293 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1294 return RADV_DYNAMIC_STENCIL_REFERENCE;
1295 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1296 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1297 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1298 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1299 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1300 return RADV_DYNAMIC_LINE_STIPPLE;
1301 default:
1302 unreachable("Unhandled dynamic state");
1303 }
1304 }
1305
1306 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1307 {
1308 uint32_t states = RADV_DYNAMIC_ALL;
1309
1310 /* If rasterization is disabled we do not care about any of the dynamic states,
1311 * since they are all rasterization related only. */
1312 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1313 return 0;
1314
1315 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1316 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1317
1318 if (!pCreateInfo->pDepthStencilState ||
1319 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1320 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1321
1322 if (!pCreateInfo->pDepthStencilState ||
1323 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1324 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1325 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1326 RADV_DYNAMIC_STENCIL_REFERENCE);
1327
1328 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1329 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1330
1331 if (!pCreateInfo->pMultisampleState ||
1332 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1333 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1335
1336 if (!pCreateInfo->pRasterizationState ||
1337 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1338 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1420 *
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1426 */
1427 if (needed_states && subpass->depth_stencil_attachment) {
1428 assert(pCreateInfo->pDepthStencilState);
1429
1430 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1431 dynamic->depth_bounds.min =
1432 pCreateInfo->pDepthStencilState->minDepthBounds;
1433 dynamic->depth_bounds.max =
1434 pCreateInfo->pDepthStencilState->maxDepthBounds;
1435 }
1436
1437 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1438 dynamic->stencil_compare_mask.front =
1439 pCreateInfo->pDepthStencilState->front.compareMask;
1440 dynamic->stencil_compare_mask.back =
1441 pCreateInfo->pDepthStencilState->back.compareMask;
1442 }
1443
1444 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1445 dynamic->stencil_write_mask.front =
1446 pCreateInfo->pDepthStencilState->front.writeMask;
1447 dynamic->stencil_write_mask.back =
1448 pCreateInfo->pDepthStencilState->back.writeMask;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1452 dynamic->stencil_reference.front =
1453 pCreateInfo->pDepthStencilState->front.reference;
1454 dynamic->stencil_reference.back =
1455 pCreateInfo->pDepthStencilState->back.reference;
1456 }
1457 }
1458
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1460 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1461 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1462 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1463 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 typed_memcpy(dynamic->discard_rectangle.rectangles,
1465 discard_rectangle_info->pDiscardRectangles,
1466 discard_rectangle_info->discardRectangleCount);
1467 }
1468 }
1469
1470 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1472 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1477 */
1478 if (sample_location_info->sampleLocationsEnable) {
1479 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1480 &sample_location_info->sampleLocationsInfo;
1481
1482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1483
1484 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1485 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1486 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1487 typed_memcpy(&dynamic->sample_location.locations[0],
1488 pSampleLocationsInfo->pSampleLocations,
1489 pSampleLocationsInfo->sampleLocationsCount);
1490 }
1491 }
1492
1493 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1494 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1495 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1496 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1497 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1498 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1499 }
1500
1501 pipeline->dynamic_state.mask = states;
1502 }
1503
1504 static void
1505 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1506 const struct radv_pipeline *pipeline,
1507 nir_shader **nir,
1508 struct radv_shader_info *infos,
1509 struct gfx9_gs_info *out)
1510 {
1511 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1512 struct radv_es_output_info *es_info;
1513 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1514 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1515 else
1516 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1517 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1518 &infos[MESA_SHADER_VERTEX].vs.es_info;
1519
1520 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1521 bool uses_adjacency;
1522 switch(key->topology) {
1523 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1525 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1527 uses_adjacency = true;
1528 break;
1529 default:
1530 uses_adjacency = false;
1531 break;
1532 }
1533
1534 /* All these are in dwords: */
1535 /* We can't allow using the whole LDS, because GS waves compete with
1536 * other shader stages for LDS space. */
1537 const unsigned max_lds_size = 8 * 1024;
1538 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1539 unsigned esgs_lds_size;
1540
1541 /* All these are per subgroup: */
1542 const unsigned max_out_prims = 32 * 1024;
1543 const unsigned max_es_verts = 255;
1544 const unsigned ideal_gs_prims = 64;
1545 unsigned max_gs_prims, gs_prims;
1546 unsigned min_es_verts, es_verts, worst_case_es_verts;
1547
1548 if (uses_adjacency || gs_num_invocations > 1)
1549 max_gs_prims = 127 / gs_num_invocations;
1550 else
1551 max_gs_prims = 255;
1552
1553 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1554 * Make sure we don't go over the maximum value.
1555 */
1556 if (gs_info->gs.vertices_out > 0) {
1557 max_gs_prims = MIN2(max_gs_prims,
1558 max_out_prims /
1559 (gs_info->gs.vertices_out * gs_num_invocations));
1560 }
1561 assert(max_gs_prims > 0);
1562
1563 /* If the primitive has adjacency, halve the number of vertices
1564 * that will be reused in multiple primitives.
1565 */
1566 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1567
1568 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1569 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1570
1571 /* Compute ESGS LDS size based on the worst case number of ES vertices
1572 * needed to create the target number of GS prims per subgroup.
1573 */
1574 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1575
1576 /* If total LDS usage is too big, refactor partitions based on ratio
1577 * of ESGS item sizes.
1578 */
1579 if (esgs_lds_size > max_lds_size) {
1580 /* Our target GS Prims Per Subgroup was too large. Calculate
1581 * the maximum number of GS Prims Per Subgroup that will fit
1582 * into LDS, capped by the maximum that the hardware can support.
1583 */
1584 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1585 max_gs_prims);
1586 assert(gs_prims > 0);
1587 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1588 max_es_verts);
1589
1590 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1591 assert(esgs_lds_size <= max_lds_size);
1592 }
1593
1594 /* Now calculate remaining ESGS information. */
1595 if (esgs_lds_size)
1596 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1597 else
1598 es_verts = max_es_verts;
1599
1600 /* Vertices for adjacency primitives are not always reused, so restore
1601 * it for ES_VERTS_PER_SUBGRP.
1602 */
1603 min_es_verts = gs_info->gs.vertices_in;
1604
1605 /* For normal primitives, the VGT only checks if they are past the ES
1606 * verts per subgroup after allocating a full GS primitive and if they
1607 * are, kick off a new subgroup. But if those additional ES verts are
1608 * unique (e.g. not reused) we need to make sure there is enough LDS
1609 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1610 */
1611 es_verts -= min_es_verts - 1;
1612
1613 uint32_t es_verts_per_subgroup = es_verts;
1614 uint32_t gs_prims_per_subgroup = gs_prims;
1615 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1616 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1617 out->lds_size = align(esgs_lds_size, 128) / 128;
1618 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1619 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1620 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1621 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1622 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1623 assert(max_prims_per_subgroup <= max_out_prims);
1624 }
1625
1626 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1627 unsigned min_verts_per_prim, bool use_adjacency)
1628 {
1629 unsigned max_reuse = max_esverts - min_verts_per_prim;
1630 if (use_adjacency)
1631 max_reuse /= 2;
1632 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1633 }
1634
1635 static unsigned
1636 radv_get_num_input_vertices(nir_shader **nir)
1637 {
1638 if (nir[MESA_SHADER_GEOMETRY]) {
1639 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1640
1641 return gs->info.gs.vertices_in;
1642 }
1643
1644 if (nir[MESA_SHADER_TESS_CTRL]) {
1645 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1646
1647 if (tes->info.tess.point_mode)
1648 return 1;
1649 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1650 return 2;
1651 return 3;
1652 }
1653
1654 return 3;
1655 }
1656
1657 static void
1658 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1659 struct radv_pipeline *pipeline,
1660 nir_shader **nir,
1661 struct radv_shader_info *infos,
1662 struct gfx10_ngg_info *ngg)
1663 {
1664 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1665 struct radv_es_output_info *es_info =
1666 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1667 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1668 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1669 unsigned min_verts_per_prim =
1670 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1671 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1672 bool uses_adjacency;
1673 switch(key->topology) {
1674 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1675 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1676 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1677 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1678 uses_adjacency = true;
1679 break;
1680 default:
1681 uses_adjacency = false;
1682 break;
1683 }
1684
1685 /* All these are in dwords: */
1686 /* We can't allow using the whole LDS, because GS waves compete with
1687 * other shader stages for LDS space.
1688 *
1689 * TODO: We should really take the shader's internal LDS use into
1690 * account. The linker will fail if the size is greater than
1691 * 8K dwords.
1692 */
1693 const unsigned max_lds_size = 8 * 1024 - 768;
1694 const unsigned target_lds_size = max_lds_size;
1695 unsigned esvert_lds_size = 0;
1696 unsigned gsprim_lds_size = 0;
1697
1698 /* All these are per subgroup: */
1699 bool max_vert_out_per_gs_instance = false;
1700 unsigned max_esverts_base = 256;
1701 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1702
1703 /* Hardware has the following non-natural restrictions on the value
1704 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1705 * the draw:
1706 * - at most 252 for any line input primitive type
1707 * - at most 251 for any quad input primitive type
1708 * - at most 251 for triangle strips with adjacency (this happens to
1709 * be the natural limit for triangle *lists* with adjacency)
1710 */
1711 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1712
1713 if (gs_type == MESA_SHADER_GEOMETRY) {
1714 unsigned max_out_verts_per_gsprim =
1715 gs_info->gs.vertices_out * gs_num_invocations;
1716
1717 if (max_out_verts_per_gsprim <= 256) {
1718 if (max_out_verts_per_gsprim) {
1719 max_gsprims_base = MIN2(max_gsprims_base,
1720 256 / max_out_verts_per_gsprim);
1721 }
1722 } else {
1723 /* Use special multi-cycling mode in which each GS
1724 * instance gets its own subgroup. Does not work with
1725 * tessellation. */
1726 max_vert_out_per_gs_instance = true;
1727 max_gsprims_base = 1;
1728 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1729 }
1730
1731 esvert_lds_size = es_info->esgs_itemsize / 4;
1732 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1733 } else {
1734 /* VS and TES. */
1735 /* LDS size for passing data from GS to ES. */
1736 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1737 ? &infos[MESA_SHADER_TESS_EVAL].so
1738 : &infos[MESA_SHADER_VERTEX].so;
1739
1740 if (so_info->num_outputs)
1741 esvert_lds_size = 4 * so_info->num_outputs + 1;
1742
1743 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1744 * corresponding to the ES thread of the provoking vertex. All
1745 * ES threads load and export PrimitiveID for their thread.
1746 */
1747 if (!nir[MESA_SHADER_TESS_CTRL] &&
1748 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1749 esvert_lds_size = MAX2(esvert_lds_size, 1);
1750 }
1751
1752 unsigned max_gsprims = max_gsprims_base;
1753 unsigned max_esverts = max_esverts_base;
1754
1755 if (esvert_lds_size)
1756 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1757 if (gsprim_lds_size)
1758 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1759
1760 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1761 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1762 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1763
1764 if (esvert_lds_size || gsprim_lds_size) {
1765 /* Now that we have a rough proportionality between esverts
1766 * and gsprims based on the primitive type, scale both of them
1767 * down simultaneously based on required LDS space.
1768 *
1769 * We could be smarter about this if we knew how much vertex
1770 * reuse to expect.
1771 */
1772 unsigned lds_total = max_esverts * esvert_lds_size +
1773 max_gsprims * gsprim_lds_size;
1774 if (lds_total > target_lds_size) {
1775 max_esverts = max_esverts * target_lds_size / lds_total;
1776 max_gsprims = max_gsprims * target_lds_size / lds_total;
1777
1778 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1779 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1780 min_verts_per_prim, uses_adjacency);
1781 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1782 }
1783 }
1784
1785 /* Round up towards full wave sizes for better ALU utilization. */
1786 if (!max_vert_out_per_gs_instance) {
1787 unsigned orig_max_esverts;
1788 unsigned orig_max_gsprims;
1789 unsigned wavesize;
1790
1791 if (gs_type == MESA_SHADER_GEOMETRY) {
1792 wavesize = gs_info->wave_size;
1793 } else {
1794 wavesize = nir[MESA_SHADER_TESS_CTRL]
1795 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1796 : infos[MESA_SHADER_VERTEX].wave_size;
1797 }
1798
1799 do {
1800 orig_max_esverts = max_esverts;
1801 orig_max_gsprims = max_gsprims;
1802
1803 max_esverts = align(max_esverts, wavesize);
1804 max_esverts = MIN2(max_esverts, max_esverts_base);
1805 if (esvert_lds_size)
1806 max_esverts = MIN2(max_esverts,
1807 (max_lds_size - max_gsprims * gsprim_lds_size) /
1808 esvert_lds_size);
1809 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1810
1811 max_gsprims = align(max_gsprims, wavesize);
1812 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1813 if (gsprim_lds_size)
1814 max_gsprims = MIN2(max_gsprims,
1815 (max_lds_size - max_esverts * esvert_lds_size) /
1816 gsprim_lds_size);
1817 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1818 min_verts_per_prim, uses_adjacency);
1819 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1820 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1821 }
1822
1823 /* Hardware restriction: minimum value of max_esverts */
1824 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1825
1826 unsigned max_out_vertices =
1827 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1828 gs_type == MESA_SHADER_GEOMETRY ?
1829 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1830 max_esverts;
1831 assert(max_out_vertices <= 256);
1832
1833 unsigned prim_amp_factor = 1;
1834 if (gs_type == MESA_SHADER_GEOMETRY) {
1835 /* Number of output primitives per GS input primitive after
1836 * GS instancing. */
1837 prim_amp_factor = gs_info->gs.vertices_out;
1838 }
1839
1840 /* The GE only checks against the maximum number of ES verts after
1841 * allocating a full GS primitive. So we need to ensure that whenever
1842 * this check passes, there is enough space for a full primitive without
1843 * vertex reuse.
1844 */
1845 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1846 ngg->max_gsprims = max_gsprims;
1847 ngg->max_out_verts = max_out_vertices;
1848 ngg->prim_amp_factor = prim_amp_factor;
1849 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1850 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1851 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1852
1853 if (gs_type == MESA_SHADER_GEOMETRY) {
1854 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1855 } else {
1856 ngg->vgt_esgs_ring_itemsize = 1;
1857 }
1858
1859 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1860
1861 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1862 }
1863
1864 static void
1865 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1866 const struct gfx9_gs_info *gs)
1867 {
1868 struct radv_device *device = pipeline->device;
1869 unsigned num_se = device->physical_device->rad_info.max_se;
1870 unsigned wave_size = 64;
1871 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1872 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1873 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1874 */
1875 unsigned gs_vertex_reuse =
1876 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1877 unsigned alignment = 256 * num_se;
1878 /* The maximum size is 63.999 MB per SE. */
1879 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1880 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1881
1882 /* Calculate the minimum size. */
1883 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1884 wave_size, alignment);
1885 /* These are recommended sizes, not minimum sizes. */
1886 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1887 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1888 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1889 gs_info->gs.max_gsvs_emit_size;
1890
1891 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1892 esgs_ring_size = align(esgs_ring_size, alignment);
1893 gsvs_ring_size = align(gsvs_ring_size, alignment);
1894
1895 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1896 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1897
1898 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1899 }
1900
1901 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1902 unsigned *lds_size)
1903 {
1904 /* If tessellation is all offchip and on-chip GS isn't used, this
1905 * workaround is not needed.
1906 */
1907 return;
1908
1909 /* SPI barrier management bug:
1910 * Make sure we have at least 4k of LDS in use to avoid the bug.
1911 * It applies to workgroup sizes of more than one wavefront.
1912 */
1913 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1914 device->physical_device->rad_info.family == CHIP_KABINI)
1915 *lds_size = MAX2(*lds_size, 8);
1916 }
1917
1918 struct radv_shader_variant *
1919 radv_get_shader(struct radv_pipeline *pipeline,
1920 gl_shader_stage stage)
1921 {
1922 if (stage == MESA_SHADER_VERTEX) {
1923 if (pipeline->shaders[MESA_SHADER_VERTEX])
1924 return pipeline->shaders[MESA_SHADER_VERTEX];
1925 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1926 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1927 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1928 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1929 } else if (stage == MESA_SHADER_TESS_EVAL) {
1930 if (!radv_pipeline_has_tess(pipeline))
1931 return NULL;
1932 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1933 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1934 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1935 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1936 }
1937 return pipeline->shaders[stage];
1938 }
1939
1940 static struct radv_tessellation_state
1941 calculate_tess_state(struct radv_pipeline *pipeline,
1942 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1943 {
1944 unsigned num_tcs_input_cp;
1945 unsigned num_tcs_output_cp;
1946 unsigned lds_size;
1947 unsigned num_patches;
1948 struct radv_tessellation_state tess = {0};
1949
1950 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1951 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1952 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1953
1954 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1955
1956 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1957 assert(lds_size <= 65536);
1958 lds_size = align(lds_size, 512) / 512;
1959 } else {
1960 assert(lds_size <= 32768);
1961 lds_size = align(lds_size, 256) / 256;
1962 }
1963 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1964
1965 tess.lds_size = lds_size;
1966
1967 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1968 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1969 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1970 tess.num_patches = num_patches;
1971
1972 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1973 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1974
1975 switch (tes->info.tes.primitive_mode) {
1976 case GL_TRIANGLES:
1977 type = V_028B6C_TESS_TRIANGLE;
1978 break;
1979 case GL_QUADS:
1980 type = V_028B6C_TESS_QUAD;
1981 break;
1982 case GL_ISOLINES:
1983 type = V_028B6C_TESS_ISOLINE;
1984 break;
1985 }
1986
1987 switch (tes->info.tes.spacing) {
1988 case TESS_SPACING_EQUAL:
1989 partitioning = V_028B6C_PART_INTEGER;
1990 break;
1991 case TESS_SPACING_FRACTIONAL_ODD:
1992 partitioning = V_028B6C_PART_FRAC_ODD;
1993 break;
1994 case TESS_SPACING_FRACTIONAL_EVEN:
1995 partitioning = V_028B6C_PART_FRAC_EVEN;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 bool ccw = tes->info.tes.ccw;
2002 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2003 vk_find_struct_const(pCreateInfo->pTessellationState,
2004 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2005
2006 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2007 ccw = !ccw;
2008
2009 if (tes->info.tes.point_mode)
2010 topology = V_028B6C_OUTPUT_POINT;
2011 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2012 topology = V_028B6C_OUTPUT_LINE;
2013 else if (ccw)
2014 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2015 else
2016 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2017
2018 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2019 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2020 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2021 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2022 else
2023 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2024 } else
2025 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2026
2027 tess.tf_param = S_028B6C_TYPE(type) |
2028 S_028B6C_PARTITIONING(partitioning) |
2029 S_028B6C_TOPOLOGY(topology) |
2030 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2031
2032 return tess;
2033 }
2034
2035 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2036 {
2037 if (radv_pipeline_has_gs(pipeline))
2038 if (radv_pipeline_has_ngg(pipeline))
2039 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2040 else
2041 return &pipeline->gs_copy_shader->info.vs.outinfo;
2042 else if (radv_pipeline_has_tess(pipeline))
2043 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2044 else
2045 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2046 }
2047
2048 static void
2049 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2050 {
2051 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2052 int shader_count = 0;
2053
2054 if(shaders[MESA_SHADER_FRAGMENT]) {
2055 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2056 }
2057 if(shaders[MESA_SHADER_GEOMETRY]) {
2058 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2059 }
2060 if(shaders[MESA_SHADER_TESS_EVAL]) {
2061 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2062 }
2063 if(shaders[MESA_SHADER_TESS_CTRL]) {
2064 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2065 }
2066 if(shaders[MESA_SHADER_VERTEX]) {
2067 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2068 }
2069
2070 if (shader_count > 1) {
2071 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2072 unsigned last = ordered_shaders[0]->info.stage;
2073
2074 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2075 ordered_shaders[1]->info.has_transform_feedback_varyings)
2076 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2077
2078 for (int i = 0; i < shader_count; ++i) {
2079 nir_variable_mode mask = 0;
2080
2081 if (ordered_shaders[i]->info.stage != first)
2082 mask = mask | nir_var_shader_in;
2083
2084 if (ordered_shaders[i]->info.stage != last)
2085 mask = mask | nir_var_shader_out;
2086
2087 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2088 radv_optimize_nir(ordered_shaders[i], false, false);
2089 }
2090 }
2091
2092 for (int i = 1; i < shader_count; ++i) {
2093 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2094 ordered_shaders[i - 1]);
2095
2096 if (nir_link_opt_varyings(ordered_shaders[i],
2097 ordered_shaders[i - 1]))
2098 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2099
2100 nir_remove_dead_variables(ordered_shaders[i],
2101 nir_var_shader_out, NULL);
2102 nir_remove_dead_variables(ordered_shaders[i - 1],
2103 nir_var_shader_in, NULL);
2104
2105 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2106 ordered_shaders[i - 1]);
2107
2108 nir_compact_varyings(ordered_shaders[i],
2109 ordered_shaders[i - 1], true);
2110
2111 if (progress) {
2112 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2113 ac_lower_indirect_derefs(ordered_shaders[i],
2114 pipeline->device->physical_device->rad_info.chip_class);
2115 }
2116 radv_optimize_nir(ordered_shaders[i], false, false);
2117
2118 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2119 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2120 pipeline->device->physical_device->rad_info.chip_class);
2121 }
2122 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2123 }
2124 }
2125 }
2126
2127 static void
2128 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2129 struct radv_shader_info infos[MESA_SHADER_STAGES])
2130 {
2131 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2132 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2133
2134 if (!has_tess && !has_gs)
2135 return;
2136
2137 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2138 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2139
2140 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2141 /* These are merged into the next stage */
2142 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2143 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2144 }
2145
2146 if (has_tess) {
2147 nir_linked_io_var_info vs2tcs =
2148 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2149 nir_linked_io_var_info tcs2tes =
2150 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2151
2152 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2153 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2154 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2155 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2156 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2157 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2158
2159 if (has_gs) {
2160 nir_linked_io_var_info tes2gs =
2161 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2162
2163 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2164 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2165 }
2166 } else if (has_gs) {
2167 nir_linked_io_var_info vs2gs =
2168 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2169
2170 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2171 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2172 }
2173 }
2174
2175 static uint32_t
2176 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2177 uint32_t attrib_binding)
2178 {
2179 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2180 const VkVertexInputBindingDescription *input_binding =
2181 &input_state->pVertexBindingDescriptions[i];
2182
2183 if (input_binding->binding == attrib_binding)
2184 return input_binding->stride;
2185 }
2186
2187 return 0;
2188 }
2189
2190 static struct radv_pipeline_key
2191 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2192 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2193 const struct radv_blend_state *blend,
2194 bool has_view_index)
2195 {
2196 const VkPipelineVertexInputStateCreateInfo *input_state =
2197 pCreateInfo->pVertexInputState;
2198 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2199 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2200
2201 struct radv_pipeline_key key;
2202 memset(&key, 0, sizeof(key));
2203
2204 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2205 key.optimisations_disabled = 1;
2206
2207 key.has_multiview_view_index = has_view_index;
2208
2209 uint32_t binding_input_rate = 0;
2210 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2211 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2212 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2213 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2214 binding_input_rate |= 1u << binding;
2215 instance_rate_divisors[binding] = 1;
2216 }
2217 }
2218 if (divisor_state) {
2219 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2220 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2221 divisor_state->pVertexBindingDivisors[i].divisor;
2222 }
2223 }
2224
2225 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2226 const VkVertexInputAttributeDescription *desc =
2227 &input_state->pVertexAttributeDescriptions[i];
2228 const struct vk_format_description *format_desc;
2229 unsigned location = desc->location;
2230 unsigned binding = desc->binding;
2231 unsigned num_format, data_format;
2232 int first_non_void;
2233
2234 if (binding_input_rate & (1u << binding)) {
2235 key.instance_rate_inputs |= 1u << location;
2236 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2237 }
2238
2239 format_desc = vk_format_description(desc->format);
2240 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2241
2242 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2243 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2244
2245 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2246 key.vertex_attribute_bindings[location] = desc->binding;
2247 key.vertex_attribute_offsets[location] = desc->offset;
2248 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2249
2250 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2251 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2252 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2253 uint64_t adjust;
2254 switch(format) {
2255 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2256 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2257 adjust = RADV_ALPHA_ADJUST_SNORM;
2258 break;
2259 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2260 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2261 adjust = RADV_ALPHA_ADJUST_SSCALED;
2262 break;
2263 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2264 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2265 adjust = RADV_ALPHA_ADJUST_SINT;
2266 break;
2267 default:
2268 adjust = 0;
2269 break;
2270 }
2271 key.vertex_alpha_adjust |= adjust << (2 * location);
2272 }
2273
2274 switch (desc->format) {
2275 case VK_FORMAT_B8G8R8A8_UNORM:
2276 case VK_FORMAT_B8G8R8A8_SNORM:
2277 case VK_FORMAT_B8G8R8A8_USCALED:
2278 case VK_FORMAT_B8G8R8A8_SSCALED:
2279 case VK_FORMAT_B8G8R8A8_UINT:
2280 case VK_FORMAT_B8G8R8A8_SINT:
2281 case VK_FORMAT_B8G8R8A8_SRGB:
2282 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2283 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2284 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2285 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2286 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2287 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2288 key.vertex_post_shuffle |= 1 << location;
2289 break;
2290 default:
2291 break;
2292 }
2293 }
2294
2295 const VkPipelineTessellationStateCreateInfo *tess =
2296 radv_pipeline_get_tessellation_state(pCreateInfo);
2297 if (tess)
2298 key.tess_input_vertices = tess->patchControlPoints;
2299
2300 const VkPipelineMultisampleStateCreateInfo *vkms =
2301 radv_pipeline_get_multisample_state(pCreateInfo);
2302 if (vkms && vkms->rasterizationSamples > 1) {
2303 uint32_t num_samples = vkms->rasterizationSamples;
2304 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2305 key.num_samples = num_samples;
2306 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2307 }
2308
2309 key.col_format = blend->spi_shader_col_format;
2310 key.is_dual_src = blend->mrt0_is_dual_src;
2311 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2312 key.is_int8 = blend->col_format_is_int8;
2313 key.is_int10 = blend->col_format_is_int10;
2314 }
2315
2316 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2317 key.topology = pCreateInfo->pInputAssemblyState->topology;
2318
2319 return key;
2320 }
2321
2322 static bool
2323 radv_nir_stage_uses_xfb(const nir_shader *nir)
2324 {
2325 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2326 bool uses_xfb = !!xfb;
2327
2328 ralloc_free(xfb);
2329 return uses_xfb;
2330 }
2331
2332 static void
2333 radv_fill_shader_keys(struct radv_device *device,
2334 struct radv_shader_variant_key *keys,
2335 const struct radv_pipeline_key *key,
2336 nir_shader **nir)
2337 {
2338 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2339 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2340 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2341 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2342 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2343 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2344 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2345 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2346 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2347 }
2348 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2349
2350 if (nir[MESA_SHADER_TESS_CTRL]) {
2351 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2352 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2353 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2354 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2355
2356 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2357 }
2358
2359 if (nir[MESA_SHADER_GEOMETRY]) {
2360 if (nir[MESA_SHADER_TESS_CTRL])
2361 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2362 else
2363 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2364 }
2365
2366 if (device->physical_device->use_ngg) {
2367 if (nir[MESA_SHADER_TESS_CTRL]) {
2368 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2369 } else {
2370 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2371 }
2372
2373 if (nir[MESA_SHADER_TESS_CTRL] &&
2374 nir[MESA_SHADER_GEOMETRY] &&
2375 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2376 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2377 /* Fallback to the legacy path if tessellation is
2378 * enabled with extreme geometry because
2379 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2380 * might hang.
2381 */
2382 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2383 }
2384
2385 if (!device->physical_device->use_ngg_gs) {
2386 if (nir[MESA_SHADER_GEOMETRY]) {
2387 if (nir[MESA_SHADER_TESS_CTRL])
2388 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2389 else
2390 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2391 }
2392 }
2393
2394 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2395
2396 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2397 if (nir[i])
2398 last_xfb_stage = i;
2399 }
2400
2401 bool uses_xfb = nir[last_xfb_stage] &&
2402 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2403
2404 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2405 if (nir[MESA_SHADER_TESS_CTRL])
2406 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2407 else
2408 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2409 }
2410
2411 /* Determine if the pipeline is eligible for the NGG passthrough
2412 * mode. It can't be enabled for geometry shaders, for NGG
2413 * streamout or for vertex shaders that export the primitive ID
2414 * (this is checked later because we don't have the info here.)
2415 */
2416 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2417 if (nir[MESA_SHADER_TESS_CTRL] &&
2418 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2419 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2420 } else if (nir[MESA_SHADER_VERTEX] &&
2421 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2422 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2423 }
2424 }
2425 }
2426
2427 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2428 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2429
2430 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2431 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2432 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2433 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2434 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2435 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2436
2437 if (nir[MESA_SHADER_COMPUTE]) {
2438 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2439 }
2440 }
2441
2442 static uint8_t
2443 radv_get_wave_size(struct radv_device *device,
2444 const VkPipelineShaderStageCreateInfo *pStage,
2445 gl_shader_stage stage,
2446 const struct radv_shader_variant_key *key)
2447 {
2448 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2449 return 64;
2450 else if (stage == MESA_SHADER_COMPUTE) {
2451 if (key->cs.subgroup_size) {
2452 /* Return the required subgroup size if specified. */
2453 return key->cs.subgroup_size;
2454 }
2455 return device->physical_device->cs_wave_size;
2456 }
2457 else if (stage == MESA_SHADER_FRAGMENT)
2458 return device->physical_device->ps_wave_size;
2459 else
2460 return device->physical_device->ge_wave_size;
2461 }
2462
2463 static uint8_t
2464 radv_get_ballot_bit_size(struct radv_device *device,
2465 const VkPipelineShaderStageCreateInfo *pStage,
2466 gl_shader_stage stage,
2467 const struct radv_shader_variant_key *key)
2468 {
2469 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2470 return key->cs.subgroup_size;
2471 return 64;
2472 }
2473
2474 static void
2475 radv_fill_shader_info(struct radv_pipeline *pipeline,
2476 const VkPipelineShaderStageCreateInfo **pStages,
2477 struct radv_shader_variant_key *keys,
2478 struct radv_shader_info *infos,
2479 nir_shader **nir)
2480 {
2481 unsigned active_stages = 0;
2482 unsigned filled_stages = 0;
2483
2484 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2485 if (nir[i])
2486 active_stages |= (1 << i);
2487 }
2488
2489 if (nir[MESA_SHADER_FRAGMENT]) {
2490 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2491 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2492 pipeline->layout,
2493 &keys[MESA_SHADER_FRAGMENT],
2494 &infos[MESA_SHADER_FRAGMENT],
2495 pipeline->device->physical_device->use_llvm);
2496
2497 /* TODO: These are no longer used as keys we should refactor this */
2498 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2499 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2500 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2501 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2502 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2503 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2504 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2505 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2506 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2507 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2508 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2509 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2510 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2511 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2512 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2513 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2514
2515 /* NGG passthrough mode can't be enabled for vertex shaders
2516 * that export the primitive ID.
2517 *
2518 * TODO: I should really refactor the keys logic.
2519 */
2520 if (nir[MESA_SHADER_VERTEX] &&
2521 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2522 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2523 }
2524
2525 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2526 }
2527
2528 if (nir[MESA_SHADER_TESS_CTRL]) {
2529 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2530 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2531 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2532 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2533 }
2534
2535 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2536 nir[MESA_SHADER_TESS_CTRL]) {
2537 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2538 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2539 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2540
2541 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2542
2543 for (int i = 0; i < 2; i++) {
2544 radv_nir_shader_info_pass(combined_nir[i],
2545 pipeline->layout, &key,
2546 &infos[MESA_SHADER_TESS_CTRL],
2547 pipeline->device->physical_device->use_llvm);
2548 }
2549
2550 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2551 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2552 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2553 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2554
2555 filled_stages |= (1 << MESA_SHADER_VERTEX);
2556 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2557 }
2558
2559 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2560 nir[MESA_SHADER_GEOMETRY]) {
2561 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2562 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2563
2564 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2565
2566 for (int i = 0; i < 2; i++) {
2567 radv_nir_shader_info_pass(combined_nir[i],
2568 pipeline->layout,
2569 &keys[pre_stage],
2570 &infos[MESA_SHADER_GEOMETRY],
2571 pipeline->device->physical_device->use_llvm);
2572 }
2573
2574 filled_stages |= (1 << pre_stage);
2575 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2576 }
2577
2578 active_stages ^= filled_stages;
2579 while (active_stages) {
2580 int i = u_bit_scan(&active_stages);
2581
2582 if (i == MESA_SHADER_TESS_CTRL) {
2583 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2584 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2585 }
2586
2587 if (i == MESA_SHADER_TESS_EVAL) {
2588 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2589 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2590 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2591 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2592 }
2593
2594 radv_nir_shader_info_init(&infos[i]);
2595 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2596 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2597 }
2598
2599 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2600 if (nir[i]) {
2601 infos[i].wave_size =
2602 radv_get_wave_size(pipeline->device, pStages[i],
2603 i, &keys[i]);
2604 infos[i].ballot_bit_size =
2605 radv_get_ballot_bit_size(pipeline->device,
2606 pStages[i], i,
2607 &keys[i]);
2608 }
2609 }
2610 }
2611
2612 static void
2613 merge_tess_info(struct shader_info *tes_info,
2614 const struct shader_info *tcs_info)
2615 {
2616 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2617 *
2618 * "PointMode. Controls generation of points rather than triangles
2619 * or lines. This functionality defaults to disabled, and is
2620 * enabled if either shader stage includes the execution mode.
2621 *
2622 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2623 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2624 * and OutputVertices, it says:
2625 *
2626 * "One mode must be set in at least one of the tessellation
2627 * shader stages."
2628 *
2629 * So, the fields can be set in either the TCS or TES, but they must
2630 * agree if set in both. Our backend looks at TES, so bitwise-or in
2631 * the values from the TCS.
2632 */
2633 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2634 tes_info->tess.tcs_vertices_out == 0 ||
2635 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2636 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2637
2638 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2639 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2640 tcs_info->tess.spacing == tes_info->tess.spacing);
2641 tes_info->tess.spacing |= tcs_info->tess.spacing;
2642
2643 assert(tcs_info->tess.primitive_mode == 0 ||
2644 tes_info->tess.primitive_mode == 0 ||
2645 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2646 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2647 tes_info->tess.ccw |= tcs_info->tess.ccw;
2648 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2649 }
2650
2651 static
2652 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2653 {
2654 if (!ext)
2655 return;
2656
2657 if (ext->pPipelineCreationFeedback) {
2658 ext->pPipelineCreationFeedback->flags = 0;
2659 ext->pPipelineCreationFeedback->duration = 0;
2660 }
2661
2662 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2663 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2664 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2665 }
2666 }
2667
2668 static
2669 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2670 {
2671 if (!feedback)
2672 return;
2673
2674 feedback->duration -= radv_get_current_time();
2675 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2676 }
2677
2678 static
2679 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2680 {
2681 if (!feedback)
2682 return;
2683
2684 feedback->duration += radv_get_current_time();
2685 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2686 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2687 }
2688
2689 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2690 struct radv_device *device,
2691 struct radv_pipeline_cache *cache,
2692 const struct radv_pipeline_key *key,
2693 const VkPipelineShaderStageCreateInfo **pStages,
2694 const VkPipelineCreateFlags flags,
2695 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2696 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2697 {
2698 struct radv_shader_module fs_m = {0};
2699 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2700 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2701 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2702 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2703 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2704 unsigned char hash[20], gs_copy_hash[20];
2705 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2706 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2707 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2708 device->keep_shader_info;
2709
2710 radv_start_feedback(pipeline_feedback);
2711
2712 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2713 if (pStages[i]) {
2714 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2715 if (modules[i]->nir)
2716 _mesa_sha1_compute(modules[i]->nir->info.name,
2717 strlen(modules[i]->nir->info.name),
2718 modules[i]->sha1);
2719
2720 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2721 }
2722 }
2723
2724 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2725 memcpy(gs_copy_hash, hash, 20);
2726 gs_copy_hash[0] ^= 1;
2727
2728 bool found_in_application_cache = true;
2729 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2730 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2731 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2732 &found_in_application_cache);
2733 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2734 }
2735
2736 if (!keep_executable_info && !keep_statistic_info &&
2737 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2738 &found_in_application_cache) &&
2739 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2740 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2741 return VK_SUCCESS;
2742 }
2743
2744 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2745 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2746 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2747 }
2748
2749 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2750 nir_builder fs_b;
2751 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2752 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2753 fs_m.nir = fs_b.shader;
2754 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2755 }
2756
2757 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2758 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2759 unsigned subgroup_size = 64, ballot_bit_size = 64;
2760
2761 if (!modules[i])
2762 continue;
2763
2764 radv_start_feedback(stage_feedbacks[i]);
2765
2766 if (key->compute_subgroup_size) {
2767 /* Only compute shaders currently support requiring a
2768 * specific subgroup size.
2769 */
2770 assert(i == MESA_SHADER_COMPUTE);
2771 subgroup_size = key->compute_subgroup_size;
2772 ballot_bit_size = key->compute_subgroup_size;
2773 }
2774
2775 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2776 stage ? stage->pName : "main", i,
2777 stage ? stage->pSpecializationInfo : NULL,
2778 flags, pipeline->layout,
2779 subgroup_size, ballot_bit_size);
2780
2781 /* We don't want to alter meta shaders IR directly so clone it
2782 * first.
2783 */
2784 if (nir[i]->info.name) {
2785 nir[i] = nir_shader_clone(NULL, nir[i]);
2786 }
2787
2788 radv_stop_feedback(stage_feedbacks[i], false);
2789 }
2790
2791 if (nir[MESA_SHADER_TESS_CTRL]) {
2792 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2793 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2794 }
2795
2796 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2797 radv_link_shaders(pipeline, nir);
2798
2799 radv_set_linked_driver_locations(pipeline, nir, infos);
2800
2801 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2802 if (nir[i]) {
2803 /* do this again since information such as outputs_read can be out-of-date */
2804 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2805
2806 if (device->physical_device->use_llvm) {
2807 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2808 } else {
2809 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2810 nir_lower_non_uniform_ubo_access |
2811 nir_lower_non_uniform_ssbo_access |
2812 nir_lower_non_uniform_texture_access |
2813 nir_lower_non_uniform_image_access);
2814 }
2815 }
2816 }
2817
2818 if (nir[MESA_SHADER_FRAGMENT])
2819 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2820
2821 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2822 if (radv_can_dump_shader(device, modules[i], false))
2823 nir_print_shader(nir[i], stderr);
2824 }
2825
2826 radv_fill_shader_keys(device, keys, key, nir);
2827
2828 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2829
2830 if ((nir[MESA_SHADER_VERTEX] &&
2831 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2832 (nir[MESA_SHADER_TESS_EVAL] &&
2833 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2834 struct gfx10_ngg_info *ngg_info;
2835
2836 if (nir[MESA_SHADER_GEOMETRY])
2837 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2838 else if (nir[MESA_SHADER_TESS_CTRL])
2839 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2840 else
2841 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2842
2843 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2844 } else if (nir[MESA_SHADER_GEOMETRY]) {
2845 struct gfx9_gs_info *gs_info =
2846 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2847
2848 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2849 }
2850
2851 if(modules[MESA_SHADER_GEOMETRY]) {
2852 struct radv_shader_binary *gs_copy_binary = NULL;
2853 if (!pipeline->gs_copy_shader &&
2854 !radv_pipeline_has_ngg(pipeline)) {
2855 struct radv_shader_info info = {};
2856 struct radv_shader_variant_key key = {};
2857
2858 key.has_multiview_view_index =
2859 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2860
2861 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2862 pipeline->layout, &key,
2863 &info, pipeline->device->physical_device->use_llvm);
2864 info.wave_size = 64; /* Wave32 not supported. */
2865 info.ballot_bit_size = 64;
2866
2867 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2868 device, nir[MESA_SHADER_GEOMETRY], &info,
2869 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2870 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2871 }
2872
2873 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2874 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2875 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2876
2877 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2878 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2879
2880 radv_pipeline_cache_insert_shaders(device, cache,
2881 gs_copy_hash,
2882 variants,
2883 binaries);
2884 }
2885 free(gs_copy_binary);
2886 }
2887
2888 if (nir[MESA_SHADER_FRAGMENT]) {
2889 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2890 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2891
2892 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2893 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2894 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2895 infos + MESA_SHADER_FRAGMENT,
2896 keep_executable_info, keep_statistic_info,
2897 &binaries[MESA_SHADER_FRAGMENT]);
2898
2899 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2900 }
2901 }
2902
2903 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2904 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2905 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2906 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2907 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2908
2909 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2910
2911 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2912 pipeline->layout,
2913 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2914 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2915
2916 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2917 }
2918 modules[MESA_SHADER_VERTEX] = NULL;
2919 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2920 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2921 }
2922
2923 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2924 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2925 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2926 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2927
2928 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2929
2930 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2931 pipeline->layout,
2932 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2933 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2934
2935 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2936 }
2937 modules[pre_stage] = NULL;
2938 }
2939
2940 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2941 if(modules[i] && !pipeline->shaders[i]) {
2942 if (i == MESA_SHADER_TESS_CTRL) {
2943 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2944 }
2945 if (i == MESA_SHADER_TESS_EVAL) {
2946 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2947 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2948 }
2949
2950 radv_start_feedback(stage_feedbacks[i]);
2951
2952 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2953 pipeline->layout,
2954 keys + i, infos + i, keep_executable_info,
2955 keep_statistic_info, &binaries[i]);
2956
2957 radv_stop_feedback(stage_feedbacks[i], false);
2958 }
2959 }
2960
2961 if (!keep_executable_info && !keep_statistic_info) {
2962 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2963 binaries);
2964 }
2965
2966 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2967 free(binaries[i]);
2968 if (nir[i]) {
2969 ralloc_free(nir[i]);
2970
2971 if (radv_can_dump_shader_stats(device, modules[i]))
2972 radv_shader_dump_stats(device,
2973 pipeline->shaders[i],
2974 i, stderr);
2975 }
2976 }
2977
2978 if (fs_m.nir)
2979 ralloc_free(fs_m.nir);
2980
2981 radv_stop_feedback(pipeline_feedback, false);
2982 return VK_SUCCESS;
2983 }
2984
2985 static uint32_t
2986 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2987 gl_shader_stage stage, enum chip_class chip_class)
2988 {
2989 bool has_gs = radv_pipeline_has_gs(pipeline);
2990 bool has_tess = radv_pipeline_has_tess(pipeline);
2991 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2992
2993 switch (stage) {
2994 case MESA_SHADER_FRAGMENT:
2995 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2996 case MESA_SHADER_VERTEX:
2997 if (has_tess) {
2998 if (chip_class >= GFX10) {
2999 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3000 } else if (chip_class == GFX9) {
3001 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3002 } else {
3003 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3004 }
3005
3006 }
3007
3008 if (has_gs) {
3009 if (chip_class >= GFX10) {
3010 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3011 } else {
3012 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3013 }
3014 }
3015
3016 if (has_ngg)
3017 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3018
3019 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3020 case MESA_SHADER_GEOMETRY:
3021 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3022 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3023 case MESA_SHADER_COMPUTE:
3024 return R_00B900_COMPUTE_USER_DATA_0;
3025 case MESA_SHADER_TESS_CTRL:
3026 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3027 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3028 case MESA_SHADER_TESS_EVAL:
3029 if (has_gs) {
3030 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3031 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3032 } else if (has_ngg) {
3033 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3034 } else {
3035 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3036 }
3037 default:
3038 unreachable("unknown shader");
3039 }
3040 }
3041
3042 struct radv_bin_size_entry {
3043 unsigned bpp;
3044 VkExtent2D extent;
3045 };
3046
3047 static VkExtent2D
3048 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3049 {
3050 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3051 {
3052 /* One RB / SE */
3053 {
3054 /* One shader engine */
3055 { 0, {128, 128}},
3056 { 1, { 64, 128}},
3057 { 2, { 32, 128}},
3058 { 3, { 16, 128}},
3059 { 17, { 0, 0}},
3060 { UINT_MAX, { 0, 0}},
3061 },
3062 {
3063 /* Two shader engines */
3064 { 0, {128, 128}},
3065 { 2, { 64, 128}},
3066 { 3, { 32, 128}},
3067 { 5, { 16, 128}},
3068 { 17, { 0, 0}},
3069 { UINT_MAX, { 0, 0}},
3070 },
3071 {
3072 /* Four shader engines */
3073 { 0, {128, 128}},
3074 { 3, { 64, 128}},
3075 { 5, { 16, 128}},
3076 { 17, { 0, 0}},
3077 { UINT_MAX, { 0, 0}},
3078 },
3079 },
3080 {
3081 /* Two RB / SE */
3082 {
3083 /* One shader engine */
3084 { 0, {128, 128}},
3085 { 2, { 64, 128}},
3086 { 3, { 32, 128}},
3087 { 5, { 16, 128}},
3088 { 33, { 0, 0}},
3089 { UINT_MAX, { 0, 0}},
3090 },
3091 {
3092 /* Two shader engines */
3093 { 0, {128, 128}},
3094 { 3, { 64, 128}},
3095 { 5, { 32, 128}},
3096 { 9, { 16, 128}},
3097 { 33, { 0, 0}},
3098 { UINT_MAX, { 0, 0}},
3099 },
3100 {
3101 /* Four shader engines */
3102 { 0, {256, 256}},
3103 { 2, {128, 256}},
3104 { 3, {128, 128}},
3105 { 5, { 64, 128}},
3106 { 9, { 16, 128}},
3107 { 33, { 0, 0}},
3108 { UINT_MAX, { 0, 0}},
3109 },
3110 },
3111 {
3112 /* Four RB / SE */
3113 {
3114 /* One shader engine */
3115 { 0, {128, 256}},
3116 { 2, {128, 128}},
3117 { 3, { 64, 128}},
3118 { 5, { 32, 128}},
3119 { 9, { 16, 128}},
3120 { 33, { 0, 0}},
3121 { UINT_MAX, { 0, 0}},
3122 },
3123 {
3124 /* Two shader engines */
3125 { 0, {256, 256}},
3126 { 2, {128, 256}},
3127 { 3, {128, 128}},
3128 { 5, { 64, 128}},
3129 { 9, { 32, 128}},
3130 { 17, { 16, 128}},
3131 { 33, { 0, 0}},
3132 { UINT_MAX, { 0, 0}},
3133 },
3134 {
3135 /* Four shader engines */
3136 { 0, {256, 512}},
3137 { 2, {256, 256}},
3138 { 3, {128, 256}},
3139 { 5, {128, 128}},
3140 { 9, { 64, 128}},
3141 { 17, { 16, 128}},
3142 { 33, { 0, 0}},
3143 { UINT_MAX, { 0, 0}},
3144 },
3145 },
3146 };
3147 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3148 {
3149 // One RB / SE
3150 {
3151 // One shader engine
3152 { 0, {128, 256}},
3153 { 2, {128, 128}},
3154 { 4, { 64, 128}},
3155 { 7, { 32, 128}},
3156 { 13, { 16, 128}},
3157 { 49, { 0, 0}},
3158 { UINT_MAX, { 0, 0}},
3159 },
3160 {
3161 // Two shader engines
3162 { 0, {256, 256}},
3163 { 2, {128, 256}},
3164 { 4, {128, 128}},
3165 { 7, { 64, 128}},
3166 { 13, { 32, 128}},
3167 { 25, { 16, 128}},
3168 { 49, { 0, 0}},
3169 { UINT_MAX, { 0, 0}},
3170 },
3171 {
3172 // Four shader engines
3173 { 0, {256, 512}},
3174 { 2, {256, 256}},
3175 { 4, {128, 256}},
3176 { 7, {128, 128}},
3177 { 13, { 64, 128}},
3178 { 25, { 16, 128}},
3179 { 49, { 0, 0}},
3180 { UINT_MAX, { 0, 0}},
3181 },
3182 },
3183 {
3184 // Two RB / SE
3185 {
3186 // One shader engine
3187 { 0, {256, 256}},
3188 { 2, {128, 256}},
3189 { 4, {128, 128}},
3190 { 7, { 64, 128}},
3191 { 13, { 32, 128}},
3192 { 25, { 16, 128}},
3193 { 97, { 0, 0}},
3194 { UINT_MAX, { 0, 0}},
3195 },
3196 {
3197 // Two shader engines
3198 { 0, {256, 512}},
3199 { 2, {256, 256}},
3200 { 4, {128, 256}},
3201 { 7, {128, 128}},
3202 { 13, { 64, 128}},
3203 { 25, { 32, 128}},
3204 { 49, { 16, 128}},
3205 { 97, { 0, 0}},
3206 { UINT_MAX, { 0, 0}},
3207 },
3208 {
3209 // Four shader engines
3210 { 0, {512, 512}},
3211 { 2, {256, 512}},
3212 { 4, {256, 256}},
3213 { 7, {128, 256}},
3214 { 13, {128, 128}},
3215 { 25, { 64, 128}},
3216 { 49, { 16, 128}},
3217 { 97, { 0, 0}},
3218 { UINT_MAX, { 0, 0}},
3219 },
3220 },
3221 {
3222 // Four RB / SE
3223 {
3224 // One shader engine
3225 { 0, {256, 512}},
3226 { 2, {256, 256}},
3227 { 4, {128, 256}},
3228 { 7, {128, 128}},
3229 { 13, { 64, 128}},
3230 { 25, { 32, 128}},
3231 { 49, { 16, 128}},
3232 { UINT_MAX, { 0, 0}},
3233 },
3234 {
3235 // Two shader engines
3236 { 0, {512, 512}},
3237 { 2, {256, 512}},
3238 { 4, {256, 256}},
3239 { 7, {128, 256}},
3240 { 13, {128, 128}},
3241 { 25, { 64, 128}},
3242 { 49, { 32, 128}},
3243 { 97, { 16, 128}},
3244 { UINT_MAX, { 0, 0}},
3245 },
3246 {
3247 // Four shader engines
3248 { 0, {512, 512}},
3249 { 4, {256, 512}},
3250 { 7, {256, 256}},
3251 { 13, {128, 256}},
3252 { 25, {128, 128}},
3253 { 49, { 64, 128}},
3254 { 97, { 16, 128}},
3255 { UINT_MAX, { 0, 0}},
3256 },
3257 },
3258 };
3259
3260 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3261 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3262 VkExtent2D extent = {512, 512};
3263
3264 unsigned log_num_rb_per_se =
3265 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3266 pipeline->device->physical_device->rad_info.max_se);
3267 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3268
3269 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3270 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3271 unsigned effective_samples = total_samples;
3272 unsigned color_bytes_per_pixel = 0;
3273
3274 const VkPipelineColorBlendStateCreateInfo *vkblend =
3275 radv_pipeline_get_color_blend_state(pCreateInfo);
3276 if (vkblend) {
3277 for (unsigned i = 0; i < subpass->color_count; i++) {
3278 if (!vkblend->pAttachments[i].colorWriteMask)
3279 continue;
3280
3281 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3282 continue;
3283
3284 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3285 color_bytes_per_pixel += vk_format_get_blocksize(format);
3286 }
3287
3288 /* MSAA images typically don't use all samples all the time. */
3289 if (effective_samples >= 2 && ps_iter_samples <= 1)
3290 effective_samples = 2;
3291 color_bytes_per_pixel *= effective_samples;
3292 }
3293
3294 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3295 while(color_entry[1].bpp <= color_bytes_per_pixel)
3296 ++color_entry;
3297
3298 extent = color_entry->extent;
3299
3300 if (subpass->depth_stencil_attachment) {
3301 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3302
3303 /* Coefficients taken from AMDVLK */
3304 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3305 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3306 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3307
3308 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3309 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3310 ++ds_entry;
3311
3312 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3313 extent = ds_entry->extent;
3314 }
3315
3316 return extent;
3317 }
3318
3319 static VkExtent2D
3320 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3321 {
3322 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3323 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3324 VkExtent2D extent = {512, 512};
3325
3326 const unsigned db_tag_size = 64;
3327 const unsigned db_tag_count = 312;
3328 const unsigned color_tag_size = 1024;
3329 const unsigned color_tag_count = 31;
3330 const unsigned fmask_tag_size = 256;
3331 const unsigned fmask_tag_count = 44;
3332
3333 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3334 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3335
3336 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3337 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3338 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3339
3340 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3341 const unsigned samples_log = util_logbase2_ceil(total_samples);
3342
3343 unsigned color_bytes_per_pixel = 0;
3344 unsigned fmask_bytes_per_pixel = 0;
3345
3346 const VkPipelineColorBlendStateCreateInfo *vkblend =
3347 radv_pipeline_get_color_blend_state(pCreateInfo);
3348 if (vkblend) {
3349 for (unsigned i = 0; i < subpass->color_count; i++) {
3350 if (!vkblend->pAttachments[i].colorWriteMask)
3351 continue;
3352
3353 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3354 continue;
3355
3356 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3357 color_bytes_per_pixel += vk_format_get_blocksize(format);
3358
3359 if (total_samples > 1) {
3360 assert(samples_log <= 3);
3361 const unsigned fmask_array[] = {0, 1, 1, 4};
3362 fmask_bytes_per_pixel += fmask_array[samples_log];
3363 }
3364 }
3365
3366 color_bytes_per_pixel *= total_samples;
3367 }
3368 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3369
3370 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3371 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3372 extent.height = 1ull << (color_pixel_count_log / 2);
3373
3374 if (fmask_bytes_per_pixel) {
3375 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3376
3377 const VkExtent2D fmask_extent = (VkExtent2D){
3378 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3379 .height = 1ull << (color_pixel_count_log / 2)
3380 };
3381
3382 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3383 extent = fmask_extent;
3384 }
3385
3386 if (subpass->depth_stencil_attachment) {
3387 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3388
3389 /* Coefficients taken from AMDVLK */
3390 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3391 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3392 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3393
3394 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3395
3396 const VkExtent2D db_extent = (VkExtent2D){
3397 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3398 .height = 1ull << (color_pixel_count_log / 2)
3399 };
3400
3401 if (db_extent.width * db_extent.height < extent.width * extent.height)
3402 extent = db_extent;
3403 }
3404
3405 extent.width = MAX2(extent.width, 128);
3406 extent.height = MAX2(extent.width, 64);
3407
3408 return extent;
3409 }
3410
3411 static void
3412 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3413 struct radv_pipeline *pipeline,
3414 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3415 {
3416 uint32_t pa_sc_binner_cntl_0 =
3417 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3418 S_028C44_DISABLE_START_OF_PRIM(1);
3419 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3420
3421 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3422 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3423 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3424 const VkPipelineColorBlendStateCreateInfo *vkblend =
3425 radv_pipeline_get_color_blend_state(pCreateInfo);
3426 unsigned min_bytes_per_pixel = 0;
3427
3428 if (vkblend) {
3429 for (unsigned i = 0; i < subpass->color_count; i++) {
3430 if (!vkblend->pAttachments[i].colorWriteMask)
3431 continue;
3432
3433 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3434 continue;
3435
3436 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3437 unsigned bytes = vk_format_get_blocksize(format);
3438 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3439 min_bytes_per_pixel = bytes;
3440 }
3441 }
3442
3443 pa_sc_binner_cntl_0 =
3444 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3445 S_028C44_BIN_SIZE_X(0) |
3446 S_028C44_BIN_SIZE_Y(0) |
3447 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3448 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3449 S_028C44_DISABLE_START_OF_PRIM(1);
3450 }
3451
3452 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3453 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3454 }
3455
3456 struct radv_binning_settings
3457 radv_get_binning_settings(const struct radv_physical_device *pdev)
3458 {
3459 struct radv_binning_settings settings;
3460 if (pdev->rad_info.has_dedicated_vram) {
3461 if (pdev->rad_info.num_render_backends > 4) {
3462 settings.context_states_per_bin = 1;
3463 settings.persistent_states_per_bin = 1;
3464 } else {
3465 settings.context_states_per_bin = 3;
3466 settings.persistent_states_per_bin = 8;
3467 }
3468 settings.fpovs_per_batch = 63;
3469 } else {
3470 /* The context states are affected by the scissor bug. */
3471 settings.context_states_per_bin = 6;
3472 /* 32 causes hangs for RAVEN. */
3473 settings.persistent_states_per_bin = 16;
3474 settings.fpovs_per_batch = 63;
3475 }
3476
3477 if (pdev->rad_info.has_gfx9_scissor_bug)
3478 settings.context_states_per_bin = 1;
3479
3480 return settings;
3481 }
3482
3483 static void
3484 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3485 struct radv_pipeline *pipeline,
3486 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3487 const struct radv_blend_state *blend)
3488 {
3489 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3490 return;
3491
3492 VkExtent2D bin_size;
3493 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3494 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3495 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3496 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3497 } else
3498 unreachable("Unhandled generation for binning bin size calculation");
3499
3500 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3501 struct radv_binning_settings settings =
3502 radv_get_binning_settings(pipeline->device->physical_device);
3503
3504 bool disable_start_of_prim = true;
3505 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3506
3507 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3508
3509 if (pipeline->device->dfsm_allowed && ps &&
3510 !ps->info.ps.can_discard &&
3511 !ps->info.ps.writes_memory &&
3512 blend->cb_target_enabled_4bit) {
3513 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3514 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3515 }
3516
3517 const uint32_t pa_sc_binner_cntl_0 =
3518 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3519 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3520 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3521 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3522 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3523 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3524 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3525 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3526 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3527 S_028C44_OPTIMAL_BIN_SELECTION(1);
3528
3529 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3530 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3531 } else
3532 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3533 }
3534
3535
3536 static void
3537 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3538 struct radv_pipeline *pipeline,
3539 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3540 const struct radv_graphics_pipeline_create_info *extra)
3541 {
3542 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3543 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3544 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3545 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3546 struct radv_render_pass_attachment *attachment = NULL;
3547 uint32_t db_depth_control = 0, db_stencil_control = 0;
3548 uint32_t db_render_control = 0, db_render_override2 = 0;
3549 uint32_t db_render_override = 0;
3550
3551 if (subpass->depth_stencil_attachment)
3552 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3553
3554 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3555 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3556
3557 if (vkds && has_depth_attachment) {
3558 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3559 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3560 S_028800_ZFUNC(vkds->depthCompareOp) |
3561 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3562
3563 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3564 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3565
3566 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3567 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3568 }
3569
3570 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3571 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3572 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3573 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3574 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3575 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3576
3577 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3578 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3579 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3580 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3581 }
3582
3583 if (attachment && extra) {
3584 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3585 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3586
3587 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3588 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3589 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3590 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3591 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3592 }
3593
3594 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3595 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3596
3597 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3598 ps->info.ps.writes_z) {
3599 /* From VK_EXT_depth_range_unrestricted spec:
3600 *
3601 * "The behavior described in Primitive Clipping still applies.
3602 * If depth clamping is disabled the depth values are still
3603 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3604 * depth clamping is enabled the above equation is ignored and
3605 * the depth values are instead clamped to the VkViewport
3606 * minDepth and maxDepth values, which in the case of this
3607 * extension can be outside of the 0.0 to 1.0 range."
3608 */
3609 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3610 }
3611
3612 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3613 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3614
3615 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3616 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3617 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3618 }
3619
3620 static void
3621 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3622 struct radv_pipeline *pipeline,
3623 const struct radv_blend_state *blend)
3624 {
3625 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3626 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3627 8);
3628 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3629 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3630
3631 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3632
3633 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3634 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3635 }
3636
3637 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3638
3639 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3640 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3641
3642 pipeline->graphics.col_format = blend->spi_shader_col_format;
3643 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3644 }
3645
3646 static const VkConservativeRasterizationModeEXT
3647 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3648 {
3649 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3650 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3651
3652 if (!conservative_raster)
3653 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3654 return conservative_raster->conservativeRasterizationMode;
3655 }
3656
3657 static void
3658 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3659 struct radv_pipeline *pipeline,
3660 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3661 {
3662 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3663 const VkConservativeRasterizationModeEXT mode =
3664 radv_get_conservative_raster_mode(vkraster);
3665 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3666 bool depth_clip_disable = vkraster->depthClampEnable;
3667
3668 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3669 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3670 if (depth_clip_state) {
3671 depth_clip_disable = !depth_clip_state->depthClipEnable;
3672 }
3673
3674 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3675 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3676 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3677 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3678 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3679 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3680
3681 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3682 S_0286D4_FLAT_SHADE_ENA(1) |
3683 S_0286D4_PNT_SPRITE_ENA(1) |
3684 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3685 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3686 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3687 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3688 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3689
3690 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3691 S_028BE4_PIX_CENTER(1) | // TODO verify
3692 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3693 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3694
3695 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3696 S_028814_FACE(vkraster->frontFace) |
3697 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3698 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3699 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3700 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3701 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3702 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3703 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3704 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3705
3706 /* Conservative rasterization. */
3707 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3708 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3709
3710 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3711 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3712 S_028804_OVERRASTERIZATION_AMOUNT(4);
3713
3714 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3715 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3716 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3717
3718 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3719 pa_sc_conservative_rast |=
3720 S_028C4C_OVER_RAST_ENABLE(1) |
3721 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3722 S_028C4C_UNDER_RAST_ENABLE(0) |
3723 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3724 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3725 } else {
3726 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3727 pa_sc_conservative_rast |=
3728 S_028C4C_OVER_RAST_ENABLE(0) |
3729 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3730 S_028C4C_UNDER_RAST_ENABLE(1) |
3731 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3732 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3733 }
3734 }
3735
3736 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3737 pa_sc_conservative_rast);
3738 }
3739
3740
3741 static void
3742 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3743 struct radv_pipeline *pipeline)
3744 {
3745 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3746
3747 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3748 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3749 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3750
3751 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3752 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3753 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3754 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3755 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3756
3757 /* The exclusion bits can be set to improve rasterization efficiency
3758 * if no sample lies on the pixel boundary (-8 sample offset). It's
3759 * currently always TRUE because the driver doesn't support 16 samples.
3760 */
3761 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3762 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3763 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3764 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3765
3766 /* GFX9: Flush DFSM when the AA mode changes. */
3767 if (pipeline->device->dfsm_allowed) {
3768 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3769 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3770 }
3771 }
3772
3773 static void
3774 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3775 struct radv_pipeline *pipeline)
3776 {
3777 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3778 const struct radv_shader_variant *vs =
3779 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3780 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3781 pipeline->shaders[MESA_SHADER_VERTEX];
3782 unsigned vgt_primitiveid_en = 0;
3783 uint32_t vgt_gs_mode = 0;
3784
3785 if (radv_pipeline_has_ngg(pipeline))
3786 return;
3787
3788 if (radv_pipeline_has_gs(pipeline)) {
3789 const struct radv_shader_variant *gs =
3790 pipeline->shaders[MESA_SHADER_GEOMETRY];
3791
3792 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3793 pipeline->device->physical_device->rad_info.chip_class);
3794 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3795 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3796 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3797 }
3798
3799 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3800 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3801 }
3802
3803 static void
3804 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3805 struct radeon_cmdbuf *cs,
3806 struct radv_pipeline *pipeline,
3807 struct radv_shader_variant *shader)
3808 {
3809 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3810
3811 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3812 radeon_emit(cs, va >> 8);
3813 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3814 radeon_emit(cs, shader->config.rsrc1);
3815 radeon_emit(cs, shader->config.rsrc2);
3816
3817 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3818 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3819 clip_dist_mask = outinfo->clip_dist_mask;
3820 cull_dist_mask = outinfo->cull_dist_mask;
3821 total_mask = clip_dist_mask | cull_dist_mask;
3822 bool misc_vec_ena = outinfo->writes_pointsize ||
3823 outinfo->writes_layer ||
3824 outinfo->writes_viewport_index;
3825 unsigned spi_vs_out_config, nparams;
3826
3827 /* VS is required to export at least one param. */
3828 nparams = MAX2(outinfo->param_exports, 1);
3829 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3830
3831 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3832 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3833 }
3834
3835 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3836
3837 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3838 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3839 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3840 V_02870C_SPI_SHADER_4COMP :
3841 V_02870C_SPI_SHADER_NONE) |
3842 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3843 V_02870C_SPI_SHADER_4COMP :
3844 V_02870C_SPI_SHADER_NONE) |
3845 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3846 V_02870C_SPI_SHADER_4COMP :
3847 V_02870C_SPI_SHADER_NONE));
3848
3849 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3850 S_028818_VTX_W0_FMT(1) |
3851 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3852 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3853 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3854
3855 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3856 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3857 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3858 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3859 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3860 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3861 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3862 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3863 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3864 cull_dist_mask << 8 |
3865 clip_dist_mask);
3866
3867 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3868 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3869 outinfo->writes_viewport_index);
3870 }
3871
3872 static void
3873 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3874 struct radv_pipeline *pipeline,
3875 struct radv_shader_variant *shader)
3876 {
3877 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3878
3879 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3880 radeon_emit(cs, va >> 8);
3881 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3882 radeon_emit(cs, shader->config.rsrc1);
3883 radeon_emit(cs, shader->config.rsrc2);
3884 }
3885
3886 static void
3887 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3888 struct radv_pipeline *pipeline,
3889 struct radv_shader_variant *shader,
3890 const struct radv_tessellation_state *tess)
3891 {
3892 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3893 uint32_t rsrc2 = shader->config.rsrc2;
3894
3895 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3896 radeon_emit(cs, va >> 8);
3897 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3898
3899 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3900 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3901 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3902 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3903
3904 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3905 radeon_emit(cs, shader->config.rsrc1);
3906 radeon_emit(cs, rsrc2);
3907 }
3908
3909 static void
3910 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3911 struct radeon_cmdbuf *cs,
3912 struct radv_pipeline *pipeline,
3913 struct radv_shader_variant *shader)
3914 {
3915 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3916 gl_shader_stage es_type =
3917 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3918 struct radv_shader_variant *es =
3919 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3920 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3921
3922 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3923 radeon_emit(cs, va >> 8);
3924 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3925 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3926 radeon_emit(cs, shader->config.rsrc1);
3927 radeon_emit(cs, shader->config.rsrc2);
3928
3929 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3930 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3931 clip_dist_mask = outinfo->clip_dist_mask;
3932 cull_dist_mask = outinfo->cull_dist_mask;
3933 total_mask = clip_dist_mask | cull_dist_mask;
3934 bool misc_vec_ena = outinfo->writes_pointsize ||
3935 outinfo->writes_layer ||
3936 outinfo->writes_viewport_index;
3937 bool es_enable_prim_id = outinfo->export_prim_id ||
3938 (es && es->info.uses_prim_id);
3939 bool break_wave_at_eoi = false;
3940 unsigned ge_cntl;
3941 unsigned nparams;
3942
3943 if (es_type == MESA_SHADER_TESS_EVAL) {
3944 struct radv_shader_variant *gs =
3945 pipeline->shaders[MESA_SHADER_GEOMETRY];
3946
3947 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3948 break_wave_at_eoi = true;
3949 }
3950
3951 nparams = MAX2(outinfo->param_exports, 1);
3952 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3953 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3954 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3955
3956 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3957 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3958 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3959 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3960 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3961 V_02870C_SPI_SHADER_4COMP :
3962 V_02870C_SPI_SHADER_NONE) |
3963 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3964 V_02870C_SPI_SHADER_4COMP :
3965 V_02870C_SPI_SHADER_NONE) |
3966 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3967 V_02870C_SPI_SHADER_4COMP :
3968 V_02870C_SPI_SHADER_NONE));
3969
3970 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3971 S_028818_VTX_W0_FMT(1) |
3972 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3973 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3974 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3975 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3976 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3977 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3978 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3979 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3980 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3981 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3982 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3983 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3984 cull_dist_mask << 8 |
3985 clip_dist_mask);
3986
3987 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3988 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3989 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
3990
3991 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3992 ngg_state->vgt_esgs_ring_itemsize);
3993
3994 /* NGG specific registers. */
3995 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3996 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3997
3998 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3999 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4000 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4001 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4002 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4003 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4004 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4005 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4006 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4007 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4008 S_028B90_CNT(gs_num_invocations) |
4009 S_028B90_ENABLE(gs_num_invocations > 1) |
4010 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4011
4012 /* User edge flags are set by the pos exports. If user edge flags are
4013 * not used, we must use hw-generated edge flags and pass them via
4014 * the prim export to prevent drawing lines on internal edges of
4015 * decomposed primitives (such as quads) with polygon mode = lines.
4016 *
4017 * TODO: We should combine hw-generated edge flags with user edge
4018 * flags in the shader.
4019 */
4020 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4021 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4022 !radv_pipeline_has_gs(pipeline)) |
4023 /* Reuse for NGG. */
4024 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4025
4026 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4027 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4028 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4029
4030 /* Bug workaround for a possible hang with non-tessellation cases.
4031 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4032 *
4033 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4034 */
4035 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4036 !radv_pipeline_has_tess(pipeline) &&
4037 ngg_state->hw_max_esverts != 256) {
4038 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4039
4040 if (ngg_state->hw_max_esverts > 5) {
4041 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4042 }
4043 }
4044
4045 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4046 }
4047
4048 static void
4049 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4050 struct radv_pipeline *pipeline,
4051 struct radv_shader_variant *shader,
4052 const struct radv_tessellation_state *tess)
4053 {
4054 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4055
4056 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4057 unsigned hs_rsrc2 = shader->config.rsrc2;
4058
4059 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4060 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4061 } else {
4062 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4063 }
4064
4065 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4066 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4067 radeon_emit(cs, va >> 8);
4068 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4069 } else {
4070 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4071 radeon_emit(cs, va >> 8);
4072 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4073 }
4074
4075 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4076 radeon_emit(cs, shader->config.rsrc1);
4077 radeon_emit(cs, hs_rsrc2);
4078 } else {
4079 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4080 radeon_emit(cs, va >> 8);
4081 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4082 radeon_emit(cs, shader->config.rsrc1);
4083 radeon_emit(cs, shader->config.rsrc2);
4084 }
4085 }
4086
4087 static void
4088 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4089 struct radeon_cmdbuf *cs,
4090 struct radv_pipeline *pipeline,
4091 const struct radv_tessellation_state *tess)
4092 {
4093 struct radv_shader_variant *vs;
4094
4095 /* Skip shaders merged into HS/GS */
4096 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4097 if (!vs)
4098 return;
4099
4100 if (vs->info.vs.as_ls)
4101 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4102 else if (vs->info.vs.as_es)
4103 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4104 else if (vs->info.is_ngg)
4105 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4106 else
4107 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4108 }
4109
4110 static void
4111 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4112 struct radeon_cmdbuf *cs,
4113 struct radv_pipeline *pipeline,
4114 const struct radv_tessellation_state *tess)
4115 {
4116 if (!radv_pipeline_has_tess(pipeline))
4117 return;
4118
4119 struct radv_shader_variant *tes, *tcs;
4120
4121 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4122 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4123
4124 if (tes) {
4125 if (tes->info.is_ngg) {
4126 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4127 } else if (tes->info.tes.as_es)
4128 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4129 else
4130 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4131 }
4132
4133 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4134
4135 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4136 tess->tf_param);
4137
4138 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4139 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4140 tess->ls_hs_config);
4141 else
4142 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4143 tess->ls_hs_config);
4144
4145 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4146 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4147 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4148 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4149 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4150 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4151 }
4152 }
4153
4154 static void
4155 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4156 struct radeon_cmdbuf *cs,
4157 struct radv_pipeline *pipeline,
4158 struct radv_shader_variant *gs)
4159 {
4160 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4161 unsigned gs_max_out_vertices;
4162 uint8_t *num_components;
4163 uint8_t max_stream;
4164 unsigned offset;
4165 uint64_t va;
4166
4167 gs_max_out_vertices = gs->info.gs.vertices_out;
4168 max_stream = gs->info.gs.max_stream;
4169 num_components = gs->info.gs.num_stream_output_components;
4170
4171 offset = num_components[0] * gs_max_out_vertices;
4172
4173 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4174 radeon_emit(ctx_cs, offset);
4175 if (max_stream >= 1)
4176 offset += num_components[1] * gs_max_out_vertices;
4177 radeon_emit(ctx_cs, offset);
4178 if (max_stream >= 2)
4179 offset += num_components[2] * gs_max_out_vertices;
4180 radeon_emit(ctx_cs, offset);
4181 if (max_stream >= 3)
4182 offset += num_components[3] * gs_max_out_vertices;
4183 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4184
4185 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4186 radeon_emit(ctx_cs, num_components[0]);
4187 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4188 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4189 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4190
4191 uint32_t gs_num_invocations = gs->info.gs.invocations;
4192 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4193 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4194 S_028B90_ENABLE(gs_num_invocations > 0));
4195
4196 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4197 gs_state->vgt_esgs_ring_itemsize);
4198
4199 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4200
4201 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4202 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4203 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4204 radeon_emit(cs, va >> 8);
4205 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4206 } else {
4207 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4208 radeon_emit(cs, va >> 8);
4209 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4210 }
4211
4212 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4213 radeon_emit(cs, gs->config.rsrc1);
4214 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4215
4216 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4217 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4218 } else {
4219 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4220 radeon_emit(cs, va >> 8);
4221 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4222 radeon_emit(cs, gs->config.rsrc1);
4223 radeon_emit(cs, gs->config.rsrc2);
4224 }
4225
4226 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4227 }
4228
4229 static void
4230 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4231 struct radeon_cmdbuf *cs,
4232 struct radv_pipeline *pipeline)
4233 {
4234 struct radv_shader_variant *gs;
4235
4236 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4237 if (!gs)
4238 return;
4239
4240 if (gs->info.is_ngg)
4241 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4242 else
4243 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4244
4245 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4246 gs->info.gs.vertices_out);
4247 }
4248
4249 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4250 bool explicit, bool float16)
4251 {
4252 uint32_t ps_input_cntl;
4253 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4254 ps_input_cntl = S_028644_OFFSET(offset);
4255 if (flat_shade || explicit)
4256 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4257 if (explicit) {
4258 /* Force parameter cache to be read in passthrough
4259 * mode.
4260 */
4261 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4262 }
4263 if (float16) {
4264 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4265 S_028644_ATTR0_VALID(1);
4266 }
4267 } else {
4268 /* The input is a DEFAULT_VAL constant. */
4269 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4270 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4271 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4272 ps_input_cntl = S_028644_OFFSET(0x20) |
4273 S_028644_DEFAULT_VAL(offset);
4274 }
4275 return ps_input_cntl;
4276 }
4277
4278 static void
4279 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4280 struct radv_pipeline *pipeline)
4281 {
4282 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4283 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4284 uint32_t ps_input_cntl[32];
4285
4286 unsigned ps_offset = 0;
4287
4288 if (ps->info.ps.prim_id_input) {
4289 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4290 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4291 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4292 ++ps_offset;
4293 }
4294 }
4295
4296 if (ps->info.ps.layer_input ||
4297 ps->info.needs_multiview_view_index) {
4298 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4299 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4300 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4301 else
4302 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4303 ++ps_offset;
4304 }
4305
4306 if (ps->info.ps.viewport_index_input) {
4307 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4308 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4309 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4310 else
4311 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4312 ++ps_offset;
4313 }
4314
4315 if (ps->info.ps.has_pcoord) {
4316 unsigned val;
4317 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4318 ps_input_cntl[ps_offset] = val;
4319 ps_offset++;
4320 }
4321
4322 if (ps->info.ps.num_input_clips_culls) {
4323 unsigned vs_offset;
4324
4325 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4326 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4327 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4328 ++ps_offset;
4329 }
4330
4331 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4332 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4333 ps->info.ps.num_input_clips_culls > 4) {
4334 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4335 ++ps_offset;
4336 }
4337 }
4338
4339 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4340 unsigned vs_offset;
4341 bool flat_shade;
4342 bool explicit;
4343 bool float16;
4344 if (!(ps->info.ps.input_mask & (1u << i)))
4345 continue;
4346
4347 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4348 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4349 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4350 ++ps_offset;
4351 continue;
4352 }
4353
4354 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4355 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4356 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4357
4358 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4359 ++ps_offset;
4360 }
4361
4362 if (ps_offset) {
4363 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4364 for (unsigned i = 0; i < ps_offset; i++) {
4365 radeon_emit(ctx_cs, ps_input_cntl[i]);
4366 }
4367 }
4368 }
4369
4370 static uint32_t
4371 radv_compute_db_shader_control(const struct radv_device *device,
4372 const struct radv_pipeline *pipeline,
4373 const struct radv_shader_variant *ps)
4374 {
4375 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4376 unsigned z_order;
4377 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4378 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4379 else
4380 z_order = V_02880C_LATE_Z;
4381
4382 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4383 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4384 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4385 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4386
4387 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4388 !device->physical_device->rad_info.rbplus_allowed;
4389
4390 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4391 * but this appears to break Project Cars (DXVK). See
4392 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4393 */
4394 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4395
4396 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4397 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4398 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4399 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4400 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4401 S_02880C_Z_ORDER(z_order) |
4402 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4403 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4404 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4405 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4406 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4407 }
4408
4409 static void
4410 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4411 struct radeon_cmdbuf *cs,
4412 struct radv_pipeline *pipeline)
4413 {
4414 struct radv_shader_variant *ps;
4415 uint64_t va;
4416 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4417
4418 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4419 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4420
4421 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4422 radeon_emit(cs, va >> 8);
4423 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4424 radeon_emit(cs, ps->config.rsrc1);
4425 radeon_emit(cs, ps->config.rsrc2);
4426
4427 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4428 radv_compute_db_shader_control(pipeline->device,
4429 pipeline, ps));
4430
4431 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4432 ps->config.spi_ps_input_ena);
4433
4434 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4435 ps->config.spi_ps_input_addr);
4436
4437 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4438 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4439 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4440
4441 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4442
4443 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4444 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4445 ps->info.ps.writes_stencil,
4446 ps->info.ps.writes_sample_mask));
4447
4448 if (pipeline->device->dfsm_allowed) {
4449 /* optimise this? */
4450 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4451 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4452 }
4453 }
4454
4455 static void
4456 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4457 struct radv_pipeline *pipeline)
4458 {
4459 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4460 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4461 return;
4462
4463 unsigned vtx_reuse_depth = 30;
4464 if (radv_pipeline_has_tess(pipeline) &&
4465 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4466 vtx_reuse_depth = 14;
4467 }
4468 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4469 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4470 }
4471
4472 static uint32_t
4473 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4474 {
4475 uint32_t stages = 0;
4476 if (radv_pipeline_has_tess(pipeline)) {
4477 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4478 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4479
4480 if (radv_pipeline_has_gs(pipeline))
4481 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4482 S_028B54_GS_EN(1);
4483 else if (radv_pipeline_has_ngg(pipeline))
4484 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4485 else
4486 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4487 } else if (radv_pipeline_has_gs(pipeline)) {
4488 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4489 S_028B54_GS_EN(1);
4490 } else if (radv_pipeline_has_ngg(pipeline)) {
4491 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4492 }
4493
4494 if (radv_pipeline_has_ngg(pipeline)) {
4495 stages |= S_028B54_PRIMGEN_EN(1);
4496 if (pipeline->streamout_shader)
4497 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4498 if (radv_pipeline_has_ngg_passthrough(pipeline))
4499 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4500 } else if (radv_pipeline_has_gs(pipeline)) {
4501 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4502 }
4503
4504 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4505 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4506
4507 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4508 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4509
4510 if (radv_pipeline_has_tess(pipeline))
4511 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4512
4513 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4514 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4515 if (pipeline->gs_copy_shader)
4516 vs_size = pipeline->gs_copy_shader->info.wave_size;
4517 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4518 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4519 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4520 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4521
4522 if (radv_pipeline_has_ngg(pipeline))
4523 gs_size = vs_size;
4524
4525 /* legacy GS only supports Wave64 */
4526 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4527 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4528 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4529 }
4530
4531 return stages;
4532 }
4533
4534 static uint32_t
4535 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4536 {
4537 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4538 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4539
4540 if (!discard_rectangle_info)
4541 return 0xffff;
4542
4543 unsigned mask = 0;
4544
4545 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4546 /* Interpret i as a bitmask, and then set the bit in the mask if
4547 * that combination of rectangles in which the pixel is contained
4548 * should pass the cliprect test. */
4549 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4550
4551 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4552 !relevant_subset)
4553 continue;
4554
4555 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4556 relevant_subset)
4557 continue;
4558
4559 mask |= 1u << i;
4560 }
4561
4562 return mask;
4563 }
4564
4565 static void
4566 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4567 struct radv_pipeline *pipeline,
4568 const struct radv_tessellation_state *tess)
4569 {
4570 bool break_wave_at_eoi = false;
4571 unsigned primgroup_size;
4572 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4573
4574 if (radv_pipeline_has_tess(pipeline)) {
4575 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4576 } else if (radv_pipeline_has_gs(pipeline)) {
4577 const struct gfx9_gs_info *gs_state =
4578 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4579 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4580 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4581 } else {
4582 primgroup_size = 128; /* recommended without a GS and tess */
4583 }
4584
4585 if (radv_pipeline_has_tess(pipeline)) {
4586 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4587 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4588 break_wave_at_eoi = true;
4589 }
4590
4591 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4592 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4593 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4594 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4595 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4596 }
4597
4598 static void
4599 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4600 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4601 const struct radv_graphics_pipeline_create_info *extra,
4602 const struct radv_blend_state *blend,
4603 const struct radv_tessellation_state *tess,
4604 unsigned prim, unsigned gs_out)
4605 {
4606 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4607 struct radeon_cmdbuf *cs = &pipeline->cs;
4608
4609 cs->max_dw = 64;
4610 ctx_cs->max_dw = 256;
4611 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4612 ctx_cs->buf = cs->buf + cs->max_dw;
4613
4614 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4615 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4616 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4617 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4618 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4619 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4620 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4621 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4622 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4623 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4624 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4625 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4626
4627 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4628 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4629
4630 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4631
4632 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4633 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4634 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4635 } else {
4636 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4637 }
4638 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4639
4640 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4641
4642 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4643
4644 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4645 assert(cs->cdw <= cs->max_dw);
4646 }
4647
4648 static struct radv_ia_multi_vgt_param_helpers
4649 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4650 const struct radv_tessellation_state *tess)
4651 {
4652 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4653 const struct radv_device *device = pipeline->device;
4654
4655 if (radv_pipeline_has_tess(pipeline))
4656 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4657 else if (radv_pipeline_has_gs(pipeline))
4658 ia_multi_vgt_param.primgroup_size = 64;
4659 else
4660 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4661
4662 /* GS requirement. */
4663 ia_multi_vgt_param.partial_es_wave = false;
4664 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4665 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4666 ia_multi_vgt_param.partial_es_wave = true;
4667
4668 ia_multi_vgt_param.ia_switch_on_eoi = false;
4669 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4670 ia_multi_vgt_param.ia_switch_on_eoi = true;
4671 if (radv_pipeline_has_gs(pipeline) &&
4672 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4673 ia_multi_vgt_param.ia_switch_on_eoi = true;
4674 if (radv_pipeline_has_tess(pipeline)) {
4675 /* SWITCH_ON_EOI must be set if PrimID is used. */
4676 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4677 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4678 ia_multi_vgt_param.ia_switch_on_eoi = true;
4679 }
4680
4681 ia_multi_vgt_param.partial_vs_wave = false;
4682 if (radv_pipeline_has_tess(pipeline)) {
4683 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4684 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4685 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4686 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4687 radv_pipeline_has_gs(pipeline))
4688 ia_multi_vgt_param.partial_vs_wave = true;
4689 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4690 if (device->physical_device->rad_info.has_distributed_tess) {
4691 if (radv_pipeline_has_gs(pipeline)) {
4692 if (device->physical_device->rad_info.chip_class <= GFX8)
4693 ia_multi_vgt_param.partial_es_wave = true;
4694 } else {
4695 ia_multi_vgt_param.partial_vs_wave = true;
4696 }
4697 }
4698 }
4699
4700 if (radv_pipeline_has_gs(pipeline)) {
4701 /* On these chips there is the possibility of a hang if the
4702 * pipeline uses a GS and partial_vs_wave is not set.
4703 *
4704 * This mostly does not hit 4-SE chips, as those typically set
4705 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4706 * with GS due to another workaround.
4707 *
4708 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4709 */
4710 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4711 device->physical_device->rad_info.family == CHIP_FIJI ||
4712 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4713 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4714 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4715 device->physical_device->rad_info.family == CHIP_VEGAM) {
4716 ia_multi_vgt_param.partial_vs_wave = true;
4717 }
4718 }
4719
4720 ia_multi_vgt_param.base =
4721 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4722 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4723 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4724 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4725 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4726
4727 return ia_multi_vgt_param;
4728 }
4729
4730
4731 static void
4732 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4733 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4734 {
4735 const VkPipelineVertexInputStateCreateInfo *vi_info =
4736 pCreateInfo->pVertexInputState;
4737 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4738
4739 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4740 const VkVertexInputAttributeDescription *desc =
4741 &vi_info->pVertexAttributeDescriptions[i];
4742 unsigned loc = desc->location;
4743 const struct vk_format_description *format_desc;
4744
4745 format_desc = vk_format_description(desc->format);
4746
4747 velems->format_size[loc] = format_desc->block.bits / 8;
4748 }
4749
4750 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4751 const VkVertexInputBindingDescription *desc =
4752 &vi_info->pVertexBindingDescriptions[i];
4753
4754 pipeline->binding_stride[desc->binding] = desc->stride;
4755 pipeline->num_vertex_bindings =
4756 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4757 }
4758 }
4759
4760 static struct radv_shader_variant *
4761 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4762 {
4763 int i;
4764
4765 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4766 struct radv_shader_variant *shader =
4767 radv_get_shader(pipeline, i);
4768
4769 if (shader && shader->info.so.num_outputs > 0)
4770 return shader;
4771 }
4772
4773 return NULL;
4774 }
4775
4776 static VkResult
4777 radv_secure_compile(struct radv_pipeline *pipeline,
4778 struct radv_device *device,
4779 const struct radv_pipeline_key *key,
4780 const VkPipelineShaderStageCreateInfo **pStages,
4781 const VkPipelineCreateFlags flags,
4782 unsigned num_stages)
4783 {
4784 uint8_t allowed_pipeline_hashes[2][20];
4785 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4786 pipeline->layout, key, get_hash_flags(device));
4787
4788 /* Generate the GC copy hash */
4789 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4790 allowed_pipeline_hashes[1][0] ^= 1;
4791
4792 uint8_t allowed_hashes[2][20];
4793 for (unsigned i = 0; i < 2; ++i) {
4794 disk_cache_compute_key(device->physical_device->disk_cache,
4795 allowed_pipeline_hashes[i], 20,
4796 allowed_hashes[i]);
4797 }
4798
4799 /* Do an early exit if all cache entries are already there. */
4800 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4801 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4802 void *copy_entry = NULL;
4803 if (may_need_copy_shader)
4804 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4805
4806 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4807 free(main_entry);
4808 free(copy_entry);
4809
4810 if(has_all_cache_entries)
4811 return VK_SUCCESS;
4812
4813 unsigned process = 0;
4814 uint8_t sc_threads = device->instance->num_sc_threads;
4815 while (true) {
4816 mtx_lock(&device->sc_state->secure_compile_mutex);
4817 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4818 device->sc_state->secure_compile_thread_counter++;
4819 for (unsigned i = 0; i < sc_threads; i++) {
4820 if (!device->sc_state->secure_compile_processes[i].in_use) {
4821 device->sc_state->secure_compile_processes[i].in_use = true;
4822 process = i;
4823 break;
4824 }
4825 }
4826 mtx_unlock(&device->sc_state->secure_compile_mutex);
4827 break;
4828 }
4829 mtx_unlock(&device->sc_state->secure_compile_mutex);
4830 }
4831
4832 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4833 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4834
4835 /* Fork a copy of the slim untainted secure compile process */
4836 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4837 write(fd_secure_input, &sc_type, sizeof(sc_type));
4838
4839 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4840 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4841 return VK_ERROR_DEVICE_LOST;
4842
4843 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4844 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4845
4846 /* Write pipeline / shader module out to secure process via pipe */
4847 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4848 write(fd_secure_input, &sc_type, sizeof(sc_type));
4849
4850 /* Write pipeline layout out to secure process */
4851 struct radv_pipeline_layout *layout = pipeline->layout;
4852 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4853 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4854 for (uint32_t set = 0; set < layout->num_sets; set++) {
4855 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4856 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4857 }
4858
4859 /* Write pipeline key out to secure process */
4860 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4861
4862 /* Write pipeline create flags out to secure process */
4863 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4864
4865 /* Write stage and shader information out to secure process */
4866 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4867 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4868 if (!pStages[i])
4869 continue;
4870
4871 /* Write stage out to secure process */
4872 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4873 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4874
4875 /* Write entry point name out to secure process */
4876 size_t name_size = strlen(pStages[i]->pName) + 1;
4877 write(fd_secure_input, &name_size, sizeof(size_t));
4878 write(fd_secure_input, pStages[i]->pName, name_size);
4879
4880 /* Write shader module out to secure process */
4881 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4882 assert(!module->nir);
4883 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4884 write(fd_secure_input, &module_size, sizeof(size_t));
4885 write(fd_secure_input, module, module_size);
4886
4887 /* Write specialization info out to secure process */
4888 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4889 bool has_spec_info = specInfo ? true : false;
4890 write(fd_secure_input, &has_spec_info, sizeof(bool));
4891 if (specInfo) {
4892 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4893 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4894
4895 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4896 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4897 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4898 }
4899 }
4900
4901 /* Read the data returned from the secure process */
4902 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4903 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4904 return VK_ERROR_DEVICE_LOST;
4905
4906 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4907 assert(device->physical_device->disk_cache);
4908
4909 uint8_t disk_sha1[20];
4910 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4911 return VK_ERROR_DEVICE_LOST;
4912
4913 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4914 memcmp(disk_sha1, allowed_hashes[1], 20))
4915 return VK_ERROR_DEVICE_LOST;
4916
4917 uint32_t entry_size;
4918 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4919 return VK_ERROR_DEVICE_LOST;
4920
4921 struct cache_entry *entry = malloc(entry_size);
4922 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4923 return VK_ERROR_DEVICE_LOST;
4924
4925 disk_cache_put(device->physical_device->disk_cache,
4926 disk_sha1, entry, entry_size,
4927 NULL);
4928
4929 free(entry);
4930 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4931 uint8_t disk_sha1[20];
4932 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4933 return VK_ERROR_DEVICE_LOST;
4934
4935 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4936 memcmp(disk_sha1, allowed_hashes[1], 20))
4937 return VK_ERROR_DEVICE_LOST;
4938
4939 size_t size;
4940 struct cache_entry *entry = (struct cache_entry *)
4941 disk_cache_get(device->physical_device->disk_cache,
4942 disk_sha1, &size);
4943
4944 uint8_t found = entry ? 1 : 0;
4945 write(fd_secure_input, &found, sizeof(uint8_t));
4946
4947 if (found) {
4948 write(fd_secure_input, &size, sizeof(size_t));
4949 write(fd_secure_input, entry, size);
4950 }
4951
4952 free(entry);
4953 }
4954 }
4955
4956 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
4957 write(fd_secure_input, &sc_type, sizeof(sc_type));
4958
4959 mtx_lock(&device->sc_state->secure_compile_mutex);
4960 device->sc_state->secure_compile_thread_counter--;
4961 device->sc_state->secure_compile_processes[process].in_use = false;
4962 mtx_unlock(&device->sc_state->secure_compile_mutex);
4963
4964 return VK_SUCCESS;
4965 }
4966
4967 static VkResult
4968 radv_pipeline_init(struct radv_pipeline *pipeline,
4969 struct radv_device *device,
4970 struct radv_pipeline_cache *cache,
4971 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4972 const struct radv_graphics_pipeline_create_info *extra)
4973 {
4974 VkResult result;
4975 bool has_view_index = false;
4976
4977 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4978 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4979 if (subpass->view_mask)
4980 has_view_index = true;
4981
4982 pipeline->device = device;
4983 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4984 assert(pipeline->layout);
4985
4986 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4987
4988 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4989 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4990 radv_init_feedback(creation_feedback);
4991
4992 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4993
4994 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4995 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4996 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4997 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4998 pStages[stage] = &pCreateInfo->pStages[i];
4999 if(creation_feedback)
5000 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5001 }
5002
5003 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5004 if (radv_device_use_secure_compile(device->instance)) {
5005 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5006 } else {
5007 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5008 pCreateInfo->flags, pipeline_feedback,
5009 stage_feedbacks);
5010 if (result != VK_SUCCESS)
5011 return result;
5012 }
5013
5014 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5015 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5016 uint32_t gs_out;
5017 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5018
5019 pipeline->graphics.topology = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5020 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5021
5022 if (radv_pipeline_has_gs(pipeline)) {
5023 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5024 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5025 } else if (radv_pipeline_has_tess(pipeline)) {
5026 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5027 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5028 else
5029 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5030 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5031 } else {
5032 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5033 }
5034 if (extra && extra->use_rectlist) {
5035 prim = V_008958_DI_PT_RECTLIST;
5036 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5037 pipeline->graphics.can_use_guardband = true;
5038 if (radv_pipeline_has_ngg(pipeline))
5039 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5040 }
5041 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5042
5043 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5044
5045 /* Ensure that some export memory is always allocated, for two reasons:
5046 *
5047 * 1) Correctness: The hardware ignores the EXEC mask if no export
5048 * memory is allocated, so KILL and alpha test do not work correctly
5049 * without this.
5050 * 2) Performance: Every shader needs at least a NULL export, even when
5051 * it writes no color/depth output. The NULL export instruction
5052 * stalls without this setting.
5053 *
5054 * Don't add this to CB_SHADER_MASK.
5055 *
5056 * GFX10 supports pixel shaders without exports by setting both the
5057 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5058 * instructions if any are present.
5059 */
5060 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5061 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5062 ps->info.ps.can_discard) &&
5063 !blend.spi_shader_col_format) {
5064 if (!ps->info.ps.writes_z &&
5065 !ps->info.ps.writes_stencil &&
5066 !ps->info.ps.writes_sample_mask)
5067 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5068 }
5069
5070 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
5071
5072 if (extra &&
5073 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
5074 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
5075 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
5076 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
5077 /* According to the CB spec states, CB_SHADER_MASK should be
5078 * set to enable writes to all four channels of MRT0.
5079 */
5080 blend.cb_shader_mask = 0xf;
5081 }
5082
5083 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5084 if (pipeline->shaders[i]) {
5085 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5086 }
5087 }
5088
5089 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5090 struct radv_shader_variant *gs =
5091 pipeline->shaders[MESA_SHADER_GEOMETRY];
5092
5093 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5094 }
5095
5096 struct radv_tessellation_state tess = {0};
5097 if (radv_pipeline_has_tess(pipeline)) {
5098 pipeline->graphics.tess_patch_control_points =
5099 pCreateInfo->pTessellationState->patchControlPoints;
5100 tess = calculate_tess_state(pipeline, pCreateInfo);
5101 }
5102
5103 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess);
5104
5105 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5106
5107 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5108 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5109
5110 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5111 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5112 if (loc->sgpr_idx != -1) {
5113 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5114 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5115 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5116 pipeline->graphics.vtx_emit_num = 3;
5117 else
5118 pipeline->graphics.vtx_emit_num = 2;
5119 }
5120
5121 /* Find the last vertex shader stage that eventually uses streamout. */
5122 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5123
5124 result = radv_pipeline_scratch_init(device, pipeline);
5125 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5126
5127 return result;
5128 }
5129
5130 VkResult
5131 radv_graphics_pipeline_create(
5132 VkDevice _device,
5133 VkPipelineCache _cache,
5134 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5135 const struct radv_graphics_pipeline_create_info *extra,
5136 const VkAllocationCallbacks *pAllocator,
5137 VkPipeline *pPipeline)
5138 {
5139 RADV_FROM_HANDLE(radv_device, device, _device);
5140 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5141 struct radv_pipeline *pipeline;
5142 VkResult result;
5143
5144 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5145 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5146 if (pipeline == NULL)
5147 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5148
5149 vk_object_base_init(&device->vk, &pipeline->base,
5150 VK_OBJECT_TYPE_PIPELINE);
5151
5152 result = radv_pipeline_init(pipeline, device, cache,
5153 pCreateInfo, extra);
5154 if (result != VK_SUCCESS) {
5155 radv_pipeline_destroy(device, pipeline, pAllocator);
5156 return result;
5157 }
5158
5159 *pPipeline = radv_pipeline_to_handle(pipeline);
5160
5161 return VK_SUCCESS;
5162 }
5163
5164 VkResult radv_CreateGraphicsPipelines(
5165 VkDevice _device,
5166 VkPipelineCache pipelineCache,
5167 uint32_t count,
5168 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5169 const VkAllocationCallbacks* pAllocator,
5170 VkPipeline* pPipelines)
5171 {
5172 VkResult result = VK_SUCCESS;
5173 unsigned i = 0;
5174
5175 for (; i < count; i++) {
5176 VkResult r;
5177 r = radv_graphics_pipeline_create(_device,
5178 pipelineCache,
5179 &pCreateInfos[i],
5180 NULL, pAllocator, &pPipelines[i]);
5181 if (r != VK_SUCCESS) {
5182 result = r;
5183 pPipelines[i] = VK_NULL_HANDLE;
5184
5185 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5186 break;
5187 }
5188 }
5189
5190 for (; i < count; ++i)
5191 pPipelines[i] = VK_NULL_HANDLE;
5192
5193 return result;
5194 }
5195
5196
5197 static void
5198 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5199 {
5200 struct radv_shader_variant *compute_shader;
5201 struct radv_device *device = pipeline->device;
5202 unsigned threads_per_threadgroup;
5203 unsigned threadgroups_per_cu = 1;
5204 unsigned waves_per_threadgroup;
5205 unsigned max_waves_per_sh = 0;
5206 uint64_t va;
5207
5208 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5209 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5210
5211 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5212 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5213
5214 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5215 radeon_emit(&pipeline->cs, va >> 8);
5216 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5217
5218 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5219 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5220 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5221 if (device->physical_device->rad_info.chip_class >= GFX10) {
5222 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5223 }
5224
5225 /* Calculate best compute resource limits. */
5226 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5227 compute_shader->info.cs.block_size[1] *
5228 compute_shader->info.cs.block_size[2];
5229 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5230 compute_shader->info.wave_size);
5231
5232 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5233 waves_per_threadgroup == 1)
5234 threadgroups_per_cu = 2;
5235
5236 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5237 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5238 waves_per_threadgroup,
5239 max_waves_per_sh,
5240 threadgroups_per_cu));
5241
5242 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5243 radeon_emit(&pipeline->cs,
5244 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5245 radeon_emit(&pipeline->cs,
5246 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5247 radeon_emit(&pipeline->cs,
5248 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5249
5250 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5251 }
5252
5253 static struct radv_pipeline_key
5254 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5255 const VkComputePipelineCreateInfo *pCreateInfo)
5256 {
5257 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5258 struct radv_pipeline_key key;
5259 memset(&key, 0, sizeof(key));
5260
5261 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5262 key.optimisations_disabled = 1;
5263
5264 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5265 vk_find_struct_const(stage->pNext,
5266 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5267
5268 if (subgroup_size) {
5269 assert(subgroup_size->requiredSubgroupSize == 32 ||
5270 subgroup_size->requiredSubgroupSize == 64);
5271 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5272 }
5273
5274 return key;
5275 }
5276
5277 static VkResult radv_compute_pipeline_create(
5278 VkDevice _device,
5279 VkPipelineCache _cache,
5280 const VkComputePipelineCreateInfo* pCreateInfo,
5281 const VkAllocationCallbacks* pAllocator,
5282 VkPipeline* pPipeline)
5283 {
5284 RADV_FROM_HANDLE(radv_device, device, _device);
5285 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5286 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5287 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5288 struct radv_pipeline *pipeline;
5289 VkResult result;
5290
5291 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5292 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5293 if (pipeline == NULL)
5294 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5295
5296 vk_object_base_init(&device->vk, &pipeline->base,
5297 VK_OBJECT_TYPE_PIPELINE);
5298
5299 pipeline->device = device;
5300 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5301 assert(pipeline->layout);
5302
5303 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5304 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5305 radv_init_feedback(creation_feedback);
5306
5307 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5308 if (creation_feedback)
5309 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5310
5311 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5312
5313 struct radv_pipeline_key key =
5314 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5315
5316 if (radv_device_use_secure_compile(device->instance)) {
5317 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5318 *pPipeline = radv_pipeline_to_handle(pipeline);
5319
5320 return result;
5321 } else {
5322 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5323 pCreateInfo->flags, pipeline_feedback,
5324 stage_feedbacks);
5325 if (result != VK_SUCCESS) {
5326 radv_pipeline_destroy(device, pipeline, pAllocator);
5327 return result;
5328 }
5329 }
5330
5331 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5332 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5333 result = radv_pipeline_scratch_init(device, pipeline);
5334 if (result != VK_SUCCESS) {
5335 radv_pipeline_destroy(device, pipeline, pAllocator);
5336 return result;
5337 }
5338
5339 radv_compute_generate_pm4(pipeline);
5340
5341 *pPipeline = radv_pipeline_to_handle(pipeline);
5342
5343 return VK_SUCCESS;
5344 }
5345
5346 VkResult radv_CreateComputePipelines(
5347 VkDevice _device,
5348 VkPipelineCache pipelineCache,
5349 uint32_t count,
5350 const VkComputePipelineCreateInfo* pCreateInfos,
5351 const VkAllocationCallbacks* pAllocator,
5352 VkPipeline* pPipelines)
5353 {
5354 VkResult result = VK_SUCCESS;
5355
5356 unsigned i = 0;
5357 for (; i < count; i++) {
5358 VkResult r;
5359 r = radv_compute_pipeline_create(_device, pipelineCache,
5360 &pCreateInfos[i],
5361 pAllocator, &pPipelines[i]);
5362 if (r != VK_SUCCESS) {
5363 result = r;
5364 pPipelines[i] = VK_NULL_HANDLE;
5365
5366 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5367 break;
5368 }
5369 }
5370
5371 for (; i < count; ++i)
5372 pPipelines[i] = VK_NULL_HANDLE;
5373
5374 return result;
5375 }
5376
5377
5378 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5379 {
5380 uint32_t ret = 0;
5381 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5382 if (!pipeline->shaders[i])
5383 continue;
5384
5385 if (i == MESA_SHADER_GEOMETRY &&
5386 !radv_pipeline_has_ngg(pipeline)) {
5387 ret += 2u;
5388 } else {
5389 ret += 1u;
5390 }
5391
5392 }
5393 return ret;
5394 }
5395
5396 static struct radv_shader_variant *
5397 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5398 {
5399 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5400 if (!pipeline->shaders[i])
5401 continue;
5402 if (!index) {
5403 *stage = i;
5404 return pipeline->shaders[i];
5405 }
5406
5407 --index;
5408
5409 if (i == MESA_SHADER_GEOMETRY &&
5410 !radv_pipeline_has_ngg(pipeline)) {
5411 if (!index) {
5412 *stage = i;
5413 return pipeline->gs_copy_shader;
5414 }
5415 --index;
5416 }
5417 }
5418
5419 *stage = -1;
5420 return NULL;
5421 }
5422
5423 /* Basically strlcpy (which does not exist on linux) specialized for
5424 * descriptions. */
5425 static void desc_copy(char *desc, const char *src) {
5426 int len = strlen(src);
5427 assert(len < VK_MAX_DESCRIPTION_SIZE);
5428 memcpy(desc, src, len);
5429 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5430 }
5431
5432 VkResult radv_GetPipelineExecutablePropertiesKHR(
5433 VkDevice _device,
5434 const VkPipelineInfoKHR* pPipelineInfo,
5435 uint32_t* pExecutableCount,
5436 VkPipelineExecutablePropertiesKHR* pProperties)
5437 {
5438 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5439 const uint32_t total_count = radv_get_executable_count(pipeline);
5440
5441 if (!pProperties) {
5442 *pExecutableCount = total_count;
5443 return VK_SUCCESS;
5444 }
5445
5446 const uint32_t count = MIN2(total_count, *pExecutableCount);
5447 for (unsigned i = 0, executable_idx = 0;
5448 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5449 if (!pipeline->shaders[i])
5450 continue;
5451 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5452 const char *name = NULL;
5453 const char *description = NULL;
5454 switch(i) {
5455 case MESA_SHADER_VERTEX:
5456 name = "Vertex Shader";
5457 description = "Vulkan Vertex Shader";
5458 break;
5459 case MESA_SHADER_TESS_CTRL:
5460 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5461 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5462 name = "Vertex + Tessellation Control Shaders";
5463 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5464 } else {
5465 name = "Tessellation Control Shader";
5466 description = "Vulkan Tessellation Control Shader";
5467 }
5468 break;
5469 case MESA_SHADER_TESS_EVAL:
5470 name = "Tessellation Evaluation Shader";
5471 description = "Vulkan Tessellation Evaluation Shader";
5472 break;
5473 case MESA_SHADER_GEOMETRY:
5474 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5475 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5476 name = "Tessellation Evaluation + Geometry Shaders";
5477 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5478 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5479 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5480 name = "Vertex + Geometry Shader";
5481 description = "Combined Vulkan Vertex and Geometry Shaders";
5482 } else {
5483 name = "Geometry Shader";
5484 description = "Vulkan Geometry Shader";
5485 }
5486 break;
5487 case MESA_SHADER_FRAGMENT:
5488 name = "Fragment Shader";
5489 description = "Vulkan Fragment Shader";
5490 break;
5491 case MESA_SHADER_COMPUTE:
5492 name = "Compute Shader";
5493 description = "Vulkan Compute Shader";
5494 break;
5495 }
5496
5497 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5498 desc_copy(pProperties[executable_idx].name, name);
5499 desc_copy(pProperties[executable_idx].description, description);
5500
5501 ++executable_idx;
5502 if (i == MESA_SHADER_GEOMETRY &&
5503 !radv_pipeline_has_ngg(pipeline)) {
5504 assert(pipeline->gs_copy_shader);
5505 if (executable_idx >= count)
5506 break;
5507
5508 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5509 pProperties[executable_idx].subgroupSize = 64;
5510 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5511 desc_copy(pProperties[executable_idx].description,
5512 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5513
5514 ++executable_idx;
5515 }
5516 }
5517
5518 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5519 *pExecutableCount = count;
5520 return result;
5521 }
5522
5523 VkResult radv_GetPipelineExecutableStatisticsKHR(
5524 VkDevice _device,
5525 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5526 uint32_t* pStatisticCount,
5527 VkPipelineExecutableStatisticKHR* pStatistics)
5528 {
5529 RADV_FROM_HANDLE(radv_device, device, _device);
5530 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5531 gl_shader_stage stage;
5532 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5533
5534 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5535 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5536 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5537
5538 VkPipelineExecutableStatisticKHR *s = pStatistics;
5539 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5540 VkResult result = VK_SUCCESS;
5541
5542 if (s < end) {
5543 desc_copy(s->name, "SGPRs");
5544 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5545 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5546 s->value.u64 = shader->config.num_sgprs;
5547 }
5548 ++s;
5549
5550 if (s < end) {
5551 desc_copy(s->name, "VGPRs");
5552 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5553 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5554 s->value.u64 = shader->config.num_vgprs;
5555 }
5556 ++s;
5557
5558 if (s < end) {
5559 desc_copy(s->name, "Spilled SGPRs");
5560 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5561 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5562 s->value.u64 = shader->config.spilled_sgprs;
5563 }
5564 ++s;
5565
5566 if (s < end) {
5567 desc_copy(s->name, "Spilled VGPRs");
5568 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5569 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5570 s->value.u64 = shader->config.spilled_vgprs;
5571 }
5572 ++s;
5573
5574 if (s < end) {
5575 desc_copy(s->name, "PrivMem VGPRs");
5576 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5577 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5578 s->value.u64 = shader->info.private_mem_vgprs;
5579 }
5580 ++s;
5581
5582 if (s < end) {
5583 desc_copy(s->name, "Code size");
5584 desc_copy(s->description, "Code size in bytes");
5585 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5586 s->value.u64 = shader->exec_size;
5587 }
5588 ++s;
5589
5590 if (s < end) {
5591 desc_copy(s->name, "LDS size");
5592 desc_copy(s->description, "LDS size in bytes per workgroup");
5593 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5594 s->value.u64 = shader->config.lds_size * lds_increment;
5595 }
5596 ++s;
5597
5598 if (s < end) {
5599 desc_copy(s->name, "Scratch size");
5600 desc_copy(s->description, "Private memory in bytes per subgroup");
5601 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5602 s->value.u64 = shader->config.scratch_bytes_per_wave;
5603 }
5604 ++s;
5605
5606 if (s < end) {
5607 desc_copy(s->name, "Subgroups per SIMD");
5608 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5609 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5610 s->value.u64 = max_waves;
5611 }
5612 ++s;
5613
5614 if (shader->statistics) {
5615 for (unsigned i = 0; i < shader->statistics->count; i++) {
5616 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5617 uint32_t value = shader->statistics->values[i];
5618 if (s < end) {
5619 desc_copy(s->name, info->name);
5620 desc_copy(s->description, info->desc);
5621 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5622 s->value.u64 = value;
5623 }
5624 ++s;
5625 }
5626 }
5627
5628 if (!pStatistics)
5629 *pStatisticCount = s - pStatistics;
5630 else if (s > end) {
5631 *pStatisticCount = end - pStatistics;
5632 result = VK_INCOMPLETE;
5633 } else {
5634 *pStatisticCount = s - pStatistics;
5635 }
5636
5637 return result;
5638 }
5639
5640 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5641 {
5642 size_t total_size = strlen(src) + 1;
5643
5644 if (!data) {
5645 *data_size = total_size;
5646 return VK_SUCCESS;
5647 }
5648
5649 size_t size = MIN2(total_size, *data_size);
5650
5651 memcpy(data, src, size);
5652 if (size)
5653 *((char*)data + size - 1) = 0;
5654 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5655 }
5656
5657 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5658 VkDevice device,
5659 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5660 uint32_t* pInternalRepresentationCount,
5661 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5662 {
5663 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5664 gl_shader_stage stage;
5665 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5666
5667 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5668 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5669 VkResult result = VK_SUCCESS;
5670 /* optimized NIR */
5671 if (p < end) {
5672 p->isText = true;
5673 desc_copy(p->name, "NIR Shader(s)");
5674 desc_copy(p->description, "The optimized NIR shader(s)");
5675 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5676 result = VK_INCOMPLETE;
5677 }
5678 ++p;
5679
5680 /* backend IR */
5681 if (p < end) {
5682 p->isText = true;
5683 if (pipeline->device->physical_device->use_llvm) {
5684 desc_copy(p->name, "LLVM IR");
5685 desc_copy(p->description, "The LLVM IR after some optimizations");
5686 } else {
5687 desc_copy(p->name, "ACO IR");
5688 desc_copy(p->description, "The ACO IR after some optimizations");
5689 }
5690 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5691 result = VK_INCOMPLETE;
5692 }
5693 ++p;
5694
5695 /* Disassembler */
5696 if (p < end) {
5697 p->isText = true;
5698 desc_copy(p->name, "Assembly");
5699 desc_copy(p->description, "Final Assembly");
5700 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5701 result = VK_INCOMPLETE;
5702 }
5703 ++p;
5704
5705 if (!pInternalRepresentations)
5706 *pInternalRepresentationCount = p - pInternalRepresentations;
5707 else if(p > end) {
5708 result = VK_INCOMPLETE;
5709 *pInternalRepresentationCount = end - pInternalRepresentations;
5710 } else {
5711 *pInternalRepresentationCount = p - pInternalRepresentations;
5712 }
5713
5714 return result;
5715 }