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[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 static void
101 radv_pipeline_destroy(struct radv_device *device,
102 struct radv_pipeline *pipeline,
103 const VkAllocationCallbacks* allocator)
104 {
105 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
106 if (pipeline->shaders[i])
107 radv_shader_variant_destroy(device, pipeline->shaders[i]);
108
109 if (pipeline->gs_copy_shader)
110 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
111
112 if(pipeline->cs.buf)
113 free(pipeline->cs.buf);
114 vk_free2(&device->alloc, allocator, pipeline);
115 }
116
117 void radv_DestroyPipeline(
118 VkDevice _device,
119 VkPipeline _pipeline,
120 const VkAllocationCallbacks* pAllocator)
121 {
122 RADV_FROM_HANDLE(radv_device, device, _device);
123 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
124
125 if (!_pipeline)
126 return;
127
128 radv_pipeline_destroy(device, pipeline, pAllocator);
129 }
130
131 static uint32_t get_hash_flags(struct radv_device *device)
132 {
133 uint32_t hash_flags = 0;
134
135 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
136 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
137 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
138 hash_flags |= RADV_HASH_SHADER_SISCHED;
139 return hash_flags;
140 }
141
142 static VkResult
143 radv_pipeline_scratch_init(struct radv_device *device,
144 struct radv_pipeline *pipeline)
145 {
146 unsigned scratch_bytes_per_wave = 0;
147 unsigned max_waves = 0;
148 unsigned min_waves = 1;
149
150 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
151 if (pipeline->shaders[i]) {
152 unsigned max_stage_waves = device->scratch_waves;
153
154 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
155 pipeline->shaders[i]->config.scratch_bytes_per_wave);
156
157 max_stage_waves = MIN2(max_stage_waves,
158 4 * device->physical_device->rad_info.num_good_compute_units *
159 (256 / pipeline->shaders[i]->config.num_vgprs));
160 max_waves = MAX2(max_waves, max_stage_waves);
161 }
162 }
163
164 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
165 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
166 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
167 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
168 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
169 }
170
171 if (scratch_bytes_per_wave)
172 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
173
174 if (scratch_bytes_per_wave && max_waves < min_waves) {
175 /* Not really true at this moment, but will be true on first
176 * execution. Avoid having hanging shaders. */
177 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
178 }
179 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
180 pipeline->max_waves = max_waves;
181 return VK_SUCCESS;
182 }
183
184 static uint32_t si_translate_blend_function(VkBlendOp op)
185 {
186 switch (op) {
187 case VK_BLEND_OP_ADD:
188 return V_028780_COMB_DST_PLUS_SRC;
189 case VK_BLEND_OP_SUBTRACT:
190 return V_028780_COMB_SRC_MINUS_DST;
191 case VK_BLEND_OP_REVERSE_SUBTRACT:
192 return V_028780_COMB_DST_MINUS_SRC;
193 case VK_BLEND_OP_MIN:
194 return V_028780_COMB_MIN_DST_SRC;
195 case VK_BLEND_OP_MAX:
196 return V_028780_COMB_MAX_DST_SRC;
197 default:
198 return 0;
199 }
200 }
201
202 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
203 {
204 switch (factor) {
205 case VK_BLEND_FACTOR_ZERO:
206 return V_028780_BLEND_ZERO;
207 case VK_BLEND_FACTOR_ONE:
208 return V_028780_BLEND_ONE;
209 case VK_BLEND_FACTOR_SRC_COLOR:
210 return V_028780_BLEND_SRC_COLOR;
211 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
212 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
213 case VK_BLEND_FACTOR_DST_COLOR:
214 return V_028780_BLEND_DST_COLOR;
215 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
216 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
217 case VK_BLEND_FACTOR_SRC_ALPHA:
218 return V_028780_BLEND_SRC_ALPHA;
219 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
220 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
221 case VK_BLEND_FACTOR_DST_ALPHA:
222 return V_028780_BLEND_DST_ALPHA;
223 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case VK_BLEND_FACTOR_CONSTANT_COLOR:
226 return V_028780_BLEND_CONSTANT_COLOR;
227 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
230 return V_028780_BLEND_CONSTANT_ALPHA;
231 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
232 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
233 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
234 return V_028780_BLEND_SRC_ALPHA_SATURATE;
235 case VK_BLEND_FACTOR_SRC1_COLOR:
236 return V_028780_BLEND_SRC1_COLOR;
237 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
238 return V_028780_BLEND_INV_SRC1_COLOR;
239 case VK_BLEND_FACTOR_SRC1_ALPHA:
240 return V_028780_BLEND_SRC1_ALPHA;
241 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
242 return V_028780_BLEND_INV_SRC1_ALPHA;
243 default:
244 return 0;
245 }
246 }
247
248 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
249 {
250 switch (op) {
251 case VK_BLEND_OP_ADD:
252 return V_028760_OPT_COMB_ADD;
253 case VK_BLEND_OP_SUBTRACT:
254 return V_028760_OPT_COMB_SUBTRACT;
255 case VK_BLEND_OP_REVERSE_SUBTRACT:
256 return V_028760_OPT_COMB_REVSUBTRACT;
257 case VK_BLEND_OP_MIN:
258 return V_028760_OPT_COMB_MIN;
259 case VK_BLEND_OP_MAX:
260 return V_028760_OPT_COMB_MAX;
261 default:
262 return V_028760_OPT_COMB_BLEND_DISABLED;
263 }
264 }
265
266 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
267 {
268 switch (factor) {
269 case VK_BLEND_FACTOR_ZERO:
270 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
271 case VK_BLEND_FACTOR_ONE:
272 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
273 case VK_BLEND_FACTOR_SRC_COLOR:
274 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
275 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
276 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
277 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
278 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
279 case VK_BLEND_FACTOR_SRC_ALPHA:
280 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
281 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
282 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
283 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
284 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
285 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
286 default:
287 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
288 }
289 }
290
291 /**
292 * Get rid of DST in the blend factors by commuting the operands:
293 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
294 */
295 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
296 unsigned *dst_factor, unsigned expected_dst,
297 unsigned replacement_src)
298 {
299 if (*src_factor == expected_dst &&
300 *dst_factor == VK_BLEND_FACTOR_ZERO) {
301 *src_factor = VK_BLEND_FACTOR_ZERO;
302 *dst_factor = replacement_src;
303
304 /* Commuting the operands requires reversing subtractions. */
305 if (*func == VK_BLEND_OP_SUBTRACT)
306 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
307 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
308 *func = VK_BLEND_OP_SUBTRACT;
309 }
310 }
311
312 static bool si_blend_factor_uses_dst(unsigned factor)
313 {
314 return factor == VK_BLEND_FACTOR_DST_COLOR ||
315 factor == VK_BLEND_FACTOR_DST_ALPHA ||
316 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
317 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
318 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
319 }
320
321 static bool is_dual_src(VkBlendFactor factor)
322 {
323 switch (factor) {
324 case VK_BLEND_FACTOR_SRC1_COLOR:
325 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
326 case VK_BLEND_FACTOR_SRC1_ALPHA:
327 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
328 return true;
329 default:
330 return false;
331 }
332 }
333
334 static unsigned si_choose_spi_color_format(VkFormat vk_format,
335 bool blend_enable,
336 bool blend_need_alpha)
337 {
338 const struct vk_format_description *desc = vk_format_description(vk_format);
339 unsigned format, ntype, swap;
340
341 /* Alpha is needed for alpha-to-coverage.
342 * Blending may be with or without alpha.
343 */
344 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
345 unsigned alpha = 0; /* exports alpha, but may not support blending */
346 unsigned blend = 0; /* supports blending, but may not export alpha */
347 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
348
349 format = radv_translate_colorformat(vk_format);
350 ntype = radv_translate_color_numformat(vk_format, desc,
351 vk_format_get_first_non_void_channel(vk_format));
352 swap = radv_translate_colorswap(vk_format, false);
353
354 /* Choose the SPI color formats. These are required values for Stoney/RB+.
355 * Other chips have multiple choices, though they are not necessarily better.
356 */
357 switch (format) {
358 case V_028C70_COLOR_5_6_5:
359 case V_028C70_COLOR_1_5_5_5:
360 case V_028C70_COLOR_5_5_5_1:
361 case V_028C70_COLOR_4_4_4_4:
362 case V_028C70_COLOR_10_11_11:
363 case V_028C70_COLOR_11_11_10:
364 case V_028C70_COLOR_8:
365 case V_028C70_COLOR_8_8:
366 case V_028C70_COLOR_8_8_8_8:
367 case V_028C70_COLOR_10_10_10_2:
368 case V_028C70_COLOR_2_10_10_10:
369 if (ntype == V_028C70_NUMBER_UINT)
370 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
371 else if (ntype == V_028C70_NUMBER_SINT)
372 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
373 else
374 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
375 break;
376
377 case V_028C70_COLOR_16:
378 case V_028C70_COLOR_16_16:
379 case V_028C70_COLOR_16_16_16_16:
380 if (ntype == V_028C70_NUMBER_UNORM ||
381 ntype == V_028C70_NUMBER_SNORM) {
382 /* UNORM16 and SNORM16 don't support blending */
383 if (ntype == V_028C70_NUMBER_UNORM)
384 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
385 else
386 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
387
388 /* Use 32 bits per channel for blending. */
389 if (format == V_028C70_COLOR_16) {
390 if (swap == V_028C70_SWAP_STD) { /* R */
391 blend = V_028714_SPI_SHADER_32_R;
392 blend_alpha = V_028714_SPI_SHADER_32_AR;
393 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
394 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
395 else
396 assert(0);
397 } else if (format == V_028C70_COLOR_16_16) {
398 if (swap == V_028C70_SWAP_STD) { /* RG */
399 blend = V_028714_SPI_SHADER_32_GR;
400 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
401 } else if (swap == V_028C70_SWAP_ALT) /* RA */
402 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
403 else
404 assert(0);
405 } else /* 16_16_16_16 */
406 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
407 } else if (ntype == V_028C70_NUMBER_UINT)
408 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
409 else if (ntype == V_028C70_NUMBER_SINT)
410 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
411 else if (ntype == V_028C70_NUMBER_FLOAT)
412 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
413 else
414 assert(0);
415 break;
416
417 case V_028C70_COLOR_32:
418 if (swap == V_028C70_SWAP_STD) { /* R */
419 blend = normal = V_028714_SPI_SHADER_32_R;
420 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
421 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
422 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
423 else
424 assert(0);
425 break;
426
427 case V_028C70_COLOR_32_32:
428 if (swap == V_028C70_SWAP_STD) { /* RG */
429 blend = normal = V_028714_SPI_SHADER_32_GR;
430 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
431 } else if (swap == V_028C70_SWAP_ALT) /* RA */
432 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
433 else
434 assert(0);
435 break;
436
437 case V_028C70_COLOR_32_32_32_32:
438 case V_028C70_COLOR_8_24:
439 case V_028C70_COLOR_24_8:
440 case V_028C70_COLOR_X24_8_32_FLOAT:
441 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
442 break;
443
444 default:
445 unreachable("unhandled blend format");
446 }
447
448 if (blend_enable && blend_need_alpha)
449 return blend_alpha;
450 else if(blend_need_alpha)
451 return alpha;
452 else if(blend_enable)
453 return blend;
454 else
455 return normal;
456 }
457
458 static void
459 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
460 const VkGraphicsPipelineCreateInfo *pCreateInfo,
461 struct radv_blend_state *blend)
462 {
463 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
464 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
465 unsigned col_format = 0;
466
467 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
468 unsigned cf;
469
470 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
471 cf = V_028714_SPI_SHADER_ZERO;
472 } else {
473 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
474 bool blend_enable =
475 blend->blend_enable_4bit & (0xfu << (i * 4));
476
477 cf = si_choose_spi_color_format(attachment->format,
478 blend_enable,
479 blend->need_src_alpha & (1 << i));
480 }
481
482 col_format |= cf << (4 * i);
483 }
484
485 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
486
487 if (blend->mrt0_is_dual_src)
488 col_format |= (col_format & 0xf) << 4;
489 blend->spi_shader_col_format = col_format;
490 }
491
492 static bool
493 format_is_int8(VkFormat format)
494 {
495 const struct vk_format_description *desc = vk_format_description(format);
496 int channel = vk_format_get_first_non_void_channel(format);
497
498 return channel >= 0 && desc->channel[channel].pure_integer &&
499 desc->channel[channel].size == 8;
500 }
501
502 static bool
503 format_is_int10(VkFormat format)
504 {
505 const struct vk_format_description *desc = vk_format_description(format);
506
507 if (desc->nr_channels != 4)
508 return false;
509 for (unsigned i = 0; i < 4; i++) {
510 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
511 return true;
512 }
513 return false;
514 }
515
516 unsigned radv_format_meta_fs_key(VkFormat format)
517 {
518 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
519 bool is_int8 = format_is_int8(format);
520 bool is_int10 = format_is_int10(format);
521
522 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
523 }
524
525 static void
526 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
527 unsigned *is_int8, unsigned *is_int10)
528 {
529 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
530 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
531 *is_int8 = 0;
532 *is_int10 = 0;
533
534 for (unsigned i = 0; i < subpass->color_count; ++i) {
535 struct radv_render_pass_attachment *attachment;
536
537 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
538 continue;
539
540 attachment = pass->attachments + subpass->color_attachments[i].attachment;
541
542 if (format_is_int8(attachment->format))
543 *is_int8 |= 1 << i;
544 if (format_is_int10(attachment->format))
545 *is_int10 |= 1 << i;
546 }
547 }
548
549 static void
550 radv_blend_check_commutativity(struct radv_blend_state *blend,
551 VkBlendOp op, VkBlendFactor src,
552 VkBlendFactor dst, unsigned chanmask)
553 {
554 /* Src factor is allowed when it does not depend on Dst. */
555 static const uint32_t src_allowed =
556 (1u << VK_BLEND_FACTOR_ONE) |
557 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
558 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
559 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
560 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
561 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
562 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
563 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
564 (1u << VK_BLEND_FACTOR_ZERO) |
565 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
566 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
567 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
568 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
569 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
570 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
571
572 if (dst == VK_BLEND_FACTOR_ONE &&
573 (src_allowed && (1u << src))) {
574 /* Addition is commutative, but floating point addition isn't
575 * associative: subtle changes can be introduced via different
576 * rounding. Be conservative, only enable for min and max.
577 */
578 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
579 blend->commutative_4bit |= chanmask;
580 }
581 }
582
583 static struct radv_blend_state
584 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
585 const VkGraphicsPipelineCreateInfo *pCreateInfo,
586 const struct radv_graphics_pipeline_create_info *extra)
587 {
588 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
589 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
590 struct radv_blend_state blend = {0};
591 unsigned mode = V_028808_CB_NORMAL;
592 int i;
593
594 if (!vkblend)
595 return blend;
596
597 if (extra && extra->custom_blend_mode) {
598 blend.single_cb_enable = true;
599 mode = extra->custom_blend_mode;
600 }
601 blend.cb_color_control = 0;
602 if (vkblend->logicOpEnable)
603 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
604 else
605 blend.cb_color_control |= S_028808_ROP3(0xcc);
606
607 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
608 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
609 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
610 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
611
612 if (vkms && vkms->alphaToCoverageEnable) {
613 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
614 }
615
616 blend.cb_target_mask = 0;
617 for (i = 0; i < vkblend->attachmentCount; i++) {
618 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
619 unsigned blend_cntl = 0;
620 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
621 VkBlendOp eqRGB = att->colorBlendOp;
622 VkBlendFactor srcRGB = att->srcColorBlendFactor;
623 VkBlendFactor dstRGB = att->dstColorBlendFactor;
624 VkBlendOp eqA = att->alphaBlendOp;
625 VkBlendFactor srcA = att->srcAlphaBlendFactor;
626 VkBlendFactor dstA = att->dstAlphaBlendFactor;
627
628 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
629
630 if (!att->colorWriteMask)
631 continue;
632
633 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
634 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
635 if (!att->blendEnable) {
636 blend.cb_blend_control[i] = blend_cntl;
637 continue;
638 }
639
640 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
641 if (i == 0)
642 blend.mrt0_is_dual_src = true;
643
644 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
645 srcRGB = VK_BLEND_FACTOR_ONE;
646 dstRGB = VK_BLEND_FACTOR_ONE;
647 }
648 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
649 srcA = VK_BLEND_FACTOR_ONE;
650 dstA = VK_BLEND_FACTOR_ONE;
651 }
652
653 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
654 0x7 << (4 * i));
655 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
656 0x8 << (4 * i));
657
658 /* Blending optimizations for RB+.
659 * These transformations don't change the behavior.
660 *
661 * First, get rid of DST in the blend factors:
662 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
663 */
664 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
665 VK_BLEND_FACTOR_DST_COLOR,
666 VK_BLEND_FACTOR_SRC_COLOR);
667
668 si_blend_remove_dst(&eqA, &srcA, &dstA,
669 VK_BLEND_FACTOR_DST_COLOR,
670 VK_BLEND_FACTOR_SRC_COLOR);
671
672 si_blend_remove_dst(&eqA, &srcA, &dstA,
673 VK_BLEND_FACTOR_DST_ALPHA,
674 VK_BLEND_FACTOR_SRC_ALPHA);
675
676 /* Look up the ideal settings from tables. */
677 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
678 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
679 srcA_opt = si_translate_blend_opt_factor(srcA, true);
680 dstA_opt = si_translate_blend_opt_factor(dstA, true);
681
682 /* Handle interdependencies. */
683 if (si_blend_factor_uses_dst(srcRGB))
684 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
685 if (si_blend_factor_uses_dst(srcA))
686 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
687
688 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
689 (dstRGB == VK_BLEND_FACTOR_ZERO ||
690 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
691 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
692 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
693
694 /* Set the final value. */
695 blend.sx_mrt_blend_opt[i] =
696 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
697 S_028760_COLOR_DST_OPT(dstRGB_opt) |
698 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
699 S_028760_ALPHA_SRC_OPT(srcA_opt) |
700 S_028760_ALPHA_DST_OPT(dstA_opt) |
701 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
702 blend_cntl |= S_028780_ENABLE(1);
703
704 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
705 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
706 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
707 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
708 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
709 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
710 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
711 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
712 }
713 blend.cb_blend_control[i] = blend_cntl;
714
715 blend.blend_enable_4bit |= 0xfu << (i * 4);
716
717 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
718 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
719 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
720 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
721 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
722 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
723 blend.need_src_alpha |= 1 << i;
724 }
725 for (i = vkblend->attachmentCount; i < 8; i++) {
726 blend.cb_blend_control[i] = 0;
727 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
728 }
729
730 if (pipeline->device->physical_device->has_rbplus) {
731 /* Disable RB+ blend optimizations for dual source blending. */
732 if (blend.mrt0_is_dual_src) {
733 for (i = 0; i < 8; i++) {
734 blend.sx_mrt_blend_opt[i] =
735 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
736 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
737 }
738 }
739
740 /* RB+ doesn't work with dual source blending, logic op and
741 * RESOLVE.
742 */
743 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
744 mode == V_028808_CB_RESOLVE)
745 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
746 }
747
748 if (blend.cb_target_mask)
749 blend.cb_color_control |= S_028808_MODE(mode);
750 else
751 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
752
753 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
754 return blend;
755 }
756
757 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
758 {
759 switch (op) {
760 case VK_STENCIL_OP_KEEP:
761 return V_02842C_STENCIL_KEEP;
762 case VK_STENCIL_OP_ZERO:
763 return V_02842C_STENCIL_ZERO;
764 case VK_STENCIL_OP_REPLACE:
765 return V_02842C_STENCIL_REPLACE_TEST;
766 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
767 return V_02842C_STENCIL_ADD_CLAMP;
768 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
769 return V_02842C_STENCIL_SUB_CLAMP;
770 case VK_STENCIL_OP_INVERT:
771 return V_02842C_STENCIL_INVERT;
772 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
773 return V_02842C_STENCIL_ADD_WRAP;
774 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
775 return V_02842C_STENCIL_SUB_WRAP;
776 default:
777 return 0;
778 }
779 }
780
781 static uint32_t si_translate_fill(VkPolygonMode func)
782 {
783 switch(func) {
784 case VK_POLYGON_MODE_FILL:
785 return V_028814_X_DRAW_TRIANGLES;
786 case VK_POLYGON_MODE_LINE:
787 return V_028814_X_DRAW_LINES;
788 case VK_POLYGON_MODE_POINT:
789 return V_028814_X_DRAW_POINTS;
790 default:
791 assert(0);
792 return V_028814_X_DRAW_POINTS;
793 }
794 }
795
796 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
797 {
798 uint32_t num_samples = vkms->rasterizationSamples;
799 uint32_t ps_iter_samples = 1;
800
801 if (vkms->sampleShadingEnable) {
802 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
803 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
804 }
805 return ps_iter_samples;
806 }
807
808 static bool
809 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
810 {
811 return pCreateInfo->depthTestEnable &&
812 pCreateInfo->depthWriteEnable &&
813 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
814 }
815
816 static bool
817 radv_writes_stencil(const VkStencilOpState *state)
818 {
819 return state->writeMask &&
820 (state->failOp != VK_STENCIL_OP_KEEP ||
821 state->passOp != VK_STENCIL_OP_KEEP ||
822 state->depthFailOp != VK_STENCIL_OP_KEEP);
823 }
824
825 static bool
826 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
827 {
828 return pCreateInfo->stencilTestEnable &&
829 (radv_writes_stencil(&pCreateInfo->front) ||
830 radv_writes_stencil(&pCreateInfo->back));
831 }
832
833 static bool
834 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
835 {
836 return radv_is_depth_write_enabled(pCreateInfo) ||
837 radv_is_stencil_write_enabled(pCreateInfo);
838 }
839
840 static bool
841 radv_order_invariant_stencil_op(VkStencilOp op)
842 {
843 /* REPLACE is normally order invariant, except when the stencil
844 * reference value is written by the fragment shader. Tracking this
845 * interaction does not seem worth the effort, so be conservative.
846 */
847 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
848 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
849 op != VK_STENCIL_OP_REPLACE;
850 }
851
852 static bool
853 radv_order_invariant_stencil_state(const VkStencilOpState *state)
854 {
855 /* Compute whether, assuming Z writes are disabled, this stencil state
856 * is order invariant in the sense that the set of passing fragments as
857 * well as the final stencil buffer result does not depend on the order
858 * of fragments.
859 */
860 return !state->writeMask ||
861 /* The following assumes that Z writes are disabled. */
862 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
863 radv_order_invariant_stencil_op(state->passOp) &&
864 radv_order_invariant_stencil_op(state->depthFailOp)) ||
865 (state->compareOp == VK_COMPARE_OP_NEVER &&
866 radv_order_invariant_stencil_op(state->failOp));
867 }
868
869 static bool
870 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
871 struct radv_blend_state *blend,
872 const VkGraphicsPipelineCreateInfo *pCreateInfo)
873 {
874 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
875 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
876 unsigned colormask = blend->cb_target_enabled_4bit;
877
878 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
879 return false;
880
881 /* Be conservative if a logic operation is enabled with color buffers. */
882 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
883 return false;
884
885 /* Default depth/stencil invariance when no attachment is bound. */
886 struct radv_dsa_order_invariance dsa_order_invariant = {
887 .zs = true, .pass_set = true
888 };
889
890 if (pCreateInfo->pDepthStencilState &&
891 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
892 const VkPipelineDepthStencilStateCreateInfo *vkds =
893 pCreateInfo->pDepthStencilState;
894 struct radv_render_pass_attachment *attachment =
895 pass->attachments + subpass->depth_stencil_attachment.attachment;
896 bool has_stencil = vk_format_is_stencil(attachment->format);
897 struct radv_dsa_order_invariance order_invariance[2];
898 struct radv_shader_variant *ps =
899 pipeline->shaders[MESA_SHADER_FRAGMENT];
900
901 /* Compute depth/stencil order invariance in order to know if
902 * it's safe to enable out-of-order.
903 */
904 bool zfunc_is_ordered =
905 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
906 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
907 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
908 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
909 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
910
911 bool nozwrite_and_order_invariant_stencil =
912 !radv_is_ds_write_enabled(vkds) ||
913 (!radv_is_depth_write_enabled(vkds) &&
914 radv_order_invariant_stencil_state(&vkds->front) &&
915 radv_order_invariant_stencil_state(&vkds->back));
916
917 order_invariance[1].zs =
918 nozwrite_and_order_invariant_stencil ||
919 (!radv_is_stencil_write_enabled(vkds) &&
920 zfunc_is_ordered);
921 order_invariance[0].zs =
922 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
923
924 order_invariance[1].pass_set =
925 nozwrite_and_order_invariant_stencil ||
926 (!radv_is_stencil_write_enabled(vkds) &&
927 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
928 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
929 order_invariance[0].pass_set =
930 !radv_is_depth_write_enabled(vkds) ||
931 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
932 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
933
934 dsa_order_invariant = order_invariance[has_stencil];
935 if (!dsa_order_invariant.zs)
936 return false;
937
938 /* The set of PS invocations is always order invariant,
939 * except when early Z/S tests are requested.
940 */
941 if (ps &&
942 ps->info.info.ps.writes_memory &&
943 ps->info.fs.early_fragment_test &&
944 !dsa_order_invariant.pass_set)
945 return false;
946
947 /* Determine if out-of-order rasterization should be disabled
948 * when occlusion queries are used.
949 */
950 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
951 !dsa_order_invariant.pass_set;
952 }
953
954 /* No color buffers are enabled for writing. */
955 if (!colormask)
956 return true;
957
958 unsigned blendmask = colormask & blend->blend_enable_4bit;
959
960 if (blendmask) {
961 /* Only commutative blending. */
962 if (blendmask & ~blend->commutative_4bit)
963 return false;
964
965 if (!dsa_order_invariant.pass_set)
966 return false;
967 }
968
969 if (colormask & ~blendmask)
970 return false;
971
972 return true;
973 }
974
975 static void
976 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
977 struct radv_blend_state *blend,
978 const VkGraphicsPipelineCreateInfo *pCreateInfo)
979 {
980 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
981 struct radv_multisample_state *ms = &pipeline->graphics.ms;
982 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
983 bool out_of_order_rast = false;
984 int ps_iter_samples = 1;
985 uint32_t mask = 0xffff;
986
987 if (vkms)
988 ms->num_samples = vkms->rasterizationSamples;
989 else
990 ms->num_samples = 1;
991
992 if (vkms)
993 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
994 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
995 ps_iter_samples = ms->num_samples;
996 }
997
998 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
999 ms->pa_sc_aa_config = 0;
1000 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1001 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1002 ms->pa_sc_mode_cntl_1 =
1003 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1004 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1005 /* always 1: */
1006 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1007 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1008 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1009 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1010 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1011 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1012 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1013 S_028A48_VPORT_SCISSOR_ENABLE(1);
1014
1015 if (ms->num_samples > 1) {
1016 unsigned log_samples = util_logbase2(ms->num_samples);
1017 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1018 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1019 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1020 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1021 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1022 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1023 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1024 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1025 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1026 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1027 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1028 if (ps_iter_samples > 1)
1029 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1030 }
1031
1032 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1033 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1034 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1035 /* Out-of-order rasterization is explicitly enabled by the
1036 * application.
1037 */
1038 out_of_order_rast = true;
1039 } else {
1040 /* Determine if the driver can enable out-of-order
1041 * rasterization internally.
1042 */
1043 out_of_order_rast =
1044 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1045 }
1046
1047 if (out_of_order_rast) {
1048 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
1049 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
1050 }
1051
1052 if (vkms && vkms->pSampleMask) {
1053 mask = vkms->pSampleMask[0] & 0xffff;
1054 }
1055
1056 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1057 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1058 }
1059
1060 static bool
1061 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1062 {
1063 switch (topology) {
1064 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1065 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1066 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1067 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1068 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1069 return false;
1070 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1071 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1072 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1073 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1074 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1075 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1076 return true;
1077 default:
1078 unreachable("unhandled primitive type");
1079 }
1080 }
1081
1082 static uint32_t
1083 si_translate_prim(enum VkPrimitiveTopology topology)
1084 {
1085 switch (topology) {
1086 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1087 return V_008958_DI_PT_POINTLIST;
1088 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1089 return V_008958_DI_PT_LINELIST;
1090 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1091 return V_008958_DI_PT_LINESTRIP;
1092 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1093 return V_008958_DI_PT_TRILIST;
1094 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1095 return V_008958_DI_PT_TRISTRIP;
1096 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1097 return V_008958_DI_PT_TRIFAN;
1098 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1099 return V_008958_DI_PT_LINELIST_ADJ;
1100 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1101 return V_008958_DI_PT_LINESTRIP_ADJ;
1102 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1103 return V_008958_DI_PT_TRILIST_ADJ;
1104 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1105 return V_008958_DI_PT_TRISTRIP_ADJ;
1106 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1107 return V_008958_DI_PT_PATCH;
1108 default:
1109 assert(0);
1110 return 0;
1111 }
1112 }
1113
1114 static uint32_t
1115 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1116 {
1117 switch (gl_prim) {
1118 case 0: /* GL_POINTS */
1119 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1120 case 1: /* GL_LINES */
1121 case 3: /* GL_LINE_STRIP */
1122 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1123 case 0x8E7A: /* GL_ISOLINES */
1124 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1125
1126 case 4: /* GL_TRIANGLES */
1127 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1128 case 5: /* GL_TRIANGLE_STRIP */
1129 case 7: /* GL_QUADS */
1130 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1131 default:
1132 assert(0);
1133 return 0;
1134 }
1135 }
1136
1137 static uint32_t
1138 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1139 {
1140 switch (topology) {
1141 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1142 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1143 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1144 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1145 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1146 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1147 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1148 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1149 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1152 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1154 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1155 default:
1156 assert(0);
1157 return 0;
1158 }
1159 }
1160
1161 static unsigned si_map_swizzle(unsigned swizzle)
1162 {
1163 switch (swizzle) {
1164 case VK_SWIZZLE_Y:
1165 return V_008F0C_SQ_SEL_Y;
1166 case VK_SWIZZLE_Z:
1167 return V_008F0C_SQ_SEL_Z;
1168 case VK_SWIZZLE_W:
1169 return V_008F0C_SQ_SEL_W;
1170 case VK_SWIZZLE_0:
1171 return V_008F0C_SQ_SEL_0;
1172 case VK_SWIZZLE_1:
1173 return V_008F0C_SQ_SEL_1;
1174 default: /* VK_SWIZZLE_X */
1175 return V_008F0C_SQ_SEL_X;
1176 }
1177 }
1178
1179
1180 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1181 {
1182 switch(state) {
1183 case VK_DYNAMIC_STATE_VIEWPORT:
1184 return RADV_DYNAMIC_VIEWPORT;
1185 case VK_DYNAMIC_STATE_SCISSOR:
1186 return RADV_DYNAMIC_SCISSOR;
1187 case VK_DYNAMIC_STATE_LINE_WIDTH:
1188 return RADV_DYNAMIC_LINE_WIDTH;
1189 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1190 return RADV_DYNAMIC_DEPTH_BIAS;
1191 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1192 return RADV_DYNAMIC_BLEND_CONSTANTS;
1193 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1194 return RADV_DYNAMIC_DEPTH_BOUNDS;
1195 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1196 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1197 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1198 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1199 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1200 return RADV_DYNAMIC_STENCIL_REFERENCE;
1201 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1202 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1203 default:
1204 unreachable("Unhandled dynamic state");
1205 }
1206 }
1207
1208 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1209 {
1210 uint32_t states = RADV_DYNAMIC_ALL;
1211
1212 /* If rasterization is disabled we do not care about any of the dynamic states,
1213 * since they are all rasterization related only. */
1214 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1215 return 0;
1216
1217 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1218 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1219
1220 if (!pCreateInfo->pDepthStencilState ||
1221 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1222 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1223
1224 if (!pCreateInfo->pDepthStencilState ||
1225 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1226 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1227 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1228 RADV_DYNAMIC_STENCIL_REFERENCE);
1229
1230 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1231 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1232
1233 /* TODO: blend constants & line width. */
1234
1235 return states;
1236 }
1237
1238
1239 static void
1240 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1241 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1242 {
1243 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1244 uint32_t states = needed_states;
1245 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1246 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1247
1248 pipeline->dynamic_state = default_dynamic_state;
1249 pipeline->graphics.needed_dynamic_state = needed_states;
1250
1251 if (pCreateInfo->pDynamicState) {
1252 /* Remove all of the states that are marked as dynamic */
1253 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1254 for (uint32_t s = 0; s < count; s++)
1255 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1256 }
1257
1258 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1259
1260 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1261 assert(pCreateInfo->pViewportState);
1262
1263 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1264 if (states & RADV_DYNAMIC_VIEWPORT) {
1265 typed_memcpy(dynamic->viewport.viewports,
1266 pCreateInfo->pViewportState->pViewports,
1267 pCreateInfo->pViewportState->viewportCount);
1268 }
1269 }
1270
1271 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1272 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1273 if (states & RADV_DYNAMIC_SCISSOR) {
1274 typed_memcpy(dynamic->scissor.scissors,
1275 pCreateInfo->pViewportState->pScissors,
1276 pCreateInfo->pViewportState->scissorCount);
1277 }
1278 }
1279
1280 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1281 assert(pCreateInfo->pRasterizationState);
1282 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1283 }
1284
1285 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1286 assert(pCreateInfo->pRasterizationState);
1287 dynamic->depth_bias.bias =
1288 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1289 dynamic->depth_bias.clamp =
1290 pCreateInfo->pRasterizationState->depthBiasClamp;
1291 dynamic->depth_bias.slope =
1292 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1293 }
1294
1295 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1296 *
1297 * pColorBlendState is [...] NULL if the pipeline has rasterization
1298 * disabled or if the subpass of the render pass the pipeline is
1299 * created against does not use any color attachments.
1300 */
1301 bool uses_color_att = false;
1302 for (unsigned i = 0; i < subpass->color_count; ++i) {
1303 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1304 uses_color_att = true;
1305 break;
1306 }
1307 }
1308
1309 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1310 assert(pCreateInfo->pColorBlendState);
1311 typed_memcpy(dynamic->blend_constants,
1312 pCreateInfo->pColorBlendState->blendConstants, 4);
1313 }
1314
1315 /* If there is no depthstencil attachment, then don't read
1316 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1317 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1318 * no need to override the depthstencil defaults in
1319 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1320 *
1321 * Section 9.2 of the Vulkan 1.0.15 spec says:
1322 *
1323 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1324 * disabled or if the subpass of the render pass the pipeline is created
1325 * against does not use a depth/stencil attachment.
1326 */
1327 if (needed_states &&
1328 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1329 assert(pCreateInfo->pDepthStencilState);
1330
1331 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1332 dynamic->depth_bounds.min =
1333 pCreateInfo->pDepthStencilState->minDepthBounds;
1334 dynamic->depth_bounds.max =
1335 pCreateInfo->pDepthStencilState->maxDepthBounds;
1336 }
1337
1338 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1339 dynamic->stencil_compare_mask.front =
1340 pCreateInfo->pDepthStencilState->front.compareMask;
1341 dynamic->stencil_compare_mask.back =
1342 pCreateInfo->pDepthStencilState->back.compareMask;
1343 }
1344
1345 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1346 dynamic->stencil_write_mask.front =
1347 pCreateInfo->pDepthStencilState->front.writeMask;
1348 dynamic->stencil_write_mask.back =
1349 pCreateInfo->pDepthStencilState->back.writeMask;
1350 }
1351
1352 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1353 dynamic->stencil_reference.front =
1354 pCreateInfo->pDepthStencilState->front.reference;
1355 dynamic->stencil_reference.back =
1356 pCreateInfo->pDepthStencilState->back.reference;
1357 }
1358 }
1359
1360 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1361 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1362 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1363 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1364 typed_memcpy(dynamic->discard_rectangle.rectangles,
1365 discard_rectangle_info->pDiscardRectangles,
1366 discard_rectangle_info->discardRectangleCount);
1367 }
1368
1369 pipeline->dynamic_state.mask = states;
1370 }
1371
1372 static struct radv_gs_state
1373 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1374 const struct radv_pipeline *pipeline)
1375 {
1376 struct radv_gs_state gs = {0};
1377 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1378 struct radv_es_output_info *es_info;
1379 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1380 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1381 else
1382 es_info = radv_pipeline_has_tess(pipeline) ?
1383 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1384 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1385
1386 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1387 bool uses_adjacency;
1388 switch(pCreateInfo->pInputAssemblyState->topology) {
1389 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1390 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1391 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1392 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1393 uses_adjacency = true;
1394 break;
1395 default:
1396 uses_adjacency = false;
1397 break;
1398 }
1399
1400 /* All these are in dwords: */
1401 /* We can't allow using the whole LDS, because GS waves compete with
1402 * other shader stages for LDS space. */
1403 const unsigned max_lds_size = 8 * 1024;
1404 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1405 unsigned esgs_lds_size;
1406
1407 /* All these are per subgroup: */
1408 const unsigned max_out_prims = 32 * 1024;
1409 const unsigned max_es_verts = 255;
1410 const unsigned ideal_gs_prims = 64;
1411 unsigned max_gs_prims, gs_prims;
1412 unsigned min_es_verts, es_verts, worst_case_es_verts;
1413
1414 if (uses_adjacency || gs_num_invocations > 1)
1415 max_gs_prims = 127 / gs_num_invocations;
1416 else
1417 max_gs_prims = 255;
1418
1419 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1420 * Make sure we don't go over the maximum value.
1421 */
1422 if (gs_info->gs.vertices_out > 0) {
1423 max_gs_prims = MIN2(max_gs_prims,
1424 max_out_prims /
1425 (gs_info->gs.vertices_out * gs_num_invocations));
1426 }
1427 assert(max_gs_prims > 0);
1428
1429 /* If the primitive has adjacency, halve the number of vertices
1430 * that will be reused in multiple primitives.
1431 */
1432 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1433
1434 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1435 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1436
1437 /* Compute ESGS LDS size based on the worst case number of ES vertices
1438 * needed to create the target number of GS prims per subgroup.
1439 */
1440 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1441
1442 /* If total LDS usage is too big, refactor partitions based on ratio
1443 * of ESGS item sizes.
1444 */
1445 if (esgs_lds_size > max_lds_size) {
1446 /* Our target GS Prims Per Subgroup was too large. Calculate
1447 * the maximum number of GS Prims Per Subgroup that will fit
1448 * into LDS, capped by the maximum that the hardware can support.
1449 */
1450 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1451 max_gs_prims);
1452 assert(gs_prims > 0);
1453 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1454 max_es_verts);
1455
1456 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1457 assert(esgs_lds_size <= max_lds_size);
1458 }
1459
1460 /* Now calculate remaining ESGS information. */
1461 if (esgs_lds_size)
1462 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1463 else
1464 es_verts = max_es_verts;
1465
1466 /* Vertices for adjacency primitives are not always reused, so restore
1467 * it for ES_VERTS_PER_SUBGRP.
1468 */
1469 min_es_verts = gs_info->gs.vertices_in;
1470
1471 /* For normal primitives, the VGT only checks if they are past the ES
1472 * verts per subgroup after allocating a full GS primitive and if they
1473 * are, kick off a new subgroup. But if those additional ES verts are
1474 * unique (e.g. not reused) we need to make sure there is enough LDS
1475 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1476 */
1477 es_verts -= min_es_verts - 1;
1478
1479 uint32_t es_verts_per_subgroup = es_verts;
1480 uint32_t gs_prims_per_subgroup = gs_prims;
1481 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1482 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1483 gs.lds_size = align(esgs_lds_size, 128) / 128;
1484 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1485 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1486 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1487 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1488 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1489 assert(max_prims_per_subgroup <= max_out_prims);
1490
1491 return gs;
1492 }
1493
1494 static void
1495 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1496 {
1497 struct radv_device *device = pipeline->device;
1498 unsigned num_se = device->physical_device->rad_info.max_se;
1499 unsigned wave_size = 64;
1500 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1501 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1502 unsigned alignment = 256 * num_se;
1503 /* The maximum size is 63.999 MB per SE. */
1504 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1505 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1506
1507 /* Calculate the minimum size. */
1508 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1509 wave_size, alignment);
1510 /* These are recommended sizes, not minimum sizes. */
1511 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1512 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1513 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1514 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1515
1516 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1517 esgs_ring_size = align(esgs_ring_size, alignment);
1518 gsvs_ring_size = align(gsvs_ring_size, alignment);
1519
1520 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1521 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1522
1523 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1524 }
1525
1526 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1527 unsigned *lds_size)
1528 {
1529 /* If tessellation is all offchip and on-chip GS isn't used, this
1530 * workaround is not needed.
1531 */
1532 return;
1533
1534 /* SPI barrier management bug:
1535 * Make sure we have at least 4k of LDS in use to avoid the bug.
1536 * It applies to workgroup sizes of more than one wavefront.
1537 */
1538 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1539 device->physical_device->rad_info.family == CHIP_KABINI ||
1540 device->physical_device->rad_info.family == CHIP_MULLINS)
1541 *lds_size = MAX2(*lds_size, 8);
1542 }
1543
1544 struct radv_shader_variant *
1545 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1546 {
1547 if (pipeline->shaders[MESA_SHADER_VERTEX])
1548 return pipeline->shaders[MESA_SHADER_VERTEX];
1549 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1550 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1551 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1552 }
1553
1554 static struct radv_shader_variant *
1555 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1556 {
1557 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1558 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1559 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1560 }
1561
1562 static struct radv_tessellation_state
1563 calculate_tess_state(struct radv_pipeline *pipeline,
1564 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1565 {
1566 unsigned num_tcs_input_cp;
1567 unsigned num_tcs_output_cp;
1568 unsigned lds_size;
1569 unsigned num_patches;
1570 struct radv_tessellation_state tess = {0};
1571
1572 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1573 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1574 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1575
1576 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1577
1578 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1579 assert(lds_size <= 65536);
1580 lds_size = align(lds_size, 512) / 512;
1581 } else {
1582 assert(lds_size <= 32768);
1583 lds_size = align(lds_size, 256) / 256;
1584 }
1585 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1586
1587 tess.lds_size = lds_size;
1588
1589 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1590 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1591 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1592 tess.num_patches = num_patches;
1593
1594 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1595 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1596
1597 switch (tes->info.tes.primitive_mode) {
1598 case GL_TRIANGLES:
1599 type = V_028B6C_TESS_TRIANGLE;
1600 break;
1601 case GL_QUADS:
1602 type = V_028B6C_TESS_QUAD;
1603 break;
1604 case GL_ISOLINES:
1605 type = V_028B6C_TESS_ISOLINE;
1606 break;
1607 }
1608
1609 switch (tes->info.tes.spacing) {
1610 case TESS_SPACING_EQUAL:
1611 partitioning = V_028B6C_PART_INTEGER;
1612 break;
1613 case TESS_SPACING_FRACTIONAL_ODD:
1614 partitioning = V_028B6C_PART_FRAC_ODD;
1615 break;
1616 case TESS_SPACING_FRACTIONAL_EVEN:
1617 partitioning = V_028B6C_PART_FRAC_EVEN;
1618 break;
1619 default:
1620 break;
1621 }
1622
1623 bool ccw = tes->info.tes.ccw;
1624 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1625 vk_find_struct_const(pCreateInfo->pTessellationState,
1626 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1627
1628 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1629 ccw = !ccw;
1630
1631 if (tes->info.tes.point_mode)
1632 topology = V_028B6C_OUTPUT_POINT;
1633 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1634 topology = V_028B6C_OUTPUT_LINE;
1635 else if (ccw)
1636 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1637 else
1638 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1639
1640 if (pipeline->device->has_distributed_tess) {
1641 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1642 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1643 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1644 else
1645 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1646 } else
1647 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1648
1649 tess.tf_param = S_028B6C_TYPE(type) |
1650 S_028B6C_PARTITIONING(partitioning) |
1651 S_028B6C_TOPOLOGY(topology) |
1652 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1653
1654 return tess;
1655 }
1656
1657 static const struct radv_prim_vertex_count prim_size_table[] = {
1658 [V_008958_DI_PT_NONE] = {0, 0},
1659 [V_008958_DI_PT_POINTLIST] = {1, 1},
1660 [V_008958_DI_PT_LINELIST] = {2, 2},
1661 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1662 [V_008958_DI_PT_TRILIST] = {3, 3},
1663 [V_008958_DI_PT_TRIFAN] = {3, 1},
1664 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1665 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1666 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1667 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1668 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1669 [V_008958_DI_PT_RECTLIST] = {3, 3},
1670 [V_008958_DI_PT_LINELOOP] = {2, 1},
1671 [V_008958_DI_PT_POLYGON] = {3, 1},
1672 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1673 };
1674
1675 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1676 {
1677 if (radv_pipeline_has_gs(pipeline))
1678 return &pipeline->gs_copy_shader->info.vs.outinfo;
1679 else if (radv_pipeline_has_tess(pipeline))
1680 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1681 else
1682 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1683 }
1684
1685 static void
1686 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1687 {
1688 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1689 int shader_count = 0;
1690
1691 if(shaders[MESA_SHADER_FRAGMENT]) {
1692 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1693 }
1694 if(shaders[MESA_SHADER_GEOMETRY]) {
1695 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1696 }
1697 if(shaders[MESA_SHADER_TESS_EVAL]) {
1698 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1699 }
1700 if(shaders[MESA_SHADER_TESS_CTRL]) {
1701 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1702 }
1703 if(shaders[MESA_SHADER_VERTEX]) {
1704 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1705 }
1706
1707 for (int i = 1; i < shader_count; ++i) {
1708 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1709 ordered_shaders[i - 1]);
1710
1711 nir_remove_dead_variables(ordered_shaders[i],
1712 nir_var_shader_out);
1713 nir_remove_dead_variables(ordered_shaders[i - 1],
1714 nir_var_shader_in);
1715
1716 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1717 ordered_shaders[i - 1]);
1718
1719 nir_compact_varyings(ordered_shaders[i],
1720 ordered_shaders[i - 1], true);
1721
1722 if (progress) {
1723 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1724 ac_lower_indirect_derefs(ordered_shaders[i],
1725 pipeline->device->physical_device->rad_info.chip_class);
1726 }
1727 radv_optimize_nir(ordered_shaders[i]);
1728
1729 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1730 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1731 pipeline->device->physical_device->rad_info.chip_class);
1732 }
1733 radv_optimize_nir(ordered_shaders[i - 1]);
1734 }
1735 }
1736 }
1737
1738
1739 static struct radv_pipeline_key
1740 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1741 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1742 const struct radv_blend_state *blend,
1743 bool has_view_index)
1744 {
1745 const VkPipelineVertexInputStateCreateInfo *input_state =
1746 pCreateInfo->pVertexInputState;
1747 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
1748 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1749
1750 struct radv_pipeline_key key;
1751 memset(&key, 0, sizeof(key));
1752
1753 key.has_multiview_view_index = has_view_index;
1754
1755 uint32_t binding_input_rate = 0;
1756 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
1757 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1758 if (input_state->pVertexBindingDescriptions[i].inputRate) {
1759 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
1760 binding_input_rate |= 1u << binding;
1761 instance_rate_divisors[binding] = 1;
1762 }
1763 }
1764 if (divisor_state) {
1765 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
1766 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
1767 divisor_state->pVertexBindingDivisors[i].divisor;
1768 }
1769 }
1770
1771 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1772 unsigned binding;
1773 binding = input_state->pVertexAttributeDescriptions[i].binding;
1774 if (binding_input_rate & (1u << binding)) {
1775 unsigned location = input_state->pVertexAttributeDescriptions[i].location;
1776 key.instance_rate_inputs |= 1u << location;
1777 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
1778 }
1779 }
1780
1781 if (pCreateInfo->pTessellationState)
1782 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1783
1784
1785 if (pCreateInfo->pMultisampleState &&
1786 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1787 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1788 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1789 key.multisample = true;
1790 key.log2_num_samples = util_logbase2(num_samples);
1791 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1792 }
1793
1794 key.col_format = blend->spi_shader_col_format;
1795 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1796 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1797
1798 return key;
1799 }
1800
1801 static void
1802 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1803 const struct radv_pipeline_key *key,
1804 nir_shader **nir)
1805 {
1806 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1807 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
1808 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
1809
1810 if (nir[MESA_SHADER_TESS_CTRL]) {
1811 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1812 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1813 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1814 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1815
1816 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1817 }
1818
1819 if (nir[MESA_SHADER_GEOMETRY]) {
1820 if (nir[MESA_SHADER_TESS_CTRL])
1821 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1822 else
1823 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1824 }
1825
1826 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1827 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1828
1829 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1830 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1831 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1832 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1833 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1834 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1835 }
1836
1837 static void
1838 merge_tess_info(struct shader_info *tes_info,
1839 const struct shader_info *tcs_info)
1840 {
1841 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1842 *
1843 * "PointMode. Controls generation of points rather than triangles
1844 * or lines. This functionality defaults to disabled, and is
1845 * enabled if either shader stage includes the execution mode.
1846 *
1847 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1848 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1849 * and OutputVertices, it says:
1850 *
1851 * "One mode must be set in at least one of the tessellation
1852 * shader stages."
1853 *
1854 * So, the fields can be set in either the TCS or TES, but they must
1855 * agree if set in both. Our backend looks at TES, so bitwise-or in
1856 * the values from the TCS.
1857 */
1858 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1859 tes_info->tess.tcs_vertices_out == 0 ||
1860 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1861 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1862
1863 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1864 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1865 tcs_info->tess.spacing == tes_info->tess.spacing);
1866 tes_info->tess.spacing |= tcs_info->tess.spacing;
1867
1868 assert(tcs_info->tess.primitive_mode == 0 ||
1869 tes_info->tess.primitive_mode == 0 ||
1870 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1871 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1872 tes_info->tess.ccw |= tcs_info->tess.ccw;
1873 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1874 }
1875
1876 static
1877 void radv_create_shaders(struct radv_pipeline *pipeline,
1878 struct radv_device *device,
1879 struct radv_pipeline_cache *cache,
1880 struct radv_pipeline_key key,
1881 const VkPipelineShaderStageCreateInfo **pStages)
1882 {
1883 struct radv_shader_module fs_m = {0};
1884 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1885 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1886 void *codes[MESA_SHADER_STAGES] = {0};
1887 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1888 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1889 unsigned char hash[20], gs_copy_hash[20];
1890
1891 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1892 if (pStages[i]) {
1893 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1894 if (modules[i]->nir)
1895 _mesa_sha1_compute(modules[i]->nir->info.name,
1896 strlen(modules[i]->nir->info.name),
1897 modules[i]->sha1);
1898 }
1899 }
1900
1901 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1902 memcpy(gs_copy_hash, hash, 20);
1903 gs_copy_hash[0] ^= 1;
1904
1905 if (modules[MESA_SHADER_GEOMETRY]) {
1906 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1907 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1908 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1909 }
1910
1911 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1912 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1913 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1914 if (pipeline->shaders[i])
1915 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1916 }
1917 return;
1918 }
1919
1920 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1921 nir_builder fs_b;
1922 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1923 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1924 fs_m.nir = fs_b.shader;
1925 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1926 }
1927
1928 /* Determine first and last stage. */
1929 unsigned first = MESA_SHADER_STAGES;
1930 unsigned last = 0;
1931 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1932 if (!pStages[i])
1933 continue;
1934 if (first == MESA_SHADER_STAGES)
1935 first = i;
1936 last = i;
1937 }
1938
1939 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1940 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1941
1942 if (!modules[i])
1943 continue;
1944
1945 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1946 stage ? stage->pName : "main", i,
1947 stage ? stage->pSpecializationInfo : NULL);
1948 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1949
1950 /* We don't want to alter meta shaders IR directly so clone it
1951 * first.
1952 */
1953 if (nir[i]->info.name) {
1954 nir[i] = nir_shader_clone(NULL, nir[i]);
1955 }
1956
1957 if (first != last) {
1958 nir_variable_mode mask = 0;
1959
1960 if (i != first)
1961 mask = mask | nir_var_shader_in;
1962
1963 if (i != last)
1964 mask = mask | nir_var_shader_out;
1965
1966 nir_lower_io_to_scalar_early(nir[i], mask);
1967 radv_optimize_nir(nir[i]);
1968 }
1969 }
1970
1971 if (nir[MESA_SHADER_TESS_CTRL]) {
1972 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1973 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1974 }
1975
1976 radv_link_shaders(pipeline, nir);
1977
1978 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1979 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1980 nir_print_shader(nir[i], stderr);
1981 }
1982
1983 radv_fill_shader_keys(keys, &key, nir);
1984
1985 if (nir[MESA_SHADER_FRAGMENT]) {
1986 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1987 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1988 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1989 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1990 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1991 }
1992
1993 /* TODO: These are no longer used as keys we should refactor this */
1994 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1995 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1996 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
1997 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1998 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1999 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2000 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
2001 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2002 }
2003
2004 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2005 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2006 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2007 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2008 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2009 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2010 pipeline->layout,
2011 &key, &codes[MESA_SHADER_TESS_CTRL],
2012 &code_sizes[MESA_SHADER_TESS_CTRL]);
2013 }
2014 modules[MESA_SHADER_VERTEX] = NULL;
2015 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2016 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2017 }
2018
2019 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2020 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2021 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2022 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2023 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2024 pipeline->layout,
2025 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
2026 &code_sizes[MESA_SHADER_GEOMETRY]);
2027 }
2028 modules[pre_stage] = NULL;
2029 }
2030
2031 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2032 if(modules[i] && !pipeline->shaders[i]) {
2033 if (i == MESA_SHADER_TESS_CTRL) {
2034 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2035 }
2036 if (i == MESA_SHADER_TESS_EVAL) {
2037 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2038 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2039 }
2040 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
2041 pipeline->layout,
2042 keys + i, &codes[i],
2043 &code_sizes[i]);
2044 }
2045 }
2046
2047 if(modules[MESA_SHADER_GEOMETRY]) {
2048 void *gs_copy_code = NULL;
2049 unsigned gs_copy_code_size = 0;
2050 if (!pipeline->gs_copy_shader) {
2051 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2052 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
2053 &gs_copy_code_size,
2054 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2055 }
2056
2057 if (pipeline->gs_copy_shader) {
2058 void *code[MESA_SHADER_STAGES] = {0};
2059 unsigned code_size[MESA_SHADER_STAGES] = {0};
2060 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2061
2062 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
2063 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
2064 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2065
2066 radv_pipeline_cache_insert_shaders(device, cache,
2067 gs_copy_hash,
2068 variants,
2069 (const void**)code,
2070 code_size);
2071 }
2072 free(gs_copy_code);
2073 }
2074
2075 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2076 (const void**)codes, code_sizes);
2077
2078 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2079 free(codes[i]);
2080 if (modules[i]) {
2081 if (!pipeline->device->keep_shader_info)
2082 ralloc_free(nir[i]);
2083
2084 if (radv_can_dump_shader_stats(device, modules[i]))
2085 radv_shader_dump_stats(device,
2086 pipeline->shaders[i],
2087 i, stderr);
2088 }
2089 }
2090
2091 if (fs_m.nir)
2092 ralloc_free(fs_m.nir);
2093 }
2094
2095 static uint32_t
2096 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2097 gl_shader_stage stage, enum chip_class chip_class)
2098 {
2099 bool has_gs = radv_pipeline_has_gs(pipeline);
2100 bool has_tess = radv_pipeline_has_tess(pipeline);
2101 switch (stage) {
2102 case MESA_SHADER_FRAGMENT:
2103 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2104 case MESA_SHADER_VERTEX:
2105 if (chip_class >= GFX9) {
2106 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2107 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2108 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2109 }
2110 if (has_tess)
2111 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2112 else
2113 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
2114 case MESA_SHADER_GEOMETRY:
2115 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2116 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2117 case MESA_SHADER_COMPUTE:
2118 return R_00B900_COMPUTE_USER_DATA_0;
2119 case MESA_SHADER_TESS_CTRL:
2120 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2121 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2122 case MESA_SHADER_TESS_EVAL:
2123 if (chip_class >= GFX9) {
2124 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2125 R_00B130_SPI_SHADER_USER_DATA_VS_0;
2126 }
2127 if (has_gs)
2128 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2129 else
2130 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2131 default:
2132 unreachable("unknown shader");
2133 }
2134 }
2135
2136 struct radv_bin_size_entry {
2137 unsigned bpp;
2138 VkExtent2D extent;
2139 };
2140
2141 static VkExtent2D
2142 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2143 {
2144 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2145 {
2146 /* One RB / SE */
2147 {
2148 /* One shader engine */
2149 { 0, {128, 128}},
2150 { 1, { 64, 128}},
2151 { 2, { 32, 128}},
2152 { 3, { 16, 128}},
2153 { 17, { 0, 0}},
2154 { UINT_MAX, { 0, 0}},
2155 },
2156 {
2157 /* Two shader engines */
2158 { 0, {128, 128}},
2159 { 2, { 64, 128}},
2160 { 3, { 32, 128}},
2161 { 5, { 16, 128}},
2162 { 17, { 0, 0}},
2163 { UINT_MAX, { 0, 0}},
2164 },
2165 {
2166 /* Four shader engines */
2167 { 0, {128, 128}},
2168 { 3, { 64, 128}},
2169 { 5, { 16, 128}},
2170 { 17, { 0, 0}},
2171 { UINT_MAX, { 0, 0}},
2172 },
2173 },
2174 {
2175 /* Two RB / SE */
2176 {
2177 /* One shader engine */
2178 { 0, {128, 128}},
2179 { 2, { 64, 128}},
2180 { 3, { 32, 128}},
2181 { 5, { 16, 128}},
2182 { 33, { 0, 0}},
2183 { UINT_MAX, { 0, 0}},
2184 },
2185 {
2186 /* Two shader engines */
2187 { 0, {128, 128}},
2188 { 3, { 64, 128}},
2189 { 5, { 32, 128}},
2190 { 9, { 16, 128}},
2191 { 33, { 0, 0}},
2192 { UINT_MAX, { 0, 0}},
2193 },
2194 {
2195 /* Four shader engines */
2196 { 0, {256, 256}},
2197 { 2, {128, 256}},
2198 { 3, {128, 128}},
2199 { 5, { 64, 128}},
2200 { 9, { 16, 128}},
2201 { 33, { 0, 0}},
2202 { UINT_MAX, { 0, 0}},
2203 },
2204 },
2205 {
2206 /* Four RB / SE */
2207 {
2208 /* One shader engine */
2209 { 0, {128, 256}},
2210 { 2, {128, 128}},
2211 { 3, { 64, 128}},
2212 { 5, { 32, 128}},
2213 { 9, { 16, 128}},
2214 { 33, { 0, 0}},
2215 { UINT_MAX, { 0, 0}},
2216 },
2217 {
2218 /* Two shader engines */
2219 { 0, {256, 256}},
2220 { 2, {128, 256}},
2221 { 3, {128, 128}},
2222 { 5, { 64, 128}},
2223 { 9, { 32, 128}},
2224 { 17, { 16, 128}},
2225 { 33, { 0, 0}},
2226 { UINT_MAX, { 0, 0}},
2227 },
2228 {
2229 /* Four shader engines */
2230 { 0, {256, 512}},
2231 { 2, {256, 256}},
2232 { 3, {128, 256}},
2233 { 5, {128, 128}},
2234 { 9, { 64, 128}},
2235 { 17, { 16, 128}},
2236 { 33, { 0, 0}},
2237 { UINT_MAX, { 0, 0}},
2238 },
2239 },
2240 };
2241 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2242 {
2243 // One RB / SE
2244 {
2245 // One shader engine
2246 { 0, {128, 256}},
2247 { 2, {128, 128}},
2248 { 4, { 64, 128}},
2249 { 7, { 32, 128}},
2250 { 13, { 16, 128}},
2251 { 49, { 0, 0}},
2252 { UINT_MAX, { 0, 0}},
2253 },
2254 {
2255 // Two shader engines
2256 { 0, {256, 256}},
2257 { 2, {128, 256}},
2258 { 4, {128, 128}},
2259 { 7, { 64, 128}},
2260 { 13, { 32, 128}},
2261 { 25, { 16, 128}},
2262 { 49, { 0, 0}},
2263 { UINT_MAX, { 0, 0}},
2264 },
2265 {
2266 // Four shader engines
2267 { 0, {256, 512}},
2268 { 2, {256, 256}},
2269 { 4, {128, 256}},
2270 { 7, {128, 128}},
2271 { 13, { 64, 128}},
2272 { 25, { 16, 128}},
2273 { 49, { 0, 0}},
2274 { UINT_MAX, { 0, 0}},
2275 },
2276 },
2277 {
2278 // Two RB / SE
2279 {
2280 // One shader engine
2281 { 0, {256, 256}},
2282 { 2, {128, 256}},
2283 { 4, {128, 128}},
2284 { 7, { 64, 128}},
2285 { 13, { 32, 128}},
2286 { 25, { 16, 128}},
2287 { 97, { 0, 0}},
2288 { UINT_MAX, { 0, 0}},
2289 },
2290 {
2291 // Two shader engines
2292 { 0, {256, 512}},
2293 { 2, {256, 256}},
2294 { 4, {128, 256}},
2295 { 7, {128, 128}},
2296 { 13, { 64, 128}},
2297 { 25, { 32, 128}},
2298 { 49, { 16, 128}},
2299 { 97, { 0, 0}},
2300 { UINT_MAX, { 0, 0}},
2301 },
2302 {
2303 // Four shader engines
2304 { 0, {512, 512}},
2305 { 2, {256, 512}},
2306 { 4, {256, 256}},
2307 { 7, {128, 256}},
2308 { 13, {128, 128}},
2309 { 25, { 64, 128}},
2310 { 49, { 16, 128}},
2311 { 97, { 0, 0}},
2312 { UINT_MAX, { 0, 0}},
2313 },
2314 },
2315 {
2316 // Four RB / SE
2317 {
2318 // One shader engine
2319 { 0, {256, 512}},
2320 { 2, {256, 256}},
2321 { 4, {128, 256}},
2322 { 7, {128, 128}},
2323 { 13, { 64, 128}},
2324 { 25, { 32, 128}},
2325 { 49, { 16, 128}},
2326 { UINT_MAX, { 0, 0}},
2327 },
2328 {
2329 // Two shader engines
2330 { 0, {512, 512}},
2331 { 2, {256, 512}},
2332 { 4, {256, 256}},
2333 { 7, {128, 256}},
2334 { 13, {128, 128}},
2335 { 25, { 64, 128}},
2336 { 49, { 32, 128}},
2337 { 97, { 16, 128}},
2338 { UINT_MAX, { 0, 0}},
2339 },
2340 {
2341 // Four shader engines
2342 { 0, {512, 512}},
2343 { 4, {256, 512}},
2344 { 7, {256, 256}},
2345 { 13, {128, 256}},
2346 { 25, {128, 128}},
2347 { 49, { 64, 128}},
2348 { 97, { 16, 128}},
2349 { UINT_MAX, { 0, 0}},
2350 },
2351 },
2352 };
2353
2354 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2355 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2356 VkExtent2D extent = {512, 512};
2357
2358 unsigned log_num_rb_per_se =
2359 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2360 pipeline->device->physical_device->rad_info.max_se);
2361 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2362
2363 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2364 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2365 unsigned effective_samples = total_samples;
2366 unsigned color_bytes_per_pixel = 0;
2367
2368 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2369 if (vkblend) {
2370 for (unsigned i = 0; i < subpass->color_count; i++) {
2371 if (!vkblend->pAttachments[i].colorWriteMask)
2372 continue;
2373
2374 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2375 continue;
2376
2377 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2378 color_bytes_per_pixel += vk_format_get_blocksize(format);
2379 }
2380
2381 /* MSAA images typically don't use all samples all the time. */
2382 if (effective_samples >= 2 && ps_iter_samples <= 1)
2383 effective_samples = 2;
2384 color_bytes_per_pixel *= effective_samples;
2385 }
2386
2387 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2388 while(color_entry->bpp <= color_bytes_per_pixel)
2389 ++color_entry;
2390
2391 extent = color_entry->extent;
2392
2393 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2394 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2395
2396 /* Coefficients taken from AMDVLK */
2397 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2398 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2399 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2400
2401 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2402 while(ds_entry->bpp <= ds_bytes_per_pixel)
2403 ++ds_entry;
2404
2405 extent.width = MIN2(extent.width, ds_entry->extent.width);
2406 extent.height = MIN2(extent.height, ds_entry->extent.height);
2407 }
2408
2409 return extent;
2410 }
2411
2412 static void
2413 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2414 struct radv_pipeline *pipeline,
2415 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2416 {
2417 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2418 return;
2419
2420 uint32_t pa_sc_binner_cntl_0 =
2421 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2422 S_028C44_DISABLE_START_OF_PRIM(1);
2423 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2424
2425 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2426
2427 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2428 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2429 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2430
2431 switch (pipeline->device->physical_device->rad_info.family) {
2432 case CHIP_VEGA10:
2433 case CHIP_VEGA12:
2434 context_states_per_bin = 1;
2435 persistent_states_per_bin = 1;
2436 fpovs_per_batch = 63;
2437 break;
2438 case CHIP_RAVEN:
2439 context_states_per_bin = 6;
2440 persistent_states_per_bin = 32;
2441 fpovs_per_batch = 63;
2442 break;
2443 default:
2444 unreachable("unhandled family while determining binning state.");
2445 }
2446
2447 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2448 pa_sc_binner_cntl_0 =
2449 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2450 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2451 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2452 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2453 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2454 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2455 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2456 S_028C44_DISABLE_START_OF_PRIM(1) |
2457 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2458 S_028C44_OPTIMAL_BIN_SELECTION(1);
2459 }
2460
2461 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2462 pa_sc_binner_cntl_0);
2463 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2464 db_dfsm_control);
2465 }
2466
2467
2468 static void
2469 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2470 struct radv_pipeline *pipeline,
2471 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2472 const struct radv_graphics_pipeline_create_info *extra)
2473 {
2474 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2475 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2476 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2477 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2478 struct radv_render_pass_attachment *attachment = NULL;
2479 uint32_t db_depth_control = 0, db_stencil_control = 0;
2480 uint32_t db_render_control = 0, db_render_override2 = 0;
2481 uint32_t db_render_override = 0;
2482
2483 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2484 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2485
2486 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2487 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2488
2489 if (vkds && has_depth_attachment) {
2490 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2491 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2492 S_028800_ZFUNC(vkds->depthCompareOp) |
2493 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2494
2495 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2496 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2497 }
2498
2499 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2500 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2501 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2502 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2503 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2504 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2505
2506 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2507 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2508 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2509 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2510 }
2511
2512 if (attachment && extra) {
2513 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2514 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2515
2516 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2517 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2518 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2519 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2520 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2521 }
2522
2523 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2524 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2525
2526 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2527 !pCreateInfo->pRasterizationState->depthClampEnable &&
2528 ps->info.info.ps.writes_z) {
2529 /* From VK_EXT_depth_range_unrestricted spec:
2530 *
2531 * "The behavior described in Primitive Clipping still applies.
2532 * If depth clamping is disabled the depth values are still
2533 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2534 * depth clamping is enabled the above equation is ignored and
2535 * the depth values are instead clamped to the VkViewport
2536 * minDepth and maxDepth values, which in the case of this
2537 * extension can be outside of the 0.0 to 1.0 range."
2538 */
2539 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2540 }
2541
2542 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2543 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2544
2545 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2546 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2547 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2548 }
2549
2550 static void
2551 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2552 struct radv_pipeline *pipeline,
2553 const struct radv_blend_state *blend)
2554 {
2555 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2556 radeon_emit_array(cs, blend->cb_blend_control,
2557 8);
2558 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2559 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2560
2561 if (pipeline->device->physical_device->has_rbplus) {
2562
2563 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2564 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2565 }
2566
2567 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2568
2569 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2570 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2571
2572 pipeline->graphics.col_format = blend->spi_shader_col_format;
2573 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
2574 }
2575
2576
2577 static void
2578 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2579 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2580 {
2581 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2582
2583 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2584 S_028810_PS_UCP_MODE(3) |
2585 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2586 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2587 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2588 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2589 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2590
2591 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2592 S_0286D4_FLAT_SHADE_ENA(1) |
2593 S_0286D4_PNT_SPRITE_ENA(1) |
2594 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2595 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2596 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2597 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2598 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2599
2600 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2601 S_028BE4_PIX_CENTER(1) | // TODO verify
2602 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2603 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2604
2605 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2606 S_028814_FACE(vkraster->frontFace) |
2607 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2608 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2609 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2610 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2611 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2612 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2613 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2614 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2615 }
2616
2617
2618 static void
2619 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2620 struct radv_pipeline *pipeline)
2621 {
2622 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2623
2624 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2625 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2626 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2627
2628 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2629 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2630
2631 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2632 uint32_t offset;
2633 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2634 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2635 if (loc->sgpr_idx == -1)
2636 return;
2637 assert(loc->num_sgprs == 1);
2638 assert(!loc->indirect);
2639 switch (pipeline->graphics.ms.num_samples) {
2640 default:
2641 offset = 0;
2642 break;
2643 case 2:
2644 offset = 1;
2645 break;
2646 case 4:
2647 offset = 3;
2648 break;
2649 case 8:
2650 offset = 7;
2651 break;
2652 case 16:
2653 offset = 15;
2654 break;
2655 }
2656
2657 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2658 }
2659 }
2660
2661 static void
2662 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2663 const struct radv_pipeline *pipeline)
2664 {
2665 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2666
2667 uint32_t vgt_primitiveid_en = false;
2668 uint32_t vgt_gs_mode = 0;
2669
2670 if (radv_pipeline_has_gs(pipeline)) {
2671 const struct radv_shader_variant *gs =
2672 pipeline->shaders[MESA_SHADER_GEOMETRY];
2673
2674 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2675 pipeline->device->physical_device->rad_info.chip_class);
2676 } else if (outinfo->export_prim_id) {
2677 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2678 vgt_primitiveid_en = true;
2679 }
2680
2681 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2682 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2683 }
2684
2685 static void
2686 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2687 struct radv_pipeline *pipeline,
2688 struct radv_shader_variant *shader)
2689 {
2690 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2691
2692 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2693 radeon_emit(cs, va >> 8);
2694 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2695 radeon_emit(cs, shader->rsrc1);
2696 radeon_emit(cs, shader->rsrc2);
2697
2698 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2699 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2700 clip_dist_mask = outinfo->clip_dist_mask;
2701 cull_dist_mask = outinfo->cull_dist_mask;
2702 total_mask = clip_dist_mask | cull_dist_mask;
2703 bool misc_vec_ena = outinfo->writes_pointsize ||
2704 outinfo->writes_layer ||
2705 outinfo->writes_viewport_index;
2706
2707 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2708 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2709
2710 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2711 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2712 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2713 V_02870C_SPI_SHADER_4COMP :
2714 V_02870C_SPI_SHADER_NONE) |
2715 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2716 V_02870C_SPI_SHADER_4COMP :
2717 V_02870C_SPI_SHADER_NONE) |
2718 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2719 V_02870C_SPI_SHADER_4COMP :
2720 V_02870C_SPI_SHADER_NONE));
2721
2722 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2723 S_028818_VTX_W0_FMT(1) |
2724 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2725 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2726 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2727
2728 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2729 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2730 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2731 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2732 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2733 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2734 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2735 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2736 cull_dist_mask << 8 |
2737 clip_dist_mask);
2738
2739 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2740 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2741 outinfo->writes_viewport_index);
2742 }
2743
2744 static void
2745 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2746 struct radv_pipeline *pipeline,
2747 struct radv_shader_variant *shader)
2748 {
2749 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2750
2751 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2752 radeon_emit(cs, va >> 8);
2753 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2754 radeon_emit(cs, shader->rsrc1);
2755 radeon_emit(cs, shader->rsrc2);
2756 }
2757
2758 static void
2759 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2760 struct radv_pipeline *pipeline,
2761 struct radv_shader_variant *shader,
2762 const struct radv_tessellation_state *tess)
2763 {
2764 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2765 uint32_t rsrc2 = shader->rsrc2;
2766
2767 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2768 radeon_emit(cs, va >> 8);
2769 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2770
2771 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2772 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2773 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2774 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2775
2776 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2777 radeon_emit(cs, shader->rsrc1);
2778 radeon_emit(cs, rsrc2);
2779 }
2780
2781 static void
2782 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2783 struct radv_pipeline *pipeline,
2784 struct radv_shader_variant *shader,
2785 const struct radv_tessellation_state *tess)
2786 {
2787 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2788
2789 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2790 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2791 radeon_emit(cs, va >> 8);
2792 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2793
2794 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2795 radeon_emit(cs, shader->rsrc1);
2796 radeon_emit(cs, shader->rsrc2 |
2797 S_00B42C_LDS_SIZE(tess->lds_size));
2798 } else {
2799 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2800 radeon_emit(cs, va >> 8);
2801 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2802 radeon_emit(cs, shader->rsrc1);
2803 radeon_emit(cs, shader->rsrc2);
2804 }
2805 }
2806
2807 static void
2808 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2809 struct radv_pipeline *pipeline,
2810 const struct radv_tessellation_state *tess)
2811 {
2812 struct radv_shader_variant *vs;
2813
2814 /* Skip shaders merged into HS/GS */
2815 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2816 if (!vs)
2817 return;
2818
2819 if (vs->info.vs.as_ls)
2820 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2821 else if (vs->info.vs.as_es)
2822 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2823 else
2824 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2825 }
2826
2827 static void
2828 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2829 struct radv_pipeline *pipeline,
2830 const struct radv_tessellation_state *tess)
2831 {
2832 if (!radv_pipeline_has_tess(pipeline))
2833 return;
2834
2835 struct radv_shader_variant *tes, *tcs;
2836
2837 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2838 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2839
2840 if (tes) {
2841 if (tes->info.tes.as_es)
2842 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2843 else
2844 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2845 }
2846
2847 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2848
2849 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2850 tess->tf_param);
2851
2852 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2853 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2854 tess->ls_hs_config);
2855 else
2856 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2857 tess->ls_hs_config);
2858 }
2859
2860 static void
2861 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2862 struct radv_pipeline *pipeline,
2863 const struct radv_gs_state *gs_state)
2864 {
2865 struct radv_shader_variant *gs;
2866 uint64_t va;
2867
2868 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2869 if (!gs)
2870 return;
2871
2872 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2873
2874 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2875 radeon_emit(cs, gsvs_itemsize);
2876 radeon_emit(cs, gsvs_itemsize);
2877 radeon_emit(cs, gsvs_itemsize);
2878
2879 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2880
2881 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2882
2883 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2884 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2885 radeon_emit(cs, gs_vert_itemsize >> 2);
2886 radeon_emit(cs, 0);
2887 radeon_emit(cs, 0);
2888 radeon_emit(cs, 0);
2889
2890 uint32_t gs_num_invocations = gs->info.gs.invocations;
2891 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2892 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2893 S_028B90_ENABLE(gs_num_invocations > 0));
2894
2895 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2896 gs_state->vgt_esgs_ring_itemsize);
2897
2898 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2899
2900 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2901 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2902 radeon_emit(cs, va >> 8);
2903 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2904
2905 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2906 radeon_emit(cs, gs->rsrc1);
2907 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2908
2909 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2910 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2911 } else {
2912 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2913 radeon_emit(cs, va >> 8);
2914 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2915 radeon_emit(cs, gs->rsrc1);
2916 radeon_emit(cs, gs->rsrc2);
2917 }
2918
2919 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2920 }
2921
2922 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2923 {
2924 uint32_t ps_input_cntl;
2925 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2926 ps_input_cntl = S_028644_OFFSET(offset);
2927 if (flat_shade)
2928 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2929 } else {
2930 /* The input is a DEFAULT_VAL constant. */
2931 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2932 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2933 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2934 ps_input_cntl = S_028644_OFFSET(0x20) |
2935 S_028644_DEFAULT_VAL(offset);
2936 }
2937 return ps_input_cntl;
2938 }
2939
2940 static void
2941 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2942 struct radv_pipeline *pipeline)
2943 {
2944 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2945 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2946 uint32_t ps_input_cntl[32];
2947
2948 unsigned ps_offset = 0;
2949
2950 if (ps->info.info.ps.prim_id_input) {
2951 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2952 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2953 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2954 ++ps_offset;
2955 }
2956 }
2957
2958 if (ps->info.info.ps.layer_input ||
2959 ps->info.info.ps.uses_input_attachments ||
2960 ps->info.info.needs_multiview_view_index) {
2961 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2962 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2963 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2964 else
2965 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2966 ++ps_offset;
2967 }
2968
2969 if (ps->info.info.ps.has_pcoord) {
2970 unsigned val;
2971 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2972 ps_input_cntl[ps_offset] = val;
2973 ps_offset++;
2974 }
2975
2976 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2977 unsigned vs_offset;
2978 bool flat_shade;
2979 if (!(ps->info.fs.input_mask & (1u << i)))
2980 continue;
2981
2982 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2983 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2984 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2985 ++ps_offset;
2986 continue;
2987 }
2988
2989 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2990
2991 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2992 ++ps_offset;
2993 }
2994
2995 if (ps_offset) {
2996 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2997 for (unsigned i = 0; i < ps_offset; i++) {
2998 radeon_emit(cs, ps_input_cntl[i]);
2999 }
3000 }
3001 }
3002
3003 static uint32_t
3004 radv_compute_db_shader_control(const struct radv_device *device,
3005 const struct radv_shader_variant *ps)
3006 {
3007 unsigned z_order;
3008 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3009 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3010 else
3011 z_order = V_02880C_LATE_Z;
3012
3013 bool disable_rbplus = device->physical_device->has_rbplus &&
3014 !device->physical_device->rbplus_allowed;
3015
3016 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
3017 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
3018 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
3019 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
3020 S_02880C_Z_ORDER(z_order) |
3021 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
3022 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
3023 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
3024 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
3025 }
3026
3027 static void
3028 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
3029 struct radv_pipeline *pipeline)
3030 {
3031 struct radv_shader_variant *ps;
3032 uint64_t va;
3033 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
3034
3035 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3036 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
3037
3038 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
3039 radeon_emit(cs, va >> 8);
3040 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
3041 radeon_emit(cs, ps->rsrc1);
3042 radeon_emit(cs, ps->rsrc2);
3043
3044 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
3045 radv_compute_db_shader_control(pipeline->device, ps));
3046
3047 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
3048 ps->config.spi_ps_input_ena);
3049
3050 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
3051 ps->config.spi_ps_input_addr);
3052
3053 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
3054 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
3055
3056 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3057
3058 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
3059 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
3060 ps->info.info.ps.writes_stencil,
3061 ps->info.info.ps.writes_sample_mask));
3062
3063 if (pipeline->device->dfsm_allowed) {
3064 /* optimise this? */
3065 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3066 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3067 }
3068 }
3069
3070 static void
3071 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
3072 struct radv_pipeline *pipeline)
3073 {
3074 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
3075 return;
3076
3077 unsigned vtx_reuse_depth = 30;
3078 if (radv_pipeline_has_tess(pipeline) &&
3079 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
3080 vtx_reuse_depth = 14;
3081 }
3082 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
3083 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
3084 }
3085
3086 static uint32_t
3087 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
3088 {
3089 uint32_t stages = 0;
3090 if (radv_pipeline_has_tess(pipeline)) {
3091 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3092 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3093
3094 if (radv_pipeline_has_gs(pipeline))
3095 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3096 S_028B54_GS_EN(1) |
3097 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3098 else
3099 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3100
3101 } else if (radv_pipeline_has_gs(pipeline))
3102 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3103 S_028B54_GS_EN(1) |
3104 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3105
3106 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
3107 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3108
3109 return stages;
3110 }
3111
3112 static uint32_t
3113 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
3114 {
3115 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
3116 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
3117
3118 if (!discard_rectangle_info)
3119 return 0xffff;
3120
3121 unsigned mask = 0;
3122
3123 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
3124 /* Interpret i as a bitmask, and then set the bit in the mask if
3125 * that combination of rectangles in which the pixel is contained
3126 * should pass the cliprect test. */
3127 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
3128
3129 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
3130 !relevant_subset)
3131 continue;
3132
3133 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
3134 relevant_subset)
3135 continue;
3136
3137 mask |= 1u << i;
3138 }
3139
3140 return mask;
3141 }
3142
3143 static void
3144 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
3145 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3146 const struct radv_graphics_pipeline_create_info *extra,
3147 const struct radv_blend_state *blend,
3148 const struct radv_tessellation_state *tess,
3149 const struct radv_gs_state *gs,
3150 unsigned prim, unsigned gs_out)
3151 {
3152 pipeline->cs.buf = malloc(4 * 256);
3153 pipeline->cs.max_dw = 256;
3154
3155 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
3156 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
3157 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
3158 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
3159 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
3160 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
3161 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
3162 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
3163 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
3164 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
3165 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
3166 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
3167
3168 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
3169 S_0286E8_WAVES(pipeline->max_waves) |
3170 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3171
3172 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
3173
3174 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
3175 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
3176 } else {
3177 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
3178 }
3179 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
3180
3181 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
3182
3183 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3184 }
3185
3186 static struct radv_ia_multi_vgt_param_helpers
3187 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
3188 const struct radv_tessellation_state *tess,
3189 uint32_t prim)
3190 {
3191 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
3192 const struct radv_device *device = pipeline->device;
3193
3194 if (radv_pipeline_has_tess(pipeline))
3195 ia_multi_vgt_param.primgroup_size = tess->num_patches;
3196 else if (radv_pipeline_has_gs(pipeline))
3197 ia_multi_vgt_param.primgroup_size = 64;
3198 else
3199 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
3200
3201 ia_multi_vgt_param.partial_es_wave = false;
3202 if (pipeline->device->has_distributed_tess) {
3203 if (radv_pipeline_has_gs(pipeline)) {
3204 if (device->physical_device->rad_info.chip_class <= VI)
3205 ia_multi_vgt_param.partial_es_wave = true;
3206 }
3207 }
3208 /* GS requirement. */
3209 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3210 ia_multi_vgt_param.partial_es_wave = true;
3211
3212 ia_multi_vgt_param.wd_switch_on_eop = false;
3213 if (device->physical_device->rad_info.chip_class >= CIK) {
3214 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3215 * 4 shader engines. Set 1 to pass the assertion below.
3216 * The other cases are hardware requirements. */
3217 if (device->physical_device->rad_info.max_se < 4 ||
3218 prim == V_008958_DI_PT_POLYGON ||
3219 prim == V_008958_DI_PT_LINELOOP ||
3220 prim == V_008958_DI_PT_TRIFAN ||
3221 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3222 (pipeline->graphics.prim_restart_enable &&
3223 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3224 (prim != V_008958_DI_PT_POINTLIST &&
3225 prim != V_008958_DI_PT_LINESTRIP &&
3226 prim != V_008958_DI_PT_TRISTRIP))))
3227 ia_multi_vgt_param.wd_switch_on_eop = true;
3228 }
3229
3230 ia_multi_vgt_param.ia_switch_on_eoi = false;
3231 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
3232 ia_multi_vgt_param.ia_switch_on_eoi = true;
3233 if (radv_pipeline_has_gs(pipeline) &&
3234 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3235 ia_multi_vgt_param.ia_switch_on_eoi = true;
3236 if (radv_pipeline_has_tess(pipeline)) {
3237 /* SWITCH_ON_EOI must be set if PrimID is used. */
3238 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3239 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3240 ia_multi_vgt_param.ia_switch_on_eoi = true;
3241 }
3242
3243 ia_multi_vgt_param.partial_vs_wave = false;
3244 if (radv_pipeline_has_tess(pipeline)) {
3245 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3246 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3247 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3248 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3249 radv_pipeline_has_gs(pipeline))
3250 ia_multi_vgt_param.partial_vs_wave = true;
3251 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3252 if (device->has_distributed_tess) {
3253 if (radv_pipeline_has_gs(pipeline)) {
3254 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3255 device->physical_device->rad_info.family == CHIP_FIJI ||
3256 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3257 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3258 device->physical_device->rad_info.family == CHIP_POLARIS12)
3259 ia_multi_vgt_param.partial_vs_wave = true;
3260 } else {
3261 ia_multi_vgt_param.partial_vs_wave = true;
3262 }
3263 }
3264 }
3265
3266 ia_multi_vgt_param.base =
3267 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3268 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3269 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3270 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3271 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3272
3273 return ia_multi_vgt_param;
3274 }
3275
3276
3277 static void
3278 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3279 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3280 {
3281 const VkPipelineVertexInputStateCreateInfo *vi_info =
3282 pCreateInfo->pVertexInputState;
3283 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3284
3285 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3286 const VkVertexInputAttributeDescription *desc =
3287 &vi_info->pVertexAttributeDescriptions[i];
3288 unsigned loc = desc->location;
3289 const struct vk_format_description *format_desc;
3290 int first_non_void;
3291 uint32_t num_format, data_format;
3292 format_desc = vk_format_description(desc->format);
3293 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3294
3295 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3296 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3297
3298 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3299 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3300 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3301 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3302 S_008F0C_NUM_FORMAT(num_format) |
3303 S_008F0C_DATA_FORMAT(data_format);
3304 velems->format_size[loc] = format_desc->block.bits / 8;
3305 velems->offset[loc] = desc->offset;
3306 velems->binding[loc] = desc->binding;
3307 velems->count = MAX2(velems->count, loc + 1);
3308 }
3309
3310 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3311 const VkVertexInputBindingDescription *desc =
3312 &vi_info->pVertexBindingDescriptions[i];
3313
3314 pipeline->binding_stride[desc->binding] = desc->stride;
3315 }
3316 }
3317
3318 static VkResult
3319 radv_pipeline_init(struct radv_pipeline *pipeline,
3320 struct radv_device *device,
3321 struct radv_pipeline_cache *cache,
3322 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3323 const struct radv_graphics_pipeline_create_info *extra,
3324 const VkAllocationCallbacks *alloc)
3325 {
3326 VkResult result;
3327 bool has_view_index = false;
3328
3329 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3330 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3331 if (subpass->view_mask)
3332 has_view_index = true;
3333 if (alloc == NULL)
3334 alloc = &device->alloc;
3335
3336 pipeline->device = device;
3337 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3338 assert(pipeline->layout);
3339
3340 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3341
3342 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3343 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3344 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3345 pStages[stage] = &pCreateInfo->pStages[i];
3346 }
3347
3348 radv_create_shaders(pipeline, device, cache,
3349 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3350 pStages);
3351
3352 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3353 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
3354 uint32_t gs_out;
3355 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3356
3357 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3358
3359 if (radv_pipeline_has_gs(pipeline)) {
3360 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3361 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3362 } else {
3363 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3364 }
3365 if (extra && extra->use_rectlist) {
3366 prim = V_008958_DI_PT_RECTLIST;
3367 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3368 pipeline->graphics.can_use_guardband = true;
3369 }
3370 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3371 /* prim vertex count will need TESS changes */
3372 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3373
3374 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3375
3376 /* Ensure that some export memory is always allocated, for two reasons:
3377 *
3378 * 1) Correctness: The hardware ignores the EXEC mask if no export
3379 * memory is allocated, so KILL and alpha test do not work correctly
3380 * without this.
3381 * 2) Performance: Every shader needs at least a NULL export, even when
3382 * it writes no color/depth output. The NULL export instruction
3383 * stalls without this setting.
3384 *
3385 * Don't add this to CB_SHADER_MASK.
3386 */
3387 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3388 if (!blend.spi_shader_col_format) {
3389 if (!ps->info.info.ps.writes_z &&
3390 !ps->info.info.ps.writes_stencil &&
3391 !ps->info.info.ps.writes_sample_mask)
3392 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3393 }
3394
3395 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3396 if (pipeline->shaders[i]) {
3397 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3398 }
3399 }
3400
3401 struct radv_gs_state gs = {0};
3402 if (radv_pipeline_has_gs(pipeline)) {
3403 gs = calculate_gs_info(pCreateInfo, pipeline);
3404 calculate_gs_ring_sizes(pipeline, &gs);
3405 }
3406
3407 struct radv_tessellation_state tess = {0};
3408 if (radv_pipeline_has_tess(pipeline)) {
3409 if (prim == V_008958_DI_PT_PATCH) {
3410 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3411 pipeline->graphics.prim_vertex_count.incr = 1;
3412 }
3413 tess = calculate_tess_state(pipeline, pCreateInfo);
3414 }
3415
3416 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3417
3418 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3419
3420 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3421 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3422
3423 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3424 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3425 if (loc->sgpr_idx != -1) {
3426 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3427 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3428 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3429 pipeline->graphics.vtx_emit_num = 3;
3430 else
3431 pipeline->graphics.vtx_emit_num = 2;
3432 }
3433
3434 result = radv_pipeline_scratch_init(device, pipeline);
3435 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3436
3437 return result;
3438 }
3439
3440 VkResult
3441 radv_graphics_pipeline_create(
3442 VkDevice _device,
3443 VkPipelineCache _cache,
3444 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3445 const struct radv_graphics_pipeline_create_info *extra,
3446 const VkAllocationCallbacks *pAllocator,
3447 VkPipeline *pPipeline)
3448 {
3449 RADV_FROM_HANDLE(radv_device, device, _device);
3450 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3451 struct radv_pipeline *pipeline;
3452 VkResult result;
3453
3454 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3455 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3456 if (pipeline == NULL)
3457 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3458
3459 result = radv_pipeline_init(pipeline, device, cache,
3460 pCreateInfo, extra, pAllocator);
3461 if (result != VK_SUCCESS) {
3462 radv_pipeline_destroy(device, pipeline, pAllocator);
3463 return result;
3464 }
3465
3466 *pPipeline = radv_pipeline_to_handle(pipeline);
3467
3468 return VK_SUCCESS;
3469 }
3470
3471 VkResult radv_CreateGraphicsPipelines(
3472 VkDevice _device,
3473 VkPipelineCache pipelineCache,
3474 uint32_t count,
3475 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3476 const VkAllocationCallbacks* pAllocator,
3477 VkPipeline* pPipelines)
3478 {
3479 VkResult result = VK_SUCCESS;
3480 unsigned i = 0;
3481
3482 for (; i < count; i++) {
3483 VkResult r;
3484 r = radv_graphics_pipeline_create(_device,
3485 pipelineCache,
3486 &pCreateInfos[i],
3487 NULL, pAllocator, &pPipelines[i]);
3488 if (r != VK_SUCCESS) {
3489 result = r;
3490 pPipelines[i] = VK_NULL_HANDLE;
3491 }
3492 }
3493
3494 return result;
3495 }
3496
3497
3498 static void
3499 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3500 {
3501 struct radv_shader_variant *compute_shader;
3502 struct radv_device *device = pipeline->device;
3503 unsigned compute_resource_limits;
3504 unsigned waves_per_threadgroup;
3505 uint64_t va;
3506
3507 pipeline->cs.buf = malloc(20 * 4);
3508 pipeline->cs.max_dw = 20;
3509
3510 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3511 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3512
3513 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3514 radeon_emit(&pipeline->cs, va >> 8);
3515 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3516
3517 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3518 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3519 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3520
3521 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3522 S_00B860_WAVES(pipeline->max_waves) |
3523 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3524
3525 /* Calculate best compute resource limits. */
3526 waves_per_threadgroup =
3527 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3528 compute_shader->info.cs.block_size[1] *
3529 compute_shader->info.cs.block_size[2], 64);
3530 compute_resource_limits =
3531 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3532
3533 if (device->physical_device->rad_info.chip_class >= CIK) {
3534 unsigned num_cu_per_se =
3535 device->physical_device->rad_info.num_good_compute_units /
3536 device->physical_device->rad_info.max_se;
3537
3538 /* Force even distribution on all SIMDs in CU if the workgroup
3539 * size is 64. This has shown some good improvements if # of
3540 * CUs per SE is not a multiple of 4.
3541 */
3542 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3543 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3544 }
3545
3546 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3547 compute_resource_limits);
3548
3549 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3550 radeon_emit(&pipeline->cs,
3551 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3552 radeon_emit(&pipeline->cs,
3553 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3554 radeon_emit(&pipeline->cs,
3555 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3556
3557 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3558 }
3559
3560 static VkResult radv_compute_pipeline_create(
3561 VkDevice _device,
3562 VkPipelineCache _cache,
3563 const VkComputePipelineCreateInfo* pCreateInfo,
3564 const VkAllocationCallbacks* pAllocator,
3565 VkPipeline* pPipeline)
3566 {
3567 RADV_FROM_HANDLE(radv_device, device, _device);
3568 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3569 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3570 struct radv_pipeline *pipeline;
3571 VkResult result;
3572
3573 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3574 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3575 if (pipeline == NULL)
3576 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3577
3578 pipeline->device = device;
3579 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3580 assert(pipeline->layout);
3581
3582 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3583 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3584
3585 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3586 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3587 result = radv_pipeline_scratch_init(device, pipeline);
3588 if (result != VK_SUCCESS) {
3589 radv_pipeline_destroy(device, pipeline, pAllocator);
3590 return result;
3591 }
3592
3593 radv_compute_generate_pm4(pipeline);
3594
3595 *pPipeline = radv_pipeline_to_handle(pipeline);
3596
3597 return VK_SUCCESS;
3598 }
3599
3600 VkResult radv_CreateComputePipelines(
3601 VkDevice _device,
3602 VkPipelineCache pipelineCache,
3603 uint32_t count,
3604 const VkComputePipelineCreateInfo* pCreateInfos,
3605 const VkAllocationCallbacks* pAllocator,
3606 VkPipeline* pPipelines)
3607 {
3608 VkResult result = VK_SUCCESS;
3609
3610 unsigned i = 0;
3611 for (; i < count; i++) {
3612 VkResult r;
3613 r = radv_compute_pipeline_create(_device, pipelineCache,
3614 &pCreateInfos[i],
3615 pAllocator, &pPipelines[i]);
3616 if (r != VK_SUCCESS) {
3617 result = r;
3618 pPipelines[i] = VK_NULL_HANDLE;
3619 }
3620 }
3621
3622 return result;
3623 }