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radv: Split out processing the vertex input state.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t cb_color_control;
54 uint32_t cb_target_mask;
55 uint32_t sx_mrt_blend_opt[8];
56 uint32_t cb_blend_control[8];
57
58 uint32_t spi_shader_col_format;
59 uint32_t cb_shader_mask;
60 uint32_t db_alpha_to_mask;
61 };
62
63 struct radv_tessellation_state {
64 uint32_t ls_hs_config;
65 uint32_t tcs_in_layout;
66 uint32_t tcs_out_layout;
67 uint32_t tcs_out_offsets;
68 uint32_t offchip_layout;
69 unsigned num_patches;
70 unsigned lds_size;
71 unsigned num_tcs_input_cp;
72 uint32_t tf_param;
73 };
74
75 static void
76 radv_pipeline_destroy(struct radv_device *device,
77 struct radv_pipeline *pipeline,
78 const VkAllocationCallbacks* allocator)
79 {
80 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
81 if (pipeline->shaders[i])
82 radv_shader_variant_destroy(device, pipeline->shaders[i]);
83
84 if (pipeline->gs_copy_shader)
85 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
86
87 if(pipeline->cs.buf)
88 free(pipeline->cs.buf);
89 vk_free2(&device->alloc, allocator, pipeline);
90 }
91
92 void radv_DestroyPipeline(
93 VkDevice _device,
94 VkPipeline _pipeline,
95 const VkAllocationCallbacks* pAllocator)
96 {
97 RADV_FROM_HANDLE(radv_device, device, _device);
98 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
99
100 if (!_pipeline)
101 return;
102
103 radv_pipeline_destroy(device, pipeline, pAllocator);
104 }
105
106 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
107 {
108 int i;
109
110 for (i = 0; i < MESA_SHADER_STAGES; i++) {
111 if (!pipeline->shaders[i])
112 continue;
113
114 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
115 }
116 }
117
118 static uint32_t get_hash_flags(struct radv_device *device)
119 {
120 uint32_t hash_flags = 0;
121
122 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
123 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
124 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
125 hash_flags |= RADV_HASH_SHADER_SISCHED;
126 return hash_flags;
127 }
128
129 static VkResult
130 radv_pipeline_scratch_init(struct radv_device *device,
131 struct radv_pipeline *pipeline)
132 {
133 unsigned scratch_bytes_per_wave = 0;
134 unsigned max_waves = 0;
135 unsigned min_waves = 1;
136
137 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
138 if (pipeline->shaders[i]) {
139 unsigned max_stage_waves = device->scratch_waves;
140
141 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
142 pipeline->shaders[i]->config.scratch_bytes_per_wave);
143
144 max_stage_waves = MIN2(max_stage_waves,
145 4 * device->physical_device->rad_info.num_good_compute_units *
146 (256 / pipeline->shaders[i]->config.num_vgprs));
147 max_waves = MAX2(max_waves, max_stage_waves);
148 }
149 }
150
151 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
152 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
153 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
154 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
155 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
156 }
157
158 if (scratch_bytes_per_wave)
159 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
160
161 if (scratch_bytes_per_wave && max_waves < min_waves) {
162 /* Not really true at this moment, but will be true on first
163 * execution. Avoid having hanging shaders. */
164 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
165 }
166 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
167 pipeline->max_waves = max_waves;
168 return VK_SUCCESS;
169 }
170
171 static uint32_t si_translate_blend_function(VkBlendOp op)
172 {
173 switch (op) {
174 case VK_BLEND_OP_ADD:
175 return V_028780_COMB_DST_PLUS_SRC;
176 case VK_BLEND_OP_SUBTRACT:
177 return V_028780_COMB_SRC_MINUS_DST;
178 case VK_BLEND_OP_REVERSE_SUBTRACT:
179 return V_028780_COMB_DST_MINUS_SRC;
180 case VK_BLEND_OP_MIN:
181 return V_028780_COMB_MIN_DST_SRC;
182 case VK_BLEND_OP_MAX:
183 return V_028780_COMB_MAX_DST_SRC;
184 default:
185 return 0;
186 }
187 }
188
189 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
190 {
191 switch (factor) {
192 case VK_BLEND_FACTOR_ZERO:
193 return V_028780_BLEND_ZERO;
194 case VK_BLEND_FACTOR_ONE:
195 return V_028780_BLEND_ONE;
196 case VK_BLEND_FACTOR_SRC_COLOR:
197 return V_028780_BLEND_SRC_COLOR;
198 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
199 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
200 case VK_BLEND_FACTOR_DST_COLOR:
201 return V_028780_BLEND_DST_COLOR;
202 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
203 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
204 case VK_BLEND_FACTOR_SRC_ALPHA:
205 return V_028780_BLEND_SRC_ALPHA;
206 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
207 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
208 case VK_BLEND_FACTOR_DST_ALPHA:
209 return V_028780_BLEND_DST_ALPHA;
210 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
211 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
212 case VK_BLEND_FACTOR_CONSTANT_COLOR:
213 return V_028780_BLEND_CONSTANT_COLOR;
214 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
215 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
216 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
217 return V_028780_BLEND_CONSTANT_ALPHA;
218 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
219 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
220 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
221 return V_028780_BLEND_SRC_ALPHA_SATURATE;
222 case VK_BLEND_FACTOR_SRC1_COLOR:
223 return V_028780_BLEND_SRC1_COLOR;
224 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
225 return V_028780_BLEND_INV_SRC1_COLOR;
226 case VK_BLEND_FACTOR_SRC1_ALPHA:
227 return V_028780_BLEND_SRC1_ALPHA;
228 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
229 return V_028780_BLEND_INV_SRC1_ALPHA;
230 default:
231 return 0;
232 }
233 }
234
235 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
236 {
237 switch (op) {
238 case VK_BLEND_OP_ADD:
239 return V_028760_OPT_COMB_ADD;
240 case VK_BLEND_OP_SUBTRACT:
241 return V_028760_OPT_COMB_SUBTRACT;
242 case VK_BLEND_OP_REVERSE_SUBTRACT:
243 return V_028760_OPT_COMB_REVSUBTRACT;
244 case VK_BLEND_OP_MIN:
245 return V_028760_OPT_COMB_MIN;
246 case VK_BLEND_OP_MAX:
247 return V_028760_OPT_COMB_MAX;
248 default:
249 return V_028760_OPT_COMB_BLEND_DISABLED;
250 }
251 }
252
253 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
254 {
255 switch (factor) {
256 case VK_BLEND_FACTOR_ZERO:
257 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
258 case VK_BLEND_FACTOR_ONE:
259 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
260 case VK_BLEND_FACTOR_SRC_COLOR:
261 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
262 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
263 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
264 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
265 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
266 case VK_BLEND_FACTOR_SRC_ALPHA:
267 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
268 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
269 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
270 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
271 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
272 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
273 default:
274 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
275 }
276 }
277
278 /**
279 * Get rid of DST in the blend factors by commuting the operands:
280 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
281 */
282 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
283 unsigned *dst_factor, unsigned expected_dst,
284 unsigned replacement_src)
285 {
286 if (*src_factor == expected_dst &&
287 *dst_factor == VK_BLEND_FACTOR_ZERO) {
288 *src_factor = VK_BLEND_FACTOR_ZERO;
289 *dst_factor = replacement_src;
290
291 /* Commuting the operands requires reversing subtractions. */
292 if (*func == VK_BLEND_OP_SUBTRACT)
293 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
294 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
295 *func = VK_BLEND_OP_SUBTRACT;
296 }
297 }
298
299 static bool si_blend_factor_uses_dst(unsigned factor)
300 {
301 return factor == VK_BLEND_FACTOR_DST_COLOR ||
302 factor == VK_BLEND_FACTOR_DST_ALPHA ||
303 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
304 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
305 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
306 }
307
308 static bool is_dual_src(VkBlendFactor factor)
309 {
310 switch (factor) {
311 case VK_BLEND_FACTOR_SRC1_COLOR:
312 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
313 case VK_BLEND_FACTOR_SRC1_ALPHA:
314 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
315 return true;
316 default:
317 return false;
318 }
319 }
320
321 static unsigned si_choose_spi_color_format(VkFormat vk_format,
322 bool blend_enable,
323 bool blend_need_alpha)
324 {
325 const struct vk_format_description *desc = vk_format_description(vk_format);
326 unsigned format, ntype, swap;
327
328 /* Alpha is needed for alpha-to-coverage.
329 * Blending may be with or without alpha.
330 */
331 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
332 unsigned alpha = 0; /* exports alpha, but may not support blending */
333 unsigned blend = 0; /* supports blending, but may not export alpha */
334 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
335
336 format = radv_translate_colorformat(vk_format);
337 ntype = radv_translate_color_numformat(vk_format, desc,
338 vk_format_get_first_non_void_channel(vk_format));
339 swap = radv_translate_colorswap(vk_format, false);
340
341 /* Choose the SPI color formats. These are required values for Stoney/RB+.
342 * Other chips have multiple choices, though they are not necessarily better.
343 */
344 switch (format) {
345 case V_028C70_COLOR_5_6_5:
346 case V_028C70_COLOR_1_5_5_5:
347 case V_028C70_COLOR_5_5_5_1:
348 case V_028C70_COLOR_4_4_4_4:
349 case V_028C70_COLOR_10_11_11:
350 case V_028C70_COLOR_11_11_10:
351 case V_028C70_COLOR_8:
352 case V_028C70_COLOR_8_8:
353 case V_028C70_COLOR_8_8_8_8:
354 case V_028C70_COLOR_10_10_10_2:
355 case V_028C70_COLOR_2_10_10_10:
356 if (ntype == V_028C70_NUMBER_UINT)
357 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
358 else if (ntype == V_028C70_NUMBER_SINT)
359 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
360 else
361 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
362 break;
363
364 case V_028C70_COLOR_16:
365 case V_028C70_COLOR_16_16:
366 case V_028C70_COLOR_16_16_16_16:
367 if (ntype == V_028C70_NUMBER_UNORM ||
368 ntype == V_028C70_NUMBER_SNORM) {
369 /* UNORM16 and SNORM16 don't support blending */
370 if (ntype == V_028C70_NUMBER_UNORM)
371 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
372 else
373 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
374
375 /* Use 32 bits per channel for blending. */
376 if (format == V_028C70_COLOR_16) {
377 if (swap == V_028C70_SWAP_STD) { /* R */
378 blend = V_028714_SPI_SHADER_32_R;
379 blend_alpha = V_028714_SPI_SHADER_32_AR;
380 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
381 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
382 else
383 assert(0);
384 } else if (format == V_028C70_COLOR_16_16) {
385 if (swap == V_028C70_SWAP_STD) { /* RG */
386 blend = V_028714_SPI_SHADER_32_GR;
387 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
388 } else if (swap == V_028C70_SWAP_ALT) /* RA */
389 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
390 else
391 assert(0);
392 } else /* 16_16_16_16 */
393 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
394 } else if (ntype == V_028C70_NUMBER_UINT)
395 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
396 else if (ntype == V_028C70_NUMBER_SINT)
397 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
398 else if (ntype == V_028C70_NUMBER_FLOAT)
399 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
400 else
401 assert(0);
402 break;
403
404 case V_028C70_COLOR_32:
405 if (swap == V_028C70_SWAP_STD) { /* R */
406 blend = normal = V_028714_SPI_SHADER_32_R;
407 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
408 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
409 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
410 else
411 assert(0);
412 break;
413
414 case V_028C70_COLOR_32_32:
415 if (swap == V_028C70_SWAP_STD) { /* RG */
416 blend = normal = V_028714_SPI_SHADER_32_GR;
417 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
418 } else if (swap == V_028C70_SWAP_ALT) /* RA */
419 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
420 else
421 assert(0);
422 break;
423
424 case V_028C70_COLOR_32_32_32_32:
425 case V_028C70_COLOR_8_24:
426 case V_028C70_COLOR_24_8:
427 case V_028C70_COLOR_X24_8_32_FLOAT:
428 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
429 break;
430
431 default:
432 unreachable("unhandled blend format");
433 }
434
435 if (blend_enable && blend_need_alpha)
436 return blend_alpha;
437 else if(blend_need_alpha)
438 return alpha;
439 else if(blend_enable)
440 return blend;
441 else
442 return normal;
443 }
444
445 static void
446 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
447 const VkGraphicsPipelineCreateInfo *pCreateInfo,
448 uint32_t blend_enable,
449 uint32_t blend_need_alpha,
450 bool single_cb_enable,
451 bool blend_mrt0_is_dual_src,
452 struct radv_blend_state *blend)
453 {
454 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
455 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
456 unsigned col_format = 0;
457
458 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
459 unsigned cf;
460
461 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
462 cf = V_028714_SPI_SHADER_ZERO;
463 } else {
464 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
465
466 cf = si_choose_spi_color_format(attachment->format,
467 blend_enable & (1 << i),
468 blend_need_alpha & (1 << i));
469 }
470
471 col_format |= cf << (4 * i);
472 }
473
474 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
475
476 if (blend_mrt0_is_dual_src)
477 col_format |= (col_format & 0xf) << 4;
478 blend->spi_shader_col_format = col_format;
479 }
480
481 static bool
482 format_is_int8(VkFormat format)
483 {
484 const struct vk_format_description *desc = vk_format_description(format);
485 int channel = vk_format_get_first_non_void_channel(format);
486
487 return channel >= 0 && desc->channel[channel].pure_integer &&
488 desc->channel[channel].size == 8;
489 }
490
491 static bool
492 format_is_int10(VkFormat format)
493 {
494 const struct vk_format_description *desc = vk_format_description(format);
495
496 if (desc->nr_channels != 4)
497 return false;
498 for (unsigned i = 0; i < 4; i++) {
499 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
500 return true;
501 }
502 return false;
503 }
504
505 unsigned radv_format_meta_fs_key(VkFormat format)
506 {
507 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
508 bool is_int8 = format_is_int8(format);
509 bool is_int10 = format_is_int10(format);
510
511 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
512 }
513
514 static void
515 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
516 unsigned *is_int8, unsigned *is_int10)
517 {
518 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
519 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
520 *is_int8 = 0;
521 *is_int10 = 0;
522
523 for (unsigned i = 0; i < subpass->color_count; ++i) {
524 struct radv_render_pass_attachment *attachment;
525
526 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
527 continue;
528
529 attachment = pass->attachments + subpass->color_attachments[i].attachment;
530
531 if (format_is_int8(attachment->format))
532 *is_int8 |= 1 << i;
533 if (format_is_int10(attachment->format))
534 *is_int10 |= 1 << i;
535 }
536 }
537
538 static struct radv_blend_state
539 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
540 const VkGraphicsPipelineCreateInfo *pCreateInfo,
541 const struct radv_graphics_pipeline_create_info *extra)
542 {
543 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
544 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
545 struct radv_blend_state blend = {0};
546 unsigned mode = V_028808_CB_NORMAL;
547 uint32_t blend_enable = 0, blend_need_alpha = 0;
548 bool blend_mrt0_is_dual_src = false;
549 int i;
550 bool single_cb_enable = false;
551
552 if (!vkblend)
553 return blend;
554
555 if (extra && extra->custom_blend_mode) {
556 single_cb_enable = true;
557 mode = extra->custom_blend_mode;
558 }
559 blend.cb_color_control = 0;
560 if (vkblend->logicOpEnable)
561 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
562 else
563 blend.cb_color_control |= S_028808_ROP3(0xcc);
564
565 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
566 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
567 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
568 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
569
570 if (vkms && vkms->alphaToCoverageEnable) {
571 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
572 }
573
574 blend.cb_target_mask = 0;
575 for (i = 0; i < vkblend->attachmentCount; i++) {
576 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
577 unsigned blend_cntl = 0;
578 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
579 VkBlendOp eqRGB = att->colorBlendOp;
580 VkBlendFactor srcRGB = att->srcColorBlendFactor;
581 VkBlendFactor dstRGB = att->dstColorBlendFactor;
582 VkBlendOp eqA = att->alphaBlendOp;
583 VkBlendFactor srcA = att->srcAlphaBlendFactor;
584 VkBlendFactor dstA = att->dstAlphaBlendFactor;
585
586 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
587
588 if (!att->colorWriteMask)
589 continue;
590
591 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
592 if (!att->blendEnable) {
593 blend.cb_blend_control[i] = blend_cntl;
594 continue;
595 }
596
597 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
598 if (i == 0)
599 blend_mrt0_is_dual_src = true;
600
601 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
602 srcRGB = VK_BLEND_FACTOR_ONE;
603 dstRGB = VK_BLEND_FACTOR_ONE;
604 }
605 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
606 srcA = VK_BLEND_FACTOR_ONE;
607 dstA = VK_BLEND_FACTOR_ONE;
608 }
609
610 /* Blending optimizations for RB+.
611 * These transformations don't change the behavior.
612 *
613 * First, get rid of DST in the blend factors:
614 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
615 */
616 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
617 VK_BLEND_FACTOR_DST_COLOR,
618 VK_BLEND_FACTOR_SRC_COLOR);
619
620 si_blend_remove_dst(&eqA, &srcA, &dstA,
621 VK_BLEND_FACTOR_DST_COLOR,
622 VK_BLEND_FACTOR_SRC_COLOR);
623
624 si_blend_remove_dst(&eqA, &srcA, &dstA,
625 VK_BLEND_FACTOR_DST_ALPHA,
626 VK_BLEND_FACTOR_SRC_ALPHA);
627
628 /* Look up the ideal settings from tables. */
629 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
630 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
631 srcA_opt = si_translate_blend_opt_factor(srcA, true);
632 dstA_opt = si_translate_blend_opt_factor(dstA, true);
633
634 /* Handle interdependencies. */
635 if (si_blend_factor_uses_dst(srcRGB))
636 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
637 if (si_blend_factor_uses_dst(srcA))
638 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
639
640 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
641 (dstRGB == VK_BLEND_FACTOR_ZERO ||
642 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
643 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
644 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
645
646 /* Set the final value. */
647 blend.sx_mrt_blend_opt[i] =
648 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
649 S_028760_COLOR_DST_OPT(dstRGB_opt) |
650 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
651 S_028760_ALPHA_SRC_OPT(srcA_opt) |
652 S_028760_ALPHA_DST_OPT(dstA_opt) |
653 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
654 blend_cntl |= S_028780_ENABLE(1);
655
656 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
657 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
658 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
659 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
660 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
661 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
662 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
663 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
664 }
665 blend.cb_blend_control[i] = blend_cntl;
666
667 blend_enable |= 1 << i;
668
669 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
670 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
671 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
672 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
673 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
674 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
675 blend_need_alpha |= 1 << i;
676 }
677 for (i = vkblend->attachmentCount; i < 8; i++) {
678 blend.cb_blend_control[i] = 0;
679 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
680 }
681
682 /* disable RB+ for now */
683 if (pipeline->device->physical_device->has_rbplus)
684 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
685
686 if (blend.cb_target_mask)
687 blend.cb_color_control |= S_028808_MODE(mode);
688 else
689 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
690
691 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
692 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src,
693 &blend);
694 return blend;
695 }
696
697 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
698 {
699 switch (op) {
700 case VK_STENCIL_OP_KEEP:
701 return V_02842C_STENCIL_KEEP;
702 case VK_STENCIL_OP_ZERO:
703 return V_02842C_STENCIL_ZERO;
704 case VK_STENCIL_OP_REPLACE:
705 return V_02842C_STENCIL_REPLACE_TEST;
706 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
707 return V_02842C_STENCIL_ADD_CLAMP;
708 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
709 return V_02842C_STENCIL_SUB_CLAMP;
710 case VK_STENCIL_OP_INVERT:
711 return V_02842C_STENCIL_INVERT;
712 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
713 return V_02842C_STENCIL_ADD_WRAP;
714 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
715 return V_02842C_STENCIL_SUB_WRAP;
716 default:
717 return 0;
718 }
719 }
720
721 static uint32_t si_translate_fill(VkPolygonMode func)
722 {
723 switch(func) {
724 case VK_POLYGON_MODE_FILL:
725 return V_028814_X_DRAW_TRIANGLES;
726 case VK_POLYGON_MODE_LINE:
727 return V_028814_X_DRAW_LINES;
728 case VK_POLYGON_MODE_POINT:
729 return V_028814_X_DRAW_POINTS;
730 default:
731 assert(0);
732 return V_028814_X_DRAW_POINTS;
733 }
734 }
735 static void
736 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
737 const VkGraphicsPipelineCreateInfo *pCreateInfo)
738 {
739 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
740 struct radv_raster_state *raster = &pipeline->graphics.raster;
741
742 raster->spi_interp_control =
743 S_0286D4_FLAT_SHADE_ENA(1) |
744 S_0286D4_PNT_SPRITE_ENA(1) |
745 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
746 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
747 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
748 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
749 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
750
751
752 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
753 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
754 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
755 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
756 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
757 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
758
759 raster->pa_su_vtx_cntl =
760 S_028BE4_PIX_CENTER(1) | // TODO verify
761 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
762 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
763
764 raster->pa_su_sc_mode_cntl =
765 S_028814_FACE(vkraster->frontFace) |
766 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
767 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
768 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
769 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
770 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
771 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
772 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
773 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
774
775 }
776
777 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
778 {
779 uint32_t num_samples = vkms->rasterizationSamples;
780 uint32_t ps_iter_samples = 1;
781
782 if (vkms->sampleShadingEnable) {
783 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
784 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
785 }
786 return ps_iter_samples;
787 }
788
789 static void
790 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
791 const VkGraphicsPipelineCreateInfo *pCreateInfo)
792 {
793 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
794 struct radv_multisample_state *ms = &pipeline->graphics.ms;
795 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
796 int ps_iter_samples = 1;
797 uint32_t mask = 0xffff;
798
799 if (vkms)
800 ms->num_samples = vkms->rasterizationSamples;
801 else
802 ms->num_samples = 1;
803
804 if (vkms)
805 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
806 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
807 ps_iter_samples = ms->num_samples;
808 }
809
810 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
811 ms->pa_sc_aa_config = 0;
812 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
813 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
814 ms->pa_sc_mode_cntl_1 =
815 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
816 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
817 /* always 1: */
818 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
819 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
820 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
821 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
822 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
823 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
824 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
825 S_028A48_VPORT_SCISSOR_ENABLE(1);
826
827 if (ms->num_samples > 1) {
828 unsigned log_samples = util_logbase2(ms->num_samples);
829 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
830 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
831 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
832 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
833 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
834 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
835 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
836 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
837 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
838 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
839 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
840 if (ps_iter_samples > 1)
841 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
842 }
843
844 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
845 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
846 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
847 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
848 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
849 }
850
851 if (vkms && vkms->pSampleMask) {
852 mask = vkms->pSampleMask[0] & 0xffff;
853 }
854
855 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
856 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
857 }
858
859 static bool
860 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
861 {
862 switch (topology) {
863 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
864 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
865 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
866 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
867 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
868 return false;
869 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
870 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
871 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
872 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
873 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
874 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
875 return true;
876 default:
877 unreachable("unhandled primitive type");
878 }
879 }
880
881 static uint32_t
882 si_translate_prim(enum VkPrimitiveTopology topology)
883 {
884 switch (topology) {
885 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
886 return V_008958_DI_PT_POINTLIST;
887 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
888 return V_008958_DI_PT_LINELIST;
889 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
890 return V_008958_DI_PT_LINESTRIP;
891 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
892 return V_008958_DI_PT_TRILIST;
893 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
894 return V_008958_DI_PT_TRISTRIP;
895 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
896 return V_008958_DI_PT_TRIFAN;
897 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
898 return V_008958_DI_PT_LINELIST_ADJ;
899 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
900 return V_008958_DI_PT_LINESTRIP_ADJ;
901 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
902 return V_008958_DI_PT_TRILIST_ADJ;
903 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
904 return V_008958_DI_PT_TRISTRIP_ADJ;
905 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
906 return V_008958_DI_PT_PATCH;
907 default:
908 assert(0);
909 return 0;
910 }
911 }
912
913 static uint32_t
914 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
915 {
916 switch (gl_prim) {
917 case 0: /* GL_POINTS */
918 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
919 case 1: /* GL_LINES */
920 case 3: /* GL_LINE_STRIP */
921 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
922 case 0x8E7A: /* GL_ISOLINES */
923 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
924
925 case 4: /* GL_TRIANGLES */
926 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
927 case 5: /* GL_TRIANGLE_STRIP */
928 case 7: /* GL_QUADS */
929 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
930 default:
931 assert(0);
932 return 0;
933 }
934 }
935
936 static uint32_t
937 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
938 {
939 switch (topology) {
940 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
941 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
942 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
943 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
944 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
945 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
946 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
947 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
948 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
949 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
950 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
951 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
952 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
953 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
954 default:
955 assert(0);
956 return 0;
957 }
958 }
959
960 static unsigned si_map_swizzle(unsigned swizzle)
961 {
962 switch (swizzle) {
963 case VK_SWIZZLE_Y:
964 return V_008F0C_SQ_SEL_Y;
965 case VK_SWIZZLE_Z:
966 return V_008F0C_SQ_SEL_Z;
967 case VK_SWIZZLE_W:
968 return V_008F0C_SQ_SEL_W;
969 case VK_SWIZZLE_0:
970 return V_008F0C_SQ_SEL_0;
971 case VK_SWIZZLE_1:
972 return V_008F0C_SQ_SEL_1;
973 default: /* VK_SWIZZLE_X */
974 return V_008F0C_SQ_SEL_X;
975 }
976 }
977
978
979 static unsigned radv_dynamic_state_mask(VkDynamicState state)
980 {
981 switch(state) {
982 case VK_DYNAMIC_STATE_VIEWPORT:
983 return RADV_DYNAMIC_VIEWPORT;
984 case VK_DYNAMIC_STATE_SCISSOR:
985 return RADV_DYNAMIC_SCISSOR;
986 case VK_DYNAMIC_STATE_LINE_WIDTH:
987 return RADV_DYNAMIC_LINE_WIDTH;
988 case VK_DYNAMIC_STATE_DEPTH_BIAS:
989 return RADV_DYNAMIC_DEPTH_BIAS;
990 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
991 return RADV_DYNAMIC_BLEND_CONSTANTS;
992 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
993 return RADV_DYNAMIC_DEPTH_BOUNDS;
994 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
995 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
996 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
997 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
998 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
999 return RADV_DYNAMIC_STENCIL_REFERENCE;
1000 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1001 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1002 default:
1003 unreachable("Unhandled dynamic state");
1004 }
1005 }
1006
1007 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1008 {
1009 uint32_t states = RADV_DYNAMIC_ALL;
1010
1011 /* If rasterization is disabled we do not care about any of the dynamic states,
1012 * since they are all rasterization related only. */
1013 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1014 return 0;
1015
1016 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1017 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1018
1019 if (!pCreateInfo->pDepthStencilState ||
1020 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1021 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1022
1023 if (!pCreateInfo->pDepthStencilState ||
1024 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1025 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1026 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1027 RADV_DYNAMIC_STENCIL_REFERENCE);
1028
1029 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1030 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1031
1032 /* TODO: blend constants & line width. */
1033
1034 return states;
1035 }
1036
1037
1038 static void
1039 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1040 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1041 {
1042 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1043 uint32_t states = needed_states;
1044 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1045 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1046
1047 pipeline->dynamic_state = default_dynamic_state;
1048 pipeline->graphics.needed_dynamic_state = needed_states;
1049
1050 if (pCreateInfo->pDynamicState) {
1051 /* Remove all of the states that are marked as dynamic */
1052 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1053 for (uint32_t s = 0; s < count; s++)
1054 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1055 }
1056
1057 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1058
1059 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1060 assert(pCreateInfo->pViewportState);
1061
1062 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1063 if (states & RADV_DYNAMIC_VIEWPORT) {
1064 typed_memcpy(dynamic->viewport.viewports,
1065 pCreateInfo->pViewportState->pViewports,
1066 pCreateInfo->pViewportState->viewportCount);
1067 }
1068 }
1069
1070 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1071 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1072 if (states & RADV_DYNAMIC_SCISSOR) {
1073 typed_memcpy(dynamic->scissor.scissors,
1074 pCreateInfo->pViewportState->pScissors,
1075 pCreateInfo->pViewportState->scissorCount);
1076 }
1077 }
1078
1079 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1080 assert(pCreateInfo->pRasterizationState);
1081 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1082 }
1083
1084 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1085 assert(pCreateInfo->pRasterizationState);
1086 dynamic->depth_bias.bias =
1087 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1088 dynamic->depth_bias.clamp =
1089 pCreateInfo->pRasterizationState->depthBiasClamp;
1090 dynamic->depth_bias.slope =
1091 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1092 }
1093
1094 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1095 *
1096 * pColorBlendState is [...] NULL if the pipeline has rasterization
1097 * disabled or if the subpass of the render pass the pipeline is
1098 * created against does not use any color attachments.
1099 */
1100 bool uses_color_att = false;
1101 for (unsigned i = 0; i < subpass->color_count; ++i) {
1102 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1103 uses_color_att = true;
1104 break;
1105 }
1106 }
1107
1108 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1109 assert(pCreateInfo->pColorBlendState);
1110 typed_memcpy(dynamic->blend_constants,
1111 pCreateInfo->pColorBlendState->blendConstants, 4);
1112 }
1113
1114 /* If there is no depthstencil attachment, then don't read
1115 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1116 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1117 * no need to override the depthstencil defaults in
1118 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1119 *
1120 * Section 9.2 of the Vulkan 1.0.15 spec says:
1121 *
1122 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1123 * disabled or if the subpass of the render pass the pipeline is created
1124 * against does not use a depth/stencil attachment.
1125 */
1126 if (needed_states &&
1127 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1128 assert(pCreateInfo->pDepthStencilState);
1129
1130 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1131 dynamic->depth_bounds.min =
1132 pCreateInfo->pDepthStencilState->minDepthBounds;
1133 dynamic->depth_bounds.max =
1134 pCreateInfo->pDepthStencilState->maxDepthBounds;
1135 }
1136
1137 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1138 dynamic->stencil_compare_mask.front =
1139 pCreateInfo->pDepthStencilState->front.compareMask;
1140 dynamic->stencil_compare_mask.back =
1141 pCreateInfo->pDepthStencilState->back.compareMask;
1142 }
1143
1144 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1145 dynamic->stencil_write_mask.front =
1146 pCreateInfo->pDepthStencilState->front.writeMask;
1147 dynamic->stencil_write_mask.back =
1148 pCreateInfo->pDepthStencilState->back.writeMask;
1149 }
1150
1151 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1152 dynamic->stencil_reference.front =
1153 pCreateInfo->pDepthStencilState->front.reference;
1154 dynamic->stencil_reference.back =
1155 pCreateInfo->pDepthStencilState->back.reference;
1156 }
1157 }
1158
1159 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1160 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1161 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1162 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1163 typed_memcpy(dynamic->discard_rectangle.rectangles,
1164 discard_rectangle_info->pDiscardRectangles,
1165 discard_rectangle_info->discardRectangleCount);
1166
1167 unsigned mask = 0;
1168
1169 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
1170 /* Interpret i as a bitmask, and then set the bit in the mask if
1171 * that combination of rectangles in which the pixel is contained
1172 * should pass the cliprect test. */
1173 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
1174
1175 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
1176 !relevant_subset)
1177 continue;
1178
1179 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
1180 relevant_subset)
1181 continue;
1182
1183 mask |= 1u << i;
1184 }
1185 pipeline->graphics.pa_sc_cliprect_rule = mask;
1186 } else {
1187 /* Allow from all rectangle combinations */
1188 pipeline->graphics.pa_sc_cliprect_rule = 0xffff;
1189 }
1190 pipeline->dynamic_state.mask = states;
1191 }
1192
1193 static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1194 struct radv_pipeline *pipeline)
1195 {
1196 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1197 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1198 &gs_info->tes.es_info : &gs_info->vs.es_info;
1199 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1200 bool uses_adjacency;
1201 switch(pCreateInfo->pInputAssemblyState->topology) {
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1206 uses_adjacency = true;
1207 break;
1208 default:
1209 uses_adjacency = false;
1210 break;
1211 }
1212
1213 /* All these are in dwords: */
1214 /* We can't allow using the whole LDS, because GS waves compete with
1215 * other shader stages for LDS space. */
1216 const unsigned max_lds_size = 8 * 1024;
1217 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1218 unsigned esgs_lds_size;
1219
1220 /* All these are per subgroup: */
1221 const unsigned max_out_prims = 32 * 1024;
1222 const unsigned max_es_verts = 255;
1223 const unsigned ideal_gs_prims = 64;
1224 unsigned max_gs_prims, gs_prims;
1225 unsigned min_es_verts, es_verts, worst_case_es_verts;
1226
1227 if (uses_adjacency || gs_num_invocations > 1)
1228 max_gs_prims = 127 / gs_num_invocations;
1229 else
1230 max_gs_prims = 255;
1231
1232 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1233 * Make sure we don't go over the maximum value.
1234 */
1235 if (gs_info->gs.vertices_out > 0) {
1236 max_gs_prims = MIN2(max_gs_prims,
1237 max_out_prims /
1238 (gs_info->gs.vertices_out * gs_num_invocations));
1239 }
1240 assert(max_gs_prims > 0);
1241
1242 /* If the primitive has adjacency, halve the number of vertices
1243 * that will be reused in multiple primitives.
1244 */
1245 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1246
1247 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1248 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1249
1250 /* Compute ESGS LDS size based on the worst case number of ES vertices
1251 * needed to create the target number of GS prims per subgroup.
1252 */
1253 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1254
1255 /* If total LDS usage is too big, refactor partitions based on ratio
1256 * of ESGS item sizes.
1257 */
1258 if (esgs_lds_size > max_lds_size) {
1259 /* Our target GS Prims Per Subgroup was too large. Calculate
1260 * the maximum number of GS Prims Per Subgroup that will fit
1261 * into LDS, capped by the maximum that the hardware can support.
1262 */
1263 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1264 max_gs_prims);
1265 assert(gs_prims > 0);
1266 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1267 max_es_verts);
1268
1269 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1270 assert(esgs_lds_size <= max_lds_size);
1271 }
1272
1273 /* Now calculate remaining ESGS information. */
1274 if (esgs_lds_size)
1275 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1276 else
1277 es_verts = max_es_verts;
1278
1279 /* Vertices for adjacency primitives are not always reused, so restore
1280 * it for ES_VERTS_PER_SUBGRP.
1281 */
1282 min_es_verts = gs_info->gs.vertices_in;
1283
1284 /* For normal primitives, the VGT only checks if they are past the ES
1285 * verts per subgroup after allocating a full GS primitive and if they
1286 * are, kick off a new subgroup. But if those additional ES verts are
1287 * unique (e.g. not reused) we need to make sure there is enough LDS
1288 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1289 */
1290 es_verts -= min_es_verts - 1;
1291
1292 uint32_t es_verts_per_subgroup = es_verts;
1293 uint32_t gs_prims_per_subgroup = gs_prims;
1294 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1295 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1296 pipeline->graphics.gs.lds_size = align(esgs_lds_size, 128) / 128;
1297 pipeline->graphics.gs.vgt_gs_onchip_cntl =
1298 S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1299 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1300 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1301 pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup =
1302 S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1303 pipeline->graphics.gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1304 assert(max_prims_per_subgroup <= max_out_prims);
1305 }
1306
1307 static void
1308 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1309 {
1310 struct radv_device *device = pipeline->device;
1311 unsigned num_se = device->physical_device->rad_info.max_se;
1312 unsigned wave_size = 64;
1313 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1314 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1315 unsigned alignment = 256 * num_se;
1316 /* The maximum size is 63.999 MB per SE. */
1317 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1318 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1319 struct ac_es_output_info *es_info;
1320 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1321 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1322 else
1323 es_info = radv_pipeline_has_tess(pipeline) ?
1324 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1325 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1326
1327 /* Calculate the minimum size. */
1328 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1329 wave_size, alignment);
1330 /* These are recommended sizes, not minimum sizes. */
1331 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1332 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1333 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1334 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1335
1336 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1337 esgs_ring_size = align(esgs_ring_size, alignment);
1338 gsvs_ring_size = align(gsvs_ring_size, alignment);
1339
1340 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1341 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1342
1343 pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1344 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1345 }
1346
1347 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1348 unsigned *lds_size)
1349 {
1350 /* SPI barrier management bug:
1351 * Make sure we have at least 4k of LDS in use to avoid the bug.
1352 * It applies to workgroup sizes of more than one wavefront.
1353 */
1354 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1355 device->physical_device->rad_info.family == CHIP_KABINI ||
1356 device->physical_device->rad_info.family == CHIP_MULLINS)
1357 *lds_size = MAX2(*lds_size, 8);
1358 }
1359
1360 struct radv_shader_variant *
1361 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1362 {
1363 if (pipeline->shaders[MESA_SHADER_VERTEX])
1364 return pipeline->shaders[MESA_SHADER_VERTEX];
1365 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1366 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1367 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1368 }
1369
1370 static struct radv_shader_variant *
1371 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1372 {
1373 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1374 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1375 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1376 }
1377
1378 static struct radv_tessellation_state
1379 calculate_tess_state(struct radv_pipeline *pipeline,
1380 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1381 {
1382 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1383 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1384 unsigned num_tcs_patch_outputs;
1385 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1386 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1387 unsigned lds_size, hardware_lds_size;
1388 unsigned perpatch_output_offset;
1389 unsigned num_patches;
1390 struct radv_tessellation_state tess = {0};
1391
1392 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1393 * are laid out in LDS. */
1394 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1395
1396 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1397 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1398 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1399
1400 /* Ensure that we only need one wave per SIMD so we don't need to check
1401 * resource usage. Also ensures that the number of tcs in and out
1402 * vertices per threadgroup are at most 256.
1403 */
1404 input_vertex_size = num_tcs_inputs * 16;
1405 output_vertex_size = num_tcs_outputs * 16;
1406
1407 input_patch_size = num_tcs_input_cp * input_vertex_size;
1408
1409 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1410 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1411 /* Ensure that we only need one wave per SIMD so we don't need to check
1412 * resource usage. Also ensures that the number of tcs in and out
1413 * vertices per threadgroup are at most 256.
1414 */
1415 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1416
1417 /* Make sure that the data fits in LDS. This assumes the shaders only
1418 * use LDS for the inputs and outputs.
1419 */
1420 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1421 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1422
1423 /* Make sure the output data fits in the offchip buffer */
1424 num_patches = MIN2(num_patches,
1425 (pipeline->device->tess_offchip_block_dw_size * 4) /
1426 output_patch_size);
1427
1428 /* Not necessary for correctness, but improves performance. The
1429 * specific value is taken from the proprietary driver.
1430 */
1431 num_patches = MIN2(num_patches, 40);
1432
1433 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1434 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1435 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1436 num_patches = MIN2(num_patches, one_wave);
1437 }
1438
1439 output_patch0_offset = input_patch_size * num_patches;
1440 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1441
1442 lds_size = output_patch0_offset + output_patch_size * num_patches;
1443
1444 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1445 assert(lds_size <= 65536);
1446 lds_size = align(lds_size, 512) / 512;
1447 } else {
1448 assert(lds_size <= 32768);
1449 lds_size = align(lds_size, 256) / 256;
1450 }
1451 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1452
1453 tess.lds_size = lds_size;
1454
1455 tess.tcs_in_layout = (input_patch_size / 4) |
1456 ((input_vertex_size / 4) << 13);
1457 tess.tcs_out_layout = (output_patch_size / 4) |
1458 ((output_vertex_size / 4) << 13);
1459 tess.tcs_out_offsets = (output_patch0_offset / 16) |
1460 ((perpatch_output_offset / 16) << 16);
1461 tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1462 (num_tcs_output_cp << 9) | num_patches;
1463
1464 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1465 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1466 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1467 tess.num_patches = num_patches;
1468 tess.num_tcs_input_cp = num_tcs_input_cp;
1469
1470 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1471 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1472
1473 switch (tes->info.tes.primitive_mode) {
1474 case GL_TRIANGLES:
1475 type = V_028B6C_TESS_TRIANGLE;
1476 break;
1477 case GL_QUADS:
1478 type = V_028B6C_TESS_QUAD;
1479 break;
1480 case GL_ISOLINES:
1481 type = V_028B6C_TESS_ISOLINE;
1482 break;
1483 }
1484
1485 switch (tes->info.tes.spacing) {
1486 case TESS_SPACING_EQUAL:
1487 partitioning = V_028B6C_PART_INTEGER;
1488 break;
1489 case TESS_SPACING_FRACTIONAL_ODD:
1490 partitioning = V_028B6C_PART_FRAC_ODD;
1491 break;
1492 case TESS_SPACING_FRACTIONAL_EVEN:
1493 partitioning = V_028B6C_PART_FRAC_EVEN;
1494 break;
1495 default:
1496 break;
1497 }
1498
1499 bool ccw = tes->info.tes.ccw;
1500 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1501 vk_find_struct_const(pCreateInfo->pTessellationState,
1502 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1503
1504 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1505 ccw = !ccw;
1506
1507 if (tes->info.tes.point_mode)
1508 topology = V_028B6C_OUTPUT_POINT;
1509 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1510 topology = V_028B6C_OUTPUT_LINE;
1511 else if (ccw)
1512 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1513 else
1514 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1515
1516 if (pipeline->device->has_distributed_tess) {
1517 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1518 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1519 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1520 else
1521 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1522 } else
1523 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1524
1525 tess.tf_param = S_028B6C_TYPE(type) |
1526 S_028B6C_PARTITIONING(partitioning) |
1527 S_028B6C_TOPOLOGY(topology) |
1528 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1529
1530 return tess;
1531 }
1532
1533 static const struct radv_prim_vertex_count prim_size_table[] = {
1534 [V_008958_DI_PT_NONE] = {0, 0},
1535 [V_008958_DI_PT_POINTLIST] = {1, 1},
1536 [V_008958_DI_PT_LINELIST] = {2, 2},
1537 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1538 [V_008958_DI_PT_TRILIST] = {3, 3},
1539 [V_008958_DI_PT_TRIFAN] = {3, 1},
1540 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1541 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1542 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1543 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1544 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1545 [V_008958_DI_PT_RECTLIST] = {3, 3},
1546 [V_008958_DI_PT_LINELOOP] = {2, 1},
1547 [V_008958_DI_PT_POLYGON] = {3, 1},
1548 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1549 };
1550
1551 static const struct ac_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1552 {
1553 if (radv_pipeline_has_gs(pipeline))
1554 return &pipeline->gs_copy_shader->info.vs.outinfo;
1555 else if (radv_pipeline_has_tess(pipeline))
1556 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1557 else
1558 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1559 }
1560
1561 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1562 {
1563 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1564
1565 pipeline->graphics.vgt_primitiveid_en = false;
1566 pipeline->graphics.vgt_gs_mode = 0;
1567
1568 if (radv_pipeline_has_gs(pipeline)) {
1569 struct radv_shader_variant *gs =
1570 pipeline->shaders[MESA_SHADER_GEOMETRY];
1571
1572 pipeline->graphics.vgt_gs_mode =
1573 ac_vgt_gs_mode(gs->info.gs.vertices_out,
1574 pipeline->device->physical_device->rad_info.chip_class);
1575 } else if (outinfo->export_prim_id) {
1576 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1577 pipeline->graphics.vgt_primitiveid_en = true;
1578 }
1579 }
1580
1581 static void
1582 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1583 {
1584 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1585 int shader_count = 0;
1586
1587 if(shaders[MESA_SHADER_FRAGMENT]) {
1588 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1589 }
1590 if(shaders[MESA_SHADER_GEOMETRY]) {
1591 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1592 }
1593 if(shaders[MESA_SHADER_TESS_EVAL]) {
1594 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1595 }
1596 if(shaders[MESA_SHADER_TESS_CTRL]) {
1597 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1598 }
1599 if(shaders[MESA_SHADER_VERTEX]) {
1600 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1601 }
1602
1603 for (int i = 1; i < shader_count; ++i) {
1604 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1605 ordered_shaders[i - 1]);
1606
1607 nir_remove_dead_variables(ordered_shaders[i],
1608 nir_var_shader_out);
1609 nir_remove_dead_variables(ordered_shaders[i - 1],
1610 nir_var_shader_in);
1611
1612 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1613 ordered_shaders[i - 1]);
1614
1615 if (progress) {
1616 nir_lower_global_vars_to_local(ordered_shaders[i]);
1617 radv_optimize_nir(ordered_shaders[i]);
1618 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1619 radv_optimize_nir(ordered_shaders[i - 1]);
1620 }
1621 }
1622 }
1623
1624
1625 static struct radv_pipeline_key
1626 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1627 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1628 const struct radv_blend_state *blend,
1629 bool has_view_index)
1630 {
1631 const VkPipelineVertexInputStateCreateInfo *input_state =
1632 pCreateInfo->pVertexInputState;
1633 struct radv_pipeline_key key;
1634 memset(&key, 0, sizeof(key));
1635
1636 key.has_multiview_view_index = has_view_index;
1637
1638 uint32_t binding_input_rate = 0;
1639 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1640 if (input_state->pVertexBindingDescriptions[i].inputRate)
1641 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1642 }
1643
1644 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1645 unsigned binding;
1646 binding = input_state->pVertexAttributeDescriptions[i].binding;
1647 if (binding_input_rate & (1u << binding))
1648 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1649 }
1650
1651 if (pCreateInfo->pTessellationState)
1652 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1653
1654
1655 if (pCreateInfo->pMultisampleState &&
1656 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1657 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1658 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1659 key.multisample = true;
1660 key.log2_num_samples = util_logbase2(num_samples);
1661 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1662 }
1663
1664 key.col_format = blend->spi_shader_col_format;
1665 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1666 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1667
1668 return key;
1669 }
1670
1671 static void
1672 radv_fill_shader_keys(struct ac_shader_variant_key *keys,
1673 const struct radv_pipeline_key *key,
1674 nir_shader **nir)
1675 {
1676 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1677
1678 if (nir[MESA_SHADER_TESS_CTRL]) {
1679 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1680 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1681 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1682
1683 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1684 }
1685
1686 if (nir[MESA_SHADER_GEOMETRY]) {
1687 if (nir[MESA_SHADER_TESS_CTRL])
1688 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1689 else
1690 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1691 }
1692
1693 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1694 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1695
1696 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1697 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1698 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1699 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1700 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1701 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1702 }
1703
1704 static void
1705 merge_tess_info(struct shader_info *tes_info,
1706 const struct shader_info *tcs_info)
1707 {
1708 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1709 *
1710 * "PointMode. Controls generation of points rather than triangles
1711 * or lines. This functionality defaults to disabled, and is
1712 * enabled if either shader stage includes the execution mode.
1713 *
1714 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1715 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1716 * and OutputVertices, it says:
1717 *
1718 * "One mode must be set in at least one of the tessellation
1719 * shader stages."
1720 *
1721 * So, the fields can be set in either the TCS or TES, but they must
1722 * agree if set in both. Our backend looks at TES, so bitwise-or in
1723 * the values from the TCS.
1724 */
1725 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1726 tes_info->tess.tcs_vertices_out == 0 ||
1727 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1728 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1729
1730 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1731 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1732 tcs_info->tess.spacing == tes_info->tess.spacing);
1733 tes_info->tess.spacing |= tcs_info->tess.spacing;
1734
1735 assert(tcs_info->tess.primitive_mode == 0 ||
1736 tes_info->tess.primitive_mode == 0 ||
1737 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1738 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1739 tes_info->tess.ccw |= tcs_info->tess.ccw;
1740 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1741 }
1742
1743 static
1744 void radv_create_shaders(struct radv_pipeline *pipeline,
1745 struct radv_device *device,
1746 struct radv_pipeline_cache *cache,
1747 struct radv_pipeline_key key,
1748 const VkPipelineShaderStageCreateInfo **pStages)
1749 {
1750 struct radv_shader_module fs_m = {0};
1751 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1752 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1753 void *codes[MESA_SHADER_STAGES] = {0};
1754 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1755 struct ac_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1756 unsigned char hash[20], gs_copy_hash[20];
1757
1758 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1759 if (pStages[i]) {
1760 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1761 if (modules[i]->nir)
1762 _mesa_sha1_compute(modules[i]->nir->info.name,
1763 strlen(modules[i]->nir->info.name),
1764 modules[i]->sha1);
1765 }
1766 }
1767
1768 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1769 memcpy(gs_copy_hash, hash, 20);
1770 gs_copy_hash[0] ^= 1;
1771
1772 if (modules[MESA_SHADER_GEOMETRY]) {
1773 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1774 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1775 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1776 }
1777
1778 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1779 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1780 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1781 if (pipeline->shaders[i])
1782 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1783 }
1784 return;
1785 }
1786
1787 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1788 nir_builder fs_b;
1789 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1790 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1791 fs_m.nir = fs_b.shader;
1792 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1793 }
1794
1795 /* Determine first and last stage. */
1796 unsigned first = MESA_SHADER_STAGES;
1797 unsigned last = 0;
1798 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1799 if (!pStages[i])
1800 continue;
1801 if (first == MESA_SHADER_STAGES)
1802 first = i;
1803 last = i;
1804 }
1805
1806 int prev = -1;
1807 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1808 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1809
1810 if (!modules[i])
1811 continue;
1812
1813 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1814 stage ? stage->pName : "main", i,
1815 stage ? stage->pSpecializationInfo : NULL);
1816 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1817
1818 /* We don't want to alter meta shaders IR directly so clone it
1819 * first.
1820 */
1821 if (nir[i]->info.name) {
1822 nir[i] = nir_shader_clone(NULL, nir[i]);
1823 }
1824
1825 if (first != last) {
1826 nir_variable_mode mask = 0;
1827
1828 if (i != first)
1829 mask = mask | nir_var_shader_in;
1830
1831 if (i != last)
1832 mask = mask | nir_var_shader_out;
1833
1834 nir_lower_io_to_scalar_early(nir[i], mask);
1835 radv_optimize_nir(nir[i]);
1836 }
1837
1838 if (prev != -1) {
1839 nir_compact_varyings(nir[prev], nir[i], true);
1840 }
1841 prev = i;
1842 }
1843
1844 if (nir[MESA_SHADER_TESS_CTRL]) {
1845 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1846 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1847 }
1848
1849 radv_link_shaders(pipeline, nir);
1850
1851 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1852 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1853 nir_print_shader(nir[i], stderr);
1854 }
1855
1856 radv_fill_shader_keys(keys, &key, nir);
1857
1858 if (nir[MESA_SHADER_FRAGMENT]) {
1859 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1860 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1861 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1862 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1863 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1864 }
1865
1866 /* TODO: These are no longer used as keys we should refactor this */
1867 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1868 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1869 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1870 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1871 }
1872
1873 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1874 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1875 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1876 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1877 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1878 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1879 pipeline->layout,
1880 &key, &codes[MESA_SHADER_TESS_CTRL],
1881 &code_sizes[MESA_SHADER_TESS_CTRL]);
1882 }
1883 modules[MESA_SHADER_VERTEX] = NULL;
1884 }
1885
1886 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1887 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1888 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1889 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1890 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1891 pipeline->layout,
1892 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1893 &code_sizes[MESA_SHADER_GEOMETRY]);
1894 }
1895 modules[pre_stage] = NULL;
1896 }
1897
1898 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1899 if(modules[i] && !pipeline->shaders[i]) {
1900 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1901 pipeline->layout,
1902 keys + i, &codes[i],
1903 &code_sizes[i]);
1904 }
1905 }
1906
1907 if(modules[MESA_SHADER_GEOMETRY]) {
1908 void *gs_copy_code = NULL;
1909 unsigned gs_copy_code_size = 0;
1910 if (!pipeline->gs_copy_shader) {
1911 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1912 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1913 &gs_copy_code_size,
1914 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1915 }
1916
1917 if (pipeline->gs_copy_shader) {
1918 void *code[MESA_SHADER_STAGES] = {0};
1919 unsigned code_size[MESA_SHADER_STAGES] = {0};
1920 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1921
1922 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1923 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1924 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1925
1926 radv_pipeline_cache_insert_shaders(device, cache,
1927 gs_copy_hash,
1928 variants,
1929 (const void**)code,
1930 code_size);
1931 }
1932 free(gs_copy_code);
1933 }
1934
1935 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1936 (const void**)codes, code_sizes);
1937
1938 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1939 free(codes[i]);
1940 if (modules[i] && !pipeline->device->keep_shader_info)
1941 ralloc_free(nir[i]);
1942 }
1943
1944 if (fs_m.nir)
1945 ralloc_free(fs_m.nir);
1946 }
1947
1948 static uint32_t
1949 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1950 gl_shader_stage stage, enum chip_class chip_class)
1951 {
1952 bool has_gs = radv_pipeline_has_gs(pipeline);
1953 bool has_tess = radv_pipeline_has_tess(pipeline);
1954 switch (stage) {
1955 case MESA_SHADER_FRAGMENT:
1956 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1957 case MESA_SHADER_VERTEX:
1958 if (chip_class >= GFX9) {
1959 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1960 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1961 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1962 }
1963 if (has_tess)
1964 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1965 else
1966 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1967 case MESA_SHADER_GEOMETRY:
1968 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1969 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1970 case MESA_SHADER_COMPUTE:
1971 return R_00B900_COMPUTE_USER_DATA_0;
1972 case MESA_SHADER_TESS_CTRL:
1973 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1974 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1975 case MESA_SHADER_TESS_EVAL:
1976 if (chip_class >= GFX9) {
1977 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1978 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1979 }
1980 if (has_gs)
1981 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1982 else
1983 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1984 default:
1985 unreachable("unknown shader");
1986 }
1987 }
1988
1989 struct radv_bin_size_entry {
1990 unsigned bpp;
1991 VkExtent2D extent;
1992 };
1993
1994 static VkExtent2D
1995 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1996 {
1997 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1998 {
1999 /* One RB / SE */
2000 {
2001 /* One shader engine */
2002 { 0, {128, 128}},
2003 { 1, { 64, 128}},
2004 { 2, { 32, 128}},
2005 { 3, { 16, 128}},
2006 { 17, { 0, 0}},
2007 { UINT_MAX, { 0, 0}},
2008 },
2009 {
2010 /* Two shader engines */
2011 { 0, {128, 128}},
2012 { 2, { 64, 128}},
2013 { 3, { 32, 128}},
2014 { 5, { 16, 128}},
2015 { 17, { 0, 0}},
2016 { UINT_MAX, { 0, 0}},
2017 },
2018 {
2019 /* Four shader engines */
2020 { 0, {128, 128}},
2021 { 3, { 64, 128}},
2022 { 5, { 16, 128}},
2023 { 17, { 0, 0}},
2024 { UINT_MAX, { 0, 0}},
2025 },
2026 },
2027 {
2028 /* Two RB / SE */
2029 {
2030 /* One shader engine */
2031 { 0, {128, 128}},
2032 { 2, { 64, 128}},
2033 { 3, { 32, 128}},
2034 { 5, { 16, 128}},
2035 { 33, { 0, 0}},
2036 { UINT_MAX, { 0, 0}},
2037 },
2038 {
2039 /* Two shader engines */
2040 { 0, {128, 128}},
2041 { 3, { 64, 128}},
2042 { 5, { 32, 128}},
2043 { 9, { 16, 128}},
2044 { 33, { 0, 0}},
2045 { UINT_MAX, { 0, 0}},
2046 },
2047 {
2048 /* Four shader engines */
2049 { 0, {256, 256}},
2050 { 2, {128, 256}},
2051 { 3, {128, 128}},
2052 { 5, { 64, 128}},
2053 { 9, { 16, 128}},
2054 { 33, { 0, 0}},
2055 { UINT_MAX, { 0, 0}},
2056 },
2057 },
2058 {
2059 /* Four RB / SE */
2060 {
2061 /* One shader engine */
2062 { 0, {128, 256}},
2063 { 2, {128, 128}},
2064 { 3, { 64, 128}},
2065 { 5, { 32, 128}},
2066 { 9, { 16, 128}},
2067 { 33, { 0, 0}},
2068 { UINT_MAX, { 0, 0}},
2069 },
2070 {
2071 /* Two shader engines */
2072 { 0, {256, 256}},
2073 { 2, {128, 256}},
2074 { 3, {128, 128}},
2075 { 5, { 64, 128}},
2076 { 9, { 32, 128}},
2077 { 17, { 16, 128}},
2078 { 33, { 0, 0}},
2079 { UINT_MAX, { 0, 0}},
2080 },
2081 {
2082 /* Four shader engines */
2083 { 0, {256, 512}},
2084 { 2, {256, 256}},
2085 { 3, {128, 256}},
2086 { 5, {128, 128}},
2087 { 9, { 64, 128}},
2088 { 17, { 16, 128}},
2089 { 33, { 0, 0}},
2090 { UINT_MAX, { 0, 0}},
2091 },
2092 },
2093 };
2094 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2095 {
2096 // One RB / SE
2097 {
2098 // One shader engine
2099 { 0, {128, 256}},
2100 { 2, {128, 128}},
2101 { 4, { 64, 128}},
2102 { 7, { 32, 128}},
2103 { 13, { 16, 128}},
2104 { 49, { 0, 0}},
2105 { UINT_MAX, { 0, 0}},
2106 },
2107 {
2108 // Two shader engines
2109 { 0, {256, 256}},
2110 { 2, {128, 256}},
2111 { 4, {128, 128}},
2112 { 7, { 64, 128}},
2113 { 13, { 32, 128}},
2114 { 25, { 16, 128}},
2115 { 49, { 0, 0}},
2116 { UINT_MAX, { 0, 0}},
2117 },
2118 {
2119 // Four shader engines
2120 { 0, {256, 512}},
2121 { 2, {256, 256}},
2122 { 4, {128, 256}},
2123 { 7, {128, 128}},
2124 { 13, { 64, 128}},
2125 { 25, { 16, 128}},
2126 { 49, { 0, 0}},
2127 { UINT_MAX, { 0, 0}},
2128 },
2129 },
2130 {
2131 // Two RB / SE
2132 {
2133 // One shader engine
2134 { 0, {256, 256}},
2135 { 2, {128, 256}},
2136 { 4, {128, 128}},
2137 { 7, { 64, 128}},
2138 { 13, { 32, 128}},
2139 { 25, { 16, 128}},
2140 { 97, { 0, 0}},
2141 { UINT_MAX, { 0, 0}},
2142 },
2143 {
2144 // Two shader engines
2145 { 0, {256, 512}},
2146 { 2, {256, 256}},
2147 { 4, {128, 256}},
2148 { 7, {128, 128}},
2149 { 13, { 64, 128}},
2150 { 25, { 32, 128}},
2151 { 49, { 16, 128}},
2152 { 97, { 0, 0}},
2153 { UINT_MAX, { 0, 0}},
2154 },
2155 {
2156 // Four shader engines
2157 { 0, {512, 512}},
2158 { 2, {256, 512}},
2159 { 4, {256, 256}},
2160 { 7, {128, 256}},
2161 { 13, {128, 128}},
2162 { 25, { 64, 128}},
2163 { 49, { 16, 128}},
2164 { 97, { 0, 0}},
2165 { UINT_MAX, { 0, 0}},
2166 },
2167 },
2168 {
2169 // Four RB / SE
2170 {
2171 // One shader engine
2172 { 0, {256, 512}},
2173 { 2, {256, 256}},
2174 { 4, {128, 256}},
2175 { 7, {128, 128}},
2176 { 13, { 64, 128}},
2177 { 25, { 32, 128}},
2178 { 49, { 16, 128}},
2179 { UINT_MAX, { 0, 0}},
2180 },
2181 {
2182 // Two shader engines
2183 { 0, {512, 512}},
2184 { 2, {256, 512}},
2185 { 4, {256, 256}},
2186 { 7, {128, 256}},
2187 { 13, {128, 128}},
2188 { 25, { 64, 128}},
2189 { 49, { 32, 128}},
2190 { 97, { 16, 128}},
2191 { UINT_MAX, { 0, 0}},
2192 },
2193 {
2194 // Four shader engines
2195 { 0, {512, 512}},
2196 { 4, {256, 512}},
2197 { 7, {256, 256}},
2198 { 13, {128, 256}},
2199 { 25, {128, 128}},
2200 { 49, { 64, 128}},
2201 { 97, { 16, 128}},
2202 { UINT_MAX, { 0, 0}},
2203 },
2204 },
2205 };
2206
2207 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2208 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2209 VkExtent2D extent = {512, 512};
2210
2211 unsigned log_num_rb_per_se =
2212 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2213 pipeline->device->physical_device->rad_info.max_se);
2214 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2215
2216 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2217 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2218 unsigned effective_samples = total_samples;
2219 unsigned color_bytes_per_pixel = 0;
2220
2221 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2222 if (vkblend) {
2223 for (unsigned i = 0; i < subpass->color_count; i++) {
2224 if (!vkblend->pAttachments[i].colorWriteMask)
2225 continue;
2226
2227 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2228 continue;
2229
2230 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2231 color_bytes_per_pixel += vk_format_get_blocksize(format);
2232 }
2233
2234 /* MSAA images typically don't use all samples all the time. */
2235 if (effective_samples >= 2 && ps_iter_samples <= 1)
2236 effective_samples = 2;
2237 color_bytes_per_pixel *= effective_samples;
2238 }
2239
2240 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2241 while(color_entry->bpp <= color_bytes_per_pixel)
2242 ++color_entry;
2243
2244 extent = color_entry->extent;
2245
2246 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2247 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2248
2249 /* Coefficients taken from AMDVLK */
2250 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2251 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2252 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2253
2254 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2255 while(ds_entry->bpp <= ds_bytes_per_pixel)
2256 ++ds_entry;
2257
2258 extent.width = MIN2(extent.width, ds_entry->extent.width);
2259 extent.height = MIN2(extent.height, ds_entry->extent.height);
2260 }
2261
2262 return extent;
2263 }
2264
2265 static void
2266 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2267 struct radv_pipeline *pipeline,
2268 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2269 {
2270 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2271 return;
2272
2273 uint32_t pa_sc_binner_cntl_0 =
2274 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2275 S_028C44_DISABLE_START_OF_PRIM(1);
2276 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2277
2278 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2279
2280 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2281 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2282 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2283
2284 switch (pipeline->device->physical_device->rad_info.family) {
2285 case CHIP_VEGA10:
2286 context_states_per_bin = 1;
2287 persistent_states_per_bin = 1;
2288 fpovs_per_batch = 63;
2289 break;
2290 case CHIP_RAVEN:
2291 context_states_per_bin = 6;
2292 persistent_states_per_bin = 32;
2293 fpovs_per_batch = 63;
2294 break;
2295 default:
2296 unreachable("unhandled family while determining binning state.");
2297 }
2298
2299 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2300 pa_sc_binner_cntl_0 =
2301 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2302 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2303 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2304 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2305 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2306 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2307 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2308 S_028C44_DISABLE_START_OF_PRIM(1) |
2309 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2310 S_028C44_OPTIMAL_BIN_SELECTION(1);
2311 }
2312
2313 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2314 pa_sc_binner_cntl_0);
2315 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2316 db_dfsm_control);
2317 }
2318
2319
2320 static void
2321 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2322 struct radv_pipeline *pipeline,
2323 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2324 const struct radv_graphics_pipeline_create_info *extra)
2325 {
2326 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2327 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2328 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2329 struct radv_render_pass_attachment *attachment = NULL;
2330 uint32_t db_depth_control = 0, db_stencil_control = 0;
2331 uint32_t db_render_control = 0, db_render_override2 = 0;
2332
2333 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2334 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2335
2336 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2337 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2338
2339 if (vkds && has_depth_attachment) {
2340 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2341 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2342 S_028800_ZFUNC(vkds->depthCompareOp) |
2343 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2344
2345 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2346 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2347 }
2348
2349 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2350 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2351 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2352 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2353 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2354 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2355
2356 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2357 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2358 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2359 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2360 }
2361
2362 if (attachment && extra) {
2363 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2364 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2365
2366 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2367 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2368 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2369 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2370 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2371 }
2372
2373 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2374 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2375
2376 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2377 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2378 }
2379
2380 static void
2381 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2382 struct radv_pipeline *pipeline,
2383 const struct radv_blend_state *blend)
2384 {
2385 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2386 radeon_emit_array(cs, blend->cb_blend_control,
2387 8);
2388 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2389 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2390
2391 if (pipeline->device->physical_device->has_rbplus) {
2392
2393 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2394 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2395
2396 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2397 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2398 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2399 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2400 }
2401
2402 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2403
2404 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2405 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2406 }
2407
2408
2409 static void
2410 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2411 struct radv_pipeline *pipeline)
2412 {
2413 struct radv_raster_state *raster = &pipeline->graphics.raster;
2414
2415 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2416 raster->pa_cl_clip_cntl);
2417 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2418 raster->spi_interp_control);
2419 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2420 raster->pa_su_vtx_cntl);
2421 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2422 raster->pa_su_sc_mode_cntl);
2423 }
2424
2425
2426 static void
2427 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2428 struct radv_pipeline *pipeline)
2429 {
2430 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2431
2432 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2433 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2434 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2435
2436 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2437 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2438
2439 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2440 uint32_t offset;
2441 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2442 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2443 if (loc->sgpr_idx == -1)
2444 return;
2445 assert(loc->num_sgprs == 1);
2446 assert(!loc->indirect);
2447 switch (pipeline->graphics.ms.num_samples) {
2448 default:
2449 offset = 0;
2450 break;
2451 case 2:
2452 offset = 1;
2453 break;
2454 case 4:
2455 offset = 3;
2456 break;
2457 case 8:
2458 offset = 7;
2459 break;
2460 case 16:
2461 offset = 15;
2462 break;
2463 }
2464
2465 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2466 }
2467 }
2468
2469 static void
2470 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2471 struct radv_pipeline *pipeline,
2472 struct radv_shader_variant *shader)
2473 {
2474 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2475
2476 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2477 radeon_emit(cs, va >> 8);
2478 radeon_emit(cs, va >> 40);
2479 radeon_emit(cs, shader->rsrc1);
2480 radeon_emit(cs, shader->rsrc2);
2481
2482 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2483 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2484 clip_dist_mask = outinfo->clip_dist_mask;
2485 cull_dist_mask = outinfo->cull_dist_mask;
2486 total_mask = clip_dist_mask | cull_dist_mask;
2487 bool misc_vec_ena = outinfo->writes_pointsize ||
2488 outinfo->writes_layer ||
2489 outinfo->writes_viewport_index;
2490
2491 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2492 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2493
2494 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2495 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2496 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2497 V_02870C_SPI_SHADER_4COMP :
2498 V_02870C_SPI_SHADER_NONE) |
2499 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2500 V_02870C_SPI_SHADER_4COMP :
2501 V_02870C_SPI_SHADER_NONE) |
2502 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2503 V_02870C_SPI_SHADER_4COMP :
2504 V_02870C_SPI_SHADER_NONE));
2505
2506 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2507 S_028818_VTX_W0_FMT(1) |
2508 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2509 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2510 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2511
2512 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2513 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2514 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2515 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2516 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2517 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2518 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2519 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2520 cull_dist_mask << 8 |
2521 clip_dist_mask);
2522
2523 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2524 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2525 outinfo->writes_viewport_index);
2526 }
2527
2528 static void
2529 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2530 struct radv_pipeline *pipeline,
2531 struct radv_shader_variant *shader)
2532 {
2533 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2534
2535 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2536 radeon_emit(cs, va >> 8);
2537 radeon_emit(cs, va >> 40);
2538 radeon_emit(cs, shader->rsrc1);
2539 radeon_emit(cs, shader->rsrc2);
2540 }
2541
2542 static void
2543 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2544 struct radv_pipeline *pipeline,
2545 struct radv_shader_variant *shader,
2546 const struct radv_tessellation_state *tess)
2547 {
2548 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2549 uint32_t rsrc2 = shader->rsrc2;
2550
2551 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2552 radeon_emit(cs, va >> 8);
2553 radeon_emit(cs, va >> 40);
2554
2555 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2556 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2557 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2558 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2559
2560 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2561 radeon_emit(cs, shader->rsrc1);
2562 radeon_emit(cs, rsrc2);
2563 }
2564
2565 static void
2566 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2567 struct radv_pipeline *pipeline,
2568 struct radv_shader_variant *shader,
2569 const struct radv_tessellation_state *tess)
2570 {
2571 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2572
2573 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2574 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2575 radeon_emit(cs, va >> 8);
2576 radeon_emit(cs, va >> 40);
2577
2578 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2579 radeon_emit(cs, shader->rsrc1);
2580 radeon_emit(cs, shader->rsrc2 |
2581 S_00B42C_LDS_SIZE(tess->lds_size));
2582 } else {
2583 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2584 radeon_emit(cs, va >> 8);
2585 radeon_emit(cs, va >> 40);
2586 radeon_emit(cs, shader->rsrc1);
2587 radeon_emit(cs, shader->rsrc2);
2588 }
2589 }
2590
2591 static void
2592 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2593 struct radv_pipeline *pipeline,
2594 const struct radv_tessellation_state *tess)
2595 {
2596 struct radv_shader_variant *vs;
2597
2598 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
2599
2600 /* Skip shaders merged into HS/GS */
2601 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2602 if (!vs)
2603 return;
2604
2605 if (vs->info.vs.as_ls)
2606 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2607 else if (vs->info.vs.as_es)
2608 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2609 else
2610 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2611 }
2612
2613 static void
2614 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2615 struct radv_pipeline *pipeline,
2616 const struct radv_tessellation_state *tess)
2617 {
2618 if (!radv_pipeline_has_tess(pipeline))
2619 return;
2620
2621 struct radv_shader_variant *tes, *tcs;
2622
2623 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2624 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2625
2626 if (tes) {
2627 if (tes->info.tes.as_es)
2628 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2629 else
2630 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2631 }
2632
2633 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2634
2635 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2636 tess->tf_param);
2637
2638 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2639 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2640 tess->ls_hs_config);
2641 else
2642 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2643 tess->ls_hs_config);
2644
2645 struct ac_userdata_info *loc;
2646
2647 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
2648 if (loc->sgpr_idx != -1) {
2649 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
2650 assert(loc->num_sgprs == 4);
2651 assert(!loc->indirect);
2652 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
2653 radeon_emit(cs, tess->offchip_layout);
2654 radeon_emit(cs, tess->tcs_out_offsets);
2655 radeon_emit(cs, tess->tcs_out_layout |
2656 tess->num_tcs_input_cp << 26);
2657 radeon_emit(cs, tess->tcs_in_layout);
2658 }
2659
2660 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
2661 if (loc->sgpr_idx != -1) {
2662 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
2663 assert(loc->num_sgprs == 1);
2664 assert(!loc->indirect);
2665
2666 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2667 tess->offchip_layout);
2668 }
2669
2670 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
2671 if (loc->sgpr_idx != -1) {
2672 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
2673 assert(loc->num_sgprs == 1);
2674 assert(!loc->indirect);
2675
2676 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4,
2677 tess->tcs_in_layout);
2678 }
2679 }
2680
2681 static void
2682 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2683 struct radv_pipeline *pipeline)
2684 {
2685 struct radv_shader_variant *gs;
2686 uint64_t va;
2687
2688 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
2689
2690 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2691 if (!gs)
2692 return;
2693
2694 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2695
2696 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2697 radeon_emit(cs, gsvs_itemsize);
2698 radeon_emit(cs, gsvs_itemsize);
2699 radeon_emit(cs, gsvs_itemsize);
2700
2701 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2702
2703 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2704
2705 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2706 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2707 radeon_emit(cs, gs_vert_itemsize >> 2);
2708 radeon_emit(cs, 0);
2709 radeon_emit(cs, 0);
2710 radeon_emit(cs, 0);
2711
2712 uint32_t gs_num_invocations = gs->info.gs.invocations;
2713 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2714 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2715 S_028B90_ENABLE(gs_num_invocations > 0));
2716
2717 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2718 pipeline->graphics.gs.vgt_esgs_ring_itemsize);
2719
2720 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2721
2722 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2723 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2724 radeon_emit(cs, va >> 8);
2725 radeon_emit(cs, va >> 40);
2726
2727 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2728 radeon_emit(cs, gs->rsrc1);
2729 radeon_emit(cs, gs->rsrc2 |
2730 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
2731
2732 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
2733 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
2734 } else {
2735 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2736 radeon_emit(cs, va >> 8);
2737 radeon_emit(cs, va >> 40);
2738 radeon_emit(cs, gs->rsrc1);
2739 radeon_emit(cs, gs->rsrc2);
2740 }
2741
2742 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2743
2744 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
2745 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
2746 if (loc->sgpr_idx != -1) {
2747 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
2748 uint32_t num_entries = 64;
2749 bool is_vi = pipeline->device->physical_device->rad_info.chip_class >= VI;
2750
2751 if (is_vi)
2752 num_entries *= stride;
2753
2754 stride = S_008F04_STRIDE(stride);
2755 radeon_set_sh_reg_seq(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
2756 radeon_emit(cs, stride);
2757 radeon_emit(cs, num_entries);
2758 }
2759 }
2760
2761 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2762 {
2763 uint32_t ps_input_cntl;
2764 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2765 ps_input_cntl = S_028644_OFFSET(offset);
2766 if (flat_shade)
2767 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2768 } else {
2769 /* The input is a DEFAULT_VAL constant. */
2770 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2771 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2772 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2773 ps_input_cntl = S_028644_OFFSET(0x20) |
2774 S_028644_DEFAULT_VAL(offset);
2775 }
2776 return ps_input_cntl;
2777 }
2778
2779 static void
2780 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2781 struct radv_pipeline *pipeline)
2782 {
2783 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2784 const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
2785 uint32_t ps_input_cntl[32];
2786
2787 unsigned ps_offset = 0;
2788
2789 if (ps->info.fs.prim_id_input) {
2790 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2791 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2792 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2793 ++ps_offset;
2794 }
2795 }
2796
2797 if (ps->info.fs.layer_input) {
2798 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2799 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2800 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2801 else
2802 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2803 ++ps_offset;
2804 }
2805
2806 if (ps->info.fs.has_pcoord) {
2807 unsigned val;
2808 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2809 ps_input_cntl[ps_offset] = val;
2810 ps_offset++;
2811 }
2812
2813 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2814 unsigned vs_offset;
2815 bool flat_shade;
2816 if (!(ps->info.fs.input_mask & (1u << i)))
2817 continue;
2818
2819 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2820 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2821 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2822 ++ps_offset;
2823 continue;
2824 }
2825
2826 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2827
2828 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2829 ++ps_offset;
2830 }
2831
2832 if (ps_offset) {
2833 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2834 for (unsigned i = 0; i < ps_offset; i++) {
2835 radeon_emit(cs, ps_input_cntl[i]);
2836 }
2837 }
2838 }
2839
2840 static uint32_t
2841 radv_compute_db_shader_control(const struct radv_device *device,
2842 const struct radv_shader_variant *ps)
2843 {
2844 unsigned z_order;
2845 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2846 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2847 else
2848 z_order = V_02880C_LATE_Z;
2849
2850 return S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2851 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2852 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2853 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2854 S_02880C_Z_ORDER(z_order) |
2855 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2856 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2857 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2858 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2859 }
2860
2861 static void
2862 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2863 struct radv_pipeline *pipeline)
2864 {
2865 struct radv_shader_variant *ps;
2866 uint64_t va;
2867 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2868
2869 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2870 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2871
2872 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2873 radeon_emit(cs, va >> 8);
2874 radeon_emit(cs, va >> 40);
2875 radeon_emit(cs, ps->rsrc1);
2876 radeon_emit(cs, ps->rsrc2);
2877
2878 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2879 radv_compute_db_shader_control(pipeline->device, ps));
2880
2881 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2882 ps->config.spi_ps_input_ena);
2883
2884 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2885 ps->config.spi_ps_input_addr);
2886
2887 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2888 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2889
2890 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2891
2892 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2893 ac_get_spi_shader_z_format(ps->info.fs.writes_z,
2894 ps->info.fs.writes_stencil,
2895 ps->info.fs.writes_sample_mask));
2896
2897 if (pipeline->device->dfsm_allowed) {
2898 /* optimise this? */
2899 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2900 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2901 }
2902 }
2903
2904 static void
2905 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2906 struct radv_pipeline *pipeline)
2907 {
2908 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2909 return;
2910
2911 unsigned vtx_reuse_depth = 30;
2912 if (radv_pipeline_has_tess(pipeline) &&
2913 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2914 vtx_reuse_depth = 14;
2915 }
2916 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2917 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2918 }
2919
2920 static uint32_t
2921 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2922 {
2923 uint32_t stages = 0;
2924 if (radv_pipeline_has_tess(pipeline)) {
2925 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2926 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2927
2928 if (radv_pipeline_has_gs(pipeline))
2929 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2930 S_028B54_GS_EN(1) |
2931 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2932 else
2933 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2934
2935 } else if (radv_pipeline_has_gs(pipeline))
2936 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2937 S_028B54_GS_EN(1) |
2938 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2939
2940 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2941 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2942
2943 return stages;
2944 }
2945
2946 static void
2947 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2948 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2949 const struct radv_graphics_pipeline_create_info *extra,
2950 const struct radv_blend_state *blend,
2951 const struct radv_tessellation_state *tess)
2952 {
2953 pipeline->cs.buf = malloc(4 * 256);
2954 pipeline->cs.max_dw = 256;
2955
2956 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2957 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2958 radv_pipeline_generate_raster_state(&pipeline->cs, pipeline);
2959 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2960 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2961 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2962 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline);
2963 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2964 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2965 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2966 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2967
2968 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2969 S_0286E8_WAVES(pipeline->max_waves) |
2970 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2971
2972 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2973
2974 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2975 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
2976 } else {
2977 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
2978 }
2979 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
2980
2981 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, pipeline->graphics.pa_sc_cliprect_rule);
2982
2983 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2984 }
2985
2986 static struct radv_ia_multi_vgt_param_helpers
2987 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2988 const struct radv_tessellation_state *tess)
2989 {
2990 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2991 const struct radv_device *device = pipeline->device;
2992
2993 if (radv_pipeline_has_tess(pipeline))
2994 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2995 else if (radv_pipeline_has_gs(pipeline))
2996 ia_multi_vgt_param.primgroup_size = 64;
2997 else
2998 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2999
3000 ia_multi_vgt_param.partial_es_wave = false;
3001 if (pipeline->device->has_distributed_tess) {
3002 if (radv_pipeline_has_gs(pipeline)) {
3003 if (device->physical_device->rad_info.chip_class <= VI)
3004 ia_multi_vgt_param.partial_es_wave = true;
3005 }
3006 }
3007 /* GS requirement. */
3008 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
3009 ia_multi_vgt_param.partial_es_wave = true;
3010
3011 ia_multi_vgt_param.wd_switch_on_eop = false;
3012 if (device->physical_device->rad_info.chip_class >= CIK) {
3013 unsigned prim = pipeline->graphics.prim;
3014 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
3015 * 4 shader engines. Set 1 to pass the assertion below.
3016 * The other cases are hardware requirements. */
3017 if (device->physical_device->rad_info.max_se < 4 ||
3018 prim == V_008958_DI_PT_POLYGON ||
3019 prim == V_008958_DI_PT_LINELOOP ||
3020 prim == V_008958_DI_PT_TRIFAN ||
3021 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
3022 (pipeline->graphics.prim_restart_enable &&
3023 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
3024 (prim != V_008958_DI_PT_POINTLIST &&
3025 prim != V_008958_DI_PT_LINESTRIP &&
3026 prim != V_008958_DI_PT_TRISTRIP))))
3027 ia_multi_vgt_param.wd_switch_on_eop = true;
3028 }
3029
3030 ia_multi_vgt_param.ia_switch_on_eoi = false;
3031 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
3032 ia_multi_vgt_param.ia_switch_on_eoi = true;
3033 if (radv_pipeline_has_gs(pipeline) &&
3034 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
3035 ia_multi_vgt_param.ia_switch_on_eoi = true;
3036 if (radv_pipeline_has_tess(pipeline)) {
3037 /* SWITCH_ON_EOI must be set if PrimID is used. */
3038 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
3039 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
3040 ia_multi_vgt_param.ia_switch_on_eoi = true;
3041 }
3042
3043 ia_multi_vgt_param.partial_vs_wave = false;
3044 if (radv_pipeline_has_tess(pipeline)) {
3045 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
3046 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
3047 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
3048 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
3049 radv_pipeline_has_gs(pipeline))
3050 ia_multi_vgt_param.partial_vs_wave = true;
3051 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
3052 if (device->has_distributed_tess) {
3053 if (radv_pipeline_has_gs(pipeline)) {
3054 if (device->physical_device->rad_info.family == CHIP_TONGA ||
3055 device->physical_device->rad_info.family == CHIP_FIJI ||
3056 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
3057 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
3058 device->physical_device->rad_info.family == CHIP_POLARIS12)
3059 ia_multi_vgt_param.partial_vs_wave = true;
3060 } else {
3061 ia_multi_vgt_param.partial_vs_wave = true;
3062 }
3063 }
3064 }
3065
3066 ia_multi_vgt_param.base =
3067 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3068 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3069 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3070 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3071 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3072
3073 return ia_multi_vgt_param;
3074 }
3075
3076
3077 static void
3078 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3079 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3080 {
3081 const VkPipelineVertexInputStateCreateInfo *vi_info =
3082 pCreateInfo->pVertexInputState;
3083 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3084
3085 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3086 const VkVertexInputAttributeDescription *desc =
3087 &vi_info->pVertexAttributeDescriptions[i];
3088 unsigned loc = desc->location;
3089 const struct vk_format_description *format_desc;
3090 int first_non_void;
3091 uint32_t num_format, data_format;
3092 format_desc = vk_format_description(desc->format);
3093 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3094
3095 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3096 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3097
3098 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3099 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3100 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3101 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3102 S_008F0C_NUM_FORMAT(num_format) |
3103 S_008F0C_DATA_FORMAT(data_format);
3104 velems->format_size[loc] = format_desc->block.bits / 8;
3105 velems->offset[loc] = desc->offset;
3106 velems->binding[loc] = desc->binding;
3107 velems->count = MAX2(velems->count, loc + 1);
3108 }
3109
3110 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3111 const VkVertexInputBindingDescription *desc =
3112 &vi_info->pVertexBindingDescriptions[i];
3113
3114 pipeline->binding_stride[desc->binding] = desc->stride;
3115 }
3116 }
3117
3118 static VkResult
3119 radv_pipeline_init(struct radv_pipeline *pipeline,
3120 struct radv_device *device,
3121 struct radv_pipeline_cache *cache,
3122 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3123 const struct radv_graphics_pipeline_create_info *extra,
3124 const VkAllocationCallbacks *alloc)
3125 {
3126 VkResult result;
3127 bool has_view_index = false;
3128
3129 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3130 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3131 if (subpass->view_mask)
3132 has_view_index = true;
3133 if (alloc == NULL)
3134 alloc = &device->alloc;
3135
3136 pipeline->device = device;
3137 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3138 assert(pipeline->layout);
3139
3140 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3141
3142 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3143 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3144 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3145 pStages[stage] = &pCreateInfo->pStages[i];
3146 }
3147
3148 radv_create_shaders(pipeline, device, cache,
3149 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3150 pStages);
3151
3152 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3153 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
3154 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3155 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3156 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3157
3158 if (radv_pipeline_has_gs(pipeline)) {
3159 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3160 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3161 } else {
3162 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3163 }
3164 if (extra && extra->use_rectlist) {
3165 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
3166 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3167 pipeline->graphics.can_use_guardband = true;
3168 }
3169 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3170 /* prim vertex count will need TESS changes */
3171 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
3172
3173 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3174
3175 /* Ensure that some export memory is always allocated, for two reasons:
3176 *
3177 * 1) Correctness: The hardware ignores the EXEC mask if no export
3178 * memory is allocated, so KILL and alpha test do not work correctly
3179 * without this.
3180 * 2) Performance: Every shader needs at least a NULL export, even when
3181 * it writes no color/depth output. The NULL export instruction
3182 * stalls without this setting.
3183 *
3184 * Don't add this to CB_SHADER_MASK.
3185 */
3186 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3187 if (!blend.spi_shader_col_format) {
3188 if (!ps->info.fs.writes_z &&
3189 !ps->info.fs.writes_stencil &&
3190 !ps->info.fs.writes_sample_mask)
3191 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3192 }
3193
3194 calculate_vgt_gs_mode(pipeline);
3195
3196 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3197 if (pipeline->shaders[i]) {
3198 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3199 }
3200 }
3201
3202 if (radv_pipeline_has_gs(pipeline)) {
3203 calculate_gs_ring_sizes(pipeline);
3204 if (device->physical_device->rad_info.chip_class >= GFX9)
3205 calculate_gfx9_gs_info(pCreateInfo, pipeline);
3206 }
3207
3208 struct radv_tessellation_state tess = {0};
3209 if (radv_pipeline_has_tess(pipeline)) {
3210 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
3211 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3212 pipeline->graphics.prim_vertex_count.incr = 1;
3213 }
3214 tess = calculate_tess_state(pipeline, pCreateInfo);
3215 }
3216
3217 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess);
3218
3219 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3220
3221 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3222 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3223
3224 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3225 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3226 if (loc->sgpr_idx != -1) {
3227 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3228 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3229 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3230 pipeline->graphics.vtx_emit_num = 3;
3231 else
3232 pipeline->graphics.vtx_emit_num = 2;
3233 }
3234
3235 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
3236 radv_dump_pipeline_stats(device, pipeline);
3237 }
3238
3239 result = radv_pipeline_scratch_init(device, pipeline);
3240 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess);
3241
3242 return result;
3243 }
3244
3245 VkResult
3246 radv_graphics_pipeline_create(
3247 VkDevice _device,
3248 VkPipelineCache _cache,
3249 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3250 const struct radv_graphics_pipeline_create_info *extra,
3251 const VkAllocationCallbacks *pAllocator,
3252 VkPipeline *pPipeline)
3253 {
3254 RADV_FROM_HANDLE(radv_device, device, _device);
3255 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3256 struct radv_pipeline *pipeline;
3257 VkResult result;
3258
3259 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3260 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3261 if (pipeline == NULL)
3262 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3263
3264 result = radv_pipeline_init(pipeline, device, cache,
3265 pCreateInfo, extra, pAllocator);
3266 if (result != VK_SUCCESS) {
3267 radv_pipeline_destroy(device, pipeline, pAllocator);
3268 return result;
3269 }
3270
3271 *pPipeline = radv_pipeline_to_handle(pipeline);
3272
3273 return VK_SUCCESS;
3274 }
3275
3276 VkResult radv_CreateGraphicsPipelines(
3277 VkDevice _device,
3278 VkPipelineCache pipelineCache,
3279 uint32_t count,
3280 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3281 const VkAllocationCallbacks* pAllocator,
3282 VkPipeline* pPipelines)
3283 {
3284 VkResult result = VK_SUCCESS;
3285 unsigned i = 0;
3286
3287 for (; i < count; i++) {
3288 VkResult r;
3289 r = radv_graphics_pipeline_create(_device,
3290 pipelineCache,
3291 &pCreateInfos[i],
3292 NULL, pAllocator, &pPipelines[i]);
3293 if (r != VK_SUCCESS) {
3294 result = r;
3295 pPipelines[i] = VK_NULL_HANDLE;
3296 }
3297 }
3298
3299 return result;
3300 }
3301
3302
3303 static void
3304 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3305 {
3306 struct radv_shader_variant *compute_shader;
3307 struct radv_device *device = pipeline->device;
3308 unsigned compute_resource_limits;
3309 unsigned waves_per_threadgroup;
3310 uint64_t va;
3311
3312 pipeline->cs.buf = malloc(20 * 4);
3313 pipeline->cs.max_dw = 20;
3314
3315 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3316 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3317
3318 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3319 radeon_emit(&pipeline->cs, va >> 8);
3320 radeon_emit(&pipeline->cs, va >> 40);
3321
3322 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3323 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3324 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3325
3326 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3327 S_00B860_WAVES(pipeline->max_waves) |
3328 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3329
3330 /* Calculate best compute resource limits. */
3331 waves_per_threadgroup =
3332 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3333 compute_shader->info.cs.block_size[1] *
3334 compute_shader->info.cs.block_size[2], 64);
3335 compute_resource_limits =
3336 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3337
3338 if (device->physical_device->rad_info.chip_class >= CIK) {
3339 unsigned num_cu_per_se =
3340 device->physical_device->rad_info.num_good_compute_units /
3341 device->physical_device->rad_info.max_se;
3342
3343 /* Force even distribution on all SIMDs in CU if the workgroup
3344 * size is 64. This has shown some good improvements if # of
3345 * CUs per SE is not a multiple of 4.
3346 */
3347 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3348 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3349 }
3350
3351 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3352 compute_resource_limits);
3353
3354 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3355 radeon_emit(&pipeline->cs,
3356 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3357 radeon_emit(&pipeline->cs,
3358 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3359 radeon_emit(&pipeline->cs,
3360 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3361
3362 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3363 }
3364
3365 static VkResult radv_compute_pipeline_create(
3366 VkDevice _device,
3367 VkPipelineCache _cache,
3368 const VkComputePipelineCreateInfo* pCreateInfo,
3369 const VkAllocationCallbacks* pAllocator,
3370 VkPipeline* pPipeline)
3371 {
3372 RADV_FROM_HANDLE(radv_device, device, _device);
3373 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3374 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3375 struct radv_pipeline *pipeline;
3376 VkResult result;
3377
3378 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3379 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3380 if (pipeline == NULL)
3381 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3382
3383 pipeline->device = device;
3384 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3385 assert(pipeline->layout);
3386
3387 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3388 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3389
3390 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3391 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3392 result = radv_pipeline_scratch_init(device, pipeline);
3393 if (result != VK_SUCCESS) {
3394 radv_pipeline_destroy(device, pipeline, pAllocator);
3395 return result;
3396 }
3397
3398 radv_compute_generate_pm4(pipeline);
3399
3400 *pPipeline = radv_pipeline_to_handle(pipeline);
3401
3402 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
3403 radv_dump_pipeline_stats(device, pipeline);
3404 }
3405 return VK_SUCCESS;
3406 }
3407
3408 VkResult radv_CreateComputePipelines(
3409 VkDevice _device,
3410 VkPipelineCache pipelineCache,
3411 uint32_t count,
3412 const VkComputePipelineCreateInfo* pCreateInfos,
3413 const VkAllocationCallbacks* pAllocator,
3414 VkPipeline* pPipelines)
3415 {
3416 VkResult result = VK_SUCCESS;
3417
3418 unsigned i = 0;
3419 for (; i < count; i++) {
3420 VkResult r;
3421 r = radv_compute_pipeline_create(_device, pipelineCache,
3422 &pCreateInfos[i],
3423 pAllocator, &pPipelines[i]);
3424 if (r != VK_SUCCESS) {
3425 result = r;
3426 pPipelines[i] = VK_NULL_HANDLE;
3427 }
3428 }
3429
3430 return result;
3431 }