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radv: use SPI_SHADER_ZERO for non-written color attachments
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 static const VkPipelineMultisampleStateCreateInfo *
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
94 {
95 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
96 return pCreateInfo->pMultisampleState;
97 return NULL;
98 }
99
100 static const VkPipelineTessellationStateCreateInfo *
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
102 {
103 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
104 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
105 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
106 return pCreateInfo->pTessellationState;
107 }
108 }
109 return NULL;
110 }
111
112 static const VkPipelineDepthStencilStateCreateInfo *
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
114 {
115 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
116 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
117
118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
119 subpass->depth_stencil_attachment)
120 return pCreateInfo->pDepthStencilState;
121 return NULL;
122 }
123
124 static const VkPipelineColorBlendStateCreateInfo *
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
126 {
127 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
128 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
129
130 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
131 subpass->has_color_att)
132 return pCreateInfo->pColorBlendState;
133 return NULL;
134 }
135
136 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
137 {
138 struct radv_shader_variant *variant = NULL;
139 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
140 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
141 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
142 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
143 else if (pipeline->shaders[MESA_SHADER_VERTEX])
144 variant = pipeline->shaders[MESA_SHADER_VERTEX];
145 else
146 return false;
147 return variant->info.is_ngg;
148 }
149
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
151 {
152 assert(radv_pipeline_has_ngg(pipeline));
153
154 struct radv_shader_variant *variant = NULL;
155 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
156 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
157 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
158 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
159 else if (pipeline->shaders[MESA_SHADER_VERTEX])
160 variant = pipeline->shaders[MESA_SHADER_VERTEX];
161 else
162 return false;
163 return variant->info.is_ngg_passthrough;
164 }
165
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
167 {
168 if (!radv_pipeline_has_gs(pipeline))
169 return false;
170
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
173 * enable NGG.
174 */
175 if (radv_pipeline_has_ngg(pipeline))
176 return false;
177
178 assert(pipeline->gs_copy_shader);
179 return true;
180 }
181
182 static void
183 radv_pipeline_destroy(struct radv_device *device,
184 struct radv_pipeline *pipeline,
185 const VkAllocationCallbacks* allocator)
186 {
187 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
188 if (pipeline->shaders[i])
189 radv_shader_variant_destroy(device, pipeline->shaders[i]);
190
191 if (pipeline->gs_copy_shader)
192 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
193
194 if(pipeline->cs.buf)
195 free(pipeline->cs.buf);
196
197 vk_object_base_finish(&pipeline->base);
198 vk_free2(&device->vk.alloc, allocator, pipeline);
199 }
200
201 void radv_DestroyPipeline(
202 VkDevice _device,
203 VkPipeline _pipeline,
204 const VkAllocationCallbacks* pAllocator)
205 {
206 RADV_FROM_HANDLE(radv_device, device, _device);
207 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
208
209 if (!_pipeline)
210 return;
211
212 radv_pipeline_destroy(device, pipeline, pAllocator);
213 }
214
215 static uint32_t get_hash_flags(struct radv_device *device)
216 {
217 uint32_t hash_flags = 0;
218
219 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
220 hash_flags |= RADV_HASH_SHADER_NO_NGG;
221 if (device->physical_device->cs_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
223 if (device->physical_device->ps_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
225 if (device->physical_device->ge_wave_size == 32)
226 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
227 if (device->physical_device->use_llvm)
228 hash_flags |= RADV_HASH_SHADER_LLVM;
229 return hash_flags;
230 }
231
232 static VkResult
233 radv_pipeline_scratch_init(struct radv_device *device,
234 struct radv_pipeline *pipeline)
235 {
236 unsigned scratch_bytes_per_wave = 0;
237 unsigned max_waves = 0;
238 unsigned min_waves = 1;
239
240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
241 if (pipeline->shaders[i] &&
242 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
243 unsigned max_stage_waves = device->scratch_waves;
244
245 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
246 pipeline->shaders[i]->config.scratch_bytes_per_wave);
247
248 max_stage_waves = MIN2(max_stage_waves,
249 4 * device->physical_device->rad_info.num_good_compute_units *
250 (256 / pipeline->shaders[i]->config.num_vgprs));
251 max_waves = MAX2(max_waves, max_stage_waves);
252 }
253 }
254
255 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
256 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
258 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
259 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
260 }
261
262 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
263 pipeline->max_waves = max_waves;
264 return VK_SUCCESS;
265 }
266
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
268 {
269 switch (op) {
270 case VK_LOGIC_OP_CLEAR:
271 return V_028808_ROP3_CLEAR;
272 case VK_LOGIC_OP_AND:
273 return V_028808_ROP3_AND;
274 case VK_LOGIC_OP_AND_REVERSE:
275 return V_028808_ROP3_AND_REVERSE;
276 case VK_LOGIC_OP_COPY:
277 return V_028808_ROP3_COPY;
278 case VK_LOGIC_OP_AND_INVERTED:
279 return V_028808_ROP3_AND_INVERTED;
280 case VK_LOGIC_OP_NO_OP:
281 return V_028808_ROP3_NO_OP;
282 case VK_LOGIC_OP_XOR:
283 return V_028808_ROP3_XOR;
284 case VK_LOGIC_OP_OR:
285 return V_028808_ROP3_OR;
286 case VK_LOGIC_OP_NOR:
287 return V_028808_ROP3_NOR;
288 case VK_LOGIC_OP_EQUIVALENT:
289 return V_028808_ROP3_EQUIVALENT;
290 case VK_LOGIC_OP_INVERT:
291 return V_028808_ROP3_INVERT;
292 case VK_LOGIC_OP_OR_REVERSE:
293 return V_028808_ROP3_OR_REVERSE;
294 case VK_LOGIC_OP_COPY_INVERTED:
295 return V_028808_ROP3_COPY_INVERTED;
296 case VK_LOGIC_OP_OR_INVERTED:
297 return V_028808_ROP3_OR_INVERTED;
298 case VK_LOGIC_OP_NAND:
299 return V_028808_ROP3_NAND;
300 case VK_LOGIC_OP_SET:
301 return V_028808_ROP3_SET;
302 default:
303 unreachable("Unhandled logic op");
304 }
305 }
306
307
308 static uint32_t si_translate_blend_function(VkBlendOp op)
309 {
310 switch (op) {
311 case VK_BLEND_OP_ADD:
312 return V_028780_COMB_DST_PLUS_SRC;
313 case VK_BLEND_OP_SUBTRACT:
314 return V_028780_COMB_SRC_MINUS_DST;
315 case VK_BLEND_OP_REVERSE_SUBTRACT:
316 return V_028780_COMB_DST_MINUS_SRC;
317 case VK_BLEND_OP_MIN:
318 return V_028780_COMB_MIN_DST_SRC;
319 case VK_BLEND_OP_MAX:
320 return V_028780_COMB_MAX_DST_SRC;
321 default:
322 return 0;
323 }
324 }
325
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
327 {
328 switch (factor) {
329 case VK_BLEND_FACTOR_ZERO:
330 return V_028780_BLEND_ZERO;
331 case VK_BLEND_FACTOR_ONE:
332 return V_028780_BLEND_ONE;
333 case VK_BLEND_FACTOR_SRC_COLOR:
334 return V_028780_BLEND_SRC_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
337 case VK_BLEND_FACTOR_DST_COLOR:
338 return V_028780_BLEND_DST_COLOR;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case VK_BLEND_FACTOR_SRC_ALPHA:
342 return V_028780_BLEND_SRC_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
345 case VK_BLEND_FACTOR_DST_ALPHA:
346 return V_028780_BLEND_DST_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR:
350 return V_028780_BLEND_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
354 return V_028780_BLEND_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE;
359 case VK_BLEND_FACTOR_SRC1_COLOR:
360 return V_028780_BLEND_SRC1_COLOR;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
362 return V_028780_BLEND_INV_SRC1_COLOR;
363 case VK_BLEND_FACTOR_SRC1_ALPHA:
364 return V_028780_BLEND_SRC1_ALPHA;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
366 return V_028780_BLEND_INV_SRC1_ALPHA;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
373 {
374 switch (op) {
375 case VK_BLEND_OP_ADD:
376 return V_028760_OPT_COMB_ADD;
377 case VK_BLEND_OP_SUBTRACT:
378 return V_028760_OPT_COMB_SUBTRACT;
379 case VK_BLEND_OP_REVERSE_SUBTRACT:
380 return V_028760_OPT_COMB_REVSUBTRACT;
381 case VK_BLEND_OP_MIN:
382 return V_028760_OPT_COMB_MIN;
383 case VK_BLEND_OP_MAX:
384 return V_028760_OPT_COMB_MAX;
385 default:
386 return V_028760_OPT_COMB_BLEND_DISABLED;
387 }
388 }
389
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
391 {
392 switch (factor) {
393 case VK_BLEND_FACTOR_ZERO:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
395 case VK_BLEND_FACTOR_ONE:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
397 case VK_BLEND_FACTOR_SRC_COLOR:
398 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
403 case VK_BLEND_FACTOR_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
408 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
410 default:
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == VK_BLEND_FACTOR_ZERO) {
425 *src_factor = VK_BLEND_FACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == VK_BLEND_OP_SUBTRACT)
430 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
431 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
432 *func = VK_BLEND_OP_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == VK_BLEND_FACTOR_DST_COLOR ||
439 factor == VK_BLEND_FACTOR_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
442 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
443 }
444
445 static bool is_dual_src(VkBlendFactor factor)
446 {
447 switch (factor) {
448 case VK_BLEND_FACTOR_SRC1_COLOR:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
450 case VK_BLEND_FACTOR_SRC1_ALPHA:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
452 return true;
453 default:
454 return false;
455 }
456 }
457
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
459 bool blend_enable,
460 bool blend_need_alpha)
461 {
462 const struct vk_format_description *desc = vk_format_description(vk_format);
463 struct ac_spi_color_formats formats = {};
464 unsigned format, ntype, swap;
465
466 format = radv_translate_colorformat(vk_format);
467 ntype = radv_translate_color_numformat(vk_format, desc,
468 vk_format_get_first_non_void_channel(vk_format));
469 swap = radv_translate_colorswap(vk_format, false);
470
471 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
472
473 if (blend_enable && blend_need_alpha)
474 return formats.blend_alpha;
475 else if(blend_need_alpha)
476 return formats.alpha;
477 else if(blend_enable)
478 return formats.blend;
479 else
480 return formats.normal;
481 }
482
483 static bool
484 format_is_int8(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487 int channel = vk_format_get_first_non_void_channel(format);
488
489 return channel >= 0 && desc->channel[channel].pure_integer &&
490 desc->channel[channel].size == 8;
491 }
492
493 static bool
494 format_is_int10(VkFormat format)
495 {
496 const struct vk_format_description *desc = vk_format_description(format);
497
498 if (desc->nr_channels != 4)
499 return false;
500 for (unsigned i = 0; i < 4; i++) {
501 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
502 return true;
503 }
504 return false;
505 }
506
507 static void
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 struct radv_blend_state *blend)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
515 unsigned num_targets;
516
517 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
518 unsigned cf;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
521 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
522 cf = V_028714_SPI_SHADER_ZERO;
523 } else {
524 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
525 bool blend_enable =
526 blend->blend_enable_4bit & (0xfu << (i * 4));
527
528 cf = radv_choose_spi_color_format(attachment->format,
529 blend_enable,
530 blend->need_src_alpha & (1 << i));
531
532 if (format_is_int8(attachment->format))
533 is_int8 |= 1 << i;
534 if (format_is_int10(attachment->format))
535 is_int10 |= 1 << i;
536 }
537
538 col_format |= cf << (4 * i);
539 }
540
541 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
545 */
546 col_format |= V_028714_SPI_SHADER_32_AR;
547 }
548
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
551 */
552 num_targets = (util_last_bit(col_format) + 3) / 4;
553 for (unsigned i = 0; i < num_targets; i++) {
554 if (!(col_format & (0xf << (i * 4)))) {
555 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
556 }
557 }
558
559 /* The output for dual source blending should have the same format as
560 * the first output.
561 */
562 if (blend->mrt0_is_dual_src)
563 col_format |= (col_format & 0xf) << 4;
564
565 blend->spi_shader_col_format = col_format;
566 blend->col_format_is_int8 = is_int8;
567 blend->col_format_is_int10 = is_int10;
568 }
569
570 /*
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 */
574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
575 VK_FORMAT_R32_SFLOAT,
576 VK_FORMAT_R32G32_SFLOAT,
577 VK_FORMAT_R8G8B8A8_UNORM,
578 VK_FORMAT_R16G16B16A16_UNORM,
579 VK_FORMAT_R16G16B16A16_SNORM,
580 VK_FORMAT_R16G16B16A16_UINT,
581 VK_FORMAT_R16G16B16A16_SINT,
582 VK_FORMAT_R32G32B32A32_SFLOAT,
583 VK_FORMAT_R8G8B8A8_UINT,
584 VK_FORMAT_R8G8B8A8_SINT,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32,
587 };
588
589 unsigned radv_format_meta_fs_key(VkFormat format)
590 {
591 unsigned col_format = radv_choose_spi_color_format(format, false, false);
592
593 assert(col_format != V_028714_SPI_SHADER_32_AR);
594 if (col_format >= V_028714_SPI_SHADER_32_AR)
595 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596
597 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8 = format_is_int8(format);
599 bool is_int10 = format_is_int10(format);
600
601 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
602 }
603
604 static void
605 radv_blend_check_commutativity(struct radv_blend_state *blend,
606 VkBlendOp op, VkBlendFactor src,
607 VkBlendFactor dst, unsigned chanmask)
608 {
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed =
611 (1u << VK_BLEND_FACTOR_ONE) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ZERO) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
626
627 if (dst == VK_BLEND_FACTOR_ONE &&
628 (src_allowed & (1u << src))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
632 */
633 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
634 blend->commutative_4bit |= chanmask;
635 }
636 }
637
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
640 const VkGraphicsPipelineCreateInfo *pCreateInfo,
641 const struct radv_graphics_pipeline_create_info *extra)
642 {
643 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
644 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
645 struct radv_blend_state blend = {0};
646 unsigned mode = V_028808_CB_NORMAL;
647 int i;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653
654 blend.cb_color_control = 0;
655 if (vkblend) {
656 if (vkblend->logicOpEnable)
657 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
658 else
659 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
660 }
661
662 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
667
668 if (vkms && vkms->alphaToCoverageEnable) {
669 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend.need_src_alpha |= 0x1;
671 }
672
673 blend.cb_target_mask = 0;
674 if (vkblend) {
675 for (i = 0; i < vkblend->attachmentCount; i++) {
676 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
677 unsigned blend_cntl = 0;
678 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
679 VkBlendOp eqRGB = att->colorBlendOp;
680 VkBlendFactor srcRGB = att->srcColorBlendFactor;
681 VkBlendFactor dstRGB = att->dstColorBlendFactor;
682 VkBlendOp eqA = att->alphaBlendOp;
683 VkBlendFactor srcA = att->srcAlphaBlendFactor;
684 VkBlendFactor dstA = att->dstAlphaBlendFactor;
685
686 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
687
688 if (!att->colorWriteMask)
689 continue;
690
691 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
692 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
693 if (!att->blendEnable) {
694 blend.cb_blend_control[i] = blend_cntl;
695 continue;
696 }
697
698 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
699 if (i == 0)
700 blend.mrt0_is_dual_src = true;
701
702 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
703 srcRGB = VK_BLEND_FACTOR_ONE;
704 dstRGB = VK_BLEND_FACTOR_ONE;
705 }
706 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
707 srcA = VK_BLEND_FACTOR_ONE;
708 dstA = VK_BLEND_FACTOR_ONE;
709 }
710
711 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
712 0x7 << (4 * i));
713 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
714 0x8 << (4 * i));
715
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
718 *
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 */
722 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
723 VK_BLEND_FACTOR_DST_COLOR,
724 VK_BLEND_FACTOR_SRC_COLOR);
725
726 si_blend_remove_dst(&eqA, &srcA, &dstA,
727 VK_BLEND_FACTOR_DST_COLOR,
728 VK_BLEND_FACTOR_SRC_COLOR);
729
730 si_blend_remove_dst(&eqA, &srcA, &dstA,
731 VK_BLEND_FACTOR_DST_ALPHA,
732 VK_BLEND_FACTOR_SRC_ALPHA);
733
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
736 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
737 srcA_opt = si_translate_blend_opt_factor(srcA, true);
738 dstA_opt = si_translate_blend_opt_factor(dstA, true);
739
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
743 if (si_blend_factor_uses_dst(srcA))
744 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
745
746 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
747 (dstRGB == VK_BLEND_FACTOR_ZERO ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
749 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
750 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
751
752 /* Set the final value. */
753 blend.sx_mrt_blend_opt[i] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt) |
758 S_028760_ALPHA_DST_OPT(dstA_opt) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
760 blend_cntl |= S_028780_ENABLE(1);
761
762 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
763 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
764 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
768 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
769 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
770 }
771 blend.cb_blend_control[i] = blend_cntl;
772
773 blend.blend_enable_4bit |= 0xfu << (i * 4);
774
775 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
777 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
779 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
781 blend.need_src_alpha |= 1 << i;
782 }
783 for (i = vkblend->attachmentCount; i < 8; i++) {
784 blend.cb_blend_control[i] = 0;
785 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
786 }
787 }
788
789 if (pipeline->device->physical_device->rad_info.has_rbplus) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend.mrt0_is_dual_src) {
792 for (i = 0; i < 8; i++) {
793 blend.sx_mrt_blend_opt[i] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
796 }
797 }
798
799 /* RB+ doesn't work with dual source blending, logic op and
800 * RESOLVE.
801 */
802 if (blend.mrt0_is_dual_src ||
803 (vkblend && vkblend->logicOpEnable) ||
804 mode == V_028808_CB_RESOLVE)
805 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
806 }
807
808 if (blend.cb_target_mask)
809 blend.cb_color_control |= S_028808_MODE(mode);
810 else
811 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
812
813 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
814 return blend;
815 }
816
817 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
818 {
819 switch (op) {
820 case VK_STENCIL_OP_KEEP:
821 return V_02842C_STENCIL_KEEP;
822 case VK_STENCIL_OP_ZERO:
823 return V_02842C_STENCIL_ZERO;
824 case VK_STENCIL_OP_REPLACE:
825 return V_02842C_STENCIL_REPLACE_TEST;
826 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
827 return V_02842C_STENCIL_ADD_CLAMP;
828 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
829 return V_02842C_STENCIL_SUB_CLAMP;
830 case VK_STENCIL_OP_INVERT:
831 return V_02842C_STENCIL_INVERT;
832 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
833 return V_02842C_STENCIL_ADD_WRAP;
834 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
835 return V_02842C_STENCIL_SUB_WRAP;
836 default:
837 return 0;
838 }
839 }
840
841 static uint32_t si_translate_fill(VkPolygonMode func)
842 {
843 switch(func) {
844 case VK_POLYGON_MODE_FILL:
845 return V_028814_X_DRAW_TRIANGLES;
846 case VK_POLYGON_MODE_LINE:
847 return V_028814_X_DRAW_LINES;
848 case VK_POLYGON_MODE_POINT:
849 return V_028814_X_DRAW_POINTS;
850 default:
851 assert(0);
852 return V_028814_X_DRAW_POINTS;
853 }
854 }
855
856 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
857 {
858 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
859 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
860 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
861 uint32_t ps_iter_samples = 1;
862 uint32_t num_samples;
863
864 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
865 *
866 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
867 * subpass uses color attachments, totalSamples is the number of
868 * samples of the color attachments. Otherwise, totalSamples is the
869 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
870 * specified at pipeline creation time."
871 */
872 if (subpass->has_color_att) {
873 num_samples = subpass->color_sample_count;
874 } else {
875 num_samples = vkms->rasterizationSamples;
876 }
877
878 if (vkms->sampleShadingEnable) {
879 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
880 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
881 }
882 return ps_iter_samples;
883 }
884
885 static bool
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return pCreateInfo->depthTestEnable &&
889 pCreateInfo->depthWriteEnable &&
890 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
891 }
892
893 static bool
894 radv_writes_stencil(const VkStencilOpState *state)
895 {
896 return state->writeMask &&
897 (state->failOp != VK_STENCIL_OP_KEEP ||
898 state->passOp != VK_STENCIL_OP_KEEP ||
899 state->depthFailOp != VK_STENCIL_OP_KEEP);
900 }
901
902 static bool
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
904 {
905 return pCreateInfo->stencilTestEnable &&
906 (radv_writes_stencil(&pCreateInfo->front) ||
907 radv_writes_stencil(&pCreateInfo->back));
908 }
909
910 static bool
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
912 {
913 return radv_is_depth_write_enabled(pCreateInfo) ||
914 radv_is_stencil_write_enabled(pCreateInfo);
915 }
916
917 static bool
918 radv_order_invariant_stencil_op(VkStencilOp op)
919 {
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
923 */
924 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
925 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
926 op != VK_STENCIL_OP_REPLACE;
927 }
928
929 static bool
930 radv_order_invariant_stencil_state(const VkStencilOpState *state)
931 {
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
935 * of fragments.
936 */
937 return !state->writeMask ||
938 /* The following assumes that Z writes are disabled. */
939 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
940 radv_order_invariant_stencil_op(state->passOp) &&
941 radv_order_invariant_stencil_op(state->depthFailOp)) ||
942 (state->compareOp == VK_COMPARE_OP_NEVER &&
943 radv_order_invariant_stencil_op(state->failOp));
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
954 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
955 unsigned colormask = blend->cb_target_enabled_4bit;
956
957 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
958 return false;
959
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask && vkblend && vkblend->logicOpEnable)
962 return false;
963
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant = {
966 .zs = true, .pass_set = true
967 };
968
969 if (vkds) {
970 struct radv_render_pass_attachment *attachment =
971 pass->attachments + subpass->depth_stencil_attachment->attachment;
972 bool has_stencil = vk_format_is_stencil(attachment->format);
973 struct radv_dsa_order_invariance order_invariance[2];
974 struct radv_shader_variant *ps =
975 pipeline->shaders[MESA_SHADER_FRAGMENT];
976
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
979 */
980 bool zfunc_is_ordered =
981 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
986
987 bool nozwrite_and_order_invariant_stencil =
988 !radv_is_ds_write_enabled(vkds) ||
989 (!radv_is_depth_write_enabled(vkds) &&
990 radv_order_invariant_stencil_state(&vkds->front) &&
991 radv_order_invariant_stencil_state(&vkds->back));
992
993 order_invariance[1].zs =
994 nozwrite_and_order_invariant_stencil ||
995 (!radv_is_stencil_write_enabled(vkds) &&
996 zfunc_is_ordered);
997 order_invariance[0].zs =
998 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
999
1000 order_invariance[1].pass_set =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1004 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1005 order_invariance[0].pass_set =
1006 !radv_is_depth_write_enabled(vkds) ||
1007 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1008 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1009
1010 dsa_order_invariant = order_invariance[has_stencil];
1011 if (!dsa_order_invariant.zs)
1012 return false;
1013
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1016 */
1017 if (ps &&
1018 ps->info.ps.writes_memory &&
1019 ps->info.ps.early_fragment_test &&
1020 !dsa_order_invariant.pass_set)
1021 return false;
1022
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1025 */
1026 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1027 !dsa_order_invariant.pass_set;
1028 }
1029
1030 /* No color buffers are enabled for writing. */
1031 if (!colormask)
1032 return true;
1033
1034 unsigned blendmask = colormask & blend->blend_enable_4bit;
1035
1036 if (blendmask) {
1037 /* Only commutative blending. */
1038 if (blendmask & ~blend->commutative_4bit)
1039 return false;
1040
1041 if (!dsa_order_invariant.pass_set)
1042 return false;
1043 }
1044
1045 if (colormask & ~blendmask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 static void
1052 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1053 struct radv_blend_state *blend,
1054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1055 {
1056 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1057 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1058 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1059 bool out_of_order_rast = false;
1060 int ps_iter_samples = 1;
1061 uint32_t mask = 0xffff;
1062
1063 if (vkms) {
1064 ms->num_samples = vkms->rasterizationSamples;
1065
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1067 *
1068 * "Sample shading is enabled for a graphics pipeline:
1069 *
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1079 *
1080 * Otherwise, sample shading is considered disabled."
1081 */
1082 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1083 ps_iter_samples = ms->num_samples;
1084 } else {
1085 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1086 }
1087 } else {
1088 ms->num_samples = 1;
1089 }
1090
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1092 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1093 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1095 * application.
1096 */
1097 out_of_order_rast = true;
1098 } else {
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1101 */
1102 out_of_order_rast =
1103 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1104 }
1105
1106 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1107 ms->pa_sc_aa_config = 0;
1108 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1109 S_028804_INCOHERENT_EQAA_READS(1) |
1110 S_028804_INTERPOLATE_COMP_Z(1) |
1111 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1112 ms->pa_sc_mode_cntl_1 =
1113 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1114 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1115 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1116 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1117 /* always 1: */
1118 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1119 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1121 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1123 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1124 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1125 S_028A48_VPORT_SCISSOR_ENABLE(1);
1126
1127 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1128 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1129 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1130 if (rast_line) {
1131 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1132 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1133 /* From the Vulkan spec 1.1.129:
1134 *
1135 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1136 * are being rasterized, sample locations may all be
1137 * treated as being at the pixel center (this may
1138 * affect attribute and depth interpolation)."
1139 */
1140 ms->num_samples = 1;
1141 }
1142 }
1143
1144 if (ms->num_samples > 1) {
1145 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1146 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1147 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1148 unsigned log_samples = util_logbase2(ms->num_samples);
1149 unsigned log_z_samples = util_logbase2(z_samples);
1150 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1152 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1153 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1154 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1155 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1156 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1157 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1158 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1159 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1160 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1161 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1162 if (ps_iter_samples > 1)
1163 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1164 }
1165
1166 if (vkms && vkms->pSampleMask) {
1167 mask = vkms->pSampleMask[0] & 0xffff;
1168 }
1169
1170 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1171 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1172 }
1173
1174 static bool
1175 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1176 {
1177 switch (topology) {
1178 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1182 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1183 return false;
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1189 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1190 return true;
1191 default:
1192 unreachable("unhandled primitive type");
1193 }
1194 }
1195
1196 static uint32_t
1197 si_translate_prim(enum VkPrimitiveTopology topology)
1198 {
1199 switch (topology) {
1200 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1201 return V_008958_DI_PT_POINTLIST;
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1203 return V_008958_DI_PT_LINELIST;
1204 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1205 return V_008958_DI_PT_LINESTRIP;
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1207 return V_008958_DI_PT_TRILIST;
1208 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1209 return V_008958_DI_PT_TRISTRIP;
1210 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1211 return V_008958_DI_PT_TRIFAN;
1212 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1213 return V_008958_DI_PT_LINELIST_ADJ;
1214 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1215 return V_008958_DI_PT_LINESTRIP_ADJ;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1217 return V_008958_DI_PT_TRILIST_ADJ;
1218 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1219 return V_008958_DI_PT_TRISTRIP_ADJ;
1220 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1221 return V_008958_DI_PT_PATCH;
1222 default:
1223 assert(0);
1224 return 0;
1225 }
1226 }
1227
1228 static uint32_t
1229 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1230 {
1231 switch (gl_prim) {
1232 case 0: /* GL_POINTS */
1233 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1234 case 1: /* GL_LINES */
1235 case 3: /* GL_LINE_STRIP */
1236 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1237 case 0x8E7A: /* GL_ISOLINES */
1238 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1239
1240 case 4: /* GL_TRIANGLES */
1241 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1242 case 5: /* GL_TRIANGLE_STRIP */
1243 case 7: /* GL_QUADS */
1244 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1245 default:
1246 assert(0);
1247 return 0;
1248 }
1249 }
1250
1251 static uint32_t
1252 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1253 {
1254 switch (topology) {
1255 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1256 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1257 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1258 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1259 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1260 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1261 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1262 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1263 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1264 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1266 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1267 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1268 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1269 default:
1270 assert(0);
1271 return 0;
1272 }
1273 }
1274
1275 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1276 {
1277 switch(state) {
1278 case VK_DYNAMIC_STATE_VIEWPORT:
1279 return RADV_DYNAMIC_VIEWPORT;
1280 case VK_DYNAMIC_STATE_SCISSOR:
1281 return RADV_DYNAMIC_SCISSOR;
1282 case VK_DYNAMIC_STATE_LINE_WIDTH:
1283 return RADV_DYNAMIC_LINE_WIDTH;
1284 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1285 return RADV_DYNAMIC_DEPTH_BIAS;
1286 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1287 return RADV_DYNAMIC_BLEND_CONSTANTS;
1288 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1289 return RADV_DYNAMIC_DEPTH_BOUNDS;
1290 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1291 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1292 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1293 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1294 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1295 return RADV_DYNAMIC_STENCIL_REFERENCE;
1296 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1297 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1298 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1299 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1300 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1301 return RADV_DYNAMIC_LINE_STIPPLE;
1302 default:
1303 unreachable("Unhandled dynamic state");
1304 }
1305 }
1306
1307 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1308 {
1309 uint32_t states = RADV_DYNAMIC_ALL;
1310
1311 /* If rasterization is disabled we do not care about any of the dynamic states,
1312 * since they are all rasterization related only. */
1313 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1314 return 0;
1315
1316 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1317 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1318
1319 if (!pCreateInfo->pDepthStencilState ||
1320 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1321 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1322
1323 if (!pCreateInfo->pDepthStencilState ||
1324 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1325 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1326 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1327 RADV_DYNAMIC_STENCIL_REFERENCE);
1328
1329 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1330 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1331
1332 if (!pCreateInfo->pMultisampleState ||
1333 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1334 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1335 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1336
1337 if (!pCreateInfo->pRasterizationState ||
1338 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1339 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1340 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1341
1342 /* TODO: blend constants & line width. */
1343
1344 return states;
1345 }
1346
1347
1348 static void
1349 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1350 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1351 {
1352 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1353 uint32_t states = needed_states;
1354 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1355 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1356
1357 pipeline->dynamic_state = default_dynamic_state;
1358 pipeline->graphics.needed_dynamic_state = needed_states;
1359
1360 if (pCreateInfo->pDynamicState) {
1361 /* Remove all of the states that are marked as dynamic */
1362 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1363 for (uint32_t s = 0; s < count; s++)
1364 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1365 }
1366
1367 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1368
1369 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1370 assert(pCreateInfo->pViewportState);
1371
1372 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1373 if (states & RADV_DYNAMIC_VIEWPORT) {
1374 typed_memcpy(dynamic->viewport.viewports,
1375 pCreateInfo->pViewportState->pViewports,
1376 pCreateInfo->pViewportState->viewportCount);
1377 }
1378 }
1379
1380 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1381 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1382 if (states & RADV_DYNAMIC_SCISSOR) {
1383 typed_memcpy(dynamic->scissor.scissors,
1384 pCreateInfo->pViewportState->pScissors,
1385 pCreateInfo->pViewportState->scissorCount);
1386 }
1387 }
1388
1389 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1390 assert(pCreateInfo->pRasterizationState);
1391 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1392 }
1393
1394 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1395 assert(pCreateInfo->pRasterizationState);
1396 dynamic->depth_bias.bias =
1397 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1398 dynamic->depth_bias.clamp =
1399 pCreateInfo->pRasterizationState->depthBiasClamp;
1400 dynamic->depth_bias.slope =
1401 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1402 }
1403
1404 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1405 *
1406 * pColorBlendState is [...] NULL if the pipeline has rasterization
1407 * disabled or if the subpass of the render pass the pipeline is
1408 * created against does not use any color attachments.
1409 */
1410 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1411 assert(pCreateInfo->pColorBlendState);
1412 typed_memcpy(dynamic->blend_constants,
1413 pCreateInfo->pColorBlendState->blendConstants, 4);
1414 }
1415
1416 /* If there is no depthstencil attachment, then don't read
1417 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1418 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1419 * no need to override the depthstencil defaults in
1420 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1421 *
1422 * Section 9.2 of the Vulkan 1.0.15 spec says:
1423 *
1424 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1425 * disabled or if the subpass of the render pass the pipeline is created
1426 * against does not use a depth/stencil attachment.
1427 */
1428 if (needed_states && subpass->depth_stencil_attachment) {
1429 assert(pCreateInfo->pDepthStencilState);
1430
1431 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1432 dynamic->depth_bounds.min =
1433 pCreateInfo->pDepthStencilState->minDepthBounds;
1434 dynamic->depth_bounds.max =
1435 pCreateInfo->pDepthStencilState->maxDepthBounds;
1436 }
1437
1438 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1439 dynamic->stencil_compare_mask.front =
1440 pCreateInfo->pDepthStencilState->front.compareMask;
1441 dynamic->stencil_compare_mask.back =
1442 pCreateInfo->pDepthStencilState->back.compareMask;
1443 }
1444
1445 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1446 dynamic->stencil_write_mask.front =
1447 pCreateInfo->pDepthStencilState->front.writeMask;
1448 dynamic->stencil_write_mask.back =
1449 pCreateInfo->pDepthStencilState->back.writeMask;
1450 }
1451
1452 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1453 dynamic->stencil_reference.front =
1454 pCreateInfo->pDepthStencilState->front.reference;
1455 dynamic->stencil_reference.back =
1456 pCreateInfo->pDepthStencilState->back.reference;
1457 }
1458 }
1459
1460 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1461 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1462 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1463 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1464 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1465 typed_memcpy(dynamic->discard_rectangle.rectangles,
1466 discard_rectangle_info->pDiscardRectangles,
1467 discard_rectangle_info->discardRectangleCount);
1468 }
1469 }
1470
1471 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1472 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1473 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1474 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1475 /* If sampleLocationsEnable is VK_FALSE, the default sample
1476 * locations are used and the values specified in
1477 * sampleLocationsInfo are ignored.
1478 */
1479 if (sample_location_info->sampleLocationsEnable) {
1480 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1481 &sample_location_info->sampleLocationsInfo;
1482
1483 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1484
1485 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1486 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1487 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1488 typed_memcpy(&dynamic->sample_location.locations[0],
1489 pSampleLocationsInfo->pSampleLocations,
1490 pSampleLocationsInfo->sampleLocationsCount);
1491 }
1492 }
1493
1494 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1495 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1496 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1497 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1498 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1499 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1500 }
1501
1502 pipeline->dynamic_state.mask = states;
1503 }
1504
1505 static void
1506 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1507 const struct radv_pipeline *pipeline,
1508 nir_shader **nir,
1509 struct radv_shader_info *infos,
1510 struct gfx9_gs_info *out)
1511 {
1512 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1513 struct radv_es_output_info *es_info;
1514 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1515 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1516 else
1517 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1518 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1519 &infos[MESA_SHADER_VERTEX].vs.es_info;
1520
1521 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1522 bool uses_adjacency;
1523 switch(key->topology) {
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1525 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1527 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1528 uses_adjacency = true;
1529 break;
1530 default:
1531 uses_adjacency = false;
1532 break;
1533 }
1534
1535 /* All these are in dwords: */
1536 /* We can't allow using the whole LDS, because GS waves compete with
1537 * other shader stages for LDS space. */
1538 const unsigned max_lds_size = 8 * 1024;
1539 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1540 unsigned esgs_lds_size;
1541
1542 /* All these are per subgroup: */
1543 const unsigned max_out_prims = 32 * 1024;
1544 const unsigned max_es_verts = 255;
1545 const unsigned ideal_gs_prims = 64;
1546 unsigned max_gs_prims, gs_prims;
1547 unsigned min_es_verts, es_verts, worst_case_es_verts;
1548
1549 if (uses_adjacency || gs_num_invocations > 1)
1550 max_gs_prims = 127 / gs_num_invocations;
1551 else
1552 max_gs_prims = 255;
1553
1554 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1555 * Make sure we don't go over the maximum value.
1556 */
1557 if (gs_info->gs.vertices_out > 0) {
1558 max_gs_prims = MIN2(max_gs_prims,
1559 max_out_prims /
1560 (gs_info->gs.vertices_out * gs_num_invocations));
1561 }
1562 assert(max_gs_prims > 0);
1563
1564 /* If the primitive has adjacency, halve the number of vertices
1565 * that will be reused in multiple primitives.
1566 */
1567 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1568
1569 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1570 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1571
1572 /* Compute ESGS LDS size based on the worst case number of ES vertices
1573 * needed to create the target number of GS prims per subgroup.
1574 */
1575 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1576
1577 /* If total LDS usage is too big, refactor partitions based on ratio
1578 * of ESGS item sizes.
1579 */
1580 if (esgs_lds_size > max_lds_size) {
1581 /* Our target GS Prims Per Subgroup was too large. Calculate
1582 * the maximum number of GS Prims Per Subgroup that will fit
1583 * into LDS, capped by the maximum that the hardware can support.
1584 */
1585 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1586 max_gs_prims);
1587 assert(gs_prims > 0);
1588 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1589 max_es_verts);
1590
1591 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1592 assert(esgs_lds_size <= max_lds_size);
1593 }
1594
1595 /* Now calculate remaining ESGS information. */
1596 if (esgs_lds_size)
1597 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1598 else
1599 es_verts = max_es_verts;
1600
1601 /* Vertices for adjacency primitives are not always reused, so restore
1602 * it for ES_VERTS_PER_SUBGRP.
1603 */
1604 min_es_verts = gs_info->gs.vertices_in;
1605
1606 /* For normal primitives, the VGT only checks if they are past the ES
1607 * verts per subgroup after allocating a full GS primitive and if they
1608 * are, kick off a new subgroup. But if those additional ES verts are
1609 * unique (e.g. not reused) we need to make sure there is enough LDS
1610 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1611 */
1612 es_verts -= min_es_verts - 1;
1613
1614 uint32_t es_verts_per_subgroup = es_verts;
1615 uint32_t gs_prims_per_subgroup = gs_prims;
1616 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1617 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1618 out->lds_size = align(esgs_lds_size, 128) / 128;
1619 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1620 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1621 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1622 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1623 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1624 assert(max_prims_per_subgroup <= max_out_prims);
1625 }
1626
1627 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1628 unsigned min_verts_per_prim, bool use_adjacency)
1629 {
1630 unsigned max_reuse = max_esverts - min_verts_per_prim;
1631 if (use_adjacency)
1632 max_reuse /= 2;
1633 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1634 }
1635
1636 static unsigned
1637 radv_get_num_input_vertices(nir_shader **nir)
1638 {
1639 if (nir[MESA_SHADER_GEOMETRY]) {
1640 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1641
1642 return gs->info.gs.vertices_in;
1643 }
1644
1645 if (nir[MESA_SHADER_TESS_CTRL]) {
1646 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1647
1648 if (tes->info.tess.point_mode)
1649 return 1;
1650 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1651 return 2;
1652 return 3;
1653 }
1654
1655 return 3;
1656 }
1657
1658 static void
1659 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1660 struct radv_pipeline *pipeline,
1661 nir_shader **nir,
1662 struct radv_shader_info *infos,
1663 struct gfx10_ngg_info *ngg)
1664 {
1665 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1666 struct radv_es_output_info *es_info =
1667 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1668 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1669 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1670 unsigned min_verts_per_prim =
1671 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1672 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1673 bool uses_adjacency;
1674 switch(key->topology) {
1675 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1676 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1677 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1678 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1679 uses_adjacency = true;
1680 break;
1681 default:
1682 uses_adjacency = false;
1683 break;
1684 }
1685
1686 /* All these are in dwords: */
1687 /* We can't allow using the whole LDS, because GS waves compete with
1688 * other shader stages for LDS space.
1689 *
1690 * TODO: We should really take the shader's internal LDS use into
1691 * account. The linker will fail if the size is greater than
1692 * 8K dwords.
1693 */
1694 const unsigned max_lds_size = 8 * 1024 - 768;
1695 const unsigned target_lds_size = max_lds_size;
1696 unsigned esvert_lds_size = 0;
1697 unsigned gsprim_lds_size = 0;
1698
1699 /* All these are per subgroup: */
1700 bool max_vert_out_per_gs_instance = false;
1701 unsigned max_esverts_base = 256;
1702 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1703
1704 /* Hardware has the following non-natural restrictions on the value
1705 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1706 * the draw:
1707 * - at most 252 for any line input primitive type
1708 * - at most 251 for any quad input primitive type
1709 * - at most 251 for triangle strips with adjacency (this happens to
1710 * be the natural limit for triangle *lists* with adjacency)
1711 */
1712 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1713
1714 if (gs_type == MESA_SHADER_GEOMETRY) {
1715 unsigned max_out_verts_per_gsprim =
1716 gs_info->gs.vertices_out * gs_num_invocations;
1717
1718 if (max_out_verts_per_gsprim <= 256) {
1719 if (max_out_verts_per_gsprim) {
1720 max_gsprims_base = MIN2(max_gsprims_base,
1721 256 / max_out_verts_per_gsprim);
1722 }
1723 } else {
1724 /* Use special multi-cycling mode in which each GS
1725 * instance gets its own subgroup. Does not work with
1726 * tessellation. */
1727 max_vert_out_per_gs_instance = true;
1728 max_gsprims_base = 1;
1729 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1730 }
1731
1732 esvert_lds_size = es_info->esgs_itemsize / 4;
1733 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1734 } else {
1735 /* VS and TES. */
1736 /* LDS size for passing data from GS to ES. */
1737 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1738 ? &infos[MESA_SHADER_TESS_EVAL].so
1739 : &infos[MESA_SHADER_VERTEX].so;
1740
1741 if (so_info->num_outputs)
1742 esvert_lds_size = 4 * so_info->num_outputs + 1;
1743
1744 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1745 * corresponding to the ES thread of the provoking vertex. All
1746 * ES threads load and export PrimitiveID for their thread.
1747 */
1748 if (!nir[MESA_SHADER_TESS_CTRL] &&
1749 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1750 esvert_lds_size = MAX2(esvert_lds_size, 1);
1751 }
1752
1753 unsigned max_gsprims = max_gsprims_base;
1754 unsigned max_esverts = max_esverts_base;
1755
1756 if (esvert_lds_size)
1757 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1758 if (gsprim_lds_size)
1759 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1760
1761 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1762 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1763 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1764
1765 if (esvert_lds_size || gsprim_lds_size) {
1766 /* Now that we have a rough proportionality between esverts
1767 * and gsprims based on the primitive type, scale both of them
1768 * down simultaneously based on required LDS space.
1769 *
1770 * We could be smarter about this if we knew how much vertex
1771 * reuse to expect.
1772 */
1773 unsigned lds_total = max_esverts * esvert_lds_size +
1774 max_gsprims * gsprim_lds_size;
1775 if (lds_total > target_lds_size) {
1776 max_esverts = max_esverts * target_lds_size / lds_total;
1777 max_gsprims = max_gsprims * target_lds_size / lds_total;
1778
1779 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1780 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1781 min_verts_per_prim, uses_adjacency);
1782 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1783 }
1784 }
1785
1786 /* Round up towards full wave sizes for better ALU utilization. */
1787 if (!max_vert_out_per_gs_instance) {
1788 unsigned orig_max_esverts;
1789 unsigned orig_max_gsprims;
1790 unsigned wavesize;
1791
1792 if (gs_type == MESA_SHADER_GEOMETRY) {
1793 wavesize = gs_info->wave_size;
1794 } else {
1795 wavesize = nir[MESA_SHADER_TESS_CTRL]
1796 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1797 : infos[MESA_SHADER_VERTEX].wave_size;
1798 }
1799
1800 do {
1801 orig_max_esverts = max_esverts;
1802 orig_max_gsprims = max_gsprims;
1803
1804 max_esverts = align(max_esverts, wavesize);
1805 max_esverts = MIN2(max_esverts, max_esverts_base);
1806 if (esvert_lds_size)
1807 max_esverts = MIN2(max_esverts,
1808 (max_lds_size - max_gsprims * gsprim_lds_size) /
1809 esvert_lds_size);
1810 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1811
1812 max_gsprims = align(max_gsprims, wavesize);
1813 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1814 if (gsprim_lds_size)
1815 max_gsprims = MIN2(max_gsprims,
1816 (max_lds_size - max_esverts * esvert_lds_size) /
1817 gsprim_lds_size);
1818 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1819 min_verts_per_prim, uses_adjacency);
1820 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1821 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1822 }
1823
1824 /* Hardware restriction: minimum value of max_esverts */
1825 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1826
1827 unsigned max_out_vertices =
1828 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1829 gs_type == MESA_SHADER_GEOMETRY ?
1830 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1831 max_esverts;
1832 assert(max_out_vertices <= 256);
1833
1834 unsigned prim_amp_factor = 1;
1835 if (gs_type == MESA_SHADER_GEOMETRY) {
1836 /* Number of output primitives per GS input primitive after
1837 * GS instancing. */
1838 prim_amp_factor = gs_info->gs.vertices_out;
1839 }
1840
1841 /* The GE only checks against the maximum number of ES verts after
1842 * allocating a full GS primitive. So we need to ensure that whenever
1843 * this check passes, there is enough space for a full primitive without
1844 * vertex reuse.
1845 */
1846 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1847 ngg->max_gsprims = max_gsprims;
1848 ngg->max_out_verts = max_out_vertices;
1849 ngg->prim_amp_factor = prim_amp_factor;
1850 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1851 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1852 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1853
1854 if (gs_type == MESA_SHADER_GEOMETRY) {
1855 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1856 } else {
1857 ngg->vgt_esgs_ring_itemsize = 1;
1858 }
1859
1860 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1861
1862 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1863 }
1864
1865 static void
1866 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1867 const struct gfx9_gs_info *gs)
1868 {
1869 struct radv_device *device = pipeline->device;
1870 unsigned num_se = device->physical_device->rad_info.max_se;
1871 unsigned wave_size = 64;
1872 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1873 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1874 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1875 */
1876 unsigned gs_vertex_reuse =
1877 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1878 unsigned alignment = 256 * num_se;
1879 /* The maximum size is 63.999 MB per SE. */
1880 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1881 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1882
1883 /* Calculate the minimum size. */
1884 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1885 wave_size, alignment);
1886 /* These are recommended sizes, not minimum sizes. */
1887 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1888 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1889 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1890 gs_info->gs.max_gsvs_emit_size;
1891
1892 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1893 esgs_ring_size = align(esgs_ring_size, alignment);
1894 gsvs_ring_size = align(gsvs_ring_size, alignment);
1895
1896 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1897 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1898
1899 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1900 }
1901
1902 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1903 unsigned *lds_size)
1904 {
1905 /* If tessellation is all offchip and on-chip GS isn't used, this
1906 * workaround is not needed.
1907 */
1908 return;
1909
1910 /* SPI barrier management bug:
1911 * Make sure we have at least 4k of LDS in use to avoid the bug.
1912 * It applies to workgroup sizes of more than one wavefront.
1913 */
1914 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1915 device->physical_device->rad_info.family == CHIP_KABINI)
1916 *lds_size = MAX2(*lds_size, 8);
1917 }
1918
1919 struct radv_shader_variant *
1920 radv_get_shader(struct radv_pipeline *pipeline,
1921 gl_shader_stage stage)
1922 {
1923 if (stage == MESA_SHADER_VERTEX) {
1924 if (pipeline->shaders[MESA_SHADER_VERTEX])
1925 return pipeline->shaders[MESA_SHADER_VERTEX];
1926 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1927 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1928 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1929 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1930 } else if (stage == MESA_SHADER_TESS_EVAL) {
1931 if (!radv_pipeline_has_tess(pipeline))
1932 return NULL;
1933 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1934 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1935 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1936 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1937 }
1938 return pipeline->shaders[stage];
1939 }
1940
1941 static struct radv_tessellation_state
1942 calculate_tess_state(struct radv_pipeline *pipeline,
1943 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1944 {
1945 unsigned num_tcs_input_cp;
1946 unsigned num_tcs_output_cp;
1947 unsigned lds_size;
1948 unsigned num_patches;
1949 struct radv_tessellation_state tess = {0};
1950
1951 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1952 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1953 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1954
1955 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1956
1957 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1958 assert(lds_size <= 65536);
1959 lds_size = align(lds_size, 512) / 512;
1960 } else {
1961 assert(lds_size <= 32768);
1962 lds_size = align(lds_size, 256) / 256;
1963 }
1964 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1965
1966 tess.lds_size = lds_size;
1967
1968 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1969 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1970 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1971 tess.num_patches = num_patches;
1972
1973 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1974 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1975
1976 switch (tes->info.tes.primitive_mode) {
1977 case GL_TRIANGLES:
1978 type = V_028B6C_TESS_TRIANGLE;
1979 break;
1980 case GL_QUADS:
1981 type = V_028B6C_TESS_QUAD;
1982 break;
1983 case GL_ISOLINES:
1984 type = V_028B6C_TESS_ISOLINE;
1985 break;
1986 }
1987
1988 switch (tes->info.tes.spacing) {
1989 case TESS_SPACING_EQUAL:
1990 partitioning = V_028B6C_PART_INTEGER;
1991 break;
1992 case TESS_SPACING_FRACTIONAL_ODD:
1993 partitioning = V_028B6C_PART_FRAC_ODD;
1994 break;
1995 case TESS_SPACING_FRACTIONAL_EVEN:
1996 partitioning = V_028B6C_PART_FRAC_EVEN;
1997 break;
1998 default:
1999 break;
2000 }
2001
2002 bool ccw = tes->info.tes.ccw;
2003 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2004 vk_find_struct_const(pCreateInfo->pTessellationState,
2005 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2006
2007 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2008 ccw = !ccw;
2009
2010 if (tes->info.tes.point_mode)
2011 topology = V_028B6C_OUTPUT_POINT;
2012 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2013 topology = V_028B6C_OUTPUT_LINE;
2014 else if (ccw)
2015 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2016 else
2017 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2018
2019 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2020 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2021 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2022 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2023 else
2024 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2025 } else
2026 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2027
2028 tess.tf_param = S_028B6C_TYPE(type) |
2029 S_028B6C_PARTITIONING(partitioning) |
2030 S_028B6C_TOPOLOGY(topology) |
2031 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2032
2033 return tess;
2034 }
2035
2036 static const struct radv_prim_vertex_count prim_size_table[] = {
2037 [V_008958_DI_PT_NONE] = {0, 0},
2038 [V_008958_DI_PT_POINTLIST] = {1, 1},
2039 [V_008958_DI_PT_LINELIST] = {2, 2},
2040 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2041 [V_008958_DI_PT_TRILIST] = {3, 3},
2042 [V_008958_DI_PT_TRIFAN] = {3, 1},
2043 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2044 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2045 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2046 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2047 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2048 [V_008958_DI_PT_RECTLIST] = {3, 3},
2049 [V_008958_DI_PT_LINELOOP] = {2, 1},
2050 [V_008958_DI_PT_POLYGON] = {3, 1},
2051 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2052 };
2053
2054 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2055 {
2056 if (radv_pipeline_has_gs(pipeline))
2057 if (radv_pipeline_has_ngg(pipeline))
2058 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2059 else
2060 return &pipeline->gs_copy_shader->info.vs.outinfo;
2061 else if (radv_pipeline_has_tess(pipeline))
2062 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2063 else
2064 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2065 }
2066
2067 static void
2068 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2069 {
2070 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2071 int shader_count = 0;
2072
2073 if(shaders[MESA_SHADER_FRAGMENT]) {
2074 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2075 }
2076 if(shaders[MESA_SHADER_GEOMETRY]) {
2077 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2078 }
2079 if(shaders[MESA_SHADER_TESS_EVAL]) {
2080 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2081 }
2082 if(shaders[MESA_SHADER_TESS_CTRL]) {
2083 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2084 }
2085 if(shaders[MESA_SHADER_VERTEX]) {
2086 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2087 }
2088
2089 if (shader_count > 1) {
2090 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2091 unsigned last = ordered_shaders[0]->info.stage;
2092
2093 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2094 ordered_shaders[1]->info.has_transform_feedback_varyings)
2095 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2096
2097 for (int i = 0; i < shader_count; ++i) {
2098 nir_variable_mode mask = 0;
2099
2100 if (ordered_shaders[i]->info.stage != first)
2101 mask = mask | nir_var_shader_in;
2102
2103 if (ordered_shaders[i]->info.stage != last)
2104 mask = mask | nir_var_shader_out;
2105
2106 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2107 radv_optimize_nir(ordered_shaders[i], false, false);
2108 }
2109 }
2110
2111 for (int i = 1; i < shader_count; ++i) {
2112 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2113 ordered_shaders[i - 1]);
2114
2115 if (nir_link_opt_varyings(ordered_shaders[i],
2116 ordered_shaders[i - 1]))
2117 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2118
2119 nir_remove_dead_variables(ordered_shaders[i],
2120 nir_var_shader_out, NULL);
2121 nir_remove_dead_variables(ordered_shaders[i - 1],
2122 nir_var_shader_in, NULL);
2123
2124 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2125 ordered_shaders[i - 1]);
2126
2127 nir_compact_varyings(ordered_shaders[i],
2128 ordered_shaders[i - 1], true);
2129
2130 if (progress) {
2131 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2132 ac_lower_indirect_derefs(ordered_shaders[i],
2133 pipeline->device->physical_device->rad_info.chip_class);
2134 }
2135 radv_optimize_nir(ordered_shaders[i], false, false);
2136
2137 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2138 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2139 pipeline->device->physical_device->rad_info.chip_class);
2140 }
2141 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2142 }
2143 }
2144 }
2145
2146 static void
2147 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2148 struct radv_shader_info infos[MESA_SHADER_STAGES])
2149 {
2150 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2151 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2152
2153 if (!has_tess && !has_gs)
2154 return;
2155
2156 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2157 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2158
2159 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2160 /* These are merged into the next stage */
2161 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2162 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2163 }
2164
2165 if (has_tess) {
2166 nir_linked_io_var_info vs2tcs =
2167 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2168 nir_linked_io_var_info tcs2tes =
2169 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2170
2171 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2172 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2173 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2174 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2175 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2176 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2177
2178 if (has_gs) {
2179 nir_linked_io_var_info tes2gs =
2180 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2181
2182 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2183 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2184 }
2185 } else if (has_gs) {
2186 nir_linked_io_var_info vs2gs =
2187 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2188
2189 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2190 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2191 }
2192 }
2193
2194 static uint32_t
2195 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2196 uint32_t attrib_binding)
2197 {
2198 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2199 const VkVertexInputBindingDescription *input_binding =
2200 &input_state->pVertexBindingDescriptions[i];
2201
2202 if (input_binding->binding == attrib_binding)
2203 return input_binding->stride;
2204 }
2205
2206 return 0;
2207 }
2208
2209 static struct radv_pipeline_key
2210 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2211 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2212 const struct radv_blend_state *blend,
2213 bool has_view_index)
2214 {
2215 const VkPipelineVertexInputStateCreateInfo *input_state =
2216 pCreateInfo->pVertexInputState;
2217 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2218 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2219
2220 struct radv_pipeline_key key;
2221 memset(&key, 0, sizeof(key));
2222
2223 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2224 key.optimisations_disabled = 1;
2225
2226 key.has_multiview_view_index = has_view_index;
2227
2228 uint32_t binding_input_rate = 0;
2229 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2230 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2231 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2232 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2233 binding_input_rate |= 1u << binding;
2234 instance_rate_divisors[binding] = 1;
2235 }
2236 }
2237 if (divisor_state) {
2238 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2239 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2240 divisor_state->pVertexBindingDivisors[i].divisor;
2241 }
2242 }
2243
2244 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2245 const VkVertexInputAttributeDescription *desc =
2246 &input_state->pVertexAttributeDescriptions[i];
2247 const struct vk_format_description *format_desc;
2248 unsigned location = desc->location;
2249 unsigned binding = desc->binding;
2250 unsigned num_format, data_format;
2251 int first_non_void;
2252
2253 if (binding_input_rate & (1u << binding)) {
2254 key.instance_rate_inputs |= 1u << location;
2255 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2256 }
2257
2258 format_desc = vk_format_description(desc->format);
2259 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2260
2261 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2262 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2263
2264 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2265 key.vertex_attribute_bindings[location] = desc->binding;
2266 key.vertex_attribute_offsets[location] = desc->offset;
2267 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2268
2269 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2270 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2271 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2272 uint64_t adjust;
2273 switch(format) {
2274 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2275 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2276 adjust = RADV_ALPHA_ADJUST_SNORM;
2277 break;
2278 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2279 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2280 adjust = RADV_ALPHA_ADJUST_SSCALED;
2281 break;
2282 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2283 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2284 adjust = RADV_ALPHA_ADJUST_SINT;
2285 break;
2286 default:
2287 adjust = 0;
2288 break;
2289 }
2290 key.vertex_alpha_adjust |= adjust << (2 * location);
2291 }
2292
2293 switch (desc->format) {
2294 case VK_FORMAT_B8G8R8A8_UNORM:
2295 case VK_FORMAT_B8G8R8A8_SNORM:
2296 case VK_FORMAT_B8G8R8A8_USCALED:
2297 case VK_FORMAT_B8G8R8A8_SSCALED:
2298 case VK_FORMAT_B8G8R8A8_UINT:
2299 case VK_FORMAT_B8G8R8A8_SINT:
2300 case VK_FORMAT_B8G8R8A8_SRGB:
2301 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2302 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2303 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2304 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2305 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2306 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2307 key.vertex_post_shuffle |= 1 << location;
2308 break;
2309 default:
2310 break;
2311 }
2312 }
2313
2314 const VkPipelineTessellationStateCreateInfo *tess =
2315 radv_pipeline_get_tessellation_state(pCreateInfo);
2316 if (tess)
2317 key.tess_input_vertices = tess->patchControlPoints;
2318
2319 const VkPipelineMultisampleStateCreateInfo *vkms =
2320 radv_pipeline_get_multisample_state(pCreateInfo);
2321 if (vkms && vkms->rasterizationSamples > 1) {
2322 uint32_t num_samples = vkms->rasterizationSamples;
2323 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2324 key.num_samples = num_samples;
2325 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2326 }
2327
2328 key.col_format = blend->spi_shader_col_format;
2329 key.is_dual_src = blend->mrt0_is_dual_src;
2330 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2331 key.is_int8 = blend->col_format_is_int8;
2332 key.is_int10 = blend->col_format_is_int10;
2333 }
2334
2335 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2336 key.topology = pCreateInfo->pInputAssemblyState->topology;
2337
2338 return key;
2339 }
2340
2341 static bool
2342 radv_nir_stage_uses_xfb(const nir_shader *nir)
2343 {
2344 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2345 bool uses_xfb = !!xfb;
2346
2347 ralloc_free(xfb);
2348 return uses_xfb;
2349 }
2350
2351 static void
2352 radv_fill_shader_keys(struct radv_device *device,
2353 struct radv_shader_variant_key *keys,
2354 const struct radv_pipeline_key *key,
2355 nir_shader **nir)
2356 {
2357 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2358 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2359 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2360 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2361 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2362 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2363 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2364 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2365 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2366 }
2367 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2368
2369 if (nir[MESA_SHADER_TESS_CTRL]) {
2370 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2371 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2372 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2373 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2374
2375 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2376 }
2377
2378 if (nir[MESA_SHADER_GEOMETRY]) {
2379 if (nir[MESA_SHADER_TESS_CTRL])
2380 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2381 else
2382 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2383 }
2384
2385 if (device->physical_device->use_ngg) {
2386 if (nir[MESA_SHADER_TESS_CTRL]) {
2387 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2388 } else {
2389 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2390 }
2391
2392 if (nir[MESA_SHADER_TESS_CTRL] &&
2393 nir[MESA_SHADER_GEOMETRY] &&
2394 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2395 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2396 /* Fallback to the legacy path if tessellation is
2397 * enabled with extreme geometry because
2398 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2399 * might hang.
2400 */
2401 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2402 }
2403
2404 if (!device->physical_device->use_ngg_gs) {
2405 if (nir[MESA_SHADER_GEOMETRY]) {
2406 if (nir[MESA_SHADER_TESS_CTRL])
2407 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2408 else
2409 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2410 }
2411 }
2412
2413 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2414
2415 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2416 if (nir[i])
2417 last_xfb_stage = i;
2418 }
2419
2420 bool uses_xfb = nir[last_xfb_stage] &&
2421 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2422
2423 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2424 if (nir[MESA_SHADER_TESS_CTRL])
2425 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2426 else
2427 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2428 }
2429
2430 /* Determine if the pipeline is eligible for the NGG passthrough
2431 * mode. It can't be enabled for geometry shaders, for NGG
2432 * streamout or for vertex shaders that export the primitive ID
2433 * (this is checked later because we don't have the info here.)
2434 */
2435 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2436 if (nir[MESA_SHADER_TESS_CTRL] &&
2437 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2438 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2439 } else if (nir[MESA_SHADER_VERTEX] &&
2440 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2441 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2442 }
2443 }
2444 }
2445
2446 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2447 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2448
2449 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2450 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2451 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2452 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2453 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2454 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2455
2456 if (nir[MESA_SHADER_COMPUTE]) {
2457 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2458 }
2459 }
2460
2461 static uint8_t
2462 radv_get_wave_size(struct radv_device *device,
2463 const VkPipelineShaderStageCreateInfo *pStage,
2464 gl_shader_stage stage,
2465 const struct radv_shader_variant_key *key)
2466 {
2467 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2468 return 64;
2469 else if (stage == MESA_SHADER_COMPUTE) {
2470 if (key->cs.subgroup_size) {
2471 /* Return the required subgroup size if specified. */
2472 return key->cs.subgroup_size;
2473 }
2474 return device->physical_device->cs_wave_size;
2475 }
2476 else if (stage == MESA_SHADER_FRAGMENT)
2477 return device->physical_device->ps_wave_size;
2478 else
2479 return device->physical_device->ge_wave_size;
2480 }
2481
2482 static uint8_t
2483 radv_get_ballot_bit_size(struct radv_device *device,
2484 const VkPipelineShaderStageCreateInfo *pStage,
2485 gl_shader_stage stage,
2486 const struct radv_shader_variant_key *key)
2487 {
2488 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2489 return key->cs.subgroup_size;
2490 return 64;
2491 }
2492
2493 static void
2494 radv_fill_shader_info(struct radv_pipeline *pipeline,
2495 const VkPipelineShaderStageCreateInfo **pStages,
2496 struct radv_shader_variant_key *keys,
2497 struct radv_shader_info *infos,
2498 nir_shader **nir)
2499 {
2500 unsigned active_stages = 0;
2501 unsigned filled_stages = 0;
2502
2503 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2504 if (nir[i])
2505 active_stages |= (1 << i);
2506 }
2507
2508 if (nir[MESA_SHADER_FRAGMENT]) {
2509 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2510 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2511 pipeline->layout,
2512 &keys[MESA_SHADER_FRAGMENT],
2513 &infos[MESA_SHADER_FRAGMENT],
2514 pipeline->device->physical_device->use_llvm);
2515
2516 /* TODO: These are no longer used as keys we should refactor this */
2517 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2518 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2519 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2520 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2521 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2522 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2523 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2524 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2525 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2526 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2527 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2528 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2529 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2530 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2531 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2532 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2533
2534 /* NGG passthrough mode can't be enabled for vertex shaders
2535 * that export the primitive ID.
2536 *
2537 * TODO: I should really refactor the keys logic.
2538 */
2539 if (nir[MESA_SHADER_VERTEX] &&
2540 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2541 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2542 }
2543
2544 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2545 }
2546
2547 if (nir[MESA_SHADER_TESS_CTRL]) {
2548 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2549 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2550 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2551 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2552 }
2553
2554 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2555 nir[MESA_SHADER_TESS_CTRL]) {
2556 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2557 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2558 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2559
2560 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2561
2562 for (int i = 0; i < 2; i++) {
2563 radv_nir_shader_info_pass(combined_nir[i],
2564 pipeline->layout, &key,
2565 &infos[MESA_SHADER_TESS_CTRL],
2566 pipeline->device->physical_device->use_llvm);
2567 }
2568
2569 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2570 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2571 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2572 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2573
2574 filled_stages |= (1 << MESA_SHADER_VERTEX);
2575 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2576 }
2577
2578 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2579 nir[MESA_SHADER_GEOMETRY]) {
2580 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2581 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2582
2583 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2584
2585 for (int i = 0; i < 2; i++) {
2586 radv_nir_shader_info_pass(combined_nir[i],
2587 pipeline->layout,
2588 &keys[pre_stage],
2589 &infos[MESA_SHADER_GEOMETRY],
2590 pipeline->device->physical_device->use_llvm);
2591 }
2592
2593 filled_stages |= (1 << pre_stage);
2594 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2595 }
2596
2597 active_stages ^= filled_stages;
2598 while (active_stages) {
2599 int i = u_bit_scan(&active_stages);
2600
2601 if (i == MESA_SHADER_TESS_CTRL) {
2602 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2603 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2604 }
2605
2606 if (i == MESA_SHADER_TESS_EVAL) {
2607 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2608 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2609 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2610 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2611 }
2612
2613 radv_nir_shader_info_init(&infos[i]);
2614 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2615 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2616 }
2617
2618 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2619 if (nir[i]) {
2620 infos[i].wave_size =
2621 radv_get_wave_size(pipeline->device, pStages[i],
2622 i, &keys[i]);
2623 infos[i].ballot_bit_size =
2624 radv_get_ballot_bit_size(pipeline->device,
2625 pStages[i], i,
2626 &keys[i]);
2627 }
2628 }
2629 }
2630
2631 static void
2632 merge_tess_info(struct shader_info *tes_info,
2633 const struct shader_info *tcs_info)
2634 {
2635 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2636 *
2637 * "PointMode. Controls generation of points rather than triangles
2638 * or lines. This functionality defaults to disabled, and is
2639 * enabled if either shader stage includes the execution mode.
2640 *
2641 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2642 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2643 * and OutputVertices, it says:
2644 *
2645 * "One mode must be set in at least one of the tessellation
2646 * shader stages."
2647 *
2648 * So, the fields can be set in either the TCS or TES, but they must
2649 * agree if set in both. Our backend looks at TES, so bitwise-or in
2650 * the values from the TCS.
2651 */
2652 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2653 tes_info->tess.tcs_vertices_out == 0 ||
2654 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2655 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2656
2657 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2658 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2659 tcs_info->tess.spacing == tes_info->tess.spacing);
2660 tes_info->tess.spacing |= tcs_info->tess.spacing;
2661
2662 assert(tcs_info->tess.primitive_mode == 0 ||
2663 tes_info->tess.primitive_mode == 0 ||
2664 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2665 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2666 tes_info->tess.ccw |= tcs_info->tess.ccw;
2667 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2668 }
2669
2670 static
2671 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2672 {
2673 if (!ext)
2674 return;
2675
2676 if (ext->pPipelineCreationFeedback) {
2677 ext->pPipelineCreationFeedback->flags = 0;
2678 ext->pPipelineCreationFeedback->duration = 0;
2679 }
2680
2681 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2682 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2683 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2684 }
2685 }
2686
2687 static
2688 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2689 {
2690 if (!feedback)
2691 return;
2692
2693 feedback->duration -= radv_get_current_time();
2694 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2695 }
2696
2697 static
2698 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2699 {
2700 if (!feedback)
2701 return;
2702
2703 feedback->duration += radv_get_current_time();
2704 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2705 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2706 }
2707
2708 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2709 struct radv_device *device,
2710 struct radv_pipeline_cache *cache,
2711 const struct radv_pipeline_key *key,
2712 const VkPipelineShaderStageCreateInfo **pStages,
2713 const VkPipelineCreateFlags flags,
2714 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2715 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2716 {
2717 struct radv_shader_module fs_m = {0};
2718 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2719 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2720 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2721 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2722 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2723 unsigned char hash[20], gs_copy_hash[20];
2724 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2725 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2726 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2727 device->keep_shader_info;
2728
2729 radv_start_feedback(pipeline_feedback);
2730
2731 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2732 if (pStages[i]) {
2733 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2734 if (modules[i]->nir)
2735 _mesa_sha1_compute(modules[i]->nir->info.name,
2736 strlen(modules[i]->nir->info.name),
2737 modules[i]->sha1);
2738
2739 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2740 }
2741 }
2742
2743 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2744 memcpy(gs_copy_hash, hash, 20);
2745 gs_copy_hash[0] ^= 1;
2746
2747 bool found_in_application_cache = true;
2748 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2749 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2750 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2751 &found_in_application_cache);
2752 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2753 }
2754
2755 if (!keep_executable_info && !keep_statistic_info &&
2756 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2757 &found_in_application_cache) &&
2758 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2759 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2760 return VK_SUCCESS;
2761 }
2762
2763 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2764 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2765 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2766 }
2767
2768 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2769 nir_builder fs_b;
2770 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2771 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2772 fs_m.nir = fs_b.shader;
2773 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2774 }
2775
2776 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2777 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2778 unsigned subgroup_size = 64, ballot_bit_size = 64;
2779
2780 if (!modules[i])
2781 continue;
2782
2783 radv_start_feedback(stage_feedbacks[i]);
2784
2785 if (key->compute_subgroup_size) {
2786 /* Only compute shaders currently support requiring a
2787 * specific subgroup size.
2788 */
2789 assert(i == MESA_SHADER_COMPUTE);
2790 subgroup_size = key->compute_subgroup_size;
2791 ballot_bit_size = key->compute_subgroup_size;
2792 }
2793
2794 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2795 stage ? stage->pName : "main", i,
2796 stage ? stage->pSpecializationInfo : NULL,
2797 flags, pipeline->layout,
2798 subgroup_size, ballot_bit_size);
2799
2800 /* We don't want to alter meta shaders IR directly so clone it
2801 * first.
2802 */
2803 if (nir[i]->info.name) {
2804 nir[i] = nir_shader_clone(NULL, nir[i]);
2805 }
2806
2807 radv_stop_feedback(stage_feedbacks[i], false);
2808 }
2809
2810 if (nir[MESA_SHADER_TESS_CTRL]) {
2811 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2812 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2813 }
2814
2815 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2816 radv_link_shaders(pipeline, nir);
2817
2818 radv_set_linked_driver_locations(pipeline, nir, infos);
2819
2820 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2821 if (nir[i]) {
2822 /* do this again since information such as outputs_read can be out-of-date */
2823 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2824
2825 if (device->physical_device->use_llvm) {
2826 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2827 } else {
2828 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2829 nir_lower_non_uniform_ubo_access |
2830 nir_lower_non_uniform_ssbo_access |
2831 nir_lower_non_uniform_texture_access |
2832 nir_lower_non_uniform_image_access);
2833 }
2834 }
2835 }
2836
2837 if (nir[MESA_SHADER_FRAGMENT])
2838 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2839
2840 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2841 if (radv_can_dump_shader(device, modules[i], false))
2842 nir_print_shader(nir[i], stderr);
2843 }
2844
2845 radv_fill_shader_keys(device, keys, key, nir);
2846
2847 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2848
2849 if ((nir[MESA_SHADER_VERTEX] &&
2850 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2851 (nir[MESA_SHADER_TESS_EVAL] &&
2852 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2853 struct gfx10_ngg_info *ngg_info;
2854
2855 if (nir[MESA_SHADER_GEOMETRY])
2856 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2857 else if (nir[MESA_SHADER_TESS_CTRL])
2858 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2859 else
2860 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2861
2862 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2863 } else if (nir[MESA_SHADER_GEOMETRY]) {
2864 struct gfx9_gs_info *gs_info =
2865 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2866
2867 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2868 }
2869
2870 if(modules[MESA_SHADER_GEOMETRY]) {
2871 struct radv_shader_binary *gs_copy_binary = NULL;
2872 if (!pipeline->gs_copy_shader &&
2873 !radv_pipeline_has_ngg(pipeline)) {
2874 struct radv_shader_info info = {};
2875 struct radv_shader_variant_key key = {};
2876
2877 key.has_multiview_view_index =
2878 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2879
2880 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2881 pipeline->layout, &key,
2882 &info, pipeline->device->physical_device->use_llvm);
2883 info.wave_size = 64; /* Wave32 not supported. */
2884 info.ballot_bit_size = 64;
2885
2886 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2887 device, nir[MESA_SHADER_GEOMETRY], &info,
2888 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2889 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2890 }
2891
2892 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2893 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2894 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2895
2896 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2897 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2898
2899 radv_pipeline_cache_insert_shaders(device, cache,
2900 gs_copy_hash,
2901 variants,
2902 binaries);
2903 }
2904 free(gs_copy_binary);
2905 }
2906
2907 if (nir[MESA_SHADER_FRAGMENT]) {
2908 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2909 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2910
2911 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2912 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2913 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2914 infos + MESA_SHADER_FRAGMENT,
2915 keep_executable_info, keep_statistic_info,
2916 &binaries[MESA_SHADER_FRAGMENT]);
2917
2918 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2919 }
2920 }
2921
2922 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2923 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2924 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2925 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2926 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2927
2928 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2929
2930 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2931 pipeline->layout,
2932 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2933 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2934
2935 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2936 }
2937 modules[MESA_SHADER_VERTEX] = NULL;
2938 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2939 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2940 }
2941
2942 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2943 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2944 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2945 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2946
2947 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2948
2949 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2950 pipeline->layout,
2951 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2952 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2953
2954 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2955 }
2956 modules[pre_stage] = NULL;
2957 }
2958
2959 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2960 if(modules[i] && !pipeline->shaders[i]) {
2961 if (i == MESA_SHADER_TESS_CTRL) {
2962 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2963 }
2964 if (i == MESA_SHADER_TESS_EVAL) {
2965 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2966 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2967 }
2968
2969 radv_start_feedback(stage_feedbacks[i]);
2970
2971 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2972 pipeline->layout,
2973 keys + i, infos + i, keep_executable_info,
2974 keep_statistic_info, &binaries[i]);
2975
2976 radv_stop_feedback(stage_feedbacks[i], false);
2977 }
2978 }
2979
2980 if (!keep_executable_info && !keep_statistic_info) {
2981 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2982 binaries);
2983 }
2984
2985 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2986 free(binaries[i]);
2987 if (nir[i]) {
2988 ralloc_free(nir[i]);
2989
2990 if (radv_can_dump_shader_stats(device, modules[i]))
2991 radv_shader_dump_stats(device,
2992 pipeline->shaders[i],
2993 i, stderr);
2994 }
2995 }
2996
2997 if (fs_m.nir)
2998 ralloc_free(fs_m.nir);
2999
3000 radv_stop_feedback(pipeline_feedback, false);
3001 return VK_SUCCESS;
3002 }
3003
3004 static uint32_t
3005 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3006 gl_shader_stage stage, enum chip_class chip_class)
3007 {
3008 bool has_gs = radv_pipeline_has_gs(pipeline);
3009 bool has_tess = radv_pipeline_has_tess(pipeline);
3010 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3011
3012 switch (stage) {
3013 case MESA_SHADER_FRAGMENT:
3014 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3015 case MESA_SHADER_VERTEX:
3016 if (has_tess) {
3017 if (chip_class >= GFX10) {
3018 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3019 } else if (chip_class == GFX9) {
3020 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3021 } else {
3022 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3023 }
3024
3025 }
3026
3027 if (has_gs) {
3028 if (chip_class >= GFX10) {
3029 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3030 } else {
3031 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3032 }
3033 }
3034
3035 if (has_ngg)
3036 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3037
3038 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3039 case MESA_SHADER_GEOMETRY:
3040 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3041 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3042 case MESA_SHADER_COMPUTE:
3043 return R_00B900_COMPUTE_USER_DATA_0;
3044 case MESA_SHADER_TESS_CTRL:
3045 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3046 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3047 case MESA_SHADER_TESS_EVAL:
3048 if (has_gs) {
3049 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3050 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3051 } else if (has_ngg) {
3052 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3053 } else {
3054 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3055 }
3056 default:
3057 unreachable("unknown shader");
3058 }
3059 }
3060
3061 struct radv_bin_size_entry {
3062 unsigned bpp;
3063 VkExtent2D extent;
3064 };
3065
3066 static VkExtent2D
3067 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3068 {
3069 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3070 {
3071 /* One RB / SE */
3072 {
3073 /* One shader engine */
3074 { 0, {128, 128}},
3075 { 1, { 64, 128}},
3076 { 2, { 32, 128}},
3077 { 3, { 16, 128}},
3078 { 17, { 0, 0}},
3079 { UINT_MAX, { 0, 0}},
3080 },
3081 {
3082 /* Two shader engines */
3083 { 0, {128, 128}},
3084 { 2, { 64, 128}},
3085 { 3, { 32, 128}},
3086 { 5, { 16, 128}},
3087 { 17, { 0, 0}},
3088 { UINT_MAX, { 0, 0}},
3089 },
3090 {
3091 /* Four shader engines */
3092 { 0, {128, 128}},
3093 { 3, { 64, 128}},
3094 { 5, { 16, 128}},
3095 { 17, { 0, 0}},
3096 { UINT_MAX, { 0, 0}},
3097 },
3098 },
3099 {
3100 /* Two RB / SE */
3101 {
3102 /* One shader engine */
3103 { 0, {128, 128}},
3104 { 2, { 64, 128}},
3105 { 3, { 32, 128}},
3106 { 5, { 16, 128}},
3107 { 33, { 0, 0}},
3108 { UINT_MAX, { 0, 0}},
3109 },
3110 {
3111 /* Two shader engines */
3112 { 0, {128, 128}},
3113 { 3, { 64, 128}},
3114 { 5, { 32, 128}},
3115 { 9, { 16, 128}},
3116 { 33, { 0, 0}},
3117 { UINT_MAX, { 0, 0}},
3118 },
3119 {
3120 /* Four shader engines */
3121 { 0, {256, 256}},
3122 { 2, {128, 256}},
3123 { 3, {128, 128}},
3124 { 5, { 64, 128}},
3125 { 9, { 16, 128}},
3126 { 33, { 0, 0}},
3127 { UINT_MAX, { 0, 0}},
3128 },
3129 },
3130 {
3131 /* Four RB / SE */
3132 {
3133 /* One shader engine */
3134 { 0, {128, 256}},
3135 { 2, {128, 128}},
3136 { 3, { 64, 128}},
3137 { 5, { 32, 128}},
3138 { 9, { 16, 128}},
3139 { 33, { 0, 0}},
3140 { UINT_MAX, { 0, 0}},
3141 },
3142 {
3143 /* Two shader engines */
3144 { 0, {256, 256}},
3145 { 2, {128, 256}},
3146 { 3, {128, 128}},
3147 { 5, { 64, 128}},
3148 { 9, { 32, 128}},
3149 { 17, { 16, 128}},
3150 { 33, { 0, 0}},
3151 { UINT_MAX, { 0, 0}},
3152 },
3153 {
3154 /* Four shader engines */
3155 { 0, {256, 512}},
3156 { 2, {256, 256}},
3157 { 3, {128, 256}},
3158 { 5, {128, 128}},
3159 { 9, { 64, 128}},
3160 { 17, { 16, 128}},
3161 { 33, { 0, 0}},
3162 { UINT_MAX, { 0, 0}},
3163 },
3164 },
3165 };
3166 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3167 {
3168 // One RB / SE
3169 {
3170 // One shader engine
3171 { 0, {128, 256}},
3172 { 2, {128, 128}},
3173 { 4, { 64, 128}},
3174 { 7, { 32, 128}},
3175 { 13, { 16, 128}},
3176 { 49, { 0, 0}},
3177 { UINT_MAX, { 0, 0}},
3178 },
3179 {
3180 // Two shader engines
3181 { 0, {256, 256}},
3182 { 2, {128, 256}},
3183 { 4, {128, 128}},
3184 { 7, { 64, 128}},
3185 { 13, { 32, 128}},
3186 { 25, { 16, 128}},
3187 { 49, { 0, 0}},
3188 { UINT_MAX, { 0, 0}},
3189 },
3190 {
3191 // Four shader engines
3192 { 0, {256, 512}},
3193 { 2, {256, 256}},
3194 { 4, {128, 256}},
3195 { 7, {128, 128}},
3196 { 13, { 64, 128}},
3197 { 25, { 16, 128}},
3198 { 49, { 0, 0}},
3199 { UINT_MAX, { 0, 0}},
3200 },
3201 },
3202 {
3203 // Two RB / SE
3204 {
3205 // One shader engine
3206 { 0, {256, 256}},
3207 { 2, {128, 256}},
3208 { 4, {128, 128}},
3209 { 7, { 64, 128}},
3210 { 13, { 32, 128}},
3211 { 25, { 16, 128}},
3212 { 97, { 0, 0}},
3213 { UINT_MAX, { 0, 0}},
3214 },
3215 {
3216 // Two shader engines
3217 { 0, {256, 512}},
3218 { 2, {256, 256}},
3219 { 4, {128, 256}},
3220 { 7, {128, 128}},
3221 { 13, { 64, 128}},
3222 { 25, { 32, 128}},
3223 { 49, { 16, 128}},
3224 { 97, { 0, 0}},
3225 { UINT_MAX, { 0, 0}},
3226 },
3227 {
3228 // Four shader engines
3229 { 0, {512, 512}},
3230 { 2, {256, 512}},
3231 { 4, {256, 256}},
3232 { 7, {128, 256}},
3233 { 13, {128, 128}},
3234 { 25, { 64, 128}},
3235 { 49, { 16, 128}},
3236 { 97, { 0, 0}},
3237 { UINT_MAX, { 0, 0}},
3238 },
3239 },
3240 {
3241 // Four RB / SE
3242 {
3243 // One shader engine
3244 { 0, {256, 512}},
3245 { 2, {256, 256}},
3246 { 4, {128, 256}},
3247 { 7, {128, 128}},
3248 { 13, { 64, 128}},
3249 { 25, { 32, 128}},
3250 { 49, { 16, 128}},
3251 { UINT_MAX, { 0, 0}},
3252 },
3253 {
3254 // Two shader engines
3255 { 0, {512, 512}},
3256 { 2, {256, 512}},
3257 { 4, {256, 256}},
3258 { 7, {128, 256}},
3259 { 13, {128, 128}},
3260 { 25, { 64, 128}},
3261 { 49, { 32, 128}},
3262 { 97, { 16, 128}},
3263 { UINT_MAX, { 0, 0}},
3264 },
3265 {
3266 // Four shader engines
3267 { 0, {512, 512}},
3268 { 4, {256, 512}},
3269 { 7, {256, 256}},
3270 { 13, {128, 256}},
3271 { 25, {128, 128}},
3272 { 49, { 64, 128}},
3273 { 97, { 16, 128}},
3274 { UINT_MAX, { 0, 0}},
3275 },
3276 },
3277 };
3278
3279 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3280 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3281 VkExtent2D extent = {512, 512};
3282
3283 unsigned log_num_rb_per_se =
3284 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3285 pipeline->device->physical_device->rad_info.max_se);
3286 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3287
3288 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3289 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3290 unsigned effective_samples = total_samples;
3291 unsigned color_bytes_per_pixel = 0;
3292
3293 const VkPipelineColorBlendStateCreateInfo *vkblend =
3294 radv_pipeline_get_color_blend_state(pCreateInfo);
3295 if (vkblend) {
3296 for (unsigned i = 0; i < subpass->color_count; i++) {
3297 if (!vkblend->pAttachments[i].colorWriteMask)
3298 continue;
3299
3300 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3301 continue;
3302
3303 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3304 color_bytes_per_pixel += vk_format_get_blocksize(format);
3305 }
3306
3307 /* MSAA images typically don't use all samples all the time. */
3308 if (effective_samples >= 2 && ps_iter_samples <= 1)
3309 effective_samples = 2;
3310 color_bytes_per_pixel *= effective_samples;
3311 }
3312
3313 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3314 while(color_entry[1].bpp <= color_bytes_per_pixel)
3315 ++color_entry;
3316
3317 extent = color_entry->extent;
3318
3319 if (subpass->depth_stencil_attachment) {
3320 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3321
3322 /* Coefficients taken from AMDVLK */
3323 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3324 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3325 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3326
3327 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3328 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3329 ++ds_entry;
3330
3331 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3332 extent = ds_entry->extent;
3333 }
3334
3335 return extent;
3336 }
3337
3338 static VkExtent2D
3339 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3340 {
3341 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3342 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3343 VkExtent2D extent = {512, 512};
3344
3345 const unsigned db_tag_size = 64;
3346 const unsigned db_tag_count = 312;
3347 const unsigned color_tag_size = 1024;
3348 const unsigned color_tag_count = 31;
3349 const unsigned fmask_tag_size = 256;
3350 const unsigned fmask_tag_count = 44;
3351
3352 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3353 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3354
3355 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3356 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3357 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3358
3359 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3360 const unsigned samples_log = util_logbase2_ceil(total_samples);
3361
3362 unsigned color_bytes_per_pixel = 0;
3363 unsigned fmask_bytes_per_pixel = 0;
3364
3365 const VkPipelineColorBlendStateCreateInfo *vkblend =
3366 radv_pipeline_get_color_blend_state(pCreateInfo);
3367 if (vkblend) {
3368 for (unsigned i = 0; i < subpass->color_count; i++) {
3369 if (!vkblend->pAttachments[i].colorWriteMask)
3370 continue;
3371
3372 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3373 continue;
3374
3375 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3376 color_bytes_per_pixel += vk_format_get_blocksize(format);
3377
3378 if (total_samples > 1) {
3379 assert(samples_log <= 3);
3380 const unsigned fmask_array[] = {0, 1, 1, 4};
3381 fmask_bytes_per_pixel += fmask_array[samples_log];
3382 }
3383 }
3384
3385 color_bytes_per_pixel *= total_samples;
3386 }
3387 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3388
3389 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3390 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3391 extent.height = 1ull << (color_pixel_count_log / 2);
3392
3393 if (fmask_bytes_per_pixel) {
3394 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3395
3396 const VkExtent2D fmask_extent = (VkExtent2D){
3397 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3398 .height = 1ull << (color_pixel_count_log / 2)
3399 };
3400
3401 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3402 extent = fmask_extent;
3403 }
3404
3405 if (subpass->depth_stencil_attachment) {
3406 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3407
3408 /* Coefficients taken from AMDVLK */
3409 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3410 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3411 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3412
3413 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3414
3415 const VkExtent2D db_extent = (VkExtent2D){
3416 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3417 .height = 1ull << (color_pixel_count_log / 2)
3418 };
3419
3420 if (db_extent.width * db_extent.height < extent.width * extent.height)
3421 extent = db_extent;
3422 }
3423
3424 extent.width = MAX2(extent.width, 128);
3425 extent.height = MAX2(extent.width, 64);
3426
3427 return extent;
3428 }
3429
3430 static void
3431 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3432 struct radv_pipeline *pipeline,
3433 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3434 {
3435 uint32_t pa_sc_binner_cntl_0 =
3436 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3437 S_028C44_DISABLE_START_OF_PRIM(1);
3438 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3439
3440 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3441 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3442 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3443 const VkPipelineColorBlendStateCreateInfo *vkblend =
3444 radv_pipeline_get_color_blend_state(pCreateInfo);
3445 unsigned min_bytes_per_pixel = 0;
3446
3447 if (vkblend) {
3448 for (unsigned i = 0; i < subpass->color_count; i++) {
3449 if (!vkblend->pAttachments[i].colorWriteMask)
3450 continue;
3451
3452 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3453 continue;
3454
3455 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3456 unsigned bytes = vk_format_get_blocksize(format);
3457 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3458 min_bytes_per_pixel = bytes;
3459 }
3460 }
3461
3462 pa_sc_binner_cntl_0 =
3463 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3464 S_028C44_BIN_SIZE_X(0) |
3465 S_028C44_BIN_SIZE_Y(0) |
3466 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3467 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3468 S_028C44_DISABLE_START_OF_PRIM(1);
3469 }
3470
3471 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3472 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3473 }
3474
3475 struct radv_binning_settings
3476 radv_get_binning_settings(const struct radv_physical_device *pdev)
3477 {
3478 struct radv_binning_settings settings;
3479 if (pdev->rad_info.has_dedicated_vram) {
3480 if (pdev->rad_info.num_render_backends > 4) {
3481 settings.context_states_per_bin = 1;
3482 settings.persistent_states_per_bin = 1;
3483 } else {
3484 settings.context_states_per_bin = 3;
3485 settings.persistent_states_per_bin = 8;
3486 }
3487 settings.fpovs_per_batch = 63;
3488 } else {
3489 /* The context states are affected by the scissor bug. */
3490 settings.context_states_per_bin = 6;
3491 /* 32 causes hangs for RAVEN. */
3492 settings.persistent_states_per_bin = 16;
3493 settings.fpovs_per_batch = 63;
3494 }
3495
3496 if (pdev->rad_info.has_gfx9_scissor_bug)
3497 settings.context_states_per_bin = 1;
3498
3499 return settings;
3500 }
3501
3502 static void
3503 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3504 struct radv_pipeline *pipeline,
3505 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3506 const struct radv_blend_state *blend)
3507 {
3508 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3509 return;
3510
3511 VkExtent2D bin_size;
3512 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3513 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3514 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3515 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3516 } else
3517 unreachable("Unhandled generation for binning bin size calculation");
3518
3519 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3520 struct radv_binning_settings settings =
3521 radv_get_binning_settings(pipeline->device->physical_device);
3522
3523 bool disable_start_of_prim = true;
3524 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3525
3526 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3527
3528 if (pipeline->device->dfsm_allowed && ps &&
3529 !ps->info.ps.can_discard &&
3530 !ps->info.ps.writes_memory &&
3531 blend->cb_target_enabled_4bit) {
3532 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3533 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3534 }
3535
3536 const uint32_t pa_sc_binner_cntl_0 =
3537 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3538 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3539 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3540 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3541 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3542 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3543 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3544 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3545 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3546 S_028C44_OPTIMAL_BIN_SELECTION(1);
3547
3548 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3549 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3550 } else
3551 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3552 }
3553
3554
3555 static void
3556 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3557 struct radv_pipeline *pipeline,
3558 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3559 const struct radv_graphics_pipeline_create_info *extra)
3560 {
3561 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3562 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3563 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3564 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3565 struct radv_render_pass_attachment *attachment = NULL;
3566 uint32_t db_depth_control = 0, db_stencil_control = 0;
3567 uint32_t db_render_control = 0, db_render_override2 = 0;
3568 uint32_t db_render_override = 0;
3569
3570 if (subpass->depth_stencil_attachment)
3571 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3572
3573 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3574 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3575
3576 if (vkds && has_depth_attachment) {
3577 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3578 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3579 S_028800_ZFUNC(vkds->depthCompareOp) |
3580 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3581
3582 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3583 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3584
3585 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3586 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3587 }
3588
3589 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3590 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3591 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3592 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3593 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3594 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3595
3596 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3597 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3598 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3599 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3600 }
3601
3602 if (attachment && extra) {
3603 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3604 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3605
3606 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3607 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3608 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3609 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3610 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3611 }
3612
3613 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3614 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3615
3616 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3617 ps->info.ps.writes_z) {
3618 /* From VK_EXT_depth_range_unrestricted spec:
3619 *
3620 * "The behavior described in Primitive Clipping still applies.
3621 * If depth clamping is disabled the depth values are still
3622 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3623 * depth clamping is enabled the above equation is ignored and
3624 * the depth values are instead clamped to the VkViewport
3625 * minDepth and maxDepth values, which in the case of this
3626 * extension can be outside of the 0.0 to 1.0 range."
3627 */
3628 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3629 }
3630
3631 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3632 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3633
3634 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3635 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3636 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3637 }
3638
3639 static void
3640 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3641 struct radv_pipeline *pipeline,
3642 const struct radv_blend_state *blend)
3643 {
3644 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3645 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3646 8);
3647 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3648 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3649
3650 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3651
3652 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3653 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3654 }
3655
3656 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3657
3658 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3659 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3660
3661 pipeline->graphics.col_format = blend->spi_shader_col_format;
3662 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3663 }
3664
3665 static const VkConservativeRasterizationModeEXT
3666 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3667 {
3668 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3669 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3670
3671 if (!conservative_raster)
3672 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3673 return conservative_raster->conservativeRasterizationMode;
3674 }
3675
3676 static void
3677 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3678 struct radv_pipeline *pipeline,
3679 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3680 {
3681 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3682 const VkConservativeRasterizationModeEXT mode =
3683 radv_get_conservative_raster_mode(vkraster);
3684 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3685 bool depth_clip_disable = vkraster->depthClampEnable;
3686
3687 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3688 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3689 if (depth_clip_state) {
3690 depth_clip_disable = !depth_clip_state->depthClipEnable;
3691 }
3692
3693 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3694 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3695 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3696 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3697 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3698 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3699
3700 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3701 S_0286D4_FLAT_SHADE_ENA(1) |
3702 S_0286D4_PNT_SPRITE_ENA(1) |
3703 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3704 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3705 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3706 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3707 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3708
3709 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3710 S_028BE4_PIX_CENTER(1) | // TODO verify
3711 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3712 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3713
3714 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3715 S_028814_FACE(vkraster->frontFace) |
3716 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3717 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3718 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3719 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3720 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3721 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3722 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3723 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3724
3725 /* Conservative rasterization. */
3726 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3727 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3728
3729 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3730 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3731 S_028804_OVERRASTERIZATION_AMOUNT(4);
3732
3733 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3734 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3735 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3736
3737 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3738 pa_sc_conservative_rast |=
3739 S_028C4C_OVER_RAST_ENABLE(1) |
3740 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3741 S_028C4C_UNDER_RAST_ENABLE(0) |
3742 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3743 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3744 } else {
3745 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3746 pa_sc_conservative_rast |=
3747 S_028C4C_OVER_RAST_ENABLE(0) |
3748 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3749 S_028C4C_UNDER_RAST_ENABLE(1) |
3750 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3751 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3752 }
3753 }
3754
3755 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3756 pa_sc_conservative_rast);
3757 }
3758
3759
3760 static void
3761 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3762 struct radv_pipeline *pipeline)
3763 {
3764 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3765
3766 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3767 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3768 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3769
3770 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3771 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3772 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3773 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3774 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3775
3776 /* The exclusion bits can be set to improve rasterization efficiency
3777 * if no sample lies on the pixel boundary (-8 sample offset). It's
3778 * currently always TRUE because the driver doesn't support 16 samples.
3779 */
3780 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3781 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3782 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3783 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3784
3785 /* GFX9: Flush DFSM when the AA mode changes. */
3786 if (pipeline->device->dfsm_allowed) {
3787 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3788 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3789 }
3790 }
3791
3792 static void
3793 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3794 struct radv_pipeline *pipeline)
3795 {
3796 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3797 const struct radv_shader_variant *vs =
3798 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3799 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3800 pipeline->shaders[MESA_SHADER_VERTEX];
3801 unsigned vgt_primitiveid_en = 0;
3802 uint32_t vgt_gs_mode = 0;
3803
3804 if (radv_pipeline_has_ngg(pipeline))
3805 return;
3806
3807 if (radv_pipeline_has_gs(pipeline)) {
3808 const struct radv_shader_variant *gs =
3809 pipeline->shaders[MESA_SHADER_GEOMETRY];
3810
3811 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3812 pipeline->device->physical_device->rad_info.chip_class);
3813 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3814 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3815 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3816 }
3817
3818 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3819 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3820 }
3821
3822 static void
3823 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3824 struct radeon_cmdbuf *cs,
3825 struct radv_pipeline *pipeline,
3826 struct radv_shader_variant *shader)
3827 {
3828 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3829
3830 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3831 radeon_emit(cs, va >> 8);
3832 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3833 radeon_emit(cs, shader->config.rsrc1);
3834 radeon_emit(cs, shader->config.rsrc2);
3835
3836 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3837 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3838 clip_dist_mask = outinfo->clip_dist_mask;
3839 cull_dist_mask = outinfo->cull_dist_mask;
3840 total_mask = clip_dist_mask | cull_dist_mask;
3841 bool misc_vec_ena = outinfo->writes_pointsize ||
3842 outinfo->writes_layer ||
3843 outinfo->writes_viewport_index;
3844 unsigned spi_vs_out_config, nparams;
3845
3846 /* VS is required to export at least one param. */
3847 nparams = MAX2(outinfo->param_exports, 1);
3848 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3849
3850 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3851 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3852 }
3853
3854 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3855
3856 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3857 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3858 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3859 V_02870C_SPI_SHADER_4COMP :
3860 V_02870C_SPI_SHADER_NONE) |
3861 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3862 V_02870C_SPI_SHADER_4COMP :
3863 V_02870C_SPI_SHADER_NONE) |
3864 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3865 V_02870C_SPI_SHADER_4COMP :
3866 V_02870C_SPI_SHADER_NONE));
3867
3868 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3869 S_028818_VTX_W0_FMT(1) |
3870 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3871 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3872 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3873
3874 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3875 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3876 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3877 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3878 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3879 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3880 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3881 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3882 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3883 cull_dist_mask << 8 |
3884 clip_dist_mask);
3885
3886 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3887 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3888 outinfo->writes_viewport_index);
3889 }
3890
3891 static void
3892 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3893 struct radv_pipeline *pipeline,
3894 struct radv_shader_variant *shader)
3895 {
3896 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3897
3898 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3899 radeon_emit(cs, va >> 8);
3900 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3901 radeon_emit(cs, shader->config.rsrc1);
3902 radeon_emit(cs, shader->config.rsrc2);
3903 }
3904
3905 static void
3906 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3907 struct radv_pipeline *pipeline,
3908 struct radv_shader_variant *shader,
3909 const struct radv_tessellation_state *tess)
3910 {
3911 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3912 uint32_t rsrc2 = shader->config.rsrc2;
3913
3914 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3915 radeon_emit(cs, va >> 8);
3916 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3917
3918 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3919 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3920 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3921 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3922
3923 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3924 radeon_emit(cs, shader->config.rsrc1);
3925 radeon_emit(cs, rsrc2);
3926 }
3927
3928 static void
3929 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3930 struct radeon_cmdbuf *cs,
3931 struct radv_pipeline *pipeline,
3932 struct radv_shader_variant *shader)
3933 {
3934 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3935 gl_shader_stage es_type =
3936 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3937 struct radv_shader_variant *es =
3938 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3939 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3940
3941 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3942 radeon_emit(cs, va >> 8);
3943 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3944 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3945 radeon_emit(cs, shader->config.rsrc1);
3946 radeon_emit(cs, shader->config.rsrc2);
3947
3948 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3949 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3950 clip_dist_mask = outinfo->clip_dist_mask;
3951 cull_dist_mask = outinfo->cull_dist_mask;
3952 total_mask = clip_dist_mask | cull_dist_mask;
3953 bool misc_vec_ena = outinfo->writes_pointsize ||
3954 outinfo->writes_layer ||
3955 outinfo->writes_viewport_index;
3956 bool es_enable_prim_id = outinfo->export_prim_id ||
3957 (es && es->info.uses_prim_id);
3958 bool break_wave_at_eoi = false;
3959 unsigned ge_cntl;
3960 unsigned nparams;
3961
3962 if (es_type == MESA_SHADER_TESS_EVAL) {
3963 struct radv_shader_variant *gs =
3964 pipeline->shaders[MESA_SHADER_GEOMETRY];
3965
3966 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3967 break_wave_at_eoi = true;
3968 }
3969
3970 nparams = MAX2(outinfo->param_exports, 1);
3971 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3972 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3973 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3974
3975 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3976 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3977 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3978 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3979 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3980 V_02870C_SPI_SHADER_4COMP :
3981 V_02870C_SPI_SHADER_NONE) |
3982 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3983 V_02870C_SPI_SHADER_4COMP :
3984 V_02870C_SPI_SHADER_NONE) |
3985 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3986 V_02870C_SPI_SHADER_4COMP :
3987 V_02870C_SPI_SHADER_NONE));
3988
3989 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3990 S_028818_VTX_W0_FMT(1) |
3991 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3992 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3993 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3994 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3995 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3996 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3997 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3998 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3999 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4000 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4001 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4002 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4003 cull_dist_mask << 8 |
4004 clip_dist_mask);
4005
4006 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4007 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4008 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4009
4010 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4011 ngg_state->vgt_esgs_ring_itemsize);
4012
4013 /* NGG specific registers. */
4014 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4015 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4016
4017 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4018 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4019 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4020 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4021 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4022 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4023 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4024 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4025 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4026 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4027 S_028B90_CNT(gs_num_invocations) |
4028 S_028B90_ENABLE(gs_num_invocations > 1) |
4029 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4030
4031 /* User edge flags are set by the pos exports. If user edge flags are
4032 * not used, we must use hw-generated edge flags and pass them via
4033 * the prim export to prevent drawing lines on internal edges of
4034 * decomposed primitives (such as quads) with polygon mode = lines.
4035 *
4036 * TODO: We should combine hw-generated edge flags with user edge
4037 * flags in the shader.
4038 */
4039 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4040 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4041 !radv_pipeline_has_gs(pipeline)) |
4042 /* Reuse for NGG. */
4043 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4044
4045 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4046 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4047 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4048
4049 /* Bug workaround for a possible hang with non-tessellation cases.
4050 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4051 *
4052 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4053 */
4054 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4055 !radv_pipeline_has_tess(pipeline) &&
4056 ngg_state->hw_max_esverts != 256) {
4057 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4058
4059 if (ngg_state->hw_max_esverts > 5) {
4060 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4061 }
4062 }
4063
4064 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4065 }
4066
4067 static void
4068 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4069 struct radv_pipeline *pipeline,
4070 struct radv_shader_variant *shader,
4071 const struct radv_tessellation_state *tess)
4072 {
4073 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4074
4075 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4076 unsigned hs_rsrc2 = shader->config.rsrc2;
4077
4078 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4079 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4080 } else {
4081 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4082 }
4083
4084 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4085 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4086 radeon_emit(cs, va >> 8);
4087 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4088 } else {
4089 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4090 radeon_emit(cs, va >> 8);
4091 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4092 }
4093
4094 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4095 radeon_emit(cs, shader->config.rsrc1);
4096 radeon_emit(cs, hs_rsrc2);
4097 } else {
4098 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4099 radeon_emit(cs, va >> 8);
4100 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4101 radeon_emit(cs, shader->config.rsrc1);
4102 radeon_emit(cs, shader->config.rsrc2);
4103 }
4104 }
4105
4106 static void
4107 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4108 struct radeon_cmdbuf *cs,
4109 struct radv_pipeline *pipeline,
4110 const struct radv_tessellation_state *tess)
4111 {
4112 struct radv_shader_variant *vs;
4113
4114 /* Skip shaders merged into HS/GS */
4115 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4116 if (!vs)
4117 return;
4118
4119 if (vs->info.vs.as_ls)
4120 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4121 else if (vs->info.vs.as_es)
4122 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4123 else if (vs->info.is_ngg)
4124 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4125 else
4126 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4127 }
4128
4129 static void
4130 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4131 struct radeon_cmdbuf *cs,
4132 struct radv_pipeline *pipeline,
4133 const struct radv_tessellation_state *tess)
4134 {
4135 if (!radv_pipeline_has_tess(pipeline))
4136 return;
4137
4138 struct radv_shader_variant *tes, *tcs;
4139
4140 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4141 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4142
4143 if (tes) {
4144 if (tes->info.is_ngg) {
4145 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4146 } else if (tes->info.tes.as_es)
4147 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4148 else
4149 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4150 }
4151
4152 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4153
4154 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4155 tess->tf_param);
4156
4157 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4158 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4159 tess->ls_hs_config);
4160 else
4161 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4162 tess->ls_hs_config);
4163
4164 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4165 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4166 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4167 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4168 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4169 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4170 }
4171 }
4172
4173 static void
4174 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4175 struct radeon_cmdbuf *cs,
4176 struct radv_pipeline *pipeline,
4177 struct radv_shader_variant *gs)
4178 {
4179 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4180 unsigned gs_max_out_vertices;
4181 uint8_t *num_components;
4182 uint8_t max_stream;
4183 unsigned offset;
4184 uint64_t va;
4185
4186 gs_max_out_vertices = gs->info.gs.vertices_out;
4187 max_stream = gs->info.gs.max_stream;
4188 num_components = gs->info.gs.num_stream_output_components;
4189
4190 offset = num_components[0] * gs_max_out_vertices;
4191
4192 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4193 radeon_emit(ctx_cs, offset);
4194 if (max_stream >= 1)
4195 offset += num_components[1] * gs_max_out_vertices;
4196 radeon_emit(ctx_cs, offset);
4197 if (max_stream >= 2)
4198 offset += num_components[2] * gs_max_out_vertices;
4199 radeon_emit(ctx_cs, offset);
4200 if (max_stream >= 3)
4201 offset += num_components[3] * gs_max_out_vertices;
4202 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4203
4204 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4205 radeon_emit(ctx_cs, num_components[0]);
4206 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4207 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4208 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4209
4210 uint32_t gs_num_invocations = gs->info.gs.invocations;
4211 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4212 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4213 S_028B90_ENABLE(gs_num_invocations > 0));
4214
4215 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4216 gs_state->vgt_esgs_ring_itemsize);
4217
4218 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4219
4220 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4221 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4222 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4223 radeon_emit(cs, va >> 8);
4224 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4225 } else {
4226 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4227 radeon_emit(cs, va >> 8);
4228 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4229 }
4230
4231 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4232 radeon_emit(cs, gs->config.rsrc1);
4233 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4234
4235 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4236 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4237 } else {
4238 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4239 radeon_emit(cs, va >> 8);
4240 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4241 radeon_emit(cs, gs->config.rsrc1);
4242 radeon_emit(cs, gs->config.rsrc2);
4243 }
4244
4245 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4246 }
4247
4248 static void
4249 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4250 struct radeon_cmdbuf *cs,
4251 struct radv_pipeline *pipeline)
4252 {
4253 struct radv_shader_variant *gs;
4254
4255 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4256 if (!gs)
4257 return;
4258
4259 if (gs->info.is_ngg)
4260 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4261 else
4262 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4263
4264 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4265 gs->info.gs.vertices_out);
4266 }
4267
4268 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4269 bool explicit, bool float16)
4270 {
4271 uint32_t ps_input_cntl;
4272 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4273 ps_input_cntl = S_028644_OFFSET(offset);
4274 if (flat_shade || explicit)
4275 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4276 if (explicit) {
4277 /* Force parameter cache to be read in passthrough
4278 * mode.
4279 */
4280 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4281 }
4282 if (float16) {
4283 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4284 S_028644_ATTR0_VALID(1);
4285 }
4286 } else {
4287 /* The input is a DEFAULT_VAL constant. */
4288 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4289 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4290 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4291 ps_input_cntl = S_028644_OFFSET(0x20) |
4292 S_028644_DEFAULT_VAL(offset);
4293 }
4294 return ps_input_cntl;
4295 }
4296
4297 static void
4298 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4299 struct radv_pipeline *pipeline)
4300 {
4301 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4302 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4303 uint32_t ps_input_cntl[32];
4304
4305 unsigned ps_offset = 0;
4306
4307 if (ps->info.ps.prim_id_input) {
4308 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4309 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4310 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4311 ++ps_offset;
4312 }
4313 }
4314
4315 if (ps->info.ps.layer_input ||
4316 ps->info.needs_multiview_view_index) {
4317 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4318 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4319 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4320 else
4321 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4322 ++ps_offset;
4323 }
4324
4325 if (ps->info.ps.viewport_index_input) {
4326 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4327 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4328 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4329 else
4330 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4331 ++ps_offset;
4332 }
4333
4334 if (ps->info.ps.has_pcoord) {
4335 unsigned val;
4336 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4337 ps_input_cntl[ps_offset] = val;
4338 ps_offset++;
4339 }
4340
4341 if (ps->info.ps.num_input_clips_culls) {
4342 unsigned vs_offset;
4343
4344 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4345 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4346 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4347 ++ps_offset;
4348 }
4349
4350 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4351 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4352 ps->info.ps.num_input_clips_culls > 4) {
4353 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4354 ++ps_offset;
4355 }
4356 }
4357
4358 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4359 unsigned vs_offset;
4360 bool flat_shade;
4361 bool explicit;
4362 bool float16;
4363 if (!(ps->info.ps.input_mask & (1u << i)))
4364 continue;
4365
4366 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4367 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4368 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4369 ++ps_offset;
4370 continue;
4371 }
4372
4373 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4374 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4375 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4376
4377 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4378 ++ps_offset;
4379 }
4380
4381 if (ps_offset) {
4382 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4383 for (unsigned i = 0; i < ps_offset; i++) {
4384 radeon_emit(ctx_cs, ps_input_cntl[i]);
4385 }
4386 }
4387 }
4388
4389 static uint32_t
4390 radv_compute_db_shader_control(const struct radv_device *device,
4391 const struct radv_pipeline *pipeline,
4392 const struct radv_shader_variant *ps)
4393 {
4394 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4395 unsigned z_order;
4396 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4397 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4398 else
4399 z_order = V_02880C_LATE_Z;
4400
4401 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4402 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4403 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4404 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4405
4406 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4407 !device->physical_device->rad_info.rbplus_allowed;
4408
4409 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4410 * but this appears to break Project Cars (DXVK). See
4411 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4412 */
4413 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4414
4415 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4416 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4417 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4418 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4419 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4420 S_02880C_Z_ORDER(z_order) |
4421 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4422 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4423 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4424 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4425 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4426 }
4427
4428 static void
4429 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4430 struct radeon_cmdbuf *cs,
4431 struct radv_pipeline *pipeline)
4432 {
4433 struct radv_shader_variant *ps;
4434 uint64_t va;
4435 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4436
4437 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4438 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4439
4440 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4441 radeon_emit(cs, va >> 8);
4442 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4443 radeon_emit(cs, ps->config.rsrc1);
4444 radeon_emit(cs, ps->config.rsrc2);
4445
4446 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4447 radv_compute_db_shader_control(pipeline->device,
4448 pipeline, ps));
4449
4450 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4451 ps->config.spi_ps_input_ena);
4452
4453 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4454 ps->config.spi_ps_input_addr);
4455
4456 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4457 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4458 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4459
4460 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4461
4462 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4463 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4464 ps->info.ps.writes_stencil,
4465 ps->info.ps.writes_sample_mask));
4466
4467 if (pipeline->device->dfsm_allowed) {
4468 /* optimise this? */
4469 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4470 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4471 }
4472 }
4473
4474 static void
4475 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4476 struct radv_pipeline *pipeline)
4477 {
4478 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4479 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4480 return;
4481
4482 unsigned vtx_reuse_depth = 30;
4483 if (radv_pipeline_has_tess(pipeline) &&
4484 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4485 vtx_reuse_depth = 14;
4486 }
4487 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4488 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4489 }
4490
4491 static uint32_t
4492 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4493 {
4494 uint32_t stages = 0;
4495 if (radv_pipeline_has_tess(pipeline)) {
4496 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4497 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4498
4499 if (radv_pipeline_has_gs(pipeline))
4500 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4501 S_028B54_GS_EN(1);
4502 else if (radv_pipeline_has_ngg(pipeline))
4503 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4504 else
4505 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4506 } else if (radv_pipeline_has_gs(pipeline)) {
4507 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4508 S_028B54_GS_EN(1);
4509 } else if (radv_pipeline_has_ngg(pipeline)) {
4510 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4511 }
4512
4513 if (radv_pipeline_has_ngg(pipeline)) {
4514 stages |= S_028B54_PRIMGEN_EN(1);
4515 if (pipeline->streamout_shader)
4516 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4517 if (radv_pipeline_has_ngg_passthrough(pipeline))
4518 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4519 } else if (radv_pipeline_has_gs(pipeline)) {
4520 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4521 }
4522
4523 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4524 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4525
4526 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4527 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4528
4529 if (radv_pipeline_has_tess(pipeline))
4530 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4531
4532 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4533 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4534 if (pipeline->gs_copy_shader)
4535 vs_size = pipeline->gs_copy_shader->info.wave_size;
4536 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4537 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4538 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4539 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4540
4541 if (radv_pipeline_has_ngg(pipeline))
4542 gs_size = vs_size;
4543
4544 /* legacy GS only supports Wave64 */
4545 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4546 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4547 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4548 }
4549
4550 return stages;
4551 }
4552
4553 static uint32_t
4554 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4555 {
4556 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4557 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4558
4559 if (!discard_rectangle_info)
4560 return 0xffff;
4561
4562 unsigned mask = 0;
4563
4564 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4565 /* Interpret i as a bitmask, and then set the bit in the mask if
4566 * that combination of rectangles in which the pixel is contained
4567 * should pass the cliprect test. */
4568 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4569
4570 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4571 !relevant_subset)
4572 continue;
4573
4574 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4575 relevant_subset)
4576 continue;
4577
4578 mask |= 1u << i;
4579 }
4580
4581 return mask;
4582 }
4583
4584 static void
4585 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4586 struct radv_pipeline *pipeline,
4587 const struct radv_tessellation_state *tess)
4588 {
4589 bool break_wave_at_eoi = false;
4590 unsigned primgroup_size;
4591 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4592
4593 if (radv_pipeline_has_tess(pipeline)) {
4594 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4595 } else if (radv_pipeline_has_gs(pipeline)) {
4596 const struct gfx9_gs_info *gs_state =
4597 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4598 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4599 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4600 } else {
4601 primgroup_size = 128; /* recommended without a GS and tess */
4602 }
4603
4604 if (radv_pipeline_has_tess(pipeline)) {
4605 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4606 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4607 break_wave_at_eoi = true;
4608 }
4609
4610 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4611 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4612 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4613 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4614 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4615 }
4616
4617 static void
4618 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4619 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4620 const struct radv_graphics_pipeline_create_info *extra,
4621 const struct radv_blend_state *blend,
4622 const struct radv_tessellation_state *tess,
4623 unsigned prim, unsigned gs_out)
4624 {
4625 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4626 struct radeon_cmdbuf *cs = &pipeline->cs;
4627
4628 cs->max_dw = 64;
4629 ctx_cs->max_dw = 256;
4630 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4631 ctx_cs->buf = cs->buf + cs->max_dw;
4632
4633 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4634 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4635 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4636 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4637 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4638 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4639 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4640 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4641 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4642 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4643 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4644 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4645
4646 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4647 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4648
4649 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4650
4651 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4652 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4653 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4654 } else {
4655 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4656 }
4657 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4658
4659 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4660
4661 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4662
4663 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4664 assert(cs->cdw <= cs->max_dw);
4665 }
4666
4667 static struct radv_ia_multi_vgt_param_helpers
4668 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4669 const struct radv_tessellation_state *tess,
4670 uint32_t prim)
4671 {
4672 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4673 const struct radv_device *device = pipeline->device;
4674
4675 if (radv_pipeline_has_tess(pipeline))
4676 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4677 else if (radv_pipeline_has_gs(pipeline))
4678 ia_multi_vgt_param.primgroup_size = 64;
4679 else
4680 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4681
4682 /* GS requirement. */
4683 ia_multi_vgt_param.partial_es_wave = false;
4684 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4685 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4686 ia_multi_vgt_param.partial_es_wave = true;
4687
4688 ia_multi_vgt_param.wd_switch_on_eop = false;
4689 if (device->physical_device->rad_info.chip_class >= GFX7) {
4690 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4691 * 4 shader engines. Set 1 to pass the assertion below.
4692 * The other cases are hardware requirements. */
4693 if (device->physical_device->rad_info.max_se < 4 ||
4694 prim == V_008958_DI_PT_POLYGON ||
4695 prim == V_008958_DI_PT_LINELOOP ||
4696 prim == V_008958_DI_PT_TRIFAN ||
4697 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4698 (pipeline->graphics.prim_restart_enable &&
4699 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4700 (prim != V_008958_DI_PT_POINTLIST &&
4701 prim != V_008958_DI_PT_LINESTRIP))))
4702 ia_multi_vgt_param.wd_switch_on_eop = true;
4703 }
4704
4705 ia_multi_vgt_param.ia_switch_on_eoi = false;
4706 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4707 ia_multi_vgt_param.ia_switch_on_eoi = true;
4708 if (radv_pipeline_has_gs(pipeline) &&
4709 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4710 ia_multi_vgt_param.ia_switch_on_eoi = true;
4711 if (radv_pipeline_has_tess(pipeline)) {
4712 /* SWITCH_ON_EOI must be set if PrimID is used. */
4713 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4714 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4715 ia_multi_vgt_param.ia_switch_on_eoi = true;
4716 }
4717
4718 ia_multi_vgt_param.partial_vs_wave = false;
4719 if (radv_pipeline_has_tess(pipeline)) {
4720 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4721 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4722 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4723 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4724 radv_pipeline_has_gs(pipeline))
4725 ia_multi_vgt_param.partial_vs_wave = true;
4726 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4727 if (device->physical_device->rad_info.has_distributed_tess) {
4728 if (radv_pipeline_has_gs(pipeline)) {
4729 if (device->physical_device->rad_info.chip_class <= GFX8)
4730 ia_multi_vgt_param.partial_es_wave = true;
4731 } else {
4732 ia_multi_vgt_param.partial_vs_wave = true;
4733 }
4734 }
4735 }
4736
4737 /* Workaround for a VGT hang when strip primitive types are used with
4738 * primitive restart.
4739 */
4740 if (pipeline->graphics.prim_restart_enable &&
4741 (prim == V_008958_DI_PT_LINESTRIP ||
4742 prim == V_008958_DI_PT_TRISTRIP ||
4743 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4744 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4745 ia_multi_vgt_param.partial_vs_wave = true;
4746 }
4747
4748 if (radv_pipeline_has_gs(pipeline)) {
4749 /* On these chips there is the possibility of a hang if the
4750 * pipeline uses a GS and partial_vs_wave is not set.
4751 *
4752 * This mostly does not hit 4-SE chips, as those typically set
4753 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4754 * with GS due to another workaround.
4755 *
4756 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4757 */
4758 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4759 device->physical_device->rad_info.family == CHIP_FIJI ||
4760 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4761 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4762 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4763 device->physical_device->rad_info.family == CHIP_VEGAM) {
4764 ia_multi_vgt_param.partial_vs_wave = true;
4765 }
4766 }
4767
4768 ia_multi_vgt_param.base =
4769 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4770 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4771 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4772 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4773 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4774
4775 return ia_multi_vgt_param;
4776 }
4777
4778
4779 static void
4780 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4781 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4782 {
4783 const VkPipelineVertexInputStateCreateInfo *vi_info =
4784 pCreateInfo->pVertexInputState;
4785 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4786
4787 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4788 const VkVertexInputAttributeDescription *desc =
4789 &vi_info->pVertexAttributeDescriptions[i];
4790 unsigned loc = desc->location;
4791 const struct vk_format_description *format_desc;
4792
4793 format_desc = vk_format_description(desc->format);
4794
4795 velems->format_size[loc] = format_desc->block.bits / 8;
4796 }
4797
4798 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4799 const VkVertexInputBindingDescription *desc =
4800 &vi_info->pVertexBindingDescriptions[i];
4801
4802 pipeline->binding_stride[desc->binding] = desc->stride;
4803 pipeline->num_vertex_bindings =
4804 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4805 }
4806 }
4807
4808 static struct radv_shader_variant *
4809 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4810 {
4811 int i;
4812
4813 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4814 struct radv_shader_variant *shader =
4815 radv_get_shader(pipeline, i);
4816
4817 if (shader && shader->info.so.num_outputs > 0)
4818 return shader;
4819 }
4820
4821 return NULL;
4822 }
4823
4824 static VkResult
4825 radv_secure_compile(struct radv_pipeline *pipeline,
4826 struct radv_device *device,
4827 const struct radv_pipeline_key *key,
4828 const VkPipelineShaderStageCreateInfo **pStages,
4829 const VkPipelineCreateFlags flags,
4830 unsigned num_stages)
4831 {
4832 uint8_t allowed_pipeline_hashes[2][20];
4833 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4834 pipeline->layout, key, get_hash_flags(device));
4835
4836 /* Generate the GC copy hash */
4837 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4838 allowed_pipeline_hashes[1][0] ^= 1;
4839
4840 uint8_t allowed_hashes[2][20];
4841 for (unsigned i = 0; i < 2; ++i) {
4842 disk_cache_compute_key(device->physical_device->disk_cache,
4843 allowed_pipeline_hashes[i], 20,
4844 allowed_hashes[i]);
4845 }
4846
4847 /* Do an early exit if all cache entries are already there. */
4848 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4849 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4850 void *copy_entry = NULL;
4851 if (may_need_copy_shader)
4852 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4853
4854 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4855 free(main_entry);
4856 free(copy_entry);
4857
4858 if(has_all_cache_entries)
4859 return VK_SUCCESS;
4860
4861 unsigned process = 0;
4862 uint8_t sc_threads = device->instance->num_sc_threads;
4863 while (true) {
4864 mtx_lock(&device->sc_state->secure_compile_mutex);
4865 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4866 device->sc_state->secure_compile_thread_counter++;
4867 for (unsigned i = 0; i < sc_threads; i++) {
4868 if (!device->sc_state->secure_compile_processes[i].in_use) {
4869 device->sc_state->secure_compile_processes[i].in_use = true;
4870 process = i;
4871 break;
4872 }
4873 }
4874 mtx_unlock(&device->sc_state->secure_compile_mutex);
4875 break;
4876 }
4877 mtx_unlock(&device->sc_state->secure_compile_mutex);
4878 }
4879
4880 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4881 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4882
4883 /* Fork a copy of the slim untainted secure compile process */
4884 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4885 write(fd_secure_input, &sc_type, sizeof(sc_type));
4886
4887 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4888 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4889 return VK_ERROR_DEVICE_LOST;
4890
4891 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4892 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4893
4894 /* Write pipeline / shader module out to secure process via pipe */
4895 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4896 write(fd_secure_input, &sc_type, sizeof(sc_type));
4897
4898 /* Write pipeline layout out to secure process */
4899 struct radv_pipeline_layout *layout = pipeline->layout;
4900 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4901 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4902 for (uint32_t set = 0; set < layout->num_sets; set++) {
4903 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4904 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4905 }
4906
4907 /* Write pipeline key out to secure process */
4908 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4909
4910 /* Write pipeline create flags out to secure process */
4911 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4912
4913 /* Write stage and shader information out to secure process */
4914 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4915 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4916 if (!pStages[i])
4917 continue;
4918
4919 /* Write stage out to secure process */
4920 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4921 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4922
4923 /* Write entry point name out to secure process */
4924 size_t name_size = strlen(pStages[i]->pName) + 1;
4925 write(fd_secure_input, &name_size, sizeof(size_t));
4926 write(fd_secure_input, pStages[i]->pName, name_size);
4927
4928 /* Write shader module out to secure process */
4929 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4930 assert(!module->nir);
4931 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4932 write(fd_secure_input, &module_size, sizeof(size_t));
4933 write(fd_secure_input, module, module_size);
4934
4935 /* Write specialization info out to secure process */
4936 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4937 bool has_spec_info = specInfo ? true : false;
4938 write(fd_secure_input, &has_spec_info, sizeof(bool));
4939 if (specInfo) {
4940 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4941 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4942
4943 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4944 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4945 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4946 }
4947 }
4948
4949 /* Read the data returned from the secure process */
4950 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4951 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4952 return VK_ERROR_DEVICE_LOST;
4953
4954 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4955 assert(device->physical_device->disk_cache);
4956
4957 uint8_t disk_sha1[20];
4958 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4959 return VK_ERROR_DEVICE_LOST;
4960
4961 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4962 memcmp(disk_sha1, allowed_hashes[1], 20))
4963 return VK_ERROR_DEVICE_LOST;
4964
4965 uint32_t entry_size;
4966 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4967 return VK_ERROR_DEVICE_LOST;
4968
4969 struct cache_entry *entry = malloc(entry_size);
4970 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4971 return VK_ERROR_DEVICE_LOST;
4972
4973 disk_cache_put(device->physical_device->disk_cache,
4974 disk_sha1, entry, entry_size,
4975 NULL);
4976
4977 free(entry);
4978 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4979 uint8_t disk_sha1[20];
4980 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4981 return VK_ERROR_DEVICE_LOST;
4982
4983 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4984 memcmp(disk_sha1, allowed_hashes[1], 20))
4985 return VK_ERROR_DEVICE_LOST;
4986
4987 size_t size;
4988 struct cache_entry *entry = (struct cache_entry *)
4989 disk_cache_get(device->physical_device->disk_cache,
4990 disk_sha1, &size);
4991
4992 uint8_t found = entry ? 1 : 0;
4993 write(fd_secure_input, &found, sizeof(uint8_t));
4994
4995 if (found) {
4996 write(fd_secure_input, &size, sizeof(size_t));
4997 write(fd_secure_input, entry, size);
4998 }
4999
5000 free(entry);
5001 }
5002 }
5003
5004 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
5005 write(fd_secure_input, &sc_type, sizeof(sc_type));
5006
5007 mtx_lock(&device->sc_state->secure_compile_mutex);
5008 device->sc_state->secure_compile_thread_counter--;
5009 device->sc_state->secure_compile_processes[process].in_use = false;
5010 mtx_unlock(&device->sc_state->secure_compile_mutex);
5011
5012 return VK_SUCCESS;
5013 }
5014
5015 static VkResult
5016 radv_pipeline_init(struct radv_pipeline *pipeline,
5017 struct radv_device *device,
5018 struct radv_pipeline_cache *cache,
5019 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5020 const struct radv_graphics_pipeline_create_info *extra)
5021 {
5022 VkResult result;
5023 bool has_view_index = false;
5024
5025 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
5026 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
5027 if (subpass->view_mask)
5028 has_view_index = true;
5029
5030 pipeline->device = device;
5031 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5032 assert(pipeline->layout);
5033
5034 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
5035
5036 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5037 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5038 radv_init_feedback(creation_feedback);
5039
5040 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5041
5042 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5043 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5044 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
5045 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
5046 pStages[stage] = &pCreateInfo->pStages[i];
5047 if(creation_feedback)
5048 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5049 }
5050
5051 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5052 if (radv_device_use_secure_compile(device->instance)) {
5053 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5054 } else {
5055 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5056 pCreateInfo->flags, pipeline_feedback,
5057 stage_feedbacks);
5058 if (result != VK_SUCCESS)
5059 return result;
5060 }
5061
5062 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5063 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5064 uint32_t gs_out;
5065 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5066
5067 pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
5068 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5069
5070 if (radv_pipeline_has_gs(pipeline)) {
5071 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5072 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5073 } else if (radv_pipeline_has_tess(pipeline)) {
5074 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5075 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5076 else
5077 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5078 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5079 } else {
5080 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5081 }
5082 if (extra && extra->use_rectlist) {
5083 prim = V_008958_DI_PT_RECTLIST;
5084 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5085 pipeline->graphics.can_use_guardband = true;
5086 if (radv_pipeline_has_ngg(pipeline))
5087 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5088 }
5089 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5090 /* prim vertex count will need TESS changes */
5091 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5092
5093 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5094
5095 /* Ensure that some export memory is always allocated, for two reasons:
5096 *
5097 * 1) Correctness: The hardware ignores the EXEC mask if no export
5098 * memory is allocated, so KILL and alpha test do not work correctly
5099 * without this.
5100 * 2) Performance: Every shader needs at least a NULL export, even when
5101 * it writes no color/depth output. The NULL export instruction
5102 * stalls without this setting.
5103 *
5104 * Don't add this to CB_SHADER_MASK.
5105 *
5106 * GFX10 supports pixel shaders without exports by setting both the
5107 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5108 * instructions if any are present.
5109 */
5110 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5111 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5112 ps->info.ps.can_discard) &&
5113 !blend.spi_shader_col_format) {
5114 if (!ps->info.ps.writes_z &&
5115 !ps->info.ps.writes_stencil &&
5116 !ps->info.ps.writes_sample_mask)
5117 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5118 }
5119
5120 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
5121
5122 if (extra &&
5123 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
5124 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
5125 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
5126 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
5127 /* According to the CB spec states, CB_SHADER_MASK should be
5128 * set to enable writes to all four channels of MRT0.
5129 */
5130 blend.cb_shader_mask = 0xf;
5131 }
5132
5133 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5134 if (pipeline->shaders[i]) {
5135 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5136 }
5137 }
5138
5139 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5140 struct radv_shader_variant *gs =
5141 pipeline->shaders[MESA_SHADER_GEOMETRY];
5142
5143 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5144 }
5145
5146 struct radv_tessellation_state tess = {0};
5147 if (radv_pipeline_has_tess(pipeline)) {
5148 if (prim == V_008958_DI_PT_PATCH) {
5149 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5150 pipeline->graphics.prim_vertex_count.incr = 1;
5151 }
5152 tess = calculate_tess_state(pipeline, pCreateInfo);
5153 }
5154
5155 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5156
5157 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5158
5159 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5160 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5161
5162 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5163 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5164 if (loc->sgpr_idx != -1) {
5165 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5166 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5167 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5168 pipeline->graphics.vtx_emit_num = 3;
5169 else
5170 pipeline->graphics.vtx_emit_num = 2;
5171 }
5172
5173 /* Find the last vertex shader stage that eventually uses streamout. */
5174 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5175
5176 result = radv_pipeline_scratch_init(device, pipeline);
5177 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5178
5179 return result;
5180 }
5181
5182 VkResult
5183 radv_graphics_pipeline_create(
5184 VkDevice _device,
5185 VkPipelineCache _cache,
5186 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5187 const struct radv_graphics_pipeline_create_info *extra,
5188 const VkAllocationCallbacks *pAllocator,
5189 VkPipeline *pPipeline)
5190 {
5191 RADV_FROM_HANDLE(radv_device, device, _device);
5192 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5193 struct radv_pipeline *pipeline;
5194 VkResult result;
5195
5196 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5197 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5198 if (pipeline == NULL)
5199 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5200
5201 vk_object_base_init(&device->vk, &pipeline->base,
5202 VK_OBJECT_TYPE_PIPELINE);
5203
5204 result = radv_pipeline_init(pipeline, device, cache,
5205 pCreateInfo, extra);
5206 if (result != VK_SUCCESS) {
5207 radv_pipeline_destroy(device, pipeline, pAllocator);
5208 return result;
5209 }
5210
5211 *pPipeline = radv_pipeline_to_handle(pipeline);
5212
5213 return VK_SUCCESS;
5214 }
5215
5216 VkResult radv_CreateGraphicsPipelines(
5217 VkDevice _device,
5218 VkPipelineCache pipelineCache,
5219 uint32_t count,
5220 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5221 const VkAllocationCallbacks* pAllocator,
5222 VkPipeline* pPipelines)
5223 {
5224 VkResult result = VK_SUCCESS;
5225 unsigned i = 0;
5226
5227 for (; i < count; i++) {
5228 VkResult r;
5229 r = radv_graphics_pipeline_create(_device,
5230 pipelineCache,
5231 &pCreateInfos[i],
5232 NULL, pAllocator, &pPipelines[i]);
5233 if (r != VK_SUCCESS) {
5234 result = r;
5235 pPipelines[i] = VK_NULL_HANDLE;
5236
5237 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5238 break;
5239 }
5240 }
5241
5242 for (; i < count; ++i)
5243 pPipelines[i] = VK_NULL_HANDLE;
5244
5245 return result;
5246 }
5247
5248
5249 static void
5250 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5251 {
5252 struct radv_shader_variant *compute_shader;
5253 struct radv_device *device = pipeline->device;
5254 unsigned threads_per_threadgroup;
5255 unsigned threadgroups_per_cu = 1;
5256 unsigned waves_per_threadgroup;
5257 unsigned max_waves_per_sh = 0;
5258 uint64_t va;
5259
5260 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5261 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5262
5263 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5264 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5265
5266 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5267 radeon_emit(&pipeline->cs, va >> 8);
5268 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5269
5270 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5271 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5272 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5273 if (device->physical_device->rad_info.chip_class >= GFX10) {
5274 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5275 }
5276
5277 /* Calculate best compute resource limits. */
5278 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5279 compute_shader->info.cs.block_size[1] *
5280 compute_shader->info.cs.block_size[2];
5281 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5282 compute_shader->info.wave_size);
5283
5284 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5285 waves_per_threadgroup == 1)
5286 threadgroups_per_cu = 2;
5287
5288 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5289 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5290 waves_per_threadgroup,
5291 max_waves_per_sh,
5292 threadgroups_per_cu));
5293
5294 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5295 radeon_emit(&pipeline->cs,
5296 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5297 radeon_emit(&pipeline->cs,
5298 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5299 radeon_emit(&pipeline->cs,
5300 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5301
5302 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5303 }
5304
5305 static struct radv_pipeline_key
5306 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5307 const VkComputePipelineCreateInfo *pCreateInfo)
5308 {
5309 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5310 struct radv_pipeline_key key;
5311 memset(&key, 0, sizeof(key));
5312
5313 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5314 key.optimisations_disabled = 1;
5315
5316 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5317 vk_find_struct_const(stage->pNext,
5318 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5319
5320 if (subgroup_size) {
5321 assert(subgroup_size->requiredSubgroupSize == 32 ||
5322 subgroup_size->requiredSubgroupSize == 64);
5323 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5324 }
5325
5326 return key;
5327 }
5328
5329 static VkResult radv_compute_pipeline_create(
5330 VkDevice _device,
5331 VkPipelineCache _cache,
5332 const VkComputePipelineCreateInfo* pCreateInfo,
5333 const VkAllocationCallbacks* pAllocator,
5334 VkPipeline* pPipeline)
5335 {
5336 RADV_FROM_HANDLE(radv_device, device, _device);
5337 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5338 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5339 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5340 struct radv_pipeline *pipeline;
5341 VkResult result;
5342
5343 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5344 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5345 if (pipeline == NULL)
5346 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5347
5348 vk_object_base_init(&device->vk, &pipeline->base,
5349 VK_OBJECT_TYPE_PIPELINE);
5350
5351 pipeline->device = device;
5352 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5353 assert(pipeline->layout);
5354
5355 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5356 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5357 radv_init_feedback(creation_feedback);
5358
5359 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5360 if (creation_feedback)
5361 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5362
5363 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5364
5365 struct radv_pipeline_key key =
5366 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5367
5368 if (radv_device_use_secure_compile(device->instance)) {
5369 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5370 *pPipeline = radv_pipeline_to_handle(pipeline);
5371
5372 return result;
5373 } else {
5374 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5375 pCreateInfo->flags, pipeline_feedback,
5376 stage_feedbacks);
5377 if (result != VK_SUCCESS) {
5378 radv_pipeline_destroy(device, pipeline, pAllocator);
5379 return result;
5380 }
5381 }
5382
5383 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5384 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5385 result = radv_pipeline_scratch_init(device, pipeline);
5386 if (result != VK_SUCCESS) {
5387 radv_pipeline_destroy(device, pipeline, pAllocator);
5388 return result;
5389 }
5390
5391 radv_compute_generate_pm4(pipeline);
5392
5393 *pPipeline = radv_pipeline_to_handle(pipeline);
5394
5395 return VK_SUCCESS;
5396 }
5397
5398 VkResult radv_CreateComputePipelines(
5399 VkDevice _device,
5400 VkPipelineCache pipelineCache,
5401 uint32_t count,
5402 const VkComputePipelineCreateInfo* pCreateInfos,
5403 const VkAllocationCallbacks* pAllocator,
5404 VkPipeline* pPipelines)
5405 {
5406 VkResult result = VK_SUCCESS;
5407
5408 unsigned i = 0;
5409 for (; i < count; i++) {
5410 VkResult r;
5411 r = radv_compute_pipeline_create(_device, pipelineCache,
5412 &pCreateInfos[i],
5413 pAllocator, &pPipelines[i]);
5414 if (r != VK_SUCCESS) {
5415 result = r;
5416 pPipelines[i] = VK_NULL_HANDLE;
5417
5418 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5419 break;
5420 }
5421 }
5422
5423 for (; i < count; ++i)
5424 pPipelines[i] = VK_NULL_HANDLE;
5425
5426 return result;
5427 }
5428
5429
5430 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5431 {
5432 uint32_t ret = 0;
5433 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5434 if (!pipeline->shaders[i])
5435 continue;
5436
5437 if (i == MESA_SHADER_GEOMETRY &&
5438 !radv_pipeline_has_ngg(pipeline)) {
5439 ret += 2u;
5440 } else {
5441 ret += 1u;
5442 }
5443
5444 }
5445 return ret;
5446 }
5447
5448 static struct radv_shader_variant *
5449 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5450 {
5451 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5452 if (!pipeline->shaders[i])
5453 continue;
5454 if (!index) {
5455 *stage = i;
5456 return pipeline->shaders[i];
5457 }
5458
5459 --index;
5460
5461 if (i == MESA_SHADER_GEOMETRY &&
5462 !radv_pipeline_has_ngg(pipeline)) {
5463 if (!index) {
5464 *stage = i;
5465 return pipeline->gs_copy_shader;
5466 }
5467 --index;
5468 }
5469 }
5470
5471 *stage = -1;
5472 return NULL;
5473 }
5474
5475 /* Basically strlcpy (which does not exist on linux) specialized for
5476 * descriptions. */
5477 static void desc_copy(char *desc, const char *src) {
5478 int len = strlen(src);
5479 assert(len < VK_MAX_DESCRIPTION_SIZE);
5480 memcpy(desc, src, len);
5481 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5482 }
5483
5484 VkResult radv_GetPipelineExecutablePropertiesKHR(
5485 VkDevice _device,
5486 const VkPipelineInfoKHR* pPipelineInfo,
5487 uint32_t* pExecutableCount,
5488 VkPipelineExecutablePropertiesKHR* pProperties)
5489 {
5490 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5491 const uint32_t total_count = radv_get_executable_count(pipeline);
5492
5493 if (!pProperties) {
5494 *pExecutableCount = total_count;
5495 return VK_SUCCESS;
5496 }
5497
5498 const uint32_t count = MIN2(total_count, *pExecutableCount);
5499 for (unsigned i = 0, executable_idx = 0;
5500 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5501 if (!pipeline->shaders[i])
5502 continue;
5503 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5504 const char *name = NULL;
5505 const char *description = NULL;
5506 switch(i) {
5507 case MESA_SHADER_VERTEX:
5508 name = "Vertex Shader";
5509 description = "Vulkan Vertex Shader";
5510 break;
5511 case MESA_SHADER_TESS_CTRL:
5512 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5513 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5514 name = "Vertex + Tessellation Control Shaders";
5515 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5516 } else {
5517 name = "Tessellation Control Shader";
5518 description = "Vulkan Tessellation Control Shader";
5519 }
5520 break;
5521 case MESA_SHADER_TESS_EVAL:
5522 name = "Tessellation Evaluation Shader";
5523 description = "Vulkan Tessellation Evaluation Shader";
5524 break;
5525 case MESA_SHADER_GEOMETRY:
5526 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5527 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5528 name = "Tessellation Evaluation + Geometry Shaders";
5529 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5530 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5531 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5532 name = "Vertex + Geometry Shader";
5533 description = "Combined Vulkan Vertex and Geometry Shaders";
5534 } else {
5535 name = "Geometry Shader";
5536 description = "Vulkan Geometry Shader";
5537 }
5538 break;
5539 case MESA_SHADER_FRAGMENT:
5540 name = "Fragment Shader";
5541 description = "Vulkan Fragment Shader";
5542 break;
5543 case MESA_SHADER_COMPUTE:
5544 name = "Compute Shader";
5545 description = "Vulkan Compute Shader";
5546 break;
5547 }
5548
5549 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5550 desc_copy(pProperties[executable_idx].name, name);
5551 desc_copy(pProperties[executable_idx].description, description);
5552
5553 ++executable_idx;
5554 if (i == MESA_SHADER_GEOMETRY &&
5555 !radv_pipeline_has_ngg(pipeline)) {
5556 assert(pipeline->gs_copy_shader);
5557 if (executable_idx >= count)
5558 break;
5559
5560 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5561 pProperties[executable_idx].subgroupSize = 64;
5562 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5563 desc_copy(pProperties[executable_idx].description,
5564 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5565
5566 ++executable_idx;
5567 }
5568 }
5569
5570 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5571 *pExecutableCount = count;
5572 return result;
5573 }
5574
5575 VkResult radv_GetPipelineExecutableStatisticsKHR(
5576 VkDevice _device,
5577 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5578 uint32_t* pStatisticCount,
5579 VkPipelineExecutableStatisticKHR* pStatistics)
5580 {
5581 RADV_FROM_HANDLE(radv_device, device, _device);
5582 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5583 gl_shader_stage stage;
5584 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5585
5586 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5587 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5588 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5589
5590 VkPipelineExecutableStatisticKHR *s = pStatistics;
5591 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5592 VkResult result = VK_SUCCESS;
5593
5594 if (s < end) {
5595 desc_copy(s->name, "SGPRs");
5596 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5597 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5598 s->value.u64 = shader->config.num_sgprs;
5599 }
5600 ++s;
5601
5602 if (s < end) {
5603 desc_copy(s->name, "VGPRs");
5604 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5605 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5606 s->value.u64 = shader->config.num_vgprs;
5607 }
5608 ++s;
5609
5610 if (s < end) {
5611 desc_copy(s->name, "Spilled SGPRs");
5612 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5613 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5614 s->value.u64 = shader->config.spilled_sgprs;
5615 }
5616 ++s;
5617
5618 if (s < end) {
5619 desc_copy(s->name, "Spilled VGPRs");
5620 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5621 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5622 s->value.u64 = shader->config.spilled_vgprs;
5623 }
5624 ++s;
5625
5626 if (s < end) {
5627 desc_copy(s->name, "PrivMem VGPRs");
5628 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5629 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5630 s->value.u64 = shader->info.private_mem_vgprs;
5631 }
5632 ++s;
5633
5634 if (s < end) {
5635 desc_copy(s->name, "Code size");
5636 desc_copy(s->description, "Code size in bytes");
5637 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5638 s->value.u64 = shader->exec_size;
5639 }
5640 ++s;
5641
5642 if (s < end) {
5643 desc_copy(s->name, "LDS size");
5644 desc_copy(s->description, "LDS size in bytes per workgroup");
5645 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5646 s->value.u64 = shader->config.lds_size * lds_increment;
5647 }
5648 ++s;
5649
5650 if (s < end) {
5651 desc_copy(s->name, "Scratch size");
5652 desc_copy(s->description, "Private memory in bytes per subgroup");
5653 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5654 s->value.u64 = shader->config.scratch_bytes_per_wave;
5655 }
5656 ++s;
5657
5658 if (s < end) {
5659 desc_copy(s->name, "Subgroups per SIMD");
5660 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5661 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5662 s->value.u64 = max_waves;
5663 }
5664 ++s;
5665
5666 if (shader->statistics) {
5667 for (unsigned i = 0; i < shader->statistics->count; i++) {
5668 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5669 uint32_t value = shader->statistics->values[i];
5670 if (s < end) {
5671 desc_copy(s->name, info->name);
5672 desc_copy(s->description, info->desc);
5673 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5674 s->value.u64 = value;
5675 }
5676 ++s;
5677 }
5678 }
5679
5680 if (!pStatistics)
5681 *pStatisticCount = s - pStatistics;
5682 else if (s > end) {
5683 *pStatisticCount = end - pStatistics;
5684 result = VK_INCOMPLETE;
5685 } else {
5686 *pStatisticCount = s - pStatistics;
5687 }
5688
5689 return result;
5690 }
5691
5692 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5693 {
5694 size_t total_size = strlen(src) + 1;
5695
5696 if (!data) {
5697 *data_size = total_size;
5698 return VK_SUCCESS;
5699 }
5700
5701 size_t size = MIN2(total_size, *data_size);
5702
5703 memcpy(data, src, size);
5704 if (size)
5705 *((char*)data + size - 1) = 0;
5706 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5707 }
5708
5709 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5710 VkDevice device,
5711 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5712 uint32_t* pInternalRepresentationCount,
5713 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5714 {
5715 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5716 gl_shader_stage stage;
5717 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5718
5719 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5720 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5721 VkResult result = VK_SUCCESS;
5722 /* optimized NIR */
5723 if (p < end) {
5724 p->isText = true;
5725 desc_copy(p->name, "NIR Shader(s)");
5726 desc_copy(p->description, "The optimized NIR shader(s)");
5727 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5728 result = VK_INCOMPLETE;
5729 }
5730 ++p;
5731
5732 /* backend IR */
5733 if (p < end) {
5734 p->isText = true;
5735 if (pipeline->device->physical_device->use_llvm) {
5736 desc_copy(p->name, "LLVM IR");
5737 desc_copy(p->description, "The LLVM IR after some optimizations");
5738 } else {
5739 desc_copy(p->name, "ACO IR");
5740 desc_copy(p->description, "The ACO IR after some optimizations");
5741 }
5742 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5743 result = VK_INCOMPLETE;
5744 }
5745 ++p;
5746
5747 /* Disassembler */
5748 if (p < end) {
5749 p->isText = true;
5750 desc_copy(p->name, "Assembly");
5751 desc_copy(p->description, "Final Assembly");
5752 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5753 result = VK_INCOMPLETE;
5754 }
5755 ++p;
5756
5757 if (!pInternalRepresentations)
5758 *pInternalRepresentationCount = p - pInternalRepresentations;
5759 else if(p > end) {
5760 result = VK_INCOMPLETE;
5761 *pInternalRepresentationCount = end - pInternalRepresentations;
5762 } else {
5763 *pInternalRepresentationCount = p - pInternalRepresentations;
5764 }
5765
5766 return result;
5767 }