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radv: remove useless return value to radv_pipeline_scratch_init()
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 static const VkPipelineMultisampleStateCreateInfo *
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
87 {
88 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
89 return pCreateInfo->pMultisampleState;
90 return NULL;
91 }
92
93 static const VkPipelineTessellationStateCreateInfo *
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
95 {
96 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
97 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
98 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
99 return pCreateInfo->pTessellationState;
100 }
101 }
102 return NULL;
103 }
104
105 static const VkPipelineDepthStencilStateCreateInfo *
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
107 {
108 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
109 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
110
111 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
112 subpass->depth_stencil_attachment)
113 return pCreateInfo->pDepthStencilState;
114 return NULL;
115 }
116
117 static const VkPipelineColorBlendStateCreateInfo *
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
119 {
120 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
121 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
122
123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
124 subpass->has_color_att)
125 return pCreateInfo->pColorBlendState;
126 return NULL;
127 }
128
129 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
130 {
131 struct radv_shader_variant *variant = NULL;
132 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
133 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
134 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
135 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
136 else if (pipeline->shaders[MESA_SHADER_VERTEX])
137 variant = pipeline->shaders[MESA_SHADER_VERTEX];
138 else
139 return false;
140 return variant->info.is_ngg;
141 }
142
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
144 {
145 assert(radv_pipeline_has_ngg(pipeline));
146
147 struct radv_shader_variant *variant = NULL;
148 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
149 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
150 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
151 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
152 else if (pipeline->shaders[MESA_SHADER_VERTEX])
153 variant = pipeline->shaders[MESA_SHADER_VERTEX];
154 else
155 return false;
156 return variant->info.is_ngg_passthrough;
157 }
158
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
160 {
161 if (!radv_pipeline_has_gs(pipeline))
162 return false;
163
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
166 * enable NGG.
167 */
168 if (radv_pipeline_has_ngg(pipeline))
169 return false;
170
171 assert(pipeline->gs_copy_shader);
172 return true;
173 }
174
175 static void
176 radv_pipeline_destroy(struct radv_device *device,
177 struct radv_pipeline *pipeline,
178 const VkAllocationCallbacks* allocator)
179 {
180 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
181 if (pipeline->shaders[i])
182 radv_shader_variant_destroy(device, pipeline->shaders[i]);
183
184 if (pipeline->gs_copy_shader)
185 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
186
187 if(pipeline->cs.buf)
188 free(pipeline->cs.buf);
189
190 vk_object_base_finish(&pipeline->base);
191 vk_free2(&device->vk.alloc, allocator, pipeline);
192 }
193
194 void radv_DestroyPipeline(
195 VkDevice _device,
196 VkPipeline _pipeline,
197 const VkAllocationCallbacks* pAllocator)
198 {
199 RADV_FROM_HANDLE(radv_device, device, _device);
200 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
201
202 if (!_pipeline)
203 return;
204
205 radv_pipeline_destroy(device, pipeline, pAllocator);
206 }
207
208 static uint32_t get_hash_flags(struct radv_device *device)
209 {
210 uint32_t hash_flags = 0;
211
212 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
213 hash_flags |= RADV_HASH_SHADER_NO_NGG;
214 if (device->physical_device->cs_wave_size == 32)
215 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
216 if (device->physical_device->ps_wave_size == 32)
217 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
218 if (device->physical_device->ge_wave_size == 32)
219 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
220 if (device->physical_device->use_llvm)
221 hash_flags |= RADV_HASH_SHADER_LLVM;
222 return hash_flags;
223 }
224
225 static void
226 radv_pipeline_scratch_init(struct radv_device *device,
227 struct radv_pipeline *pipeline)
228 {
229 unsigned scratch_bytes_per_wave = 0;
230 unsigned max_waves = 0;
231 unsigned min_waves = 1;
232
233 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
234 if (pipeline->shaders[i] &&
235 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
236 unsigned max_stage_waves = device->scratch_waves;
237
238 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
239 pipeline->shaders[i]->config.scratch_bytes_per_wave);
240
241 max_stage_waves = MIN2(max_stage_waves,
242 4 * device->physical_device->rad_info.num_good_compute_units *
243 (256 / pipeline->shaders[i]->config.num_vgprs));
244 max_waves = MAX2(max_waves, max_stage_waves);
245 }
246 }
247
248 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
249 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
250 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
251 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
252 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
253 }
254
255 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
256 pipeline->max_waves = max_waves;
257 }
258
259 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
260 {
261 switch (op) {
262 case VK_LOGIC_OP_CLEAR:
263 return V_028808_ROP3_CLEAR;
264 case VK_LOGIC_OP_AND:
265 return V_028808_ROP3_AND;
266 case VK_LOGIC_OP_AND_REVERSE:
267 return V_028808_ROP3_AND_REVERSE;
268 case VK_LOGIC_OP_COPY:
269 return V_028808_ROP3_COPY;
270 case VK_LOGIC_OP_AND_INVERTED:
271 return V_028808_ROP3_AND_INVERTED;
272 case VK_LOGIC_OP_NO_OP:
273 return V_028808_ROP3_NO_OP;
274 case VK_LOGIC_OP_XOR:
275 return V_028808_ROP3_XOR;
276 case VK_LOGIC_OP_OR:
277 return V_028808_ROP3_OR;
278 case VK_LOGIC_OP_NOR:
279 return V_028808_ROP3_NOR;
280 case VK_LOGIC_OP_EQUIVALENT:
281 return V_028808_ROP3_EQUIVALENT;
282 case VK_LOGIC_OP_INVERT:
283 return V_028808_ROP3_INVERT;
284 case VK_LOGIC_OP_OR_REVERSE:
285 return V_028808_ROP3_OR_REVERSE;
286 case VK_LOGIC_OP_COPY_INVERTED:
287 return V_028808_ROP3_COPY_INVERTED;
288 case VK_LOGIC_OP_OR_INVERTED:
289 return V_028808_ROP3_OR_INVERTED;
290 case VK_LOGIC_OP_NAND:
291 return V_028808_ROP3_NAND;
292 case VK_LOGIC_OP_SET:
293 return V_028808_ROP3_SET;
294 default:
295 unreachable("Unhandled logic op");
296 }
297 }
298
299
300 static uint32_t si_translate_blend_function(VkBlendOp op)
301 {
302 switch (op) {
303 case VK_BLEND_OP_ADD:
304 return V_028780_COMB_DST_PLUS_SRC;
305 case VK_BLEND_OP_SUBTRACT:
306 return V_028780_COMB_SRC_MINUS_DST;
307 case VK_BLEND_OP_REVERSE_SUBTRACT:
308 return V_028780_COMB_DST_MINUS_SRC;
309 case VK_BLEND_OP_MIN:
310 return V_028780_COMB_MIN_DST_SRC;
311 case VK_BLEND_OP_MAX:
312 return V_028780_COMB_MAX_DST_SRC;
313 default:
314 return 0;
315 }
316 }
317
318 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
319 {
320 switch (factor) {
321 case VK_BLEND_FACTOR_ZERO:
322 return V_028780_BLEND_ZERO;
323 case VK_BLEND_FACTOR_ONE:
324 return V_028780_BLEND_ONE;
325 case VK_BLEND_FACTOR_SRC_COLOR:
326 return V_028780_BLEND_SRC_COLOR;
327 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
328 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
329 case VK_BLEND_FACTOR_DST_COLOR:
330 return V_028780_BLEND_DST_COLOR;
331 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case VK_BLEND_FACTOR_SRC_ALPHA:
334 return V_028780_BLEND_SRC_ALPHA;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
337 case VK_BLEND_FACTOR_DST_ALPHA:
338 return V_028780_BLEND_DST_ALPHA;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
340 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
341 case VK_BLEND_FACTOR_CONSTANT_COLOR:
342 return V_028780_BLEND_CONSTANT_COLOR;
343 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
344 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
345 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
346 return V_028780_BLEND_CONSTANT_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
349 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
350 return V_028780_BLEND_SRC_ALPHA_SATURATE;
351 case VK_BLEND_FACTOR_SRC1_COLOR:
352 return V_028780_BLEND_SRC1_COLOR;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
354 return V_028780_BLEND_INV_SRC1_COLOR;
355 case VK_BLEND_FACTOR_SRC1_ALPHA:
356 return V_028780_BLEND_SRC1_ALPHA;
357 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
358 return V_028780_BLEND_INV_SRC1_ALPHA;
359 default:
360 return 0;
361 }
362 }
363
364 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
365 {
366 switch (op) {
367 case VK_BLEND_OP_ADD:
368 return V_028760_OPT_COMB_ADD;
369 case VK_BLEND_OP_SUBTRACT:
370 return V_028760_OPT_COMB_SUBTRACT;
371 case VK_BLEND_OP_REVERSE_SUBTRACT:
372 return V_028760_OPT_COMB_REVSUBTRACT;
373 case VK_BLEND_OP_MIN:
374 return V_028760_OPT_COMB_MIN;
375 case VK_BLEND_OP_MAX:
376 return V_028760_OPT_COMB_MAX;
377 default:
378 return V_028760_OPT_COMB_BLEND_DISABLED;
379 }
380 }
381
382 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
383 {
384 switch (factor) {
385 case VK_BLEND_FACTOR_ZERO:
386 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
387 case VK_BLEND_FACTOR_ONE:
388 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
389 case VK_BLEND_FACTOR_SRC_COLOR:
390 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
391 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
392 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
393 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
394 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
395 case VK_BLEND_FACTOR_SRC_ALPHA:
396 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
398 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
399 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
400 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
401 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
402 default:
403 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
404 }
405 }
406
407 /**
408 * Get rid of DST in the blend factors by commuting the operands:
409 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
410 */
411 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
412 unsigned *dst_factor, unsigned expected_dst,
413 unsigned replacement_src)
414 {
415 if (*src_factor == expected_dst &&
416 *dst_factor == VK_BLEND_FACTOR_ZERO) {
417 *src_factor = VK_BLEND_FACTOR_ZERO;
418 *dst_factor = replacement_src;
419
420 /* Commuting the operands requires reversing subtractions. */
421 if (*func == VK_BLEND_OP_SUBTRACT)
422 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
423 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
424 *func = VK_BLEND_OP_SUBTRACT;
425 }
426 }
427
428 static bool si_blend_factor_uses_dst(unsigned factor)
429 {
430 return factor == VK_BLEND_FACTOR_DST_COLOR ||
431 factor == VK_BLEND_FACTOR_DST_ALPHA ||
432 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
433 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
434 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
435 }
436
437 static bool is_dual_src(VkBlendFactor factor)
438 {
439 switch (factor) {
440 case VK_BLEND_FACTOR_SRC1_COLOR:
441 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
442 case VK_BLEND_FACTOR_SRC1_ALPHA:
443 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
444 return true;
445 default:
446 return false;
447 }
448 }
449
450 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
451 bool blend_enable,
452 bool blend_need_alpha)
453 {
454 const struct vk_format_description *desc = vk_format_description(vk_format);
455 struct ac_spi_color_formats formats = {};
456 unsigned format, ntype, swap;
457
458 format = radv_translate_colorformat(vk_format);
459 ntype = radv_translate_color_numformat(vk_format, desc,
460 vk_format_get_first_non_void_channel(vk_format));
461 swap = radv_translate_colorswap(vk_format, false);
462
463 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
464
465 if (blend_enable && blend_need_alpha)
466 return formats.blend_alpha;
467 else if(blend_need_alpha)
468 return formats.alpha;
469 else if(blend_enable)
470 return formats.blend;
471 else
472 return formats.normal;
473 }
474
475 static bool
476 format_is_int8(VkFormat format)
477 {
478 const struct vk_format_description *desc = vk_format_description(format);
479 int channel = vk_format_get_first_non_void_channel(format);
480
481 return channel >= 0 && desc->channel[channel].pure_integer &&
482 desc->channel[channel].size == 8;
483 }
484
485 static bool
486 format_is_int10(VkFormat format)
487 {
488 const struct vk_format_description *desc = vk_format_description(format);
489
490 if (desc->nr_channels != 4)
491 return false;
492 for (unsigned i = 0; i < 4; i++) {
493 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
494 return true;
495 }
496 return false;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
513 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
514 cf = V_028714_SPI_SHADER_ZERO;
515 } else {
516 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
517 bool blend_enable =
518 blend->blend_enable_4bit & (0xfu << (i * 4));
519
520 cf = radv_choose_spi_color_format(attachment->format,
521 blend_enable,
522 blend->need_src_alpha & (1 << i));
523
524 if (format_is_int8(attachment->format))
525 is_int8 |= 1 << i;
526 if (format_is_int10(attachment->format))
527 is_int10 |= 1 << i;
528 }
529
530 col_format |= cf << (4 * i);
531 }
532
533 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
534 /* When a subpass doesn't have any color attachments, write the
535 * alpha channel of MRT0 when alpha coverage is enabled because
536 * the depth attachment needs it.
537 */
538 col_format |= V_028714_SPI_SHADER_32_AR;
539 }
540
541 /* If the i-th target format is set, all previous target formats must
542 * be non-zero to avoid hangs.
543 */
544 num_targets = (util_last_bit(col_format) + 3) / 4;
545 for (unsigned i = 0; i < num_targets; i++) {
546 if (!(col_format & (0xf << (i * 4)))) {
547 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
548 }
549 }
550
551 /* The output for dual source blending should have the same format as
552 * the first output.
553 */
554 if (blend->mrt0_is_dual_src)
555 col_format |= (col_format & 0xf) << 4;
556
557 blend->spi_shader_col_format = col_format;
558 blend->col_format_is_int8 = is_int8;
559 blend->col_format_is_int10 = is_int10;
560 }
561
562 /*
563 * Ordered so that for each i,
564 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
565 */
566 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
567 VK_FORMAT_R32_SFLOAT,
568 VK_FORMAT_R32G32_SFLOAT,
569 VK_FORMAT_R8G8B8A8_UNORM,
570 VK_FORMAT_R16G16B16A16_UNORM,
571 VK_FORMAT_R16G16B16A16_SNORM,
572 VK_FORMAT_R16G16B16A16_UINT,
573 VK_FORMAT_R16G16B16A16_SINT,
574 VK_FORMAT_R32G32B32A32_SFLOAT,
575 VK_FORMAT_R8G8B8A8_UINT,
576 VK_FORMAT_R8G8B8A8_SINT,
577 VK_FORMAT_A2R10G10B10_UINT_PACK32,
578 VK_FORMAT_A2R10G10B10_SINT_PACK32,
579 };
580
581 unsigned radv_format_meta_fs_key(VkFormat format)
582 {
583 unsigned col_format = radv_choose_spi_color_format(format, false, false);
584
585 assert(col_format != V_028714_SPI_SHADER_32_AR);
586 if (col_format >= V_028714_SPI_SHADER_32_AR)
587 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
588
589 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
590 bool is_int8 = format_is_int8(format);
591 bool is_int10 = format_is_int10(format);
592
593 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
594 }
595
596 static void
597 radv_blend_check_commutativity(struct radv_blend_state *blend,
598 VkBlendOp op, VkBlendFactor src,
599 VkBlendFactor dst, unsigned chanmask)
600 {
601 /* Src factor is allowed when it does not depend on Dst. */
602 static const uint32_t src_allowed =
603 (1u << VK_BLEND_FACTOR_ONE) |
604 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
605 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
607 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
609 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
610 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
611 (1u << VK_BLEND_FACTOR_ZERO) |
612 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
618
619 if (dst == VK_BLEND_FACTOR_ONE &&
620 (src_allowed & (1u << src))) {
621 /* Addition is commutative, but floating point addition isn't
622 * associative: subtle changes can be introduced via different
623 * rounding. Be conservative, only enable for min and max.
624 */
625 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
626 blend->commutative_4bit |= chanmask;
627 }
628 }
629
630 static struct radv_blend_state
631 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
632 const VkGraphicsPipelineCreateInfo *pCreateInfo,
633 const struct radv_graphics_pipeline_create_info *extra)
634 {
635 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
636 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
637 struct radv_blend_state blend = {0};
638 unsigned mode = V_028808_CB_NORMAL;
639 int i;
640
641 if (extra && extra->custom_blend_mode) {
642 blend.single_cb_enable = true;
643 mode = extra->custom_blend_mode;
644 }
645
646 blend.cb_color_control = 0;
647 if (vkblend) {
648 if (vkblend->logicOpEnable)
649 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
650 else
651 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
652 }
653
654 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
655 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
656 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
657 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
658 S_028B70_OFFSET_ROUND(1);
659
660 if (vkms && vkms->alphaToCoverageEnable) {
661 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
662 blend.need_src_alpha |= 0x1;
663 }
664
665 blend.cb_target_mask = 0;
666 if (vkblend) {
667 for (i = 0; i < vkblend->attachmentCount; i++) {
668 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
669 unsigned blend_cntl = 0;
670 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
671 VkBlendOp eqRGB = att->colorBlendOp;
672 VkBlendFactor srcRGB = att->srcColorBlendFactor;
673 VkBlendFactor dstRGB = att->dstColorBlendFactor;
674 VkBlendOp eqA = att->alphaBlendOp;
675 VkBlendFactor srcA = att->srcAlphaBlendFactor;
676 VkBlendFactor dstA = att->dstAlphaBlendFactor;
677
678 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
679
680 if (!att->colorWriteMask)
681 continue;
682
683 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
684 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
685 if (!att->blendEnable) {
686 blend.cb_blend_control[i] = blend_cntl;
687 continue;
688 }
689
690 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
691 if (i == 0)
692 blend.mrt0_is_dual_src = true;
693
694 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
695 srcRGB = VK_BLEND_FACTOR_ONE;
696 dstRGB = VK_BLEND_FACTOR_ONE;
697 }
698 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
699 srcA = VK_BLEND_FACTOR_ONE;
700 dstA = VK_BLEND_FACTOR_ONE;
701 }
702
703 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
704 0x7 << (4 * i));
705 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
706 0x8 << (4 * i));
707
708 /* Blending optimizations for RB+.
709 * These transformations don't change the behavior.
710 *
711 * First, get rid of DST in the blend factors:
712 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
713 */
714 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
715 VK_BLEND_FACTOR_DST_COLOR,
716 VK_BLEND_FACTOR_SRC_COLOR);
717
718 si_blend_remove_dst(&eqA, &srcA, &dstA,
719 VK_BLEND_FACTOR_DST_COLOR,
720 VK_BLEND_FACTOR_SRC_COLOR);
721
722 si_blend_remove_dst(&eqA, &srcA, &dstA,
723 VK_BLEND_FACTOR_DST_ALPHA,
724 VK_BLEND_FACTOR_SRC_ALPHA);
725
726 /* Look up the ideal settings from tables. */
727 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
728 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
729 srcA_opt = si_translate_blend_opt_factor(srcA, true);
730 dstA_opt = si_translate_blend_opt_factor(dstA, true);
731
732 /* Handle interdependencies. */
733 if (si_blend_factor_uses_dst(srcRGB))
734 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
735 if (si_blend_factor_uses_dst(srcA))
736 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
737
738 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
739 (dstRGB == VK_BLEND_FACTOR_ZERO ||
740 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
741 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
743
744 /* Set the final value. */
745 blend.sx_mrt_blend_opt[i] =
746 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
747 S_028760_COLOR_DST_OPT(dstRGB_opt) |
748 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
749 S_028760_ALPHA_SRC_OPT(srcA_opt) |
750 S_028760_ALPHA_DST_OPT(dstA_opt) |
751 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
752 blend_cntl |= S_028780_ENABLE(1);
753
754 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
755 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
756 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
757 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
758 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
759 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
760 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
761 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
762 }
763 blend.cb_blend_control[i] = blend_cntl;
764
765 blend.blend_enable_4bit |= 0xfu << (i * 4);
766
767 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
768 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
770 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
771 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
772 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
773 blend.need_src_alpha |= 1 << i;
774 }
775 for (i = vkblend->attachmentCount; i < 8; i++) {
776 blend.cb_blend_control[i] = 0;
777 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
778 }
779 }
780
781 if (pipeline->device->physical_device->rad_info.has_rbplus) {
782 /* Disable RB+ blend optimizations for dual source blending. */
783 if (blend.mrt0_is_dual_src) {
784 for (i = 0; i < 8; i++) {
785 blend.sx_mrt_blend_opt[i] =
786 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
787 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
788 }
789 }
790
791 /* RB+ doesn't work with dual source blending, logic op and
792 * RESOLVE.
793 */
794 if (blend.mrt0_is_dual_src ||
795 (vkblend && vkblend->logicOpEnable) ||
796 mode == V_028808_CB_RESOLVE)
797 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
798 }
799
800 if (blend.cb_target_mask)
801 blend.cb_color_control |= S_028808_MODE(mode);
802 else
803 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
804
805 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
806 return blend;
807 }
808
809 static uint32_t si_translate_fill(VkPolygonMode func)
810 {
811 switch(func) {
812 case VK_POLYGON_MODE_FILL:
813 return V_028814_X_DRAW_TRIANGLES;
814 case VK_POLYGON_MODE_LINE:
815 return V_028814_X_DRAW_LINES;
816 case VK_POLYGON_MODE_POINT:
817 return V_028814_X_DRAW_POINTS;
818 default:
819 assert(0);
820 return V_028814_X_DRAW_POINTS;
821 }
822 }
823
824 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
825 {
826 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
827 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
828 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
829 uint32_t ps_iter_samples = 1;
830 uint32_t num_samples;
831
832 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
833 *
834 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
835 * subpass uses color attachments, totalSamples is the number of
836 * samples of the color attachments. Otherwise, totalSamples is the
837 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
838 * specified at pipeline creation time."
839 */
840 if (subpass->has_color_att) {
841 num_samples = subpass->color_sample_count;
842 } else {
843 num_samples = vkms->rasterizationSamples;
844 }
845
846 if (vkms->sampleShadingEnable) {
847 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
848 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
849 }
850 return ps_iter_samples;
851 }
852
853 static bool
854 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
855 {
856 return pCreateInfo->depthTestEnable &&
857 pCreateInfo->depthWriteEnable &&
858 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
859 }
860
861 static bool
862 radv_writes_stencil(const VkStencilOpState *state)
863 {
864 return state->writeMask &&
865 (state->failOp != VK_STENCIL_OP_KEEP ||
866 state->passOp != VK_STENCIL_OP_KEEP ||
867 state->depthFailOp != VK_STENCIL_OP_KEEP);
868 }
869
870 static bool
871 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
872 {
873 return pCreateInfo->stencilTestEnable &&
874 (radv_writes_stencil(&pCreateInfo->front) ||
875 radv_writes_stencil(&pCreateInfo->back));
876 }
877
878 static bool
879 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
880 {
881 return radv_is_depth_write_enabled(pCreateInfo) ||
882 radv_is_stencil_write_enabled(pCreateInfo);
883 }
884
885 static bool
886 radv_order_invariant_stencil_op(VkStencilOp op)
887 {
888 /* REPLACE is normally order invariant, except when the stencil
889 * reference value is written by the fragment shader. Tracking this
890 * interaction does not seem worth the effort, so be conservative.
891 */
892 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
893 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
894 op != VK_STENCIL_OP_REPLACE;
895 }
896
897 static bool
898 radv_order_invariant_stencil_state(const VkStencilOpState *state)
899 {
900 /* Compute whether, assuming Z writes are disabled, this stencil state
901 * is order invariant in the sense that the set of passing fragments as
902 * well as the final stencil buffer result does not depend on the order
903 * of fragments.
904 */
905 return !state->writeMask ||
906 /* The following assumes that Z writes are disabled. */
907 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
908 radv_order_invariant_stencil_op(state->passOp) &&
909 radv_order_invariant_stencil_op(state->depthFailOp)) ||
910 (state->compareOp == VK_COMPARE_OP_NEVER &&
911 radv_order_invariant_stencil_op(state->failOp));
912 }
913
914 static bool
915 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
916 {
917 VkDynamicState ds_states[] = {
918 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
919 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
920 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
921 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
922 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
923 };
924
925 if (pCreateInfo->pDynamicState) {
926 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
927 for (uint32_t i = 0; i < count; i++) {
928 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
929 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
930 return true;
931 }
932 }
933 }
934
935 return false;
936 }
937
938 static bool
939 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
940 struct radv_blend_state *blend,
941 const VkGraphicsPipelineCreateInfo *pCreateInfo)
942 {
943 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
944 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
945 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
946 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
947 unsigned colormask = blend->cb_target_enabled_4bit;
948
949 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
950 return false;
951
952 /* Be conservative if a logic operation is enabled with color buffers. */
953 if (colormask && vkblend && vkblend->logicOpEnable)
954 return false;
955
956 /* Be conservative if an extended dynamic depth/stencil state is
957 * enabled because the driver can't update out-of-order rasterization
958 * dynamically.
959 */
960 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
961 return false;
962
963 /* Default depth/stencil invariance when no attachment is bound. */
964 struct radv_dsa_order_invariance dsa_order_invariant = {
965 .zs = true, .pass_set = true
966 };
967
968 if (vkds) {
969 struct radv_render_pass_attachment *attachment =
970 pass->attachments + subpass->depth_stencil_attachment->attachment;
971 bool has_stencil = vk_format_is_stencil(attachment->format);
972 struct radv_dsa_order_invariance order_invariance[2];
973 struct radv_shader_variant *ps =
974 pipeline->shaders[MESA_SHADER_FRAGMENT];
975
976 /* Compute depth/stencil order invariance in order to know if
977 * it's safe to enable out-of-order.
978 */
979 bool zfunc_is_ordered =
980 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
981 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
983 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
985
986 bool nozwrite_and_order_invariant_stencil =
987 !radv_is_ds_write_enabled(vkds) ||
988 (!radv_is_depth_write_enabled(vkds) &&
989 radv_order_invariant_stencil_state(&vkds->front) &&
990 radv_order_invariant_stencil_state(&vkds->back));
991
992 order_invariance[1].zs =
993 nozwrite_and_order_invariant_stencil ||
994 (!radv_is_stencil_write_enabled(vkds) &&
995 zfunc_is_ordered);
996 order_invariance[0].zs =
997 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
998
999 order_invariance[1].pass_set =
1000 nozwrite_and_order_invariant_stencil ||
1001 (!radv_is_stencil_write_enabled(vkds) &&
1002 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1003 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1004 order_invariance[0].pass_set =
1005 !radv_is_depth_write_enabled(vkds) ||
1006 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1007 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1008
1009 dsa_order_invariant = order_invariance[has_stencil];
1010 if (!dsa_order_invariant.zs)
1011 return false;
1012
1013 /* The set of PS invocations is always order invariant,
1014 * except when early Z/S tests are requested.
1015 */
1016 if (ps &&
1017 ps->info.ps.writes_memory &&
1018 ps->info.ps.early_fragment_test &&
1019 !dsa_order_invariant.pass_set)
1020 return false;
1021
1022 /* Determine if out-of-order rasterization should be disabled
1023 * when occlusion queries are used.
1024 */
1025 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1026 !dsa_order_invariant.pass_set;
1027 }
1028
1029 /* No color buffers are enabled for writing. */
1030 if (!colormask)
1031 return true;
1032
1033 unsigned blendmask = colormask & blend->blend_enable_4bit;
1034
1035 if (blendmask) {
1036 /* Only commutative blending. */
1037 if (blendmask & ~blend->commutative_4bit)
1038 return false;
1039
1040 if (!dsa_order_invariant.pass_set)
1041 return false;
1042 }
1043
1044 if (colormask & ~blendmask)
1045 return false;
1046
1047 return true;
1048 }
1049
1050 static const VkConservativeRasterizationModeEXT
1051 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
1052 {
1053 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
1054 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
1055
1056 if (!conservative_raster)
1057 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
1058 return conservative_raster->conservativeRasterizationMode;
1059 }
1060
1061 static void
1062 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1063 struct radv_blend_state *blend,
1064 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1065 {
1066 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1067 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1068 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1069 const VkConservativeRasterizationModeEXT mode =
1070 radv_get_conservative_raster_mode(pCreateInfo->pRasterizationState);
1071 bool out_of_order_rast = false;
1072 int ps_iter_samples = 1;
1073 uint32_t mask = 0xffff;
1074
1075 if (vkms) {
1076 ms->num_samples = vkms->rasterizationSamples;
1077
1078 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1079 *
1080 * "Sample shading is enabled for a graphics pipeline:
1081 *
1082 * - If the interface of the fragment shader entry point of the
1083 * graphics pipeline includes an input variable decorated
1084 * with SampleId or SamplePosition. In this case
1085 * minSampleShadingFactor takes the value 1.0.
1086 * - Else if the sampleShadingEnable member of the
1087 * VkPipelineMultisampleStateCreateInfo structure specified
1088 * when creating the graphics pipeline is set to VK_TRUE. In
1089 * this case minSampleShadingFactor takes the value of
1090 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1091 *
1092 * Otherwise, sample shading is considered disabled."
1093 */
1094 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1095 ps_iter_samples = ms->num_samples;
1096 } else {
1097 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1098 }
1099 } else {
1100 ms->num_samples = 1;
1101 }
1102
1103 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1104 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1105 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1106 /* Out-of-order rasterization is explicitly enabled by the
1107 * application.
1108 */
1109 out_of_order_rast = true;
1110 } else {
1111 /* Determine if the driver can enable out-of-order
1112 * rasterization internally.
1113 */
1114 out_of_order_rast =
1115 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1116 }
1117
1118 ms->pa_sc_aa_config = 0;
1119 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1120 S_028804_INCOHERENT_EQAA_READS(1) |
1121 S_028804_INTERPOLATE_COMP_Z(1) |
1122 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1123
1124 /* Adjust MSAA state if conservative rasterization is enabled. */
1125 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
1126 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
1127
1128 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
1129 S_028804_OVERRASTERIZATION_AMOUNT(4);
1130 }
1131
1132 ms->pa_sc_mode_cntl_1 =
1133 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1134 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1135 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1136 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1137 /* always 1: */
1138 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1139 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1140 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1141 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1142 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1143 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1144 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1145 S_028A48_VPORT_SCISSOR_ENABLE(1);
1146
1147 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1148 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1149 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1150 if (rast_line) {
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1152 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1153 /* From the Vulkan spec 1.1.129:
1154 *
1155 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1156 * are being rasterized, sample locations may all be
1157 * treated as being at the pixel center (this may
1158 * affect attribute and depth interpolation)."
1159 */
1160 ms->num_samples = 1;
1161 }
1162 }
1163
1164 if (ms->num_samples > 1) {
1165 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1166 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1167 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1168 unsigned log_samples = util_logbase2(ms->num_samples);
1169 unsigned log_z_samples = util_logbase2(z_samples);
1170 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1171 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1172 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1173 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1174 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1175 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1176 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1177 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1178 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1179 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1180 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1181 if (ps_iter_samples > 1)
1182 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1183 }
1184
1185 if (vkms && vkms->pSampleMask) {
1186 mask = vkms->pSampleMask[0] & 0xffff;
1187 }
1188
1189 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1190 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1191 }
1192
1193 static bool
1194 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1195 {
1196 switch (topology) {
1197 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1200 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1202 return false;
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1208 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1209 return true;
1210 default:
1211 unreachable("unhandled primitive type");
1212 }
1213 }
1214
1215 static uint32_t
1216 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1217 {
1218 switch (gl_prim) {
1219 case 0: /* GL_POINTS */
1220 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1221 case 1: /* GL_LINES */
1222 case 3: /* GL_LINE_STRIP */
1223 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1224 case 0x8E7A: /* GL_ISOLINES */
1225 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1226
1227 case 4: /* GL_TRIANGLES */
1228 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1229 case 5: /* GL_TRIANGLE_STRIP */
1230 case 7: /* GL_QUADS */
1231 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1232 default:
1233 assert(0);
1234 return 0;
1235 }
1236 }
1237
1238 static uint32_t
1239 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1240 {
1241 switch (topology) {
1242 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1243 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1244 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1245 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1246 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1247 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1248 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1249 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1250 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1252 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1254 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1255 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1256 default:
1257 assert(0);
1258 return 0;
1259 }
1260 }
1261
1262 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1263 {
1264 switch(state) {
1265 case VK_DYNAMIC_STATE_VIEWPORT:
1266 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1267 return RADV_DYNAMIC_VIEWPORT;
1268 case VK_DYNAMIC_STATE_SCISSOR:
1269 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1270 return RADV_DYNAMIC_SCISSOR;
1271 case VK_DYNAMIC_STATE_LINE_WIDTH:
1272 return RADV_DYNAMIC_LINE_WIDTH;
1273 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1274 return RADV_DYNAMIC_DEPTH_BIAS;
1275 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1276 return RADV_DYNAMIC_BLEND_CONSTANTS;
1277 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1278 return RADV_DYNAMIC_DEPTH_BOUNDS;
1279 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1280 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1281 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1282 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1283 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1284 return RADV_DYNAMIC_STENCIL_REFERENCE;
1285 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1286 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1287 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1288 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1289 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1290 return RADV_DYNAMIC_LINE_STIPPLE;
1291 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1292 return RADV_DYNAMIC_CULL_MODE;
1293 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1294 return RADV_DYNAMIC_FRONT_FACE;
1295 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1296 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1297 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1298 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1299 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1300 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1301 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1302 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1303 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1304 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1305 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1306 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1307 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1308 return RADV_DYNAMIC_STENCIL_OP;
1309 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1310 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1311 default:
1312 unreachable("Unhandled dynamic state");
1313 }
1314 }
1315
1316 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1317 {
1318 uint32_t states = RADV_DYNAMIC_ALL;
1319
1320 /* If rasterization is disabled we do not care about any of the
1321 * dynamic states, since they are all rasterization related only,
1322 * except primitive topology and vertex binding stride.
1323 */
1324 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1325 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1326 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1327
1328 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1329 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1330
1331 if (!pCreateInfo->pDepthStencilState ||
1332 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1333 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1334
1335 if (!pCreateInfo->pDepthStencilState ||
1336 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1337 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1338 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1339 RADV_DYNAMIC_STENCIL_REFERENCE);
1340
1341 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1342 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1343
1344 if (!pCreateInfo->pMultisampleState ||
1345 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1346 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1347 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1348
1349 if (!pCreateInfo->pRasterizationState ||
1350 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1351 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1352 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1353
1354 /* TODO: blend constants & line width. */
1355
1356 return states;
1357 }
1358
1359 static void
1360 radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
1361 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1362 const struct radv_graphics_pipeline_create_info *extra)
1363 {
1364 const VkPipelineInputAssemblyStateCreateInfo *ia_state = pCreateInfo->pInputAssemblyState;
1365 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1366 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
1367
1368 pipeline->graphics.prim_restart_enable = !!ia_state->primitiveRestartEnable;
1369 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology);
1370
1371 if (radv_pipeline_has_gs(pipeline)) {
1372 if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_OUTPRIM_TYPE_TRISTRIP)
1373 pipeline->graphics.can_use_guardband = true;
1374 } else if (radv_pipeline_has_tess(pipeline)) {
1375 if (!tes->info.tes.point_mode &&
1376 si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_OUTPRIM_TYPE_TRISTRIP)
1377 pipeline->graphics.can_use_guardband = true;
1378 }
1379
1380 if (extra && extra->use_rectlist) {
1381 pipeline->graphics.can_use_guardband = true;
1382 }
1383 }
1384
1385 static void
1386 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1387 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1388 const struct radv_graphics_pipeline_create_info *extra)
1389 {
1390 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1391 uint32_t states = needed_states;
1392 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1393 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1394
1395 pipeline->dynamic_state = default_dynamic_state;
1396 pipeline->graphics.needed_dynamic_state = needed_states;
1397
1398 if (pCreateInfo->pDynamicState) {
1399 /* Remove all of the states that are marked as dynamic */
1400 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1401 for (uint32_t s = 0; s < count; s++)
1402 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1403 }
1404
1405 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1406
1407 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1408 assert(pCreateInfo->pViewportState);
1409
1410 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1411 if (states & RADV_DYNAMIC_VIEWPORT) {
1412 typed_memcpy(dynamic->viewport.viewports,
1413 pCreateInfo->pViewportState->pViewports,
1414 pCreateInfo->pViewportState->viewportCount);
1415 }
1416 }
1417
1418 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1419 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1420 if (states & RADV_DYNAMIC_SCISSOR) {
1421 typed_memcpy(dynamic->scissor.scissors,
1422 pCreateInfo->pViewportState->pScissors,
1423 pCreateInfo->pViewportState->scissorCount);
1424 }
1425 }
1426
1427 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1428 assert(pCreateInfo->pRasterizationState);
1429 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1430 }
1431
1432 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1433 assert(pCreateInfo->pRasterizationState);
1434 dynamic->depth_bias.bias =
1435 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1436 dynamic->depth_bias.clamp =
1437 pCreateInfo->pRasterizationState->depthBiasClamp;
1438 dynamic->depth_bias.slope =
1439 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1440 }
1441
1442 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1443 *
1444 * pColorBlendState is [...] NULL if the pipeline has rasterization
1445 * disabled or if the subpass of the render pass the pipeline is
1446 * created against does not use any color attachments.
1447 */
1448 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1449 assert(pCreateInfo->pColorBlendState);
1450 typed_memcpy(dynamic->blend_constants,
1451 pCreateInfo->pColorBlendState->blendConstants, 4);
1452 }
1453
1454 if (states & RADV_DYNAMIC_CULL_MODE) {
1455 dynamic->cull_mode =
1456 pCreateInfo->pRasterizationState->cullMode;
1457 }
1458
1459 if (states & RADV_DYNAMIC_FRONT_FACE) {
1460 dynamic->front_face =
1461 pCreateInfo->pRasterizationState->frontFace;
1462 }
1463
1464 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1465 dynamic->primitive_topology =
1466 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1467 if (extra && extra->use_rectlist) {
1468 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1469 }
1470 }
1471
1472 /* If there is no depthstencil attachment, then don't read
1473 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1474 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1475 * no need to override the depthstencil defaults in
1476 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1477 *
1478 * Section 9.2 of the Vulkan 1.0.15 spec says:
1479 *
1480 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1481 * disabled or if the subpass of the render pass the pipeline is created
1482 * against does not use a depth/stencil attachment.
1483 */
1484 if (needed_states && subpass->depth_stencil_attachment) {
1485 assert(pCreateInfo->pDepthStencilState);
1486
1487 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1488 dynamic->depth_bounds.min =
1489 pCreateInfo->pDepthStencilState->minDepthBounds;
1490 dynamic->depth_bounds.max =
1491 pCreateInfo->pDepthStencilState->maxDepthBounds;
1492 }
1493
1494 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1495 dynamic->stencil_compare_mask.front =
1496 pCreateInfo->pDepthStencilState->front.compareMask;
1497 dynamic->stencil_compare_mask.back =
1498 pCreateInfo->pDepthStencilState->back.compareMask;
1499 }
1500
1501 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1502 dynamic->stencil_write_mask.front =
1503 pCreateInfo->pDepthStencilState->front.writeMask;
1504 dynamic->stencil_write_mask.back =
1505 pCreateInfo->pDepthStencilState->back.writeMask;
1506 }
1507
1508 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1509 dynamic->stencil_reference.front =
1510 pCreateInfo->pDepthStencilState->front.reference;
1511 dynamic->stencil_reference.back =
1512 pCreateInfo->pDepthStencilState->back.reference;
1513 }
1514
1515 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1516 dynamic->depth_test_enable =
1517 pCreateInfo->pDepthStencilState->depthTestEnable;
1518 }
1519
1520 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1521 dynamic->depth_write_enable =
1522 pCreateInfo->pDepthStencilState->depthWriteEnable;
1523 }
1524
1525 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1526 dynamic->depth_compare_op =
1527 pCreateInfo->pDepthStencilState->depthCompareOp;
1528 }
1529
1530 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1531 dynamic->depth_bounds_test_enable =
1532 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1533 }
1534
1535 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1536 dynamic->stencil_test_enable =
1537 pCreateInfo->pDepthStencilState->stencilTestEnable;
1538 }
1539
1540 if (states & RADV_DYNAMIC_STENCIL_OP) {
1541 dynamic->stencil_op.front.compare_op =
1542 pCreateInfo->pDepthStencilState->front.compareOp;
1543 dynamic->stencil_op.front.fail_op =
1544 pCreateInfo->pDepthStencilState->front.failOp;
1545 dynamic->stencil_op.front.pass_op =
1546 pCreateInfo->pDepthStencilState->front.passOp;
1547 dynamic->stencil_op.front.depth_fail_op =
1548 pCreateInfo->pDepthStencilState->front.depthFailOp;
1549
1550 dynamic->stencil_op.back.compare_op =
1551 pCreateInfo->pDepthStencilState->back.compareOp;
1552 dynamic->stencil_op.back.fail_op =
1553 pCreateInfo->pDepthStencilState->back.failOp;
1554 dynamic->stencil_op.back.pass_op =
1555 pCreateInfo->pDepthStencilState->back.passOp;
1556 dynamic->stencil_op.back.depth_fail_op =
1557 pCreateInfo->pDepthStencilState->back.depthFailOp;
1558 }
1559 }
1560
1561 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1562 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1563 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1564 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1565 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1566 typed_memcpy(dynamic->discard_rectangle.rectangles,
1567 discard_rectangle_info->pDiscardRectangles,
1568 discard_rectangle_info->discardRectangleCount);
1569 }
1570 }
1571
1572 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1573 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1574 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1575 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1576 /* If sampleLocationsEnable is VK_FALSE, the default sample
1577 * locations are used and the values specified in
1578 * sampleLocationsInfo are ignored.
1579 */
1580 if (sample_location_info->sampleLocationsEnable) {
1581 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1582 &sample_location_info->sampleLocationsInfo;
1583
1584 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1585
1586 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1587 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1588 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1589 typed_memcpy(&dynamic->sample_location.locations[0],
1590 pSampleLocationsInfo->pSampleLocations,
1591 pSampleLocationsInfo->sampleLocationsCount);
1592 }
1593 }
1594
1595 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1596 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1597 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1598 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1599 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1600 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1601 }
1602
1603 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1604 pipeline->graphics.uses_dynamic_stride = true;
1605
1606 pipeline->dynamic_state.mask = states;
1607 }
1608
1609 static void
1610 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1611 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1612 {
1613 const VkPipelineRasterizationStateCreateInfo *raster_info =
1614 pCreateInfo->pRasterizationState;
1615
1616 pipeline->graphics.pa_su_sc_mode_cntl =
1617 S_028814_FACE(raster_info->frontFace) |
1618 S_028814_CULL_FRONT(!!(raster_info->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1619 S_028814_CULL_BACK(!!(raster_info->cullMode & VK_CULL_MODE_BACK_BIT)) |
1620 S_028814_POLY_MODE(raster_info->polygonMode != VK_POLYGON_MODE_FILL) |
1621 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(raster_info->polygonMode)) |
1622 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(raster_info->polygonMode)) |
1623 S_028814_POLY_OFFSET_FRONT_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
1624 S_028814_POLY_OFFSET_BACK_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
1625 S_028814_POLY_OFFSET_PARA_ENABLE(raster_info->depthBiasEnable ? 1 : 0);
1626 }
1627
1628 static void
1629 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1630 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1631 {
1632 const VkPipelineDepthStencilStateCreateInfo *ds_info
1633 = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1634 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1635 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1636 struct radv_render_pass_attachment *attachment = NULL;
1637 uint32_t db_depth_control = 0;
1638
1639 if (subpass->depth_stencil_attachment)
1640 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
1641
1642 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
1643 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
1644
1645 if (ds_info) {
1646 if (has_depth_attachment) {
1647 db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) |
1648 S_028800_Z_WRITE_ENABLE(ds_info->depthWriteEnable ? 1 : 0) |
1649 S_028800_ZFUNC(ds_info->depthCompareOp) |
1650 S_028800_DEPTH_BOUNDS_ENABLE(ds_info->depthBoundsTestEnable ? 1 : 0);
1651 }
1652
1653 if (has_stencil_attachment && ds_info->stencilTestEnable) {
1654 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1655 db_depth_control |= S_028800_STENCILFUNC(ds_info->front.compareOp);
1656 db_depth_control |= S_028800_STENCILFUNC_BF(ds_info->back.compareOp);
1657 }
1658 }
1659
1660 pipeline->graphics.db_depth_control = db_depth_control;
1661 }
1662
1663 static void
1664 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1665 const struct radv_pipeline *pipeline,
1666 nir_shader **nir,
1667 struct radv_shader_info *infos,
1668 struct gfx9_gs_info *out)
1669 {
1670 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1671 struct radv_es_output_info *es_info;
1672 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1673 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1674 else
1675 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1676 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1677 &infos[MESA_SHADER_VERTEX].vs.es_info;
1678
1679 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1680 bool uses_adjacency;
1681 switch(key->topology) {
1682 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1683 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1684 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1685 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1686 uses_adjacency = true;
1687 break;
1688 default:
1689 uses_adjacency = false;
1690 break;
1691 }
1692
1693 /* All these are in dwords: */
1694 /* We can't allow using the whole LDS, because GS waves compete with
1695 * other shader stages for LDS space. */
1696 const unsigned max_lds_size = 8 * 1024;
1697 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1698 unsigned esgs_lds_size;
1699
1700 /* All these are per subgroup: */
1701 const unsigned max_out_prims = 32 * 1024;
1702 const unsigned max_es_verts = 255;
1703 const unsigned ideal_gs_prims = 64;
1704 unsigned max_gs_prims, gs_prims;
1705 unsigned min_es_verts, es_verts, worst_case_es_verts;
1706
1707 if (uses_adjacency || gs_num_invocations > 1)
1708 max_gs_prims = 127 / gs_num_invocations;
1709 else
1710 max_gs_prims = 255;
1711
1712 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1713 * Make sure we don't go over the maximum value.
1714 */
1715 if (gs_info->gs.vertices_out > 0) {
1716 max_gs_prims = MIN2(max_gs_prims,
1717 max_out_prims /
1718 (gs_info->gs.vertices_out * gs_num_invocations));
1719 }
1720 assert(max_gs_prims > 0);
1721
1722 /* If the primitive has adjacency, halve the number of vertices
1723 * that will be reused in multiple primitives.
1724 */
1725 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1726
1727 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1728 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1729
1730 /* Compute ESGS LDS size based on the worst case number of ES vertices
1731 * needed to create the target number of GS prims per subgroup.
1732 */
1733 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1734
1735 /* If total LDS usage is too big, refactor partitions based on ratio
1736 * of ESGS item sizes.
1737 */
1738 if (esgs_lds_size > max_lds_size) {
1739 /* Our target GS Prims Per Subgroup was too large. Calculate
1740 * the maximum number of GS Prims Per Subgroup that will fit
1741 * into LDS, capped by the maximum that the hardware can support.
1742 */
1743 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1744 max_gs_prims);
1745 assert(gs_prims > 0);
1746 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1747 max_es_verts);
1748
1749 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1750 assert(esgs_lds_size <= max_lds_size);
1751 }
1752
1753 /* Now calculate remaining ESGS information. */
1754 if (esgs_lds_size)
1755 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1756 else
1757 es_verts = max_es_verts;
1758
1759 /* Vertices for adjacency primitives are not always reused, so restore
1760 * it for ES_VERTS_PER_SUBGRP.
1761 */
1762 min_es_verts = gs_info->gs.vertices_in;
1763
1764 /* For normal primitives, the VGT only checks if they are past the ES
1765 * verts per subgroup after allocating a full GS primitive and if they
1766 * are, kick off a new subgroup. But if those additional ES verts are
1767 * unique (e.g. not reused) we need to make sure there is enough LDS
1768 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1769 */
1770 es_verts -= min_es_verts - 1;
1771
1772 uint32_t es_verts_per_subgroup = es_verts;
1773 uint32_t gs_prims_per_subgroup = gs_prims;
1774 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1775 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1776 out->lds_size = align(esgs_lds_size, 128) / 128;
1777 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1778 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1779 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1780 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1781 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1782 assert(max_prims_per_subgroup <= max_out_prims);
1783 }
1784
1785 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1786 unsigned min_verts_per_prim, bool use_adjacency)
1787 {
1788 unsigned max_reuse = max_esverts - min_verts_per_prim;
1789 if (use_adjacency)
1790 max_reuse /= 2;
1791 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1792 }
1793
1794 static unsigned
1795 radv_get_num_input_vertices(nir_shader **nir)
1796 {
1797 if (nir[MESA_SHADER_GEOMETRY]) {
1798 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1799
1800 return gs->info.gs.vertices_in;
1801 }
1802
1803 if (nir[MESA_SHADER_TESS_CTRL]) {
1804 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1805
1806 if (tes->info.tess.point_mode)
1807 return 1;
1808 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1809 return 2;
1810 return 3;
1811 }
1812
1813 return 3;
1814 }
1815
1816 static void
1817 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1818 struct radv_pipeline *pipeline,
1819 nir_shader **nir,
1820 struct radv_shader_info *infos,
1821 struct gfx10_ngg_info *ngg)
1822 {
1823 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1824 struct radv_es_output_info *es_info =
1825 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1826 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1827 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1828 unsigned min_verts_per_prim =
1829 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1830 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1831 bool uses_adjacency;
1832 switch(key->topology) {
1833 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1834 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1835 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1836 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1837 uses_adjacency = true;
1838 break;
1839 default:
1840 uses_adjacency = false;
1841 break;
1842 }
1843
1844 /* All these are in dwords: */
1845 /* We can't allow using the whole LDS, because GS waves compete with
1846 * other shader stages for LDS space.
1847 *
1848 * TODO: We should really take the shader's internal LDS use into
1849 * account. The linker will fail if the size is greater than
1850 * 8K dwords.
1851 */
1852 const unsigned max_lds_size = 8 * 1024 - 768;
1853 const unsigned target_lds_size = max_lds_size;
1854 unsigned esvert_lds_size = 0;
1855 unsigned gsprim_lds_size = 0;
1856
1857 /* All these are per subgroup: */
1858 bool max_vert_out_per_gs_instance = false;
1859 unsigned max_esverts_base = 256;
1860 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1861
1862 /* Hardware has the following non-natural restrictions on the value
1863 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1864 * the draw:
1865 * - at most 252 for any line input primitive type
1866 * - at most 251 for any quad input primitive type
1867 * - at most 251 for triangle strips with adjacency (this happens to
1868 * be the natural limit for triangle *lists* with adjacency)
1869 */
1870 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1871
1872 if (gs_type == MESA_SHADER_GEOMETRY) {
1873 unsigned max_out_verts_per_gsprim =
1874 gs_info->gs.vertices_out * gs_num_invocations;
1875
1876 if (max_out_verts_per_gsprim <= 256) {
1877 if (max_out_verts_per_gsprim) {
1878 max_gsprims_base = MIN2(max_gsprims_base,
1879 256 / max_out_verts_per_gsprim);
1880 }
1881 } else {
1882 /* Use special multi-cycling mode in which each GS
1883 * instance gets its own subgroup. Does not work with
1884 * tessellation. */
1885 max_vert_out_per_gs_instance = true;
1886 max_gsprims_base = 1;
1887 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1888 }
1889
1890 esvert_lds_size = es_info->esgs_itemsize / 4;
1891 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1892 } else {
1893 /* VS and TES. */
1894 /* LDS size for passing data from GS to ES. */
1895 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1896 ? &infos[MESA_SHADER_TESS_EVAL].so
1897 : &infos[MESA_SHADER_VERTEX].so;
1898
1899 if (so_info->num_outputs)
1900 esvert_lds_size = 4 * so_info->num_outputs + 1;
1901
1902 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1903 * corresponding to the ES thread of the provoking vertex. All
1904 * ES threads load and export PrimitiveID for their thread.
1905 */
1906 if (!nir[MESA_SHADER_TESS_CTRL] &&
1907 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1908 esvert_lds_size = MAX2(esvert_lds_size, 1);
1909 }
1910
1911 unsigned max_gsprims = max_gsprims_base;
1912 unsigned max_esverts = max_esverts_base;
1913
1914 if (esvert_lds_size)
1915 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1916 if (gsprim_lds_size)
1917 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1918
1919 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1920 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1921 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1922
1923 if (esvert_lds_size || gsprim_lds_size) {
1924 /* Now that we have a rough proportionality between esverts
1925 * and gsprims based on the primitive type, scale both of them
1926 * down simultaneously based on required LDS space.
1927 *
1928 * We could be smarter about this if we knew how much vertex
1929 * reuse to expect.
1930 */
1931 unsigned lds_total = max_esverts * esvert_lds_size +
1932 max_gsprims * gsprim_lds_size;
1933 if (lds_total > target_lds_size) {
1934 max_esverts = max_esverts * target_lds_size / lds_total;
1935 max_gsprims = max_gsprims * target_lds_size / lds_total;
1936
1937 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1938 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1939 min_verts_per_prim, uses_adjacency);
1940 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1941 }
1942 }
1943
1944 /* Round up towards full wave sizes for better ALU utilization. */
1945 if (!max_vert_out_per_gs_instance) {
1946 unsigned orig_max_esverts;
1947 unsigned orig_max_gsprims;
1948 unsigned wavesize;
1949
1950 if (gs_type == MESA_SHADER_GEOMETRY) {
1951 wavesize = gs_info->wave_size;
1952 } else {
1953 wavesize = nir[MESA_SHADER_TESS_CTRL]
1954 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1955 : infos[MESA_SHADER_VERTEX].wave_size;
1956 }
1957
1958 do {
1959 orig_max_esverts = max_esverts;
1960 orig_max_gsprims = max_gsprims;
1961
1962 max_esverts = align(max_esverts, wavesize);
1963 max_esverts = MIN2(max_esverts, max_esverts_base);
1964 if (esvert_lds_size)
1965 max_esverts = MIN2(max_esverts,
1966 (max_lds_size - max_gsprims * gsprim_lds_size) /
1967 esvert_lds_size);
1968 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1969
1970 max_gsprims = align(max_gsprims, wavesize);
1971 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1972 if (gsprim_lds_size)
1973 max_gsprims = MIN2(max_gsprims,
1974 (max_lds_size - max_esverts * esvert_lds_size) /
1975 gsprim_lds_size);
1976 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1977 min_verts_per_prim, uses_adjacency);
1978 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1979 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1980 }
1981
1982 /* Hardware restriction: minimum value of max_esverts */
1983 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1984
1985 unsigned max_out_vertices =
1986 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1987 gs_type == MESA_SHADER_GEOMETRY ?
1988 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1989 max_esverts;
1990 assert(max_out_vertices <= 256);
1991
1992 unsigned prim_amp_factor = 1;
1993 if (gs_type == MESA_SHADER_GEOMETRY) {
1994 /* Number of output primitives per GS input primitive after
1995 * GS instancing. */
1996 prim_amp_factor = gs_info->gs.vertices_out;
1997 }
1998
1999 /* The GE only checks against the maximum number of ES verts after
2000 * allocating a full GS primitive. So we need to ensure that whenever
2001 * this check passes, there is enough space for a full primitive without
2002 * vertex reuse.
2003 */
2004 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
2005 ngg->max_gsprims = max_gsprims;
2006 ngg->max_out_verts = max_out_vertices;
2007 ngg->prim_amp_factor = prim_amp_factor;
2008 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
2009 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
2010 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
2011
2012 if (gs_type == MESA_SHADER_GEOMETRY) {
2013 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
2014 } else {
2015 ngg->vgt_esgs_ring_itemsize = 1;
2016 }
2017
2018 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
2019
2020 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
2021 }
2022
2023 static void
2024 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
2025 const struct gfx9_gs_info *gs)
2026 {
2027 struct radv_device *device = pipeline->device;
2028 unsigned num_se = device->physical_device->rad_info.max_se;
2029 unsigned wave_size = 64;
2030 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2031 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2032 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2033 */
2034 unsigned gs_vertex_reuse =
2035 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
2036 unsigned alignment = 256 * num_se;
2037 /* The maximum size is 63.999 MB per SE. */
2038 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2039 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
2040
2041 /* Calculate the minimum size. */
2042 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
2043 wave_size, alignment);
2044 /* These are recommended sizes, not minimum sizes. */
2045 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2046 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
2047 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2048 gs_info->gs.max_gsvs_emit_size;
2049
2050 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2051 esgs_ring_size = align(esgs_ring_size, alignment);
2052 gsvs_ring_size = align(gsvs_ring_size, alignment);
2053
2054 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
2055 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2056
2057 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2058 }
2059
2060 struct radv_shader_variant *
2061 radv_get_shader(const struct radv_pipeline *pipeline,
2062 gl_shader_stage stage)
2063 {
2064 if (stage == MESA_SHADER_VERTEX) {
2065 if (pipeline->shaders[MESA_SHADER_VERTEX])
2066 return pipeline->shaders[MESA_SHADER_VERTEX];
2067 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2068 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2069 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2070 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2071 } else if (stage == MESA_SHADER_TESS_EVAL) {
2072 if (!radv_pipeline_has_tess(pipeline))
2073 return NULL;
2074 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2075 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2076 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2077 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2078 }
2079 return pipeline->shaders[stage];
2080 }
2081
2082 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2083 {
2084 if (radv_pipeline_has_gs(pipeline))
2085 if (radv_pipeline_has_ngg(pipeline))
2086 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2087 else
2088 return &pipeline->gs_copy_shader->info.vs.outinfo;
2089 else if (radv_pipeline_has_tess(pipeline))
2090 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2091 else
2092 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2093 }
2094
2095 static void
2096 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2097 {
2098 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2099 int shader_count = 0;
2100
2101 if(shaders[MESA_SHADER_FRAGMENT]) {
2102 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2103 }
2104 if(shaders[MESA_SHADER_GEOMETRY]) {
2105 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2106 }
2107 if(shaders[MESA_SHADER_TESS_EVAL]) {
2108 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2109 }
2110 if(shaders[MESA_SHADER_TESS_CTRL]) {
2111 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2112 }
2113 if(shaders[MESA_SHADER_VERTEX]) {
2114 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2115 }
2116
2117 if (shader_count > 1) {
2118 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2119 unsigned last = ordered_shaders[0]->info.stage;
2120
2121 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2122 ordered_shaders[1]->info.has_transform_feedback_varyings)
2123 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2124
2125 for (int i = 0; i < shader_count; ++i) {
2126 nir_variable_mode mask = 0;
2127
2128 if (ordered_shaders[i]->info.stage != first)
2129 mask = mask | nir_var_shader_in;
2130
2131 if (ordered_shaders[i]->info.stage != last)
2132 mask = mask | nir_var_shader_out;
2133
2134 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2135 radv_optimize_nir(ordered_shaders[i], false, false);
2136 }
2137 }
2138
2139 for (int i = 1; i < shader_count; ++i) {
2140 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2141 ordered_shaders[i - 1]);
2142
2143 if (nir_link_opt_varyings(ordered_shaders[i],
2144 ordered_shaders[i - 1]))
2145 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2146
2147 nir_remove_dead_variables(ordered_shaders[i],
2148 nir_var_shader_out, NULL);
2149 nir_remove_dead_variables(ordered_shaders[i - 1],
2150 nir_var_shader_in, NULL);
2151
2152 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2153 ordered_shaders[i - 1]);
2154
2155 nir_compact_varyings(ordered_shaders[i],
2156 ordered_shaders[i - 1], true);
2157
2158 if (progress) {
2159 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2160 ac_lower_indirect_derefs(ordered_shaders[i],
2161 pipeline->device->physical_device->rad_info.chip_class);
2162 }
2163 radv_optimize_nir(ordered_shaders[i], false, false);
2164
2165 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2166 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2167 pipeline->device->physical_device->rad_info.chip_class);
2168 }
2169 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2170 }
2171 }
2172 }
2173
2174 static void
2175 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2176 struct radv_shader_info infos[MESA_SHADER_STAGES])
2177 {
2178 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2179 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2180
2181 if (!has_tess && !has_gs)
2182 return;
2183
2184 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2185 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2186
2187 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2188 /* These are merged into the next stage */
2189 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2190 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2191 }
2192
2193 if (has_tess) {
2194 nir_linked_io_var_info vs2tcs =
2195 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2196 nir_linked_io_var_info tcs2tes =
2197 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2198
2199 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2200 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2201 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2202 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2203 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2204 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2205
2206 if (has_gs) {
2207 nir_linked_io_var_info tes2gs =
2208 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2209
2210 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2211 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2212 }
2213 } else if (has_gs) {
2214 nir_linked_io_var_info vs2gs =
2215 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2216
2217 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2218 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2219 }
2220 }
2221
2222 static uint32_t
2223 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2224 uint32_t attrib_binding)
2225 {
2226 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2227 const VkVertexInputBindingDescription *input_binding =
2228 &input_state->pVertexBindingDescriptions[i];
2229
2230 if (input_binding->binding == attrib_binding)
2231 return input_binding->stride;
2232 }
2233
2234 return 0;
2235 }
2236
2237 static struct radv_pipeline_key
2238 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2239 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2240 const struct radv_blend_state *blend)
2241 {
2242 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2243 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2244 const VkPipelineVertexInputStateCreateInfo *input_state =
2245 pCreateInfo->pVertexInputState;
2246 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2247 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2248
2249 struct radv_pipeline_key key;
2250 memset(&key, 0, sizeof(key));
2251
2252 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2253 key.optimisations_disabled = 1;
2254
2255 key.has_multiview_view_index = !!subpass->view_mask;
2256
2257 uint32_t binding_input_rate = 0;
2258 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2259 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2260 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2261 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2262 binding_input_rate |= 1u << binding;
2263 instance_rate_divisors[binding] = 1;
2264 }
2265 }
2266 if (divisor_state) {
2267 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2268 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2269 divisor_state->pVertexBindingDivisors[i].divisor;
2270 }
2271 }
2272
2273 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2274 const VkVertexInputAttributeDescription *desc =
2275 &input_state->pVertexAttributeDescriptions[i];
2276 const struct vk_format_description *format_desc;
2277 unsigned location = desc->location;
2278 unsigned binding = desc->binding;
2279 unsigned num_format, data_format;
2280 int first_non_void;
2281
2282 if (binding_input_rate & (1u << binding)) {
2283 key.instance_rate_inputs |= 1u << location;
2284 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2285 }
2286
2287 format_desc = vk_format_description(desc->format);
2288 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2289
2290 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2291 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2292
2293 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2294 key.vertex_attribute_bindings[location] = desc->binding;
2295 key.vertex_attribute_offsets[location] = desc->offset;
2296 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2297
2298 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2299 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2300 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2301 uint64_t adjust;
2302 switch(format) {
2303 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2304 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2305 adjust = RADV_ALPHA_ADJUST_SNORM;
2306 break;
2307 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2308 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2309 adjust = RADV_ALPHA_ADJUST_SSCALED;
2310 break;
2311 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2312 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2313 adjust = RADV_ALPHA_ADJUST_SINT;
2314 break;
2315 default:
2316 adjust = 0;
2317 break;
2318 }
2319 key.vertex_alpha_adjust |= adjust << (2 * location);
2320 }
2321
2322 switch (desc->format) {
2323 case VK_FORMAT_B8G8R8A8_UNORM:
2324 case VK_FORMAT_B8G8R8A8_SNORM:
2325 case VK_FORMAT_B8G8R8A8_USCALED:
2326 case VK_FORMAT_B8G8R8A8_SSCALED:
2327 case VK_FORMAT_B8G8R8A8_UINT:
2328 case VK_FORMAT_B8G8R8A8_SINT:
2329 case VK_FORMAT_B8G8R8A8_SRGB:
2330 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2331 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2332 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2333 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2334 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2335 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2336 key.vertex_post_shuffle |= 1 << location;
2337 break;
2338 default:
2339 break;
2340 }
2341 }
2342
2343 const VkPipelineTessellationStateCreateInfo *tess =
2344 radv_pipeline_get_tessellation_state(pCreateInfo);
2345 if (tess)
2346 key.tess_input_vertices = tess->patchControlPoints;
2347
2348 const VkPipelineMultisampleStateCreateInfo *vkms =
2349 radv_pipeline_get_multisample_state(pCreateInfo);
2350 if (vkms && vkms->rasterizationSamples > 1) {
2351 uint32_t num_samples = vkms->rasterizationSamples;
2352 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2353 key.num_samples = num_samples;
2354 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2355 }
2356
2357 key.col_format = blend->spi_shader_col_format;
2358 key.is_dual_src = blend->mrt0_is_dual_src;
2359 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2360 key.is_int8 = blend->col_format_is_int8;
2361 key.is_int10 = blend->col_format_is_int10;
2362 }
2363
2364 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2365 key.topology = pCreateInfo->pInputAssemblyState->topology;
2366
2367 return key;
2368 }
2369
2370 static bool
2371 radv_nir_stage_uses_xfb(const nir_shader *nir)
2372 {
2373 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2374 bool uses_xfb = !!xfb;
2375
2376 ralloc_free(xfb);
2377 return uses_xfb;
2378 }
2379
2380 static void
2381 radv_fill_shader_keys(struct radv_device *device,
2382 struct radv_shader_variant_key *keys,
2383 const struct radv_pipeline_key *key,
2384 nir_shader **nir)
2385 {
2386 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2387 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2388 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2389 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2390 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2391 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2392 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2393 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2394 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2395 }
2396 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2397
2398 if (nir[MESA_SHADER_TESS_CTRL]) {
2399 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2400 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2401 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2402 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2403
2404 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2405 }
2406
2407 if (nir[MESA_SHADER_GEOMETRY]) {
2408 if (nir[MESA_SHADER_TESS_CTRL])
2409 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2410 else
2411 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2412 }
2413
2414 if (device->physical_device->use_ngg) {
2415 if (nir[MESA_SHADER_TESS_CTRL]) {
2416 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2417 } else {
2418 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2419 }
2420
2421 if (nir[MESA_SHADER_TESS_CTRL] &&
2422 nir[MESA_SHADER_GEOMETRY] &&
2423 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2424 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2425 /* Fallback to the legacy path if tessellation is
2426 * enabled with extreme geometry because
2427 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2428 * might hang.
2429 */
2430 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2431 }
2432
2433 if (!device->physical_device->use_ngg_gs) {
2434 if (nir[MESA_SHADER_GEOMETRY]) {
2435 if (nir[MESA_SHADER_TESS_CTRL])
2436 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2437 else
2438 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2439 }
2440 }
2441
2442 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2443
2444 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2445 if (nir[i])
2446 last_xfb_stage = i;
2447 }
2448
2449 bool uses_xfb = nir[last_xfb_stage] &&
2450 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2451
2452 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2453 if (nir[MESA_SHADER_TESS_CTRL])
2454 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2455 else
2456 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2457 }
2458
2459 /* Determine if the pipeline is eligible for the NGG passthrough
2460 * mode. It can't be enabled for geometry shaders, for NGG
2461 * streamout or for vertex shaders that export the primitive ID
2462 * (this is checked later because we don't have the info here.)
2463 */
2464 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2465 if (nir[MESA_SHADER_TESS_CTRL] &&
2466 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2467 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2468 } else if (nir[MESA_SHADER_VERTEX] &&
2469 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2470 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2471 }
2472 }
2473 }
2474
2475 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2476 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2477
2478 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2479 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2480 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2481 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2482 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2483 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2484
2485 if (nir[MESA_SHADER_COMPUTE]) {
2486 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2487 }
2488 }
2489
2490 static uint8_t
2491 radv_get_wave_size(struct radv_device *device,
2492 const VkPipelineShaderStageCreateInfo *pStage,
2493 gl_shader_stage stage,
2494 const struct radv_shader_variant_key *key)
2495 {
2496 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2497 return 64;
2498 else if (stage == MESA_SHADER_COMPUTE) {
2499 if (key->cs.subgroup_size) {
2500 /* Return the required subgroup size if specified. */
2501 return key->cs.subgroup_size;
2502 }
2503 return device->physical_device->cs_wave_size;
2504 }
2505 else if (stage == MESA_SHADER_FRAGMENT)
2506 return device->physical_device->ps_wave_size;
2507 else
2508 return device->physical_device->ge_wave_size;
2509 }
2510
2511 static uint8_t
2512 radv_get_ballot_bit_size(struct radv_device *device,
2513 const VkPipelineShaderStageCreateInfo *pStage,
2514 gl_shader_stage stage,
2515 const struct radv_shader_variant_key *key)
2516 {
2517 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2518 return key->cs.subgroup_size;
2519 return 64;
2520 }
2521
2522 static void
2523 radv_fill_shader_info(struct radv_pipeline *pipeline,
2524 const VkPipelineShaderStageCreateInfo **pStages,
2525 struct radv_shader_variant_key *keys,
2526 struct radv_shader_info *infos,
2527 nir_shader **nir)
2528 {
2529 unsigned active_stages = 0;
2530 unsigned filled_stages = 0;
2531
2532 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2533 if (nir[i])
2534 active_stages |= (1 << i);
2535 }
2536
2537 if (nir[MESA_SHADER_FRAGMENT]) {
2538 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2539 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2540 pipeline->layout,
2541 &keys[MESA_SHADER_FRAGMENT],
2542 &infos[MESA_SHADER_FRAGMENT],
2543 pipeline->device->physical_device->use_llvm);
2544
2545 /* TODO: These are no longer used as keys we should refactor this */
2546 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2547 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2548 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2549 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2550 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2551 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2552 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2553 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2554 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2555 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2556 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2557 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2558 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2559 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2560 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2561 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2562
2563 /* NGG passthrough mode can't be enabled for vertex shaders
2564 * that export the primitive ID.
2565 *
2566 * TODO: I should really refactor the keys logic.
2567 */
2568 if (nir[MESA_SHADER_VERTEX] &&
2569 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2570 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2571 }
2572
2573 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2574 }
2575
2576 if (nir[MESA_SHADER_TESS_CTRL]) {
2577 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2578 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2579 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2580 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2581 }
2582
2583 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2584 nir[MESA_SHADER_TESS_CTRL]) {
2585 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2586 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2587 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2588
2589 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2590
2591 for (int i = 0; i < 2; i++) {
2592 radv_nir_shader_info_pass(combined_nir[i],
2593 pipeline->layout, &key,
2594 &infos[MESA_SHADER_TESS_CTRL],
2595 pipeline->device->physical_device->use_llvm);
2596 }
2597
2598 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2599 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2600 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2601 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2602
2603 filled_stages |= (1 << MESA_SHADER_VERTEX);
2604 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2605 }
2606
2607 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2608 nir[MESA_SHADER_GEOMETRY]) {
2609 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2610 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2611
2612 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2613
2614 for (int i = 0; i < 2; i++) {
2615 radv_nir_shader_info_pass(combined_nir[i],
2616 pipeline->layout,
2617 &keys[pre_stage],
2618 &infos[MESA_SHADER_GEOMETRY],
2619 pipeline->device->physical_device->use_llvm);
2620 }
2621
2622 filled_stages |= (1 << pre_stage);
2623 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2624 }
2625
2626 active_stages ^= filled_stages;
2627 while (active_stages) {
2628 int i = u_bit_scan(&active_stages);
2629
2630 if (i == MESA_SHADER_TESS_CTRL) {
2631 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2632 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2633 }
2634
2635 if (i == MESA_SHADER_TESS_EVAL) {
2636 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2637 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2638 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2639 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2640 }
2641
2642 radv_nir_shader_info_init(&infos[i]);
2643 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2644 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2645 }
2646
2647 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2648 if (nir[i]) {
2649 infos[i].wave_size =
2650 radv_get_wave_size(pipeline->device, pStages[i],
2651 i, &keys[i]);
2652 infos[i].ballot_bit_size =
2653 radv_get_ballot_bit_size(pipeline->device,
2654 pStages[i], i,
2655 &keys[i]);
2656 }
2657 }
2658 }
2659
2660 static void
2661 merge_tess_info(struct shader_info *tes_info,
2662 const struct shader_info *tcs_info)
2663 {
2664 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2665 *
2666 * "PointMode. Controls generation of points rather than triangles
2667 * or lines. This functionality defaults to disabled, and is
2668 * enabled if either shader stage includes the execution mode.
2669 *
2670 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2671 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2672 * and OutputVertices, it says:
2673 *
2674 * "One mode must be set in at least one of the tessellation
2675 * shader stages."
2676 *
2677 * So, the fields can be set in either the TCS or TES, but they must
2678 * agree if set in both. Our backend looks at TES, so bitwise-or in
2679 * the values from the TCS.
2680 */
2681 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2682 tes_info->tess.tcs_vertices_out == 0 ||
2683 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2684 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2685
2686 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2687 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2688 tcs_info->tess.spacing == tes_info->tess.spacing);
2689 tes_info->tess.spacing |= tcs_info->tess.spacing;
2690
2691 assert(tcs_info->tess.primitive_mode == 0 ||
2692 tes_info->tess.primitive_mode == 0 ||
2693 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2694 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2695 tes_info->tess.ccw |= tcs_info->tess.ccw;
2696 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2697 }
2698
2699 static
2700 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2701 {
2702 if (!ext)
2703 return;
2704
2705 if (ext->pPipelineCreationFeedback) {
2706 ext->pPipelineCreationFeedback->flags = 0;
2707 ext->pPipelineCreationFeedback->duration = 0;
2708 }
2709
2710 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2711 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2712 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2713 }
2714 }
2715
2716 static
2717 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2718 {
2719 if (!feedback)
2720 return;
2721
2722 feedback->duration -= radv_get_current_time();
2723 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2724 }
2725
2726 static
2727 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2728 {
2729 if (!feedback)
2730 return;
2731
2732 feedback->duration += radv_get_current_time();
2733 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2734 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2735 }
2736
2737 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2738 struct radv_device *device,
2739 struct radv_pipeline_cache *cache,
2740 const struct radv_pipeline_key *key,
2741 const VkPipelineShaderStageCreateInfo **pStages,
2742 const VkPipelineCreateFlags flags,
2743 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2744 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2745 {
2746 struct radv_shader_module fs_m = {0};
2747 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2748 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2749 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2750 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2751 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2752 unsigned char hash[20], gs_copy_hash[20];
2753 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2754 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2755 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2756 device->keep_shader_info;
2757
2758 radv_start_feedback(pipeline_feedback);
2759
2760 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2761 if (pStages[i]) {
2762 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2763 if (modules[i]->nir)
2764 _mesa_sha1_compute(modules[i]->nir->info.name,
2765 strlen(modules[i]->nir->info.name),
2766 modules[i]->sha1);
2767
2768 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2769 }
2770 }
2771
2772 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2773 memcpy(gs_copy_hash, hash, 20);
2774 gs_copy_hash[0] ^= 1;
2775
2776 bool found_in_application_cache = true;
2777 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2778 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2779 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2780 &found_in_application_cache);
2781 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2782 }
2783
2784 if (!keep_executable_info && !keep_statistic_info &&
2785 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2786 &found_in_application_cache) &&
2787 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2788 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2789 return VK_SUCCESS;
2790 }
2791
2792 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2793 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2794 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2795 }
2796
2797 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2798 nir_builder fs_b;
2799 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2800 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2801 fs_m.nir = fs_b.shader;
2802 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2803 }
2804
2805 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2806 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2807 unsigned subgroup_size = 64, ballot_bit_size = 64;
2808
2809 if (!modules[i])
2810 continue;
2811
2812 radv_start_feedback(stage_feedbacks[i]);
2813
2814 if (key->compute_subgroup_size) {
2815 /* Only compute shaders currently support requiring a
2816 * specific subgroup size.
2817 */
2818 assert(i == MESA_SHADER_COMPUTE);
2819 subgroup_size = key->compute_subgroup_size;
2820 ballot_bit_size = key->compute_subgroup_size;
2821 }
2822
2823 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2824 stage ? stage->pName : "main", i,
2825 stage ? stage->pSpecializationInfo : NULL,
2826 flags, pipeline->layout,
2827 subgroup_size, ballot_bit_size);
2828
2829 /* We don't want to alter meta shaders IR directly so clone it
2830 * first.
2831 */
2832 if (nir[i]->info.name) {
2833 nir[i] = nir_shader_clone(NULL, nir[i]);
2834 }
2835
2836 radv_stop_feedback(stage_feedbacks[i], false);
2837 }
2838
2839 if (nir[MESA_SHADER_TESS_CTRL]) {
2840 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2841 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2842 }
2843
2844 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2845 radv_link_shaders(pipeline, nir);
2846
2847 radv_set_linked_driver_locations(pipeline, nir, infos);
2848
2849 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2850 if (nir[i]) {
2851 /* do this again since information such as outputs_read can be out-of-date */
2852 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2853
2854 if (device->physical_device->use_llvm) {
2855 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2856 } else {
2857 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2858 nir_lower_non_uniform_ubo_access |
2859 nir_lower_non_uniform_ssbo_access |
2860 nir_lower_non_uniform_texture_access |
2861 nir_lower_non_uniform_image_access);
2862 }
2863 }
2864 }
2865
2866 if (nir[MESA_SHADER_FRAGMENT])
2867 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2868
2869 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2870 if (radv_can_dump_shader(device, modules[i], false))
2871 nir_print_shader(nir[i], stderr);
2872 }
2873
2874 radv_fill_shader_keys(device, keys, key, nir);
2875
2876 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2877
2878 if ((nir[MESA_SHADER_VERTEX] &&
2879 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2880 (nir[MESA_SHADER_TESS_EVAL] &&
2881 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2882 struct gfx10_ngg_info *ngg_info;
2883
2884 if (nir[MESA_SHADER_GEOMETRY])
2885 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2886 else if (nir[MESA_SHADER_TESS_CTRL])
2887 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2888 else
2889 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2890
2891 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2892 } else if (nir[MESA_SHADER_GEOMETRY]) {
2893 struct gfx9_gs_info *gs_info =
2894 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2895
2896 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2897 }
2898
2899 if(modules[MESA_SHADER_GEOMETRY]) {
2900 struct radv_shader_binary *gs_copy_binary = NULL;
2901 if (!pipeline->gs_copy_shader &&
2902 !radv_pipeline_has_ngg(pipeline)) {
2903 struct radv_shader_info info = {};
2904 struct radv_shader_variant_key key = {};
2905
2906 key.has_multiview_view_index =
2907 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2908
2909 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2910 pipeline->layout, &key,
2911 &info, pipeline->device->physical_device->use_llvm);
2912 info.wave_size = 64; /* Wave32 not supported. */
2913 info.ballot_bit_size = 64;
2914
2915 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2916 device, nir[MESA_SHADER_GEOMETRY], &info,
2917 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2918 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2919 }
2920
2921 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2922 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2923 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2924
2925 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2926 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2927
2928 radv_pipeline_cache_insert_shaders(device, cache,
2929 gs_copy_hash,
2930 variants,
2931 binaries);
2932 }
2933 free(gs_copy_binary);
2934 }
2935
2936 if (nir[MESA_SHADER_FRAGMENT]) {
2937 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2938 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2939
2940 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2941 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2942 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2943 infos + MESA_SHADER_FRAGMENT,
2944 keep_executable_info, keep_statistic_info,
2945 &binaries[MESA_SHADER_FRAGMENT]);
2946
2947 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2948 }
2949 }
2950
2951 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2952 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2953 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2954 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2955 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2956
2957 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2958
2959 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2960 pipeline->layout,
2961 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2962 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2963
2964 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2965 }
2966 modules[MESA_SHADER_VERTEX] = NULL;
2967 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2968 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2969 }
2970
2971 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2972 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2973 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2974 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2975
2976 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2977
2978 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2979 pipeline->layout,
2980 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2981 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2982
2983 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2984 }
2985 modules[pre_stage] = NULL;
2986 }
2987
2988 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2989 if(modules[i] && !pipeline->shaders[i]) {
2990 if (i == MESA_SHADER_TESS_CTRL) {
2991 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2992 }
2993 if (i == MESA_SHADER_TESS_EVAL) {
2994 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2995 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2996 }
2997
2998 radv_start_feedback(stage_feedbacks[i]);
2999
3000 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3001 pipeline->layout,
3002 keys + i, infos + i, keep_executable_info,
3003 keep_statistic_info, &binaries[i]);
3004
3005 radv_stop_feedback(stage_feedbacks[i], false);
3006 }
3007 }
3008
3009 if (!keep_executable_info && !keep_statistic_info) {
3010 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3011 binaries);
3012 }
3013
3014 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3015 free(binaries[i]);
3016 if (nir[i]) {
3017 ralloc_free(nir[i]);
3018
3019 if (radv_can_dump_shader_stats(device, modules[i]))
3020 radv_shader_dump_stats(device,
3021 pipeline->shaders[i],
3022 i, stderr);
3023 }
3024 }
3025
3026 if (fs_m.nir)
3027 ralloc_free(fs_m.nir);
3028
3029 radv_stop_feedback(pipeline_feedback, false);
3030 return VK_SUCCESS;
3031 }
3032
3033 static uint32_t
3034 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3035 gl_shader_stage stage, enum chip_class chip_class)
3036 {
3037 bool has_gs = radv_pipeline_has_gs(pipeline);
3038 bool has_tess = radv_pipeline_has_tess(pipeline);
3039 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3040
3041 switch (stage) {
3042 case MESA_SHADER_FRAGMENT:
3043 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3044 case MESA_SHADER_VERTEX:
3045 if (has_tess) {
3046 if (chip_class >= GFX10) {
3047 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3048 } else if (chip_class == GFX9) {
3049 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3050 } else {
3051 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3052 }
3053
3054 }
3055
3056 if (has_gs) {
3057 if (chip_class >= GFX10) {
3058 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3059 } else {
3060 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3061 }
3062 }
3063
3064 if (has_ngg)
3065 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3066
3067 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3068 case MESA_SHADER_GEOMETRY:
3069 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3070 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3071 case MESA_SHADER_COMPUTE:
3072 return R_00B900_COMPUTE_USER_DATA_0;
3073 case MESA_SHADER_TESS_CTRL:
3074 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3075 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3076 case MESA_SHADER_TESS_EVAL:
3077 if (has_gs) {
3078 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3079 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3080 } else if (has_ngg) {
3081 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3082 } else {
3083 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3084 }
3085 default:
3086 unreachable("unknown shader");
3087 }
3088 }
3089
3090 struct radv_bin_size_entry {
3091 unsigned bpp;
3092 VkExtent2D extent;
3093 };
3094
3095 static VkExtent2D
3096 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3097 {
3098 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3099 {
3100 /* One RB / SE */
3101 {
3102 /* One shader engine */
3103 { 0, {128, 128}},
3104 { 1, { 64, 128}},
3105 { 2, { 32, 128}},
3106 { 3, { 16, 128}},
3107 { 17, { 0, 0}},
3108 { UINT_MAX, { 0, 0}},
3109 },
3110 {
3111 /* Two shader engines */
3112 { 0, {128, 128}},
3113 { 2, { 64, 128}},
3114 { 3, { 32, 128}},
3115 { 5, { 16, 128}},
3116 { 17, { 0, 0}},
3117 { UINT_MAX, { 0, 0}},
3118 },
3119 {
3120 /* Four shader engines */
3121 { 0, {128, 128}},
3122 { 3, { 64, 128}},
3123 { 5, { 16, 128}},
3124 { 17, { 0, 0}},
3125 { UINT_MAX, { 0, 0}},
3126 },
3127 },
3128 {
3129 /* Two RB / SE */
3130 {
3131 /* One shader engine */
3132 { 0, {128, 128}},
3133 { 2, { 64, 128}},
3134 { 3, { 32, 128}},
3135 { 5, { 16, 128}},
3136 { 33, { 0, 0}},
3137 { UINT_MAX, { 0, 0}},
3138 },
3139 {
3140 /* Two shader engines */
3141 { 0, {128, 128}},
3142 { 3, { 64, 128}},
3143 { 5, { 32, 128}},
3144 { 9, { 16, 128}},
3145 { 33, { 0, 0}},
3146 { UINT_MAX, { 0, 0}},
3147 },
3148 {
3149 /* Four shader engines */
3150 { 0, {256, 256}},
3151 { 2, {128, 256}},
3152 { 3, {128, 128}},
3153 { 5, { 64, 128}},
3154 { 9, { 16, 128}},
3155 { 33, { 0, 0}},
3156 { UINT_MAX, { 0, 0}},
3157 },
3158 },
3159 {
3160 /* Four RB / SE */
3161 {
3162 /* One shader engine */
3163 { 0, {128, 256}},
3164 { 2, {128, 128}},
3165 { 3, { 64, 128}},
3166 { 5, { 32, 128}},
3167 { 9, { 16, 128}},
3168 { 33, { 0, 0}},
3169 { UINT_MAX, { 0, 0}},
3170 },
3171 {
3172 /* Two shader engines */
3173 { 0, {256, 256}},
3174 { 2, {128, 256}},
3175 { 3, {128, 128}},
3176 { 5, { 64, 128}},
3177 { 9, { 32, 128}},
3178 { 17, { 16, 128}},
3179 { 33, { 0, 0}},
3180 { UINT_MAX, { 0, 0}},
3181 },
3182 {
3183 /* Four shader engines */
3184 { 0, {256, 512}},
3185 { 2, {256, 256}},
3186 { 3, {128, 256}},
3187 { 5, {128, 128}},
3188 { 9, { 64, 128}},
3189 { 17, { 16, 128}},
3190 { 33, { 0, 0}},
3191 { UINT_MAX, { 0, 0}},
3192 },
3193 },
3194 };
3195 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3196 {
3197 // One RB / SE
3198 {
3199 // One shader engine
3200 { 0, {128, 256}},
3201 { 2, {128, 128}},
3202 { 4, { 64, 128}},
3203 { 7, { 32, 128}},
3204 { 13, { 16, 128}},
3205 { 49, { 0, 0}},
3206 { UINT_MAX, { 0, 0}},
3207 },
3208 {
3209 // Two shader engines
3210 { 0, {256, 256}},
3211 { 2, {128, 256}},
3212 { 4, {128, 128}},
3213 { 7, { 64, 128}},
3214 { 13, { 32, 128}},
3215 { 25, { 16, 128}},
3216 { 49, { 0, 0}},
3217 { UINT_MAX, { 0, 0}},
3218 },
3219 {
3220 // Four shader engines
3221 { 0, {256, 512}},
3222 { 2, {256, 256}},
3223 { 4, {128, 256}},
3224 { 7, {128, 128}},
3225 { 13, { 64, 128}},
3226 { 25, { 16, 128}},
3227 { 49, { 0, 0}},
3228 { UINT_MAX, { 0, 0}},
3229 },
3230 },
3231 {
3232 // Two RB / SE
3233 {
3234 // One shader engine
3235 { 0, {256, 256}},
3236 { 2, {128, 256}},
3237 { 4, {128, 128}},
3238 { 7, { 64, 128}},
3239 { 13, { 32, 128}},
3240 { 25, { 16, 128}},
3241 { 97, { 0, 0}},
3242 { UINT_MAX, { 0, 0}},
3243 },
3244 {
3245 // Two shader engines
3246 { 0, {256, 512}},
3247 { 2, {256, 256}},
3248 { 4, {128, 256}},
3249 { 7, {128, 128}},
3250 { 13, { 64, 128}},
3251 { 25, { 32, 128}},
3252 { 49, { 16, 128}},
3253 { 97, { 0, 0}},
3254 { UINT_MAX, { 0, 0}},
3255 },
3256 {
3257 // Four shader engines
3258 { 0, {512, 512}},
3259 { 2, {256, 512}},
3260 { 4, {256, 256}},
3261 { 7, {128, 256}},
3262 { 13, {128, 128}},
3263 { 25, { 64, 128}},
3264 { 49, { 16, 128}},
3265 { 97, { 0, 0}},
3266 { UINT_MAX, { 0, 0}},
3267 },
3268 },
3269 {
3270 // Four RB / SE
3271 {
3272 // One shader engine
3273 { 0, {256, 512}},
3274 { 2, {256, 256}},
3275 { 4, {128, 256}},
3276 { 7, {128, 128}},
3277 { 13, { 64, 128}},
3278 { 25, { 32, 128}},
3279 { 49, { 16, 128}},
3280 { UINT_MAX, { 0, 0}},
3281 },
3282 {
3283 // Two shader engines
3284 { 0, {512, 512}},
3285 { 2, {256, 512}},
3286 { 4, {256, 256}},
3287 { 7, {128, 256}},
3288 { 13, {128, 128}},
3289 { 25, { 64, 128}},
3290 { 49, { 32, 128}},
3291 { 97, { 16, 128}},
3292 { UINT_MAX, { 0, 0}},
3293 },
3294 {
3295 // Four shader engines
3296 { 0, {512, 512}},
3297 { 4, {256, 512}},
3298 { 7, {256, 256}},
3299 { 13, {128, 256}},
3300 { 25, {128, 128}},
3301 { 49, { 64, 128}},
3302 { 97, { 16, 128}},
3303 { UINT_MAX, { 0, 0}},
3304 },
3305 },
3306 };
3307
3308 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3309 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3310 VkExtent2D extent = {512, 512};
3311
3312 unsigned log_num_rb_per_se =
3313 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3314 pipeline->device->physical_device->rad_info.max_se);
3315 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3316
3317 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3318 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3319 unsigned effective_samples = total_samples;
3320 unsigned color_bytes_per_pixel = 0;
3321
3322 const VkPipelineColorBlendStateCreateInfo *vkblend =
3323 radv_pipeline_get_color_blend_state(pCreateInfo);
3324 if (vkblend) {
3325 for (unsigned i = 0; i < subpass->color_count; i++) {
3326 if (!vkblend->pAttachments[i].colorWriteMask)
3327 continue;
3328
3329 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3330 continue;
3331
3332 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3333 color_bytes_per_pixel += vk_format_get_blocksize(format);
3334 }
3335
3336 /* MSAA images typically don't use all samples all the time. */
3337 if (effective_samples >= 2 && ps_iter_samples <= 1)
3338 effective_samples = 2;
3339 color_bytes_per_pixel *= effective_samples;
3340 }
3341
3342 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3343 while(color_entry[1].bpp <= color_bytes_per_pixel)
3344 ++color_entry;
3345
3346 extent = color_entry->extent;
3347
3348 if (subpass->depth_stencil_attachment) {
3349 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3350
3351 /* Coefficients taken from AMDVLK */
3352 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3353 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3354 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3355
3356 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3357 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3358 ++ds_entry;
3359
3360 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3361 extent = ds_entry->extent;
3362 }
3363
3364 return extent;
3365 }
3366
3367 static VkExtent2D
3368 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3369 {
3370 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3371 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3372 VkExtent2D extent = {512, 512};
3373
3374 const unsigned db_tag_size = 64;
3375 const unsigned db_tag_count = 312;
3376 const unsigned color_tag_size = 1024;
3377 const unsigned color_tag_count = 31;
3378 const unsigned fmask_tag_size = 256;
3379 const unsigned fmask_tag_count = 44;
3380
3381 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3382 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3383
3384 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3385 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3386 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3387
3388 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3389 const unsigned samples_log = util_logbase2_ceil(total_samples);
3390
3391 unsigned color_bytes_per_pixel = 0;
3392 unsigned fmask_bytes_per_pixel = 0;
3393
3394 const VkPipelineColorBlendStateCreateInfo *vkblend =
3395 radv_pipeline_get_color_blend_state(pCreateInfo);
3396 if (vkblend) {
3397 for (unsigned i = 0; i < subpass->color_count; i++) {
3398 if (!vkblend->pAttachments[i].colorWriteMask)
3399 continue;
3400
3401 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3402 continue;
3403
3404 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3405 color_bytes_per_pixel += vk_format_get_blocksize(format);
3406
3407 if (total_samples > 1) {
3408 assert(samples_log <= 3);
3409 const unsigned fmask_array[] = {0, 1, 1, 4};
3410 fmask_bytes_per_pixel += fmask_array[samples_log];
3411 }
3412 }
3413
3414 color_bytes_per_pixel *= total_samples;
3415 }
3416 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3417
3418 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3419 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3420 extent.height = 1ull << (color_pixel_count_log / 2);
3421
3422 if (fmask_bytes_per_pixel) {
3423 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3424
3425 const VkExtent2D fmask_extent = (VkExtent2D){
3426 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3427 .height = 1ull << (color_pixel_count_log / 2)
3428 };
3429
3430 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3431 extent = fmask_extent;
3432 }
3433
3434 if (subpass->depth_stencil_attachment) {
3435 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3436
3437 /* Coefficients taken from AMDVLK */
3438 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3439 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3440 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3441
3442 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3443
3444 const VkExtent2D db_extent = (VkExtent2D){
3445 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3446 .height = 1ull << (color_pixel_count_log / 2)
3447 };
3448
3449 if (db_extent.width * db_extent.height < extent.width * extent.height)
3450 extent = db_extent;
3451 }
3452
3453 extent.width = MAX2(extent.width, 128);
3454 extent.height = MAX2(extent.width, 64);
3455
3456 return extent;
3457 }
3458
3459 static void
3460 radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline,
3461 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3462 {
3463 uint32_t pa_sc_binner_cntl_0 =
3464 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3465 S_028C44_DISABLE_START_OF_PRIM(1);
3466 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3467
3468 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3469 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3470 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3471 const VkPipelineColorBlendStateCreateInfo *vkblend =
3472 radv_pipeline_get_color_blend_state(pCreateInfo);
3473 unsigned min_bytes_per_pixel = 0;
3474
3475 if (vkblend) {
3476 for (unsigned i = 0; i < subpass->color_count; i++) {
3477 if (!vkblend->pAttachments[i].colorWriteMask)
3478 continue;
3479
3480 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3481 continue;
3482
3483 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3484 unsigned bytes = vk_format_get_blocksize(format);
3485 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3486 min_bytes_per_pixel = bytes;
3487 }
3488 }
3489
3490 pa_sc_binner_cntl_0 =
3491 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3492 S_028C44_BIN_SIZE_X(0) |
3493 S_028C44_BIN_SIZE_Y(0) |
3494 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3495 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3496 S_028C44_DISABLE_START_OF_PRIM(1);
3497 }
3498
3499 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3500 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3501 }
3502
3503 struct radv_binning_settings
3504 radv_get_binning_settings(const struct radv_physical_device *pdev)
3505 {
3506 struct radv_binning_settings settings;
3507 if (pdev->rad_info.has_dedicated_vram) {
3508 if (pdev->rad_info.num_render_backends > 4) {
3509 settings.context_states_per_bin = 1;
3510 settings.persistent_states_per_bin = 1;
3511 } else {
3512 settings.context_states_per_bin = 3;
3513 settings.persistent_states_per_bin = 8;
3514 }
3515 settings.fpovs_per_batch = 63;
3516 } else {
3517 /* The context states are affected by the scissor bug. */
3518 settings.context_states_per_bin = 6;
3519 /* 32 causes hangs for RAVEN. */
3520 settings.persistent_states_per_bin = 16;
3521 settings.fpovs_per_batch = 63;
3522 }
3523
3524 if (pdev->rad_info.has_gfx9_scissor_bug)
3525 settings.context_states_per_bin = 1;
3526
3527 return settings;
3528 }
3529
3530 static void
3531 radv_pipeline_init_binning_state(struct radv_pipeline *pipeline,
3532 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3533 const struct radv_blend_state *blend)
3534 {
3535 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3536 return;
3537
3538 VkExtent2D bin_size;
3539 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3540 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3541 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3542 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3543 } else
3544 unreachable("Unhandled generation for binning bin size calculation");
3545
3546 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3547 struct radv_binning_settings settings =
3548 radv_get_binning_settings(pipeline->device->physical_device);
3549
3550 bool disable_start_of_prim = true;
3551 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3552
3553 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3554
3555 if (pipeline->device->dfsm_allowed && ps &&
3556 !ps->info.ps.can_discard &&
3557 !ps->info.ps.writes_memory &&
3558 blend->cb_target_enabled_4bit) {
3559 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3560 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3561 }
3562
3563 const uint32_t pa_sc_binner_cntl_0 =
3564 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3565 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3566 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3567 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3568 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3569 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3570 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3571 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3572 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3573 S_028C44_OPTIMAL_BIN_SELECTION(1);
3574
3575 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3576 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3577 } else
3578 radv_pipeline_init_disabled_binning_state(pipeline, pCreateInfo);
3579 }
3580
3581
3582 static void
3583 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3584 const struct radv_pipeline *pipeline,
3585 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3586 const struct radv_graphics_pipeline_create_info *extra)
3587 {
3588 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3589 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3590 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3591 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3592 struct radv_render_pass_attachment *attachment = NULL;
3593 uint32_t db_render_control = 0, db_render_override2 = 0;
3594 uint32_t db_render_override = 0;
3595
3596 if (subpass->depth_stencil_attachment)
3597 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3598
3599 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3600
3601 if (vkds && has_depth_attachment) {
3602 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3603 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3604
3605 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3606 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3607 }
3608
3609 if (attachment && extra) {
3610 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3611 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3612
3613 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3614 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3615 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3616 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3617 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3618 }
3619
3620 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3621 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3622
3623 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3624 ps->info.ps.writes_z) {
3625 /* From VK_EXT_depth_range_unrestricted spec:
3626 *
3627 * "The behavior described in Primitive Clipping still applies.
3628 * If depth clamping is disabled the depth values are still
3629 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3630 * depth clamping is enabled the above equation is ignored and
3631 * the depth values are instead clamped to the VkViewport
3632 * minDepth and maxDepth values, which in the case of this
3633 * extension can be outside of the 0.0 to 1.0 range."
3634 */
3635 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3636 }
3637
3638 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3639 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3640 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3641 }
3642
3643 static void
3644 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3645 const struct radv_pipeline *pipeline,
3646 const struct radv_blend_state *blend)
3647 {
3648 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3649 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3650 8);
3651 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3652 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3653
3654 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3655
3656 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3657 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3658 }
3659
3660 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3661
3662 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3663 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3664 }
3665
3666 static void
3667 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3668 const struct radv_pipeline *pipeline,
3669 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3670 {
3671 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3672 const VkConservativeRasterizationModeEXT mode =
3673 radv_get_conservative_raster_mode(vkraster);
3674 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3675 bool depth_clip_disable = vkraster->depthClampEnable;
3676
3677 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3678 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3679 if (depth_clip_state) {
3680 depth_clip_disable = !depth_clip_state->depthClipEnable;
3681 }
3682
3683 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3684 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3685 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3686 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3687 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3688 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3689
3690 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3691 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3692
3693 /* Conservative rasterization. */
3694 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3695 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3696 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3697 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3698
3699 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3700 pa_sc_conservative_rast |=
3701 S_028C4C_OVER_RAST_ENABLE(1) |
3702 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3703 S_028C4C_UNDER_RAST_ENABLE(0) |
3704 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3705 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3706 } else {
3707 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3708 pa_sc_conservative_rast |=
3709 S_028C4C_OVER_RAST_ENABLE(0) |
3710 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3711 S_028C4C_UNDER_RAST_ENABLE(1) |
3712 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3713 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3714 }
3715 }
3716
3717 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3718 pa_sc_conservative_rast);
3719 }
3720
3721
3722 static void
3723 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3724 const struct radv_pipeline *pipeline)
3725 {
3726 const struct radv_multisample_state *ms = &pipeline->graphics.ms;
3727
3728 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3729 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3730 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3731
3732 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3733 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3734 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3735 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3736
3737 /* The exclusion bits can be set to improve rasterization efficiency
3738 * if no sample lies on the pixel boundary (-8 sample offset). It's
3739 * currently always TRUE because the driver doesn't support 16 samples.
3740 */
3741 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3742 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3743 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3744 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3745
3746 /* GFX9: Flush DFSM when the AA mode changes. */
3747 if (pipeline->device->dfsm_allowed) {
3748 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3749 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3750 }
3751 }
3752
3753 static void
3754 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3755 const struct radv_pipeline *pipeline)
3756 {
3757 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3758 const struct radv_shader_variant *vs =
3759 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3760 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3761 pipeline->shaders[MESA_SHADER_VERTEX];
3762 unsigned vgt_primitiveid_en = 0;
3763 uint32_t vgt_gs_mode = 0;
3764
3765 if (radv_pipeline_has_ngg(pipeline))
3766 return;
3767
3768 if (radv_pipeline_has_gs(pipeline)) {
3769 const struct radv_shader_variant *gs =
3770 pipeline->shaders[MESA_SHADER_GEOMETRY];
3771
3772 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3773 pipeline->device->physical_device->rad_info.chip_class);
3774 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3775 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3776 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3777 }
3778
3779 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3780 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3781 }
3782
3783 static void
3784 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3785 struct radeon_cmdbuf *cs,
3786 const struct radv_pipeline *pipeline,
3787 const struct radv_shader_variant *shader)
3788 {
3789 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3790
3791 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3792 radeon_emit(cs, va >> 8);
3793 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3794 radeon_emit(cs, shader->config.rsrc1);
3795 radeon_emit(cs, shader->config.rsrc2);
3796
3797 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3798 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3799 clip_dist_mask = outinfo->clip_dist_mask;
3800 cull_dist_mask = outinfo->cull_dist_mask;
3801 total_mask = clip_dist_mask | cull_dist_mask;
3802 bool misc_vec_ena = outinfo->writes_pointsize ||
3803 outinfo->writes_layer ||
3804 outinfo->writes_viewport_index;
3805 unsigned spi_vs_out_config, nparams;
3806
3807 /* VS is required to export at least one param. */
3808 nparams = MAX2(outinfo->param_exports, 1);
3809 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3810
3811 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3812 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3813 }
3814
3815 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3816
3817 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3818 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3819 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3820 V_02870C_SPI_SHADER_4COMP :
3821 V_02870C_SPI_SHADER_NONE) |
3822 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3823 V_02870C_SPI_SHADER_4COMP :
3824 V_02870C_SPI_SHADER_NONE) |
3825 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3826 V_02870C_SPI_SHADER_4COMP :
3827 V_02870C_SPI_SHADER_NONE));
3828
3829 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3830 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3831 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3832 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3833 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3834 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3835 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3836 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3837 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3838 cull_dist_mask << 8 |
3839 clip_dist_mask);
3840
3841 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3842 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3843 outinfo->writes_viewport_index);
3844 }
3845
3846 static void
3847 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3848 const struct radv_pipeline *pipeline,
3849 const struct radv_shader_variant *shader)
3850 {
3851 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3852
3853 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3854 radeon_emit(cs, va >> 8);
3855 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3856 radeon_emit(cs, shader->config.rsrc1);
3857 radeon_emit(cs, shader->config.rsrc2);
3858 }
3859
3860 static void
3861 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3862 const struct radv_pipeline *pipeline,
3863 const struct radv_shader_variant *shader)
3864 {
3865 unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
3866 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3867 uint32_t rsrc2 = shader->config.rsrc2;
3868
3869 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3870 radeon_emit(cs, va >> 8);
3871 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3872
3873 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks);
3874 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3875 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3876 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3877
3878 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3879 radeon_emit(cs, shader->config.rsrc1);
3880 radeon_emit(cs, rsrc2);
3881 }
3882
3883 static void
3884 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3885 struct radeon_cmdbuf *cs,
3886 const struct radv_pipeline *pipeline,
3887 const struct radv_shader_variant *shader)
3888 {
3889 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3890 gl_shader_stage es_type =
3891 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3892 struct radv_shader_variant *es =
3893 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3894 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3895
3896 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3897 radeon_emit(cs, va >> 8);
3898 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3899 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3900 radeon_emit(cs, shader->config.rsrc1);
3901 radeon_emit(cs, shader->config.rsrc2);
3902
3903 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3904 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3905 clip_dist_mask = outinfo->clip_dist_mask;
3906 cull_dist_mask = outinfo->cull_dist_mask;
3907 total_mask = clip_dist_mask | cull_dist_mask;
3908 bool misc_vec_ena = outinfo->writes_pointsize ||
3909 outinfo->writes_layer ||
3910 outinfo->writes_viewport_index;
3911 bool es_enable_prim_id = outinfo->export_prim_id ||
3912 (es && es->info.uses_prim_id);
3913 bool break_wave_at_eoi = false;
3914 unsigned ge_cntl;
3915 unsigned nparams;
3916
3917 if (es_type == MESA_SHADER_TESS_EVAL) {
3918 struct radv_shader_variant *gs =
3919 pipeline->shaders[MESA_SHADER_GEOMETRY];
3920
3921 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3922 break_wave_at_eoi = true;
3923 }
3924
3925 nparams = MAX2(outinfo->param_exports, 1);
3926 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3927 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3928 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3929
3930 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3931 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3932 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3933 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3934 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3935 V_02870C_SPI_SHADER_4COMP :
3936 V_02870C_SPI_SHADER_NONE) |
3937 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3938 V_02870C_SPI_SHADER_4COMP :
3939 V_02870C_SPI_SHADER_NONE) |
3940 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3941 V_02870C_SPI_SHADER_4COMP :
3942 V_02870C_SPI_SHADER_NONE));
3943
3944 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3945 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3946 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3947 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3948 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3949 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3950 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3951 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3952 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3953 cull_dist_mask << 8 |
3954 clip_dist_mask);
3955
3956 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3957 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3958 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
3959
3960 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3961 ngg_state->vgt_esgs_ring_itemsize);
3962
3963 /* NGG specific registers. */
3964 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3965 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3966
3967 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3968 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3969 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3970 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3971 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3972 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3973 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3974 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3975 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3976 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3977 S_028B90_CNT(gs_num_invocations) |
3978 S_028B90_ENABLE(gs_num_invocations > 1) |
3979 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3980
3981 /* User edge flags are set by the pos exports. If user edge flags are
3982 * not used, we must use hw-generated edge flags and pass them via
3983 * the prim export to prevent drawing lines on internal edges of
3984 * decomposed primitives (such as quads) with polygon mode = lines.
3985 *
3986 * TODO: We should combine hw-generated edge flags with user edge
3987 * flags in the shader.
3988 */
3989 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3990 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3991 !radv_pipeline_has_gs(pipeline)) |
3992 /* Reuse for NGG. */
3993 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
3994
3995 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3996 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
3997 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3998
3999 /* Bug workaround for a possible hang with non-tessellation cases.
4000 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4001 *
4002 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4003 */
4004 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4005 !radv_pipeline_has_tess(pipeline) &&
4006 ngg_state->hw_max_esverts != 256) {
4007 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4008
4009 if (ngg_state->hw_max_esverts > 5) {
4010 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4011 }
4012 }
4013
4014 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4015 }
4016
4017 static void
4018 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4019 const struct radv_pipeline *pipeline,
4020 const struct radv_shader_variant *shader)
4021 {
4022 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4023
4024 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4025 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4026 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4027 radeon_emit(cs, va >> 8);
4028 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4029 } else {
4030 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4031 radeon_emit(cs, va >> 8);
4032 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4033 }
4034
4035 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4036 radeon_emit(cs, shader->config.rsrc1);
4037 radeon_emit(cs, shader->config.rsrc2);
4038 } else {
4039 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4040 radeon_emit(cs, va >> 8);
4041 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4042 radeon_emit(cs, shader->config.rsrc1);
4043 radeon_emit(cs, shader->config.rsrc2);
4044 }
4045 }
4046
4047 static void
4048 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4049 struct radeon_cmdbuf *cs,
4050 const struct radv_pipeline *pipeline)
4051 {
4052 struct radv_shader_variant *vs;
4053
4054 /* Skip shaders merged into HS/GS */
4055 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4056 if (!vs)
4057 return;
4058
4059 if (vs->info.vs.as_ls)
4060 radv_pipeline_generate_hw_ls(cs, pipeline, vs);
4061 else if (vs->info.vs.as_es)
4062 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4063 else if (vs->info.is_ngg)
4064 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4065 else
4066 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4067 }
4068
4069 static void
4070 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4071 struct radeon_cmdbuf *cs,
4072 const struct radv_pipeline *pipeline)
4073 {
4074 struct radv_shader_variant *tes, *tcs;
4075
4076 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4077 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4078
4079 if (tes) {
4080 if (tes->info.is_ngg) {
4081 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4082 } else if (tes->info.tes.as_es)
4083 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4084 else
4085 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4086 }
4087
4088 radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
4089
4090 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4091 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4092 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4093 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4094 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4095 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4096 }
4097 }
4098
4099 static void
4100 radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
4101 const struct radv_pipeline *pipeline,
4102 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4103 {
4104 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
4105 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
4106 unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches;
4107 unsigned ls_hs_config;
4108
4109 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
4110 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
4111 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4112
4113 ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
4114 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
4115 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
4116
4117 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4118 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4119 2, ls_hs_config);
4120 } else {
4121 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4122 ls_hs_config);
4123 }
4124
4125 switch (tes->info.tes.primitive_mode) {
4126 case GL_TRIANGLES:
4127 type = V_028B6C_TESS_TRIANGLE;
4128 break;
4129 case GL_QUADS:
4130 type = V_028B6C_TESS_QUAD;
4131 break;
4132 case GL_ISOLINES:
4133 type = V_028B6C_TESS_ISOLINE;
4134 break;
4135 }
4136
4137 switch (tes->info.tes.spacing) {
4138 case TESS_SPACING_EQUAL:
4139 partitioning = V_028B6C_PART_INTEGER;
4140 break;
4141 case TESS_SPACING_FRACTIONAL_ODD:
4142 partitioning = V_028B6C_PART_FRAC_ODD;
4143 break;
4144 case TESS_SPACING_FRACTIONAL_EVEN:
4145 partitioning = V_028B6C_PART_FRAC_EVEN;
4146 break;
4147 default:
4148 break;
4149 }
4150
4151 bool ccw = tes->info.tes.ccw;
4152 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
4153 vk_find_struct_const(pCreateInfo->pTessellationState,
4154 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
4155
4156 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
4157 ccw = !ccw;
4158
4159 if (tes->info.tes.point_mode)
4160 topology = V_028B6C_OUTPUT_POINT;
4161 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
4162 topology = V_028B6C_OUTPUT_LINE;
4163 else if (ccw)
4164 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
4165 else
4166 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
4167
4168 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
4169 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
4170 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
4171 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
4172 else
4173 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
4174 } else
4175 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
4176
4177 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4178 S_028B6C_TYPE(type) |
4179 S_028B6C_PARTITIONING(partitioning) |
4180 S_028B6C_TOPOLOGY(topology) |
4181 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
4182 }
4183
4184 static void
4185 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4186 struct radeon_cmdbuf *cs,
4187 const struct radv_pipeline *pipeline,
4188 const struct radv_shader_variant *gs)
4189 {
4190 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4191 unsigned gs_max_out_vertices;
4192 const uint8_t *num_components;
4193 uint8_t max_stream;
4194 unsigned offset;
4195 uint64_t va;
4196
4197 gs_max_out_vertices = gs->info.gs.vertices_out;
4198 max_stream = gs->info.gs.max_stream;
4199 num_components = gs->info.gs.num_stream_output_components;
4200
4201 offset = num_components[0] * gs_max_out_vertices;
4202
4203 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4204 radeon_emit(ctx_cs, offset);
4205 if (max_stream >= 1)
4206 offset += num_components[1] * gs_max_out_vertices;
4207 radeon_emit(ctx_cs, offset);
4208 if (max_stream >= 2)
4209 offset += num_components[2] * gs_max_out_vertices;
4210 radeon_emit(ctx_cs, offset);
4211 if (max_stream >= 3)
4212 offset += num_components[3] * gs_max_out_vertices;
4213 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4214
4215 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4216 radeon_emit(ctx_cs, num_components[0]);
4217 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4218 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4219 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4220
4221 uint32_t gs_num_invocations = gs->info.gs.invocations;
4222 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4223 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4224 S_028B90_ENABLE(gs_num_invocations > 0));
4225
4226 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4227 gs_state->vgt_esgs_ring_itemsize);
4228
4229 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4230
4231 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4232 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4233 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4234 radeon_emit(cs, va >> 8);
4235 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4236 } else {
4237 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4238 radeon_emit(cs, va >> 8);
4239 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4240 }
4241
4242 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4243 radeon_emit(cs, gs->config.rsrc1);
4244 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4245
4246 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4247 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4248 } else {
4249 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4250 radeon_emit(cs, va >> 8);
4251 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4252 radeon_emit(cs, gs->config.rsrc1);
4253 radeon_emit(cs, gs->config.rsrc2);
4254 }
4255
4256 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4257 }
4258
4259 static void
4260 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4261 struct radeon_cmdbuf *cs,
4262 const struct radv_pipeline *pipeline)
4263 {
4264 struct radv_shader_variant *gs;
4265
4266 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4267 if (!gs)
4268 return;
4269
4270 if (gs->info.is_ngg)
4271 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4272 else
4273 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4274
4275 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4276 gs->info.gs.vertices_out);
4277 }
4278
4279 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4280 bool explicit, bool float16)
4281 {
4282 uint32_t ps_input_cntl;
4283 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4284 ps_input_cntl = S_028644_OFFSET(offset);
4285 if (flat_shade || explicit)
4286 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4287 if (explicit) {
4288 /* Force parameter cache to be read in passthrough
4289 * mode.
4290 */
4291 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4292 }
4293 if (float16) {
4294 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4295 S_028644_ATTR0_VALID(1);
4296 }
4297 } else {
4298 /* The input is a DEFAULT_VAL constant. */
4299 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4300 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4301 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4302 ps_input_cntl = S_028644_OFFSET(0x20) |
4303 S_028644_DEFAULT_VAL(offset);
4304 }
4305 return ps_input_cntl;
4306 }
4307
4308 static void
4309 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4310 const struct radv_pipeline *pipeline)
4311 {
4312 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4313 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4314 uint32_t ps_input_cntl[32];
4315
4316 unsigned ps_offset = 0;
4317
4318 if (ps->info.ps.prim_id_input) {
4319 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4320 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4321 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4322 ++ps_offset;
4323 }
4324 }
4325
4326 if (ps->info.ps.layer_input ||
4327 ps->info.needs_multiview_view_index) {
4328 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4329 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4330 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4331 else
4332 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4333 ++ps_offset;
4334 }
4335
4336 if (ps->info.ps.viewport_index_input) {
4337 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4338 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4339 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4340 else
4341 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4342 ++ps_offset;
4343 }
4344
4345 if (ps->info.ps.has_pcoord) {
4346 unsigned val;
4347 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4348 ps_input_cntl[ps_offset] = val;
4349 ps_offset++;
4350 }
4351
4352 if (ps->info.ps.num_input_clips_culls) {
4353 unsigned vs_offset;
4354
4355 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4356 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4357 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4358 ++ps_offset;
4359 }
4360
4361 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4362 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4363 ps->info.ps.num_input_clips_culls > 4) {
4364 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4365 ++ps_offset;
4366 }
4367 }
4368
4369 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4370 unsigned vs_offset;
4371 bool flat_shade;
4372 bool explicit;
4373 bool float16;
4374 if (!(ps->info.ps.input_mask & (1u << i)))
4375 continue;
4376
4377 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4378 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4379 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4380 ++ps_offset;
4381 continue;
4382 }
4383
4384 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4385 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4386 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4387
4388 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4389 ++ps_offset;
4390 }
4391
4392 if (ps_offset) {
4393 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4394 for (unsigned i = 0; i < ps_offset; i++) {
4395 radeon_emit(ctx_cs, ps_input_cntl[i]);
4396 }
4397 }
4398 }
4399
4400 static uint32_t
4401 radv_compute_db_shader_control(const struct radv_device *device,
4402 const struct radv_pipeline *pipeline,
4403 const struct radv_shader_variant *ps)
4404 {
4405 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4406 unsigned z_order;
4407 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4408 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4409 else
4410 z_order = V_02880C_LATE_Z;
4411
4412 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4413 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4414 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4415 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4416
4417 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4418 !device->physical_device->rad_info.rbplus_allowed;
4419
4420 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4421 * but this appears to break Project Cars (DXVK). See
4422 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4423 */
4424 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4425
4426 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4427 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4428 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4429 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4430 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4431 S_02880C_Z_ORDER(z_order) |
4432 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4433 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4434 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4435 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4436 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4437 }
4438
4439 static void
4440 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4441 struct radeon_cmdbuf *cs,
4442 struct radv_pipeline *pipeline)
4443 {
4444 struct radv_shader_variant *ps;
4445 uint64_t va;
4446 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4447
4448 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4449 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4450
4451 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4452 radeon_emit(cs, va >> 8);
4453 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4454 radeon_emit(cs, ps->config.rsrc1);
4455 radeon_emit(cs, ps->config.rsrc2);
4456
4457 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4458 radv_compute_db_shader_control(pipeline->device,
4459 pipeline, ps));
4460
4461 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4462 ps->config.spi_ps_input_ena);
4463
4464 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4465 ps->config.spi_ps_input_addr);
4466
4467 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4468 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4469 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4470
4471 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4472
4473 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4474 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4475 ps->info.ps.writes_stencil,
4476 ps->info.ps.writes_sample_mask));
4477
4478 if (pipeline->device->dfsm_allowed) {
4479 /* optimise this? */
4480 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4481 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4482 }
4483 }
4484
4485 static void
4486 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4487 const struct radv_pipeline *pipeline)
4488 {
4489 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4490 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4491 return;
4492
4493 unsigned vtx_reuse_depth = 30;
4494 if (radv_pipeline_has_tess(pipeline) &&
4495 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4496 vtx_reuse_depth = 14;
4497 }
4498 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4499 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4500 }
4501
4502 static void
4503 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
4504 const struct radv_pipeline *pipeline)
4505 {
4506 uint32_t stages = 0;
4507 if (radv_pipeline_has_tess(pipeline)) {
4508 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4509 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4510
4511 if (radv_pipeline_has_gs(pipeline))
4512 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4513 S_028B54_GS_EN(1);
4514 else if (radv_pipeline_has_ngg(pipeline))
4515 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4516 else
4517 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4518 } else if (radv_pipeline_has_gs(pipeline)) {
4519 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4520 S_028B54_GS_EN(1);
4521 } else if (radv_pipeline_has_ngg(pipeline)) {
4522 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4523 }
4524
4525 if (radv_pipeline_has_ngg(pipeline)) {
4526 stages |= S_028B54_PRIMGEN_EN(1);
4527 if (pipeline->streamout_shader)
4528 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4529 if (radv_pipeline_has_ngg_passthrough(pipeline))
4530 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4531 } else if (radv_pipeline_has_gs(pipeline)) {
4532 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4533 }
4534
4535 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4536 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4537
4538 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4539 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4540
4541 if (radv_pipeline_has_tess(pipeline))
4542 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4543
4544 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4545 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4546 if (pipeline->gs_copy_shader)
4547 vs_size = pipeline->gs_copy_shader->info.wave_size;
4548 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4549 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4550 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4551 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4552
4553 if (radv_pipeline_has_ngg(pipeline))
4554 gs_size = vs_size;
4555
4556 /* legacy GS only supports Wave64 */
4557 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4558 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4559 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4560 }
4561
4562 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
4563 }
4564
4565 static void
4566 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
4567 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4568 {
4569 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4570 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4571 uint32_t cliprect_rule = 0;
4572
4573 if (!discard_rectangle_info) {
4574 cliprect_rule = 0xffff;
4575 } else {
4576 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4577 /* Interpret i as a bitmask, and then set the bit in
4578 * the mask if that combination of rectangles in which
4579 * the pixel is contained should pass the cliprect
4580 * test.
4581 */
4582 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4583
4584 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4585 !relevant_subset)
4586 continue;
4587
4588 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4589 relevant_subset)
4590 continue;
4591
4592 cliprect_rule |= 1u << i;
4593 }
4594 }
4595
4596 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule);
4597 }
4598
4599 static void
4600 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4601 struct radv_pipeline *pipeline)
4602 {
4603 bool break_wave_at_eoi = false;
4604 unsigned primgroup_size;
4605 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4606
4607 if (radv_pipeline_has_tess(pipeline)) {
4608 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4609 } else if (radv_pipeline_has_gs(pipeline)) {
4610 const struct gfx9_gs_info *gs_state =
4611 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4612 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4613 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4614 } else {
4615 primgroup_size = 128; /* recommended without a GS and tess */
4616 }
4617
4618 if (radv_pipeline_has_tess(pipeline)) {
4619 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4620 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4621 break_wave_at_eoi = true;
4622 }
4623
4624 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4625 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4626 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4627 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4628 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4629 }
4630
4631 static void
4632 radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
4633 const struct radv_pipeline *pipeline,
4634 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4635 const struct radv_graphics_pipeline_create_info *extra)
4636 {
4637 uint32_t gs_out;
4638
4639 if (radv_pipeline_has_gs(pipeline)) {
4640 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4641 } else if (radv_pipeline_has_tess(pipeline)) {
4642 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
4643 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4644 } else {
4645 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4646 }
4647 } else {
4648 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4649 }
4650
4651 if (extra && extra->use_rectlist) {
4652 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4653 if (radv_pipeline_has_ngg(pipeline))
4654 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4655 }
4656
4657 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4658 }
4659
4660 static void
4661 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4662 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4663 const struct radv_graphics_pipeline_create_info *extra,
4664 const struct radv_blend_state *blend)
4665 {
4666 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4667 struct radeon_cmdbuf *cs = &pipeline->cs;
4668
4669 cs->max_dw = 64;
4670 ctx_cs->max_dw = 256;
4671 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4672 ctx_cs->buf = cs->buf + cs->max_dw;
4673
4674 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4675 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4676 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4677 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4678 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4679 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline);
4680
4681 if (radv_pipeline_has_tess(pipeline)) {
4682 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline);
4683 radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo);
4684 }
4685
4686 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4687 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4688 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4689 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4690 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline);
4691 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
4692 radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra);
4693
4694 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4695 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
4696
4697 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4698
4699 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4700 assert(cs->cdw <= cs->max_dw);
4701 }
4702
4703 static struct radv_ia_multi_vgt_param_helpers
4704 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
4705 {
4706 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4707 const struct radv_device *device = pipeline->device;
4708
4709 if (radv_pipeline_has_tess(pipeline))
4710 ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4711 else if (radv_pipeline_has_gs(pipeline))
4712 ia_multi_vgt_param.primgroup_size = 64;
4713 else
4714 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4715
4716 /* GS requirement. */
4717 ia_multi_vgt_param.partial_es_wave = false;
4718 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4719 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4720 ia_multi_vgt_param.partial_es_wave = true;
4721
4722 ia_multi_vgt_param.ia_switch_on_eoi = false;
4723 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4724 ia_multi_vgt_param.ia_switch_on_eoi = true;
4725 if (radv_pipeline_has_gs(pipeline) &&
4726 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4727 ia_multi_vgt_param.ia_switch_on_eoi = true;
4728 if (radv_pipeline_has_tess(pipeline)) {
4729 /* SWITCH_ON_EOI must be set if PrimID is used. */
4730 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4731 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4732 ia_multi_vgt_param.ia_switch_on_eoi = true;
4733 }
4734
4735 ia_multi_vgt_param.partial_vs_wave = false;
4736 if (radv_pipeline_has_tess(pipeline)) {
4737 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4738 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4739 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4740 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4741 radv_pipeline_has_gs(pipeline))
4742 ia_multi_vgt_param.partial_vs_wave = true;
4743 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4744 if (device->physical_device->rad_info.has_distributed_tess) {
4745 if (radv_pipeline_has_gs(pipeline)) {
4746 if (device->physical_device->rad_info.chip_class <= GFX8)
4747 ia_multi_vgt_param.partial_es_wave = true;
4748 } else {
4749 ia_multi_vgt_param.partial_vs_wave = true;
4750 }
4751 }
4752 }
4753
4754 if (radv_pipeline_has_gs(pipeline)) {
4755 /* On these chips there is the possibility of a hang if the
4756 * pipeline uses a GS and partial_vs_wave is not set.
4757 *
4758 * This mostly does not hit 4-SE chips, as those typically set
4759 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4760 * with GS due to another workaround.
4761 *
4762 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4763 */
4764 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4765 device->physical_device->rad_info.family == CHIP_FIJI ||
4766 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4767 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4768 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4769 device->physical_device->rad_info.family == CHIP_VEGAM) {
4770 ia_multi_vgt_param.partial_vs_wave = true;
4771 }
4772 }
4773
4774 ia_multi_vgt_param.base =
4775 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4776 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4777 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4778 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4779 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4780
4781 return ia_multi_vgt_param;
4782 }
4783
4784
4785 static void
4786 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4787 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4788 {
4789 const VkPipelineVertexInputStateCreateInfo *vi_info =
4790 pCreateInfo->pVertexInputState;
4791
4792 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4793 const VkVertexInputBindingDescription *desc =
4794 &vi_info->pVertexBindingDescriptions[i];
4795
4796 pipeline->binding_stride[desc->binding] = desc->stride;
4797 pipeline->num_vertex_bindings =
4798 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4799 }
4800 }
4801
4802 static struct radv_shader_variant *
4803 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4804 {
4805 int i;
4806
4807 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4808 struct radv_shader_variant *shader =
4809 radv_get_shader(pipeline, i);
4810
4811 if (shader && shader->info.so.num_outputs > 0)
4812 return shader;
4813 }
4814
4815 return NULL;
4816 }
4817
4818 static void
4819 radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline)
4820 {
4821 struct radv_device *device = pipeline->device;
4822
4823 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4824 pipeline->user_data_0[i] =
4825 radv_pipeline_stage_to_user_data_0(pipeline, i,
4826 device->physical_device->rad_info.chip_class);
4827
4828 if (pipeline->shaders[i]) {
4829 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4830 }
4831 }
4832
4833 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4834 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4835 if (loc->sgpr_idx != -1) {
4836 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4837 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4838 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4839 pipeline->graphics.vtx_emit_num = 3;
4840 else
4841 pipeline->graphics.vtx_emit_num = 2;
4842 }
4843 }
4844
4845 static VkResult
4846 radv_pipeline_init(struct radv_pipeline *pipeline,
4847 struct radv_device *device,
4848 struct radv_pipeline_cache *cache,
4849 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4850 const struct radv_graphics_pipeline_create_info *extra)
4851 {
4852 VkResult result;
4853
4854 pipeline->device = device;
4855 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4856 assert(pipeline->layout);
4857
4858 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4859
4860 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4861 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4862 radv_init_feedback(creation_feedback);
4863
4864 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4865
4866 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4867 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4868 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4869 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4870 pStages[stage] = &pCreateInfo->pStages[i];
4871 if(creation_feedback)
4872 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4873 }
4874
4875 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend);
4876
4877 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4878 pCreateInfo->flags, pipeline_feedback,
4879 stage_feedbacks);
4880 if (result != VK_SUCCESS)
4881 return result;
4882
4883 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4884 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4885 radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra);
4886 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4887 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
4888 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo);
4889
4890 /* Ensure that some export memory is always allocated, for two reasons:
4891 *
4892 * 1) Correctness: The hardware ignores the EXEC mask if no export
4893 * memory is allocated, so KILL and alpha test do not work correctly
4894 * without this.
4895 * 2) Performance: Every shader needs at least a NULL export, even when
4896 * it writes no color/depth output. The NULL export instruction
4897 * stalls without this setting.
4898 *
4899 * Don't add this to CB_SHADER_MASK.
4900 *
4901 * GFX10 supports pixel shaders without exports by setting both the
4902 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4903 * instructions if any are present.
4904 */
4905 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4906 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4907 ps->info.ps.can_discard) &&
4908 !blend.spi_shader_col_format) {
4909 if (!ps->info.ps.writes_z &&
4910 !ps->info.ps.writes_stencil &&
4911 !ps->info.ps.writes_sample_mask)
4912 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4913 }
4914
4915 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4916
4917 if (extra &&
4918 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4919 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4920 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4921 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4922 /* According to the CB spec states, CB_SHADER_MASK should be
4923 * set to enable writes to all four channels of MRT0.
4924 */
4925 blend.cb_shader_mask = 0xf;
4926 }
4927
4928 pipeline->graphics.col_format = blend.spi_shader_col_format;
4929 pipeline->graphics.cb_target_mask = blend.cb_target_mask;
4930
4931 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4932 struct radv_shader_variant *gs =
4933 pipeline->shaders[MESA_SHADER_GEOMETRY];
4934
4935 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4936 }
4937
4938 if (radv_pipeline_has_tess(pipeline)) {
4939 pipeline->graphics.tess_patch_control_points =
4940 pCreateInfo->pTessellationState->patchControlPoints;
4941 }
4942
4943 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline);
4944
4945 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4946
4947 radv_pipeline_init_binning_state(pipeline, pCreateInfo, &blend);
4948 radv_pipeline_init_shader_stages_state(pipeline);
4949
4950 /* Find the last vertex shader stage that eventually uses streamout. */
4951 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4952
4953 radv_pipeline_scratch_init(device, pipeline);
4954 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend);
4955
4956 return result;
4957 }
4958
4959 VkResult
4960 radv_graphics_pipeline_create(
4961 VkDevice _device,
4962 VkPipelineCache _cache,
4963 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4964 const struct radv_graphics_pipeline_create_info *extra,
4965 const VkAllocationCallbacks *pAllocator,
4966 VkPipeline *pPipeline)
4967 {
4968 RADV_FROM_HANDLE(radv_device, device, _device);
4969 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4970 struct radv_pipeline *pipeline;
4971 VkResult result;
4972
4973 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4974 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4975 if (pipeline == NULL)
4976 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4977
4978 vk_object_base_init(&device->vk, &pipeline->base,
4979 VK_OBJECT_TYPE_PIPELINE);
4980
4981 result = radv_pipeline_init(pipeline, device, cache,
4982 pCreateInfo, extra);
4983 if (result != VK_SUCCESS) {
4984 radv_pipeline_destroy(device, pipeline, pAllocator);
4985 return result;
4986 }
4987
4988 *pPipeline = radv_pipeline_to_handle(pipeline);
4989
4990 return VK_SUCCESS;
4991 }
4992
4993 VkResult radv_CreateGraphicsPipelines(
4994 VkDevice _device,
4995 VkPipelineCache pipelineCache,
4996 uint32_t count,
4997 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4998 const VkAllocationCallbacks* pAllocator,
4999 VkPipeline* pPipelines)
5000 {
5001 VkResult result = VK_SUCCESS;
5002 unsigned i = 0;
5003
5004 for (; i < count; i++) {
5005 VkResult r;
5006 r = radv_graphics_pipeline_create(_device,
5007 pipelineCache,
5008 &pCreateInfos[i],
5009 NULL, pAllocator, &pPipelines[i]);
5010 if (r != VK_SUCCESS) {
5011 result = r;
5012 pPipelines[i] = VK_NULL_HANDLE;
5013
5014 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5015 break;
5016 }
5017 }
5018
5019 for (; i < count; ++i)
5020 pPipelines[i] = VK_NULL_HANDLE;
5021
5022 return result;
5023 }
5024
5025 static void
5026 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs,
5027 const struct radv_pipeline *pipeline)
5028 {
5029 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5030 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
5031 struct radv_device *device = pipeline->device;
5032
5033 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
5034 radeon_emit(cs, va >> 8);
5035 radeon_emit(cs, S_00B834_DATA(va >> 40));
5036
5037 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5038 radeon_emit(cs, shader->config.rsrc1);
5039 radeon_emit(cs, shader->config.rsrc2);
5040 if (device->physical_device->rad_info.chip_class >= GFX10) {
5041 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
5042 }
5043 }
5044
5045 static void
5046 radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs,
5047 const struct radv_pipeline *pipeline)
5048 {
5049 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5050 struct radv_device *device = pipeline->device;
5051 unsigned threads_per_threadgroup;
5052 unsigned threadgroups_per_cu = 1;
5053 unsigned waves_per_threadgroup;
5054 unsigned max_waves_per_sh = 0;
5055
5056 /* Calculate best compute resource limits. */
5057 threads_per_threadgroup = shader->info.cs.block_size[0] *
5058 shader->info.cs.block_size[1] *
5059 shader->info.cs.block_size[2];
5060 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5061 shader->info.wave_size);
5062
5063 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5064 waves_per_threadgroup == 1)
5065 threadgroups_per_cu = 2;
5066
5067 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5068 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5069 waves_per_threadgroup,
5070 max_waves_per_sh,
5071 threadgroups_per_cu));
5072
5073 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5074 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
5075 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
5076 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
5077 }
5078
5079 static void
5080 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5081 {
5082 struct radv_device *device = pipeline->device;
5083 struct radeon_cmdbuf *cs = &pipeline->cs;
5084
5085 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
5086 cs->buf = malloc(cs->max_dw * 4);
5087
5088 radv_pipeline_generate_hw_cs(cs, pipeline);
5089 radv_pipeline_generate_compute_state(cs, pipeline);
5090
5091 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5092 }
5093
5094 static struct radv_pipeline_key
5095 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5096 const VkComputePipelineCreateInfo *pCreateInfo)
5097 {
5098 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5099 struct radv_pipeline_key key;
5100 memset(&key, 0, sizeof(key));
5101
5102 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5103 key.optimisations_disabled = 1;
5104
5105 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5106 vk_find_struct_const(stage->pNext,
5107 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5108
5109 if (subgroup_size) {
5110 assert(subgroup_size->requiredSubgroupSize == 32 ||
5111 subgroup_size->requiredSubgroupSize == 64);
5112 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5113 }
5114
5115 return key;
5116 }
5117
5118 static VkResult radv_compute_pipeline_create(
5119 VkDevice _device,
5120 VkPipelineCache _cache,
5121 const VkComputePipelineCreateInfo* pCreateInfo,
5122 const VkAllocationCallbacks* pAllocator,
5123 VkPipeline* pPipeline)
5124 {
5125 RADV_FROM_HANDLE(radv_device, device, _device);
5126 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5127 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5128 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5129 struct radv_pipeline *pipeline;
5130 VkResult result;
5131
5132 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5133 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5134 if (pipeline == NULL)
5135 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5136
5137 vk_object_base_init(&device->vk, &pipeline->base,
5138 VK_OBJECT_TYPE_PIPELINE);
5139
5140 pipeline->device = device;
5141 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5142 assert(pipeline->layout);
5143
5144 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5145 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5146 radv_init_feedback(creation_feedback);
5147
5148 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5149 if (creation_feedback)
5150 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5151
5152 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5153
5154 struct radv_pipeline_key key =
5155 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5156
5157 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5158 pCreateInfo->flags, pipeline_feedback,
5159 stage_feedbacks);
5160 if (result != VK_SUCCESS) {
5161 radv_pipeline_destroy(device, pipeline, pAllocator);
5162 return result;
5163 }
5164
5165 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5166 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5167 radv_pipeline_scratch_init(device, pipeline);
5168
5169 radv_compute_generate_pm4(pipeline);
5170
5171 *pPipeline = radv_pipeline_to_handle(pipeline);
5172
5173 return VK_SUCCESS;
5174 }
5175
5176 VkResult radv_CreateComputePipelines(
5177 VkDevice _device,
5178 VkPipelineCache pipelineCache,
5179 uint32_t count,
5180 const VkComputePipelineCreateInfo* pCreateInfos,
5181 const VkAllocationCallbacks* pAllocator,
5182 VkPipeline* pPipelines)
5183 {
5184 VkResult result = VK_SUCCESS;
5185
5186 unsigned i = 0;
5187 for (; i < count; i++) {
5188 VkResult r;
5189 r = radv_compute_pipeline_create(_device, pipelineCache,
5190 &pCreateInfos[i],
5191 pAllocator, &pPipelines[i]);
5192 if (r != VK_SUCCESS) {
5193 result = r;
5194 pPipelines[i] = VK_NULL_HANDLE;
5195
5196 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5197 break;
5198 }
5199 }
5200
5201 for (; i < count; ++i)
5202 pPipelines[i] = VK_NULL_HANDLE;
5203
5204 return result;
5205 }
5206
5207
5208 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5209 {
5210 uint32_t ret = 0;
5211 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5212 if (!pipeline->shaders[i])
5213 continue;
5214
5215 if (i == MESA_SHADER_GEOMETRY &&
5216 !radv_pipeline_has_ngg(pipeline)) {
5217 ret += 2u;
5218 } else {
5219 ret += 1u;
5220 }
5221
5222 }
5223 return ret;
5224 }
5225
5226 static struct radv_shader_variant *
5227 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5228 {
5229 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5230 if (!pipeline->shaders[i])
5231 continue;
5232 if (!index) {
5233 *stage = i;
5234 return pipeline->shaders[i];
5235 }
5236
5237 --index;
5238
5239 if (i == MESA_SHADER_GEOMETRY &&
5240 !radv_pipeline_has_ngg(pipeline)) {
5241 if (!index) {
5242 *stage = i;
5243 return pipeline->gs_copy_shader;
5244 }
5245 --index;
5246 }
5247 }
5248
5249 *stage = -1;
5250 return NULL;
5251 }
5252
5253 /* Basically strlcpy (which does not exist on linux) specialized for
5254 * descriptions. */
5255 static void desc_copy(char *desc, const char *src) {
5256 int len = strlen(src);
5257 assert(len < VK_MAX_DESCRIPTION_SIZE);
5258 memcpy(desc, src, len);
5259 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5260 }
5261
5262 VkResult radv_GetPipelineExecutablePropertiesKHR(
5263 VkDevice _device,
5264 const VkPipelineInfoKHR* pPipelineInfo,
5265 uint32_t* pExecutableCount,
5266 VkPipelineExecutablePropertiesKHR* pProperties)
5267 {
5268 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5269 const uint32_t total_count = radv_get_executable_count(pipeline);
5270
5271 if (!pProperties) {
5272 *pExecutableCount = total_count;
5273 return VK_SUCCESS;
5274 }
5275
5276 const uint32_t count = MIN2(total_count, *pExecutableCount);
5277 for (unsigned i = 0, executable_idx = 0;
5278 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5279 if (!pipeline->shaders[i])
5280 continue;
5281 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5282 const char *name = NULL;
5283 const char *description = NULL;
5284 switch(i) {
5285 case MESA_SHADER_VERTEX:
5286 name = "Vertex Shader";
5287 description = "Vulkan Vertex Shader";
5288 break;
5289 case MESA_SHADER_TESS_CTRL:
5290 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5291 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5292 name = "Vertex + Tessellation Control Shaders";
5293 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5294 } else {
5295 name = "Tessellation Control Shader";
5296 description = "Vulkan Tessellation Control Shader";
5297 }
5298 break;
5299 case MESA_SHADER_TESS_EVAL:
5300 name = "Tessellation Evaluation Shader";
5301 description = "Vulkan Tessellation Evaluation Shader";
5302 break;
5303 case MESA_SHADER_GEOMETRY:
5304 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5305 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5306 name = "Tessellation Evaluation + Geometry Shaders";
5307 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5308 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5309 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5310 name = "Vertex + Geometry Shader";
5311 description = "Combined Vulkan Vertex and Geometry Shaders";
5312 } else {
5313 name = "Geometry Shader";
5314 description = "Vulkan Geometry Shader";
5315 }
5316 break;
5317 case MESA_SHADER_FRAGMENT:
5318 name = "Fragment Shader";
5319 description = "Vulkan Fragment Shader";
5320 break;
5321 case MESA_SHADER_COMPUTE:
5322 name = "Compute Shader";
5323 description = "Vulkan Compute Shader";
5324 break;
5325 }
5326
5327 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5328 desc_copy(pProperties[executable_idx].name, name);
5329 desc_copy(pProperties[executable_idx].description, description);
5330
5331 ++executable_idx;
5332 if (i == MESA_SHADER_GEOMETRY &&
5333 !radv_pipeline_has_ngg(pipeline)) {
5334 assert(pipeline->gs_copy_shader);
5335 if (executable_idx >= count)
5336 break;
5337
5338 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5339 pProperties[executable_idx].subgroupSize = 64;
5340 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5341 desc_copy(pProperties[executable_idx].description,
5342 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5343
5344 ++executable_idx;
5345 }
5346 }
5347
5348 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5349 *pExecutableCount = count;
5350 return result;
5351 }
5352
5353 VkResult radv_GetPipelineExecutableStatisticsKHR(
5354 VkDevice _device,
5355 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5356 uint32_t* pStatisticCount,
5357 VkPipelineExecutableStatisticKHR* pStatistics)
5358 {
5359 RADV_FROM_HANDLE(radv_device, device, _device);
5360 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5361 gl_shader_stage stage;
5362 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5363
5364 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5365 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5366 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5367
5368 VkPipelineExecutableStatisticKHR *s = pStatistics;
5369 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5370 VkResult result = VK_SUCCESS;
5371
5372 if (s < end) {
5373 desc_copy(s->name, "SGPRs");
5374 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5375 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5376 s->value.u64 = shader->config.num_sgprs;
5377 }
5378 ++s;
5379
5380 if (s < end) {
5381 desc_copy(s->name, "VGPRs");
5382 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5383 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5384 s->value.u64 = shader->config.num_vgprs;
5385 }
5386 ++s;
5387
5388 if (s < end) {
5389 desc_copy(s->name, "Spilled SGPRs");
5390 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5391 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5392 s->value.u64 = shader->config.spilled_sgprs;
5393 }
5394 ++s;
5395
5396 if (s < end) {
5397 desc_copy(s->name, "Spilled VGPRs");
5398 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5399 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5400 s->value.u64 = shader->config.spilled_vgprs;
5401 }
5402 ++s;
5403
5404 if (s < end) {
5405 desc_copy(s->name, "PrivMem VGPRs");
5406 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5407 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5408 s->value.u64 = shader->info.private_mem_vgprs;
5409 }
5410 ++s;
5411
5412 if (s < end) {
5413 desc_copy(s->name, "Code size");
5414 desc_copy(s->description, "Code size in bytes");
5415 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5416 s->value.u64 = shader->exec_size;
5417 }
5418 ++s;
5419
5420 if (s < end) {
5421 desc_copy(s->name, "LDS size");
5422 desc_copy(s->description, "LDS size in bytes per workgroup");
5423 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5424 s->value.u64 = shader->config.lds_size * lds_increment;
5425 }
5426 ++s;
5427
5428 if (s < end) {
5429 desc_copy(s->name, "Scratch size");
5430 desc_copy(s->description, "Private memory in bytes per subgroup");
5431 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5432 s->value.u64 = shader->config.scratch_bytes_per_wave;
5433 }
5434 ++s;
5435
5436 if (s < end) {
5437 desc_copy(s->name, "Subgroups per SIMD");
5438 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5439 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5440 s->value.u64 = max_waves;
5441 }
5442 ++s;
5443
5444 if (shader->statistics) {
5445 for (unsigned i = 0; i < shader->statistics->count; i++) {
5446 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5447 uint32_t value = shader->statistics->values[i];
5448 if (s < end) {
5449 desc_copy(s->name, info->name);
5450 desc_copy(s->description, info->desc);
5451 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5452 s->value.u64 = value;
5453 }
5454 ++s;
5455 }
5456 }
5457
5458 if (!pStatistics)
5459 *pStatisticCount = s - pStatistics;
5460 else if (s > end) {
5461 *pStatisticCount = end - pStatistics;
5462 result = VK_INCOMPLETE;
5463 } else {
5464 *pStatisticCount = s - pStatistics;
5465 }
5466
5467 return result;
5468 }
5469
5470 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5471 {
5472 size_t total_size = strlen(src) + 1;
5473
5474 if (!data) {
5475 *data_size = total_size;
5476 return VK_SUCCESS;
5477 }
5478
5479 size_t size = MIN2(total_size, *data_size);
5480
5481 memcpy(data, src, size);
5482 if (size)
5483 *((char*)data + size - 1) = 0;
5484 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5485 }
5486
5487 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5488 VkDevice device,
5489 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5490 uint32_t* pInternalRepresentationCount,
5491 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5492 {
5493 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5494 gl_shader_stage stage;
5495 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5496
5497 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5498 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5499 VkResult result = VK_SUCCESS;
5500 /* optimized NIR */
5501 if (p < end) {
5502 p->isText = true;
5503 desc_copy(p->name, "NIR Shader(s)");
5504 desc_copy(p->description, "The optimized NIR shader(s)");
5505 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5506 result = VK_INCOMPLETE;
5507 }
5508 ++p;
5509
5510 /* backend IR */
5511 if (p < end) {
5512 p->isText = true;
5513 if (pipeline->device->physical_device->use_llvm) {
5514 desc_copy(p->name, "LLVM IR");
5515 desc_copy(p->description, "The LLVM IR after some optimizations");
5516 } else {
5517 desc_copy(p->name, "ACO IR");
5518 desc_copy(p->description, "The ACO IR after some optimizations");
5519 }
5520 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5521 result = VK_INCOMPLETE;
5522 }
5523 ++p;
5524
5525 /* Disassembler */
5526 if (p < end) {
5527 p->isText = true;
5528 desc_copy(p->name, "Assembly");
5529 desc_copy(p->description, "Final Assembly");
5530 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5531 result = VK_INCOMPLETE;
5532 }
5533 ++p;
5534
5535 if (!pInternalRepresentations)
5536 *pInternalRepresentationCount = p - pInternalRepresentations;
5537 else if(p > end) {
5538 result = VK_INCOMPLETE;
5539 *pInternalRepresentationCount = end - pInternalRepresentations;
5540 } else {
5541 *pInternalRepresentationCount = p - pInternalRepresentations;
5542 }
5543
5544 return result;
5545 }