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ac/nir: implement 64-bit packing and unpacking
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 void radv_shader_variant_destroy(struct radv_device *device,
49 struct radv_shader_variant *variant);
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_fsat = true,
56 .lower_fdiv = true,
57 .lower_sub = true,
58 .lower_pack_snorm_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_unorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_unpack_snorm_2x16 = true,
63 .lower_unpack_snorm_4x8 = true,
64 .lower_unpack_unorm_2x16 = true,
65 .lower_unpack_unorm_4x8 = true,
66 .lower_extract_byte = true,
67 .lower_extract_word = true,
68 .max_unroll_iterations = 32
69 };
70
71 VkResult radv_CreateShaderModule(
72 VkDevice _device,
73 const VkShaderModuleCreateInfo* pCreateInfo,
74 const VkAllocationCallbacks* pAllocator,
75 VkShaderModule* pShaderModule)
76 {
77 RADV_FROM_HANDLE(radv_device, device, _device);
78 struct radv_shader_module *module;
79
80 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
81 assert(pCreateInfo->flags == 0);
82
83 module = vk_alloc2(&device->alloc, pAllocator,
84 sizeof(*module) + pCreateInfo->codeSize, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
86 if (module == NULL)
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
88
89 module->nir = NULL;
90 module->size = pCreateInfo->codeSize;
91 memcpy(module->data, pCreateInfo->pCode, module->size);
92
93 _mesa_sha1_compute(module->data, module->size, module->sha1);
94
95 *pShaderModule = radv_shader_module_to_handle(module);
96
97 return VK_SUCCESS;
98 }
99
100 void radv_DestroyShaderModule(
101 VkDevice _device,
102 VkShaderModule _module,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_shader_module, module, _module);
107
108 if (!module)
109 return;
110
111 vk_free2(&device->alloc, pAllocator, module);
112 }
113
114
115 static void
116 radv_pipeline_destroy(struct radv_device *device,
117 struct radv_pipeline *pipeline,
118 const VkAllocationCallbacks* allocator)
119 {
120 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
121 if (pipeline->shaders[i])
122 radv_shader_variant_destroy(device, pipeline->shaders[i]);
123
124 if (pipeline->gs_copy_shader)
125 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
126
127 vk_free2(&device->alloc, allocator, pipeline);
128 }
129
130 void radv_DestroyPipeline(
131 VkDevice _device,
132 VkPipeline _pipeline,
133 const VkAllocationCallbacks* pAllocator)
134 {
135 RADV_FROM_HANDLE(radv_device, device, _device);
136 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
137
138 if (!_pipeline)
139 return;
140
141 radv_pipeline_destroy(device, pipeline, pAllocator);
142 }
143
144
145 static void
146 radv_optimize_nir(struct nir_shader *shader)
147 {
148 bool progress;
149
150 do {
151 progress = false;
152
153 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
154 NIR_PASS_V(shader, nir_lower_64bit_pack);
155 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
156 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
157
158 NIR_PASS(progress, shader, nir_copy_prop);
159 NIR_PASS(progress, shader, nir_opt_remove_phis);
160 NIR_PASS(progress, shader, nir_opt_dce);
161 if (nir_opt_trivial_continues(shader)) {
162 progress = true;
163 NIR_PASS(progress, shader, nir_copy_prop);
164 NIR_PASS(progress, shader, nir_opt_dce);
165 }
166 NIR_PASS(progress, shader, nir_opt_if);
167 NIR_PASS(progress, shader, nir_opt_dead_cf);
168 NIR_PASS(progress, shader, nir_opt_cse);
169 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
170 NIR_PASS(progress, shader, nir_opt_algebraic);
171 NIR_PASS(progress, shader, nir_opt_constant_folding);
172 NIR_PASS(progress, shader, nir_opt_undef);
173 NIR_PASS(progress, shader, nir_opt_conditional_discard);
174 if (shader->options->max_unroll_iterations) {
175 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
176 }
177 } while (progress);
178 }
179
180 static nir_shader *
181 radv_shader_compile_to_nir(struct radv_device *device,
182 struct radv_shader_module *module,
183 const char *entrypoint_name,
184 gl_shader_stage stage,
185 const VkSpecializationInfo *spec_info,
186 bool dump)
187 {
188 if (strcmp(entrypoint_name, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
190 }
191
192 nir_shader *nir;
193 nir_function *entry_point;
194 if (module->nir) {
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
198 nir = module->nir;
199 nir->options = &nir_options;
200 nir_validate_shader(nir);
201
202 assert(exec_list_length(&nir->functions) == 1);
203 struct exec_node *node = exec_list_get_head(&nir->functions);
204 entry_point = exec_node_data(nir_function, node, node);
205 } else {
206 uint32_t *spirv = (uint32_t *) module->data;
207 assert(module->size % 4 == 0);
208
209 uint32_t num_spec_entries = 0;
210 struct nir_spirv_specialization *spec_entries = NULL;
211 if (spec_info && spec_info->mapEntryCount > 0) {
212 num_spec_entries = spec_info->mapEntryCount;
213 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
214 for (uint32_t i = 0; i < num_spec_entries; i++) {
215 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
216 const void *data = spec_info->pData + entry.offset;
217 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
218
219 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
220 if (spec_info->dataSize == 8)
221 spec_entries[i].data64 = *(const uint64_t *)data;
222 else
223 spec_entries[i].data32 = *(const uint32_t *)data;
224 }
225 }
226 const struct nir_spirv_supported_extensions supported_ext = {
227 .draw_parameters = true,
228 .float64 = true,
229 .image_read_without_format = true,
230 .image_write_without_format = true,
231 .tessellation = true,
232 };
233 entry_point = spirv_to_nir(spirv, module->size / 4,
234 spec_entries, num_spec_entries,
235 stage, entrypoint_name, &supported_ext, &nir_options);
236 nir = entry_point->shader;
237 assert(nir->stage == stage);
238 nir_validate_shader(nir);
239
240 free(spec_entries);
241
242 /* We have to lower away local constant initializers right before we
243 * inline functions. That way they get properly initialized at the top
244 * of the function and not at the top of its caller.
245 */
246 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
247 NIR_PASS_V(nir, nir_lower_returns);
248 NIR_PASS_V(nir, nir_inline_functions);
249
250 /* Pick off the single entrypoint that we want */
251 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
252 if (func != entry_point)
253 exec_node_remove(&func->node);
254 }
255 assert(exec_list_length(&nir->functions) == 1);
256 entry_point->name = ralloc_strdup(entry_point, "main");
257
258 NIR_PASS_V(nir, nir_remove_dead_variables,
259 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
260
261 /* Now that we've deleted all but the main function, we can go ahead and
262 * lower the rest of the constant initializers.
263 */
264 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
265 NIR_PASS_V(nir, nir_lower_system_values);
266 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
267 }
268
269 /* Vulkan uses the separate-shader linking model */
270 nir->info.separate_shader = true;
271
272 nir_shader_gather_info(nir, entry_point->impl);
273
274 nir_variable_mode indirect_mask = 0;
275 indirect_mask |= nir_var_shader_in;
276 indirect_mask |= nir_var_local;
277
278 nir_lower_indirect_derefs(nir, indirect_mask);
279
280 static const nir_lower_tex_options tex_options = {
281 .lower_txp = ~0,
282 };
283
284 nir_lower_tex(nir, &tex_options);
285
286 nir_lower_vars_to_ssa(nir);
287 nir_lower_var_copies(nir);
288 nir_lower_global_vars_to_local(nir);
289 nir_remove_dead_variables(nir, nir_var_local);
290 radv_optimize_nir(nir);
291
292 if (dump)
293 nir_print_shader(nir, stderr);
294
295 return nir;
296 }
297
298 static const char *radv_get_shader_name(struct radv_shader_variant *var,
299 gl_shader_stage stage)
300 {
301 switch (stage) {
302 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
303 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
304 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
305 case MESA_SHADER_COMPUTE: return "Compute Shader";
306 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
307 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
308 default:
309 return "Unknown shader";
310 };
311
312 }
313 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
314 {
315 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
316 struct radv_shader_variant *var;
317 struct ac_shader_config *conf;
318 int i;
319 FILE *file = stderr;
320 unsigned max_simd_waves = 10;
321 unsigned lds_per_wave = 0;
322
323 for (i = 0; i < MESA_SHADER_STAGES; i++) {
324 if (!pipeline->shaders[i])
325 continue;
326 var = pipeline->shaders[i];
327
328 conf = &var->config;
329
330 if (i == MESA_SHADER_FRAGMENT) {
331 lds_per_wave = conf->lds_size * lds_increment +
332 align(var->info.fs.num_interp * 48, lds_increment);
333 }
334
335 if (conf->num_sgprs) {
336 if (device->physical_device->rad_info.chip_class >= VI)
337 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
338 else
339 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
340 }
341
342 if (conf->num_vgprs)
343 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
344
345 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
346 * that PS can use.
347 */
348 if (lds_per_wave)
349 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
350
351 fprintf(file, "\n%s:\n",
352 radv_get_shader_name(var, i));
353 if (i == MESA_SHADER_FRAGMENT) {
354 fprintf(file, "*** SHADER CONFIG ***\n"
355 "SPI_PS_INPUT_ADDR = 0x%04x\n"
356 "SPI_PS_INPUT_ENA = 0x%04x\n",
357 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
358 }
359 fprintf(file, "*** SHADER STATS ***\n"
360 "SGPRS: %d\n"
361 "VGPRS: %d\n"
362 "Spilled SGPRs: %d\n"
363 "Spilled VGPRs: %d\n"
364 "Code Size: %d bytes\n"
365 "LDS: %d blocks\n"
366 "Scratch: %d bytes per wave\n"
367 "Max Waves: %d\n"
368 "********************\n\n\n",
369 conf->num_sgprs, conf->num_vgprs,
370 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
371 conf->lds_size, conf->scratch_bytes_per_wave,
372 max_simd_waves);
373 }
374 }
375
376 void radv_shader_variant_destroy(struct radv_device *device,
377 struct radv_shader_variant *variant)
378 {
379 if (!p_atomic_dec_zero(&variant->ref_count))
380 return;
381
382 device->ws->buffer_destroy(variant->bo);
383 free(variant);
384 }
385
386 static void radv_fill_shader_variant(struct radv_device *device,
387 struct radv_shader_variant *variant,
388 struct ac_shader_binary *binary,
389 gl_shader_stage stage)
390 {
391 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
392 unsigned vgpr_comp_cnt = 0;
393
394 if (scratch_enabled && !device->llvm_supports_spill)
395 radv_finishme("shader scratch support only available with LLVM 4.0");
396
397 variant->code_size = binary->code_size;
398 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
399 S_00B12C_SCRATCH_EN(scratch_enabled);
400
401 switch (stage) {
402 case MESA_SHADER_TESS_EVAL:
403 vgpr_comp_cnt = 3;
404 /* fallthrough */
405 case MESA_SHADER_TESS_CTRL:
406 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
407 break;
408 case MESA_SHADER_VERTEX:
409 case MESA_SHADER_GEOMETRY:
410 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
411 break;
412 case MESA_SHADER_FRAGMENT:
413 break;
414 case MESA_SHADER_COMPUTE:
415 variant->rsrc2 |=
416 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
417 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
418 S_00B84C_TG_SIZE_EN(1) |
419 S_00B84C_LDS_SIZE(variant->config.lds_size);
420 break;
421 default:
422 unreachable("unsupported shader type");
423 break;
424 }
425
426 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
427 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
428 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
429 S_00B848_DX10_CLAMP(1) |
430 S_00B848_FLOAT_MODE(variant->config.float_mode);
431
432 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
433 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
434
435 void *ptr = device->ws->buffer_map(variant->bo);
436 memcpy(ptr, binary->code, binary->code_size);
437 device->ws->buffer_unmap(variant->bo);
438
439
440 }
441
442 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
443 struct nir_shader *shader,
444 struct radv_pipeline_layout *layout,
445 const union ac_shader_variant_key *key,
446 void** code_out,
447 unsigned *code_size_out,
448 bool dump)
449 {
450 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
451 enum radeon_family chip_family = device->physical_device->rad_info.family;
452 LLVMTargetMachineRef tm;
453 if (!variant)
454 return NULL;
455
456 struct ac_nir_compiler_options options = {0};
457 options.layout = layout;
458 if (key)
459 options.key = *key;
460
461 struct ac_shader_binary binary;
462
463 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
464 options.family = chip_family;
465 options.chip_class = device->physical_device->rad_info.chip_class;
466 options.supports_spill = device->llvm_supports_spill;
467 tm = ac_create_target_machine(chip_family, options.supports_spill);
468 ac_compile_nir_shader(tm, &binary, &variant->config,
469 &variant->info, shader, &options, dump);
470 LLVMDisposeTargetMachine(tm);
471
472 radv_fill_shader_variant(device, variant, &binary, shader->stage);
473
474 if (code_out) {
475 *code_out = binary.code;
476 *code_size_out = binary.code_size;
477 } else
478 free(binary.code);
479 free(binary.config);
480 free(binary.rodata);
481 free(binary.global_symbol_offsets);
482 free(binary.relocs);
483 free(binary.disasm_string);
484 variant->ref_count = 1;
485 return variant;
486 }
487
488 static struct radv_shader_variant *
489 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
490 struct nir_shader *nir,
491 void** code_out,
492 unsigned *code_size_out,
493 bool dump_shader)
494 {
495 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
496 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
497 LLVMTargetMachineRef tm;
498 if (!variant)
499 return NULL;
500
501 struct ac_nir_compiler_options options = {0};
502 struct ac_shader_binary binary;
503 options.family = chip_family;
504 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
505 options.supports_spill = pipeline->device->llvm_supports_spill;
506 tm = ac_create_target_machine(chip_family, options.supports_spill);
507 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
508 LLVMDisposeTargetMachine(tm);
509
510 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
511
512 if (code_out) {
513 *code_out = binary.code;
514 *code_size_out = binary.code_size;
515 } else
516 free(binary.code);
517 free(binary.config);
518 free(binary.rodata);
519 free(binary.global_symbol_offsets);
520 free(binary.relocs);
521 free(binary.disasm_string);
522 variant->ref_count = 1;
523 return variant;
524 }
525
526 static struct radv_shader_variant *
527 radv_pipeline_compile(struct radv_pipeline *pipeline,
528 struct radv_pipeline_cache *cache,
529 struct radv_shader_module *module,
530 const char *entrypoint,
531 gl_shader_stage stage,
532 const VkSpecializationInfo *spec_info,
533 struct radv_pipeline_layout *layout,
534 const union ac_shader_variant_key *key)
535 {
536 unsigned char sha1[20];
537 unsigned char gs_copy_sha1[20];
538 struct radv_shader_variant *variant;
539 nir_shader *nir;
540 void *code = NULL;
541 unsigned code_size = 0;
542 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
543
544 if (module->nir)
545 _mesa_sha1_compute(module->nir->info.name,
546 strlen(module->nir->info.name),
547 module->sha1);
548
549 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
550 if (stage == MESA_SHADER_GEOMETRY)
551 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
552 layout, key, 1);
553
554 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
555 cache,
556 sha1);
557
558 if (stage == MESA_SHADER_GEOMETRY) {
559 pipeline->gs_copy_shader =
560 radv_create_shader_variant_from_pipeline_cache(
561 pipeline->device,
562 cache,
563 gs_copy_sha1);
564 }
565
566 if (variant &&
567 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
568 return variant;
569
570 nir = radv_shader_compile_to_nir(pipeline->device,
571 module, entrypoint, stage,
572 spec_info, dump);
573 if (nir == NULL)
574 return NULL;
575
576 if (!variant) {
577 variant = radv_shader_variant_create(pipeline->device, nir,
578 layout, key, &code,
579 &code_size, dump);
580 }
581
582 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
583 void *gs_copy_code = NULL;
584 unsigned gs_copy_code_size = 0;
585 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
586 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
587
588 if (pipeline->gs_copy_shader) {
589 pipeline->gs_copy_shader =
590 radv_pipeline_cache_insert_shader(cache,
591 gs_copy_sha1,
592 pipeline->gs_copy_shader,
593 gs_copy_code,
594 gs_copy_code_size);
595 }
596 }
597 if (!module->nir)
598 ralloc_free(nir);
599
600 if (variant)
601 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
602 code, code_size);
603
604 if (code)
605 free(code);
606 return variant;
607 }
608
609 static union ac_shader_variant_key
610 radv_compute_tes_key(bool as_es, bool export_prim_id)
611 {
612 union ac_shader_variant_key key;
613 memset(&key, 0, sizeof(key));
614 key.tes.as_es = as_es;
615 /* export prim id only happens when no geom shader */
616 if (!as_es)
617 key.tes.export_prim_id = export_prim_id;
618 return key;
619 }
620
621 static union ac_shader_variant_key
622 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
623 {
624 union ac_shader_variant_key key;
625 memset(&key, 0, sizeof(key));
626 key.tcs.primitive_mode = primitive_mode;
627 key.tcs.input_vertices = input_vertices;
628 return key;
629 }
630
631 static void
632 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
633 struct radv_pipeline_cache *cache,
634 struct radv_shader_module *tcs_module,
635 struct radv_shader_module *tes_module,
636 const char *tcs_entrypoint,
637 const char *tes_entrypoint,
638 const VkSpecializationInfo *tcs_spec_info,
639 const VkSpecializationInfo *tes_spec_info,
640 struct radv_pipeline_layout *layout,
641 unsigned input_vertices)
642 {
643 unsigned char tcs_sha1[20], tes_sha1[20];
644 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
645 nir_shader *tes_nir, *tcs_nir;
646 void *tes_code = NULL, *tcs_code = NULL;
647 unsigned tes_code_size = 0, tcs_code_size = 0;
648 union ac_shader_variant_key tes_key;
649 union ac_shader_variant_key tcs_key;
650 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
651
652 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
653 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
654 if (tes_module->nir)
655 _mesa_sha1_compute(tes_module->nir->info.name,
656 strlen(tes_module->nir->info.name),
657 tes_module->sha1);
658 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
659
660 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
661 cache,
662 tes_sha1);
663
664 if (tes_variant) {
665 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
666
667 if (tcs_module->nir)
668 _mesa_sha1_compute(tcs_module->nir->info.name,
669 strlen(tcs_module->nir->info.name),
670 tcs_module->sha1);
671
672 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
673
674 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
675 cache,
676 tcs_sha1);
677 }
678
679 if (tcs_variant && tes_variant) {
680 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
681 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
682 return;
683 }
684
685 tes_nir = radv_shader_compile_to_nir(pipeline->device,
686 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
687 tes_spec_info, dump);
688 if (tes_nir == NULL)
689 return;
690
691 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
692 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
693 tcs_spec_info, dump);
694 if (tcs_nir == NULL)
695 return;
696
697 nir_lower_tes_patch_vertices(tes_nir,
698 tcs_nir->info.tess.tcs_vertices_out);
699
700 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
701 layout, &tes_key, &tes_code,
702 &tes_code_size, dump);
703
704 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
705 if (tcs_module->nir)
706 _mesa_sha1_compute(tcs_module->nir->info.name,
707 strlen(tcs_module->nir->info.name),
708 tcs_module->sha1);
709
710 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
711
712 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
713 layout, &tcs_key, &tcs_code,
714 &tcs_code_size, dump);
715
716 if (!tes_module->nir)
717 ralloc_free(tes_nir);
718
719 if (!tcs_module->nir)
720 ralloc_free(tcs_nir);
721
722 if (tes_variant)
723 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
724 tes_code, tes_code_size);
725
726 if (tcs_variant)
727 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
728 tcs_code, tcs_code_size);
729
730 if (tes_code)
731 free(tes_code);
732 if (tcs_code)
733 free(tcs_code);
734 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
735 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
736 return;
737 }
738
739 static VkResult
740 radv_pipeline_scratch_init(struct radv_device *device,
741 struct radv_pipeline *pipeline)
742 {
743 unsigned scratch_bytes_per_wave = 0;
744 unsigned max_waves = 0;
745 unsigned min_waves = 1;
746
747 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
748 if (pipeline->shaders[i]) {
749 unsigned max_stage_waves = device->scratch_waves;
750
751 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
752 pipeline->shaders[i]->config.scratch_bytes_per_wave);
753
754 max_stage_waves = MIN2(max_stage_waves,
755 4 * device->physical_device->rad_info.num_good_compute_units *
756 (256 / pipeline->shaders[i]->config.num_vgprs));
757 max_waves = MAX2(max_waves, max_stage_waves);
758 }
759 }
760
761 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
762 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
763 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
764 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
765 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
766 }
767
768 if (scratch_bytes_per_wave)
769 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
770
771 if (scratch_bytes_per_wave && max_waves < min_waves) {
772 /* Not really true at this moment, but will be true on first
773 * execution. Avoid having hanging shaders. */
774 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
775 }
776 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
777 pipeline->max_waves = max_waves;
778 return VK_SUCCESS;
779 }
780
781 static uint32_t si_translate_blend_function(VkBlendOp op)
782 {
783 switch (op) {
784 case VK_BLEND_OP_ADD:
785 return V_028780_COMB_DST_PLUS_SRC;
786 case VK_BLEND_OP_SUBTRACT:
787 return V_028780_COMB_SRC_MINUS_DST;
788 case VK_BLEND_OP_REVERSE_SUBTRACT:
789 return V_028780_COMB_DST_MINUS_SRC;
790 case VK_BLEND_OP_MIN:
791 return V_028780_COMB_MIN_DST_SRC;
792 case VK_BLEND_OP_MAX:
793 return V_028780_COMB_MAX_DST_SRC;
794 default:
795 return 0;
796 }
797 }
798
799 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
800 {
801 switch (factor) {
802 case VK_BLEND_FACTOR_ZERO:
803 return V_028780_BLEND_ZERO;
804 case VK_BLEND_FACTOR_ONE:
805 return V_028780_BLEND_ONE;
806 case VK_BLEND_FACTOR_SRC_COLOR:
807 return V_028780_BLEND_SRC_COLOR;
808 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
809 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
810 case VK_BLEND_FACTOR_DST_COLOR:
811 return V_028780_BLEND_DST_COLOR;
812 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
813 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
814 case VK_BLEND_FACTOR_SRC_ALPHA:
815 return V_028780_BLEND_SRC_ALPHA;
816 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
817 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
818 case VK_BLEND_FACTOR_DST_ALPHA:
819 return V_028780_BLEND_DST_ALPHA;
820 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
821 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
822 case VK_BLEND_FACTOR_CONSTANT_COLOR:
823 return V_028780_BLEND_CONSTANT_COLOR;
824 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
825 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
826 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
827 return V_028780_BLEND_CONSTANT_ALPHA;
828 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
829 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
830 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
831 return V_028780_BLEND_SRC_ALPHA_SATURATE;
832 case VK_BLEND_FACTOR_SRC1_COLOR:
833 return V_028780_BLEND_SRC1_COLOR;
834 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
835 return V_028780_BLEND_INV_SRC1_COLOR;
836 case VK_BLEND_FACTOR_SRC1_ALPHA:
837 return V_028780_BLEND_SRC1_ALPHA;
838 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
839 return V_028780_BLEND_INV_SRC1_ALPHA;
840 default:
841 return 0;
842 }
843 }
844
845 static bool is_dual_src(VkBlendFactor factor)
846 {
847 switch (factor) {
848 case VK_BLEND_FACTOR_SRC1_COLOR:
849 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
850 case VK_BLEND_FACTOR_SRC1_ALPHA:
851 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
852 return true;
853 default:
854 return false;
855 }
856 }
857
858 static unsigned si_choose_spi_color_format(VkFormat vk_format,
859 bool blend_enable,
860 bool blend_need_alpha)
861 {
862 const struct vk_format_description *desc = vk_format_description(vk_format);
863 unsigned format, ntype, swap;
864
865 /* Alpha is needed for alpha-to-coverage.
866 * Blending may be with or without alpha.
867 */
868 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
869 unsigned alpha = 0; /* exports alpha, but may not support blending */
870 unsigned blend = 0; /* supports blending, but may not export alpha */
871 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
872
873 format = radv_translate_colorformat(vk_format);
874 ntype = radv_translate_color_numformat(vk_format, desc,
875 vk_format_get_first_non_void_channel(vk_format));
876 swap = radv_translate_colorswap(vk_format, false);
877
878 /* Choose the SPI color formats. These are required values for Stoney/RB+.
879 * Other chips have multiple choices, though they are not necessarily better.
880 */
881 switch (format) {
882 case V_028C70_COLOR_5_6_5:
883 case V_028C70_COLOR_1_5_5_5:
884 case V_028C70_COLOR_5_5_5_1:
885 case V_028C70_COLOR_4_4_4_4:
886 case V_028C70_COLOR_10_11_11:
887 case V_028C70_COLOR_11_11_10:
888 case V_028C70_COLOR_8:
889 case V_028C70_COLOR_8_8:
890 case V_028C70_COLOR_8_8_8_8:
891 case V_028C70_COLOR_10_10_10_2:
892 case V_028C70_COLOR_2_10_10_10:
893 if (ntype == V_028C70_NUMBER_UINT)
894 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
895 else if (ntype == V_028C70_NUMBER_SINT)
896 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
897 else
898 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
899 break;
900
901 case V_028C70_COLOR_16:
902 case V_028C70_COLOR_16_16:
903 case V_028C70_COLOR_16_16_16_16:
904 if (ntype == V_028C70_NUMBER_UNORM ||
905 ntype == V_028C70_NUMBER_SNORM) {
906 /* UNORM16 and SNORM16 don't support blending */
907 if (ntype == V_028C70_NUMBER_UNORM)
908 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
909 else
910 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
911
912 /* Use 32 bits per channel for blending. */
913 if (format == V_028C70_COLOR_16) {
914 if (swap == V_028C70_SWAP_STD) { /* R */
915 blend = V_028714_SPI_SHADER_32_R;
916 blend_alpha = V_028714_SPI_SHADER_32_AR;
917 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
918 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
919 else
920 assert(0);
921 } else if (format == V_028C70_COLOR_16_16) {
922 if (swap == V_028C70_SWAP_STD) { /* RG */
923 blend = V_028714_SPI_SHADER_32_GR;
924 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
925 } else if (swap == V_028C70_SWAP_ALT) /* RA */
926 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
927 else
928 assert(0);
929 } else /* 16_16_16_16 */
930 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
931 } else if (ntype == V_028C70_NUMBER_UINT)
932 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
933 else if (ntype == V_028C70_NUMBER_SINT)
934 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
935 else if (ntype == V_028C70_NUMBER_FLOAT)
936 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
937 else
938 assert(0);
939 break;
940
941 case V_028C70_COLOR_32:
942 if (swap == V_028C70_SWAP_STD) { /* R */
943 blend = normal = V_028714_SPI_SHADER_32_R;
944 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
945 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
946 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
947 else
948 assert(0);
949 break;
950
951 case V_028C70_COLOR_32_32:
952 if (swap == V_028C70_SWAP_STD) { /* RG */
953 blend = normal = V_028714_SPI_SHADER_32_GR;
954 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
955 } else if (swap == V_028C70_SWAP_ALT) /* RA */
956 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
957 else
958 assert(0);
959 break;
960
961 case V_028C70_COLOR_32_32_32_32:
962 case V_028C70_COLOR_8_24:
963 case V_028C70_COLOR_24_8:
964 case V_028C70_COLOR_X24_8_32_FLOAT:
965 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
966 break;
967
968 default:
969 unreachable("unhandled blend format");
970 }
971
972 if (blend_enable && blend_need_alpha)
973 return blend_alpha;
974 else if(blend_need_alpha)
975 return alpha;
976 else if(blend_enable)
977 return blend;
978 else
979 return normal;
980 }
981
982 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
983 {
984 unsigned i, cb_shader_mask = 0;
985
986 for (i = 0; i < 8; i++) {
987 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
988 case V_028714_SPI_SHADER_ZERO:
989 break;
990 case V_028714_SPI_SHADER_32_R:
991 cb_shader_mask |= 0x1 << (i * 4);
992 break;
993 case V_028714_SPI_SHADER_32_GR:
994 cb_shader_mask |= 0x3 << (i * 4);
995 break;
996 case V_028714_SPI_SHADER_32_AR:
997 cb_shader_mask |= 0x9 << (i * 4);
998 break;
999 case V_028714_SPI_SHADER_FP16_ABGR:
1000 case V_028714_SPI_SHADER_UNORM16_ABGR:
1001 case V_028714_SPI_SHADER_SNORM16_ABGR:
1002 case V_028714_SPI_SHADER_UINT16_ABGR:
1003 case V_028714_SPI_SHADER_SINT16_ABGR:
1004 case V_028714_SPI_SHADER_32_ABGR:
1005 cb_shader_mask |= 0xf << (i * 4);
1006 break;
1007 default:
1008 assert(0);
1009 }
1010 }
1011 return cb_shader_mask;
1012 }
1013
1014 static void
1015 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1016 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1017 uint32_t blend_enable,
1018 uint32_t blend_need_alpha,
1019 bool single_cb_enable,
1020 bool blend_mrt0_is_dual_src)
1021 {
1022 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1023 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1024 struct radv_blend_state *blend = &pipeline->graphics.blend;
1025 unsigned col_format = 0;
1026
1027 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1028 struct radv_render_pass_attachment *attachment;
1029 unsigned cf;
1030
1031 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1032
1033 cf = si_choose_spi_color_format(attachment->format,
1034 blend_enable & (1 << i),
1035 blend_need_alpha & (1 << i));
1036
1037 col_format |= cf << (4 * i);
1038 }
1039
1040 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1041
1042 if (blend_mrt0_is_dual_src)
1043 col_format |= (col_format & 0xf) << 4;
1044 blend->spi_shader_col_format = col_format;
1045 }
1046
1047 static bool
1048 format_is_int8(VkFormat format)
1049 {
1050 const struct vk_format_description *desc = vk_format_description(format);
1051 int channel = vk_format_get_first_non_void_channel(format);
1052
1053 return channel >= 0 && desc->channel[channel].pure_integer &&
1054 desc->channel[channel].size == 8;
1055 }
1056
1057 unsigned radv_format_meta_fs_key(VkFormat format)
1058 {
1059 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1060 bool is_int8 = format_is_int8(format);
1061
1062 return col_format + (is_int8 ? 3 : 0);
1063 }
1064
1065 static unsigned
1066 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1067 {
1068 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1069 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1070 unsigned is_int8 = 0;
1071
1072 for (unsigned i = 0; i < subpass->color_count; ++i) {
1073 struct radv_render_pass_attachment *attachment;
1074
1075 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1076
1077 if (format_is_int8(attachment->format))
1078 is_int8 |= 1 << i;
1079 }
1080
1081 return is_int8;
1082 }
1083
1084 static void
1085 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1086 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1087 const struct radv_graphics_pipeline_create_info *extra)
1088 {
1089 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1090 struct radv_blend_state *blend = &pipeline->graphics.blend;
1091 unsigned mode = V_028808_CB_NORMAL;
1092 uint32_t blend_enable = 0, blend_need_alpha = 0;
1093 bool blend_mrt0_is_dual_src = false;
1094 int i;
1095 bool single_cb_enable = false;
1096
1097 if (!vkblend)
1098 return;
1099
1100 if (extra && extra->custom_blend_mode) {
1101 single_cb_enable = true;
1102 mode = extra->custom_blend_mode;
1103 }
1104 blend->cb_color_control = 0;
1105 if (vkblend->logicOpEnable)
1106 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1107 else
1108 blend->cb_color_control |= S_028808_ROP3(0xcc);
1109
1110 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1111 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1112 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1113 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1114
1115 blend->cb_target_mask = 0;
1116 for (i = 0; i < vkblend->attachmentCount; i++) {
1117 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1118 unsigned blend_cntl = 0;
1119 VkBlendOp eqRGB = att->colorBlendOp;
1120 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1121 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1122 VkBlendOp eqA = att->alphaBlendOp;
1123 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1124 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1125
1126 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1127
1128 if (!att->colorWriteMask)
1129 continue;
1130
1131 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1132 if (!att->blendEnable) {
1133 blend->cb_blend_control[i] = blend_cntl;
1134 continue;
1135 }
1136
1137 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1138 if (i == 0)
1139 blend_mrt0_is_dual_src = true;
1140
1141 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1142 srcRGB = VK_BLEND_FACTOR_ONE;
1143 dstRGB = VK_BLEND_FACTOR_ONE;
1144 }
1145 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1146 srcA = VK_BLEND_FACTOR_ONE;
1147 dstA = VK_BLEND_FACTOR_ONE;
1148 }
1149
1150 blend_cntl |= S_028780_ENABLE(1);
1151
1152 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1153 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1154 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1155 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1156 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1157 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1158 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1159 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1160 }
1161 blend->cb_blend_control[i] = blend_cntl;
1162
1163 blend_enable |= 1 << i;
1164
1165 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1166 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1167 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1168 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1169 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1170 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1171 blend_need_alpha |= 1 << i;
1172 }
1173 for (i = vkblend->attachmentCount; i < 8; i++)
1174 blend->cb_blend_control[i] = 0;
1175
1176 if (blend->cb_target_mask)
1177 blend->cb_color_control |= S_028808_MODE(mode);
1178 else
1179 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1180
1181 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1182 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1183 }
1184
1185 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1186 {
1187 switch (op) {
1188 case VK_STENCIL_OP_KEEP:
1189 return V_02842C_STENCIL_KEEP;
1190 case VK_STENCIL_OP_ZERO:
1191 return V_02842C_STENCIL_ZERO;
1192 case VK_STENCIL_OP_REPLACE:
1193 return V_02842C_STENCIL_REPLACE_TEST;
1194 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1195 return V_02842C_STENCIL_ADD_CLAMP;
1196 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1197 return V_02842C_STENCIL_SUB_CLAMP;
1198 case VK_STENCIL_OP_INVERT:
1199 return V_02842C_STENCIL_INVERT;
1200 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1201 return V_02842C_STENCIL_ADD_WRAP;
1202 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1203 return V_02842C_STENCIL_SUB_WRAP;
1204 default:
1205 return 0;
1206 }
1207 }
1208 static void
1209 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1210 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1211 const struct radv_graphics_pipeline_create_info *extra)
1212 {
1213 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1214 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1215
1216 memset(ds, 0, sizeof(*ds));
1217 if (!vkds)
1218 return;
1219 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1220 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1221 S_028800_ZFUNC(vkds->depthCompareOp) |
1222 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1223
1224 if (vkds->stencilTestEnable) {
1225 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1226 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1227 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1228 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1229 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1230
1231 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1232 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1233 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1234 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1235 }
1236
1237 if (extra) {
1238
1239 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1240 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1241
1242 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1243 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1244 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1245 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1246 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1247 }
1248 }
1249
1250 static uint32_t si_translate_fill(VkPolygonMode func)
1251 {
1252 switch(func) {
1253 case VK_POLYGON_MODE_FILL:
1254 return V_028814_X_DRAW_TRIANGLES;
1255 case VK_POLYGON_MODE_LINE:
1256 return V_028814_X_DRAW_LINES;
1257 case VK_POLYGON_MODE_POINT:
1258 return V_028814_X_DRAW_POINTS;
1259 default:
1260 assert(0);
1261 return V_028814_X_DRAW_POINTS;
1262 }
1263 }
1264 static void
1265 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1266 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1267 {
1268 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1269 struct radv_raster_state *raster = &pipeline->graphics.raster;
1270
1271 memset(raster, 0, sizeof(*raster));
1272
1273 raster->spi_interp_control =
1274 S_0286D4_FLAT_SHADE_ENA(1) |
1275 S_0286D4_PNT_SPRITE_ENA(1) |
1276 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1277 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1278 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1279 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1280 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1281
1282
1283 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1284 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1285 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1286 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1287 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1288 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1289
1290 raster->pa_su_vtx_cntl =
1291 S_028BE4_PIX_CENTER(1) | // TODO verify
1292 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1293 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1294
1295 raster->pa_su_sc_mode_cntl =
1296 S_028814_FACE(vkraster->frontFace) |
1297 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1298 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1299 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1300 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1301 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1302 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1303 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1304 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1305
1306 }
1307
1308 static void
1309 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1310 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1311 {
1312 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1313 struct radv_blend_state *blend = &pipeline->graphics.blend;
1314 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1315 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1316 int ps_iter_samples = 1;
1317 uint32_t mask = 0xffff;
1318
1319 if (vkms)
1320 ms->num_samples = vkms->rasterizationSamples;
1321 else
1322 ms->num_samples = 1;
1323
1324 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1325 ps_iter_samples = ms->num_samples;
1326 }
1327
1328 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1329 ms->pa_sc_aa_config = 0;
1330 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1331 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1332 ms->pa_sc_mode_cntl_1 =
1333 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1334 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1335 /* always 1: */
1336 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1337 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1338 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1339 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1340 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1341 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1342 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1343
1344 if (ms->num_samples > 1) {
1345 unsigned log_samples = util_logbase2(ms->num_samples);
1346 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1347 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1348 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1349 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1350 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1351 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1352 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1353 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1354 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1355 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1356 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1357 }
1358
1359 if (vkms) {
1360 if (vkms->alphaToCoverageEnable)
1361 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1362
1363 if (vkms->pSampleMask)
1364 mask = vkms->pSampleMask[0] & 0xffff;
1365 }
1366
1367 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1368 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1369 }
1370
1371 static bool
1372 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1373 {
1374 switch (topology) {
1375 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1376 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1377 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1378 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1379 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1380 return false;
1381 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1382 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1383 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1384 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1385 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1386 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1387 return true;
1388 default:
1389 unreachable("unhandled primitive type");
1390 }
1391 }
1392
1393 static uint32_t
1394 si_translate_prim(enum VkPrimitiveTopology topology)
1395 {
1396 switch (topology) {
1397 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1398 return V_008958_DI_PT_POINTLIST;
1399 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1400 return V_008958_DI_PT_LINELIST;
1401 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1402 return V_008958_DI_PT_LINESTRIP;
1403 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1404 return V_008958_DI_PT_TRILIST;
1405 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1406 return V_008958_DI_PT_TRISTRIP;
1407 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1408 return V_008958_DI_PT_TRIFAN;
1409 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1410 return V_008958_DI_PT_LINELIST_ADJ;
1411 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1412 return V_008958_DI_PT_LINESTRIP_ADJ;
1413 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1414 return V_008958_DI_PT_TRILIST_ADJ;
1415 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1416 return V_008958_DI_PT_TRISTRIP_ADJ;
1417 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1418 return V_008958_DI_PT_PATCH;
1419 default:
1420 assert(0);
1421 return 0;
1422 }
1423 }
1424
1425 static uint32_t
1426 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1427 {
1428 switch (gl_prim) {
1429 case 0: /* GL_POINTS */
1430 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1431 case 1: /* GL_LINES */
1432 case 3: /* GL_LINE_STRIP */
1433 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1434 case 0x8E7A: /* GL_ISOLINES */
1435 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1436
1437 case 4: /* GL_TRIANGLES */
1438 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1439 case 5: /* GL_TRIANGLE_STRIP */
1440 case 7: /* GL_QUADS */
1441 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1442 default:
1443 assert(0);
1444 return 0;
1445 }
1446 }
1447
1448 static uint32_t
1449 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1450 {
1451 switch (topology) {
1452 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1453 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1454 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1455 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1456 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1457 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1458 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1459 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1460 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1461 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1462 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1463 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1464 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1465 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1466 default:
1467 assert(0);
1468 return 0;
1469 }
1470 }
1471
1472 static unsigned si_map_swizzle(unsigned swizzle)
1473 {
1474 switch (swizzle) {
1475 case VK_SWIZZLE_Y:
1476 return V_008F0C_SQ_SEL_Y;
1477 case VK_SWIZZLE_Z:
1478 return V_008F0C_SQ_SEL_Z;
1479 case VK_SWIZZLE_W:
1480 return V_008F0C_SQ_SEL_W;
1481 case VK_SWIZZLE_0:
1482 return V_008F0C_SQ_SEL_0;
1483 case VK_SWIZZLE_1:
1484 return V_008F0C_SQ_SEL_1;
1485 default: /* VK_SWIZZLE_X */
1486 return V_008F0C_SQ_SEL_X;
1487 }
1488 }
1489
1490 static void
1491 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1492 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1493 {
1494 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1495 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1496 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1497
1498 pipeline->dynamic_state = default_dynamic_state;
1499
1500 if (pCreateInfo->pDynamicState) {
1501 /* Remove all of the states that are marked as dynamic */
1502 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1503 for (uint32_t s = 0; s < count; s++)
1504 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1505 }
1506
1507 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1508
1509 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1510 *
1511 * pViewportState is [...] NULL if the pipeline
1512 * has rasterization disabled.
1513 */
1514 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1515 assert(pCreateInfo->pViewportState);
1516
1517 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1518 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1519 typed_memcpy(dynamic->viewport.viewports,
1520 pCreateInfo->pViewportState->pViewports,
1521 pCreateInfo->pViewportState->viewportCount);
1522 }
1523
1524 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1525 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1526 typed_memcpy(dynamic->scissor.scissors,
1527 pCreateInfo->pViewportState->pScissors,
1528 pCreateInfo->pViewportState->scissorCount);
1529 }
1530 }
1531
1532 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1533 assert(pCreateInfo->pRasterizationState);
1534 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1535 }
1536
1537 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1538 assert(pCreateInfo->pRasterizationState);
1539 dynamic->depth_bias.bias =
1540 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1541 dynamic->depth_bias.clamp =
1542 pCreateInfo->pRasterizationState->depthBiasClamp;
1543 dynamic->depth_bias.slope =
1544 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1545 }
1546
1547 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1548 *
1549 * pColorBlendState is [...] NULL if the pipeline has rasterization
1550 * disabled or if the subpass of the render pass the pipeline is
1551 * created against does not use any color attachments.
1552 */
1553 bool uses_color_att = false;
1554 for (unsigned i = 0; i < subpass->color_count; ++i) {
1555 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1556 uses_color_att = true;
1557 break;
1558 }
1559 }
1560
1561 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1562 assert(pCreateInfo->pColorBlendState);
1563 typed_memcpy(dynamic->blend_constants,
1564 pCreateInfo->pColorBlendState->blendConstants, 4);
1565 }
1566
1567 /* If there is no depthstencil attachment, then don't read
1568 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1569 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1570 * no need to override the depthstencil defaults in
1571 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1572 *
1573 * Section 9.2 of the Vulkan 1.0.15 spec says:
1574 *
1575 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1576 * disabled or if the subpass of the render pass the pipeline is created
1577 * against does not use a depth/stencil attachment.
1578 */
1579 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1580 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1581 assert(pCreateInfo->pDepthStencilState);
1582
1583 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1584 dynamic->depth_bounds.min =
1585 pCreateInfo->pDepthStencilState->minDepthBounds;
1586 dynamic->depth_bounds.max =
1587 pCreateInfo->pDepthStencilState->maxDepthBounds;
1588 }
1589
1590 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1591 dynamic->stencil_compare_mask.front =
1592 pCreateInfo->pDepthStencilState->front.compareMask;
1593 dynamic->stencil_compare_mask.back =
1594 pCreateInfo->pDepthStencilState->back.compareMask;
1595 }
1596
1597 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1598 dynamic->stencil_write_mask.front =
1599 pCreateInfo->pDepthStencilState->front.writeMask;
1600 dynamic->stencil_write_mask.back =
1601 pCreateInfo->pDepthStencilState->back.writeMask;
1602 }
1603
1604 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1605 dynamic->stencil_reference.front =
1606 pCreateInfo->pDepthStencilState->front.reference;
1607 dynamic->stencil_reference.back =
1608 pCreateInfo->pDepthStencilState->back.reference;
1609 }
1610 }
1611
1612 pipeline->dynamic_state_mask = states;
1613 }
1614
1615 static union ac_shader_variant_key
1616 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1617 {
1618 union ac_shader_variant_key key;
1619 const VkPipelineVertexInputStateCreateInfo *input_state =
1620 pCreateInfo->pVertexInputState;
1621
1622 memset(&key, 0, sizeof(key));
1623 key.vs.instance_rate_inputs = 0;
1624 key.vs.as_es = as_es;
1625 key.vs.as_ls = as_ls;
1626 key.vs.export_prim_id = export_prim_id;
1627
1628 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1629 unsigned binding;
1630 binding = input_state->pVertexAttributeDescriptions[i].binding;
1631 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1632 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1633 }
1634 return key;
1635 }
1636
1637 static void
1638 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1639 {
1640 struct radv_device *device = pipeline->device;
1641 unsigned num_se = device->physical_device->rad_info.max_se;
1642 unsigned wave_size = 64;
1643 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1644 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1645 unsigned alignment = 256 * num_se;
1646 /* The maximum size is 63.999 MB per SE. */
1647 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1648 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1649 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1650 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1651 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1652
1653 /* Calculate the minimum size. */
1654 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1655 wave_size, alignment);
1656 /* These are recommended sizes, not minimum sizes. */
1657 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1658 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1659 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1660 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1661
1662 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1663 esgs_ring_size = align(esgs_ring_size, alignment);
1664 gsvs_ring_size = align(gsvs_ring_size, alignment);
1665
1666 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1667 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1668 }
1669
1670 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1671 unsigned *lds_size)
1672 {
1673 /* SPI barrier management bug:
1674 * Make sure we have at least 4k of LDS in use to avoid the bug.
1675 * It applies to workgroup sizes of more than one wavefront.
1676 */
1677 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1678 device->physical_device->rad_info.family == CHIP_KABINI ||
1679 device->physical_device->rad_info.family == CHIP_MULLINS)
1680 *lds_size = MAX2(*lds_size, 8);
1681 }
1682
1683 static void
1684 calculate_tess_state(struct radv_pipeline *pipeline,
1685 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1686 {
1687 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1688 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1689 unsigned num_tcs_patch_outputs;
1690 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1691 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1692 unsigned lds_size, hardware_lds_size;
1693 unsigned perpatch_output_offset;
1694 unsigned num_patches;
1695 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1696
1697 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1698 * are laid out in LDS. */
1699 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1700
1701 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1702 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1703 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1704
1705 /* Ensure that we only need one wave per SIMD so we don't need to check
1706 * resource usage. Also ensures that the number of tcs in and out
1707 * vertices per threadgroup are at most 256.
1708 */
1709 input_vertex_size = num_tcs_inputs * 16;
1710 output_vertex_size = num_tcs_outputs * 16;
1711
1712 input_patch_size = num_tcs_input_cp * input_vertex_size;
1713
1714 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1715 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1716 /* Ensure that we only need one wave per SIMD so we don't need to check
1717 * resource usage. Also ensures that the number of tcs in and out
1718 * vertices per threadgroup are at most 256.
1719 */
1720 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1721
1722 /* Make sure that the data fits in LDS. This assumes the shaders only
1723 * use LDS for the inputs and outputs.
1724 */
1725 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1726 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1727
1728 /* Make sure the output data fits in the offchip buffer */
1729 num_patches = MIN2(num_patches,
1730 (pipeline->device->tess_offchip_block_dw_size * 4) /
1731 output_patch_size);
1732
1733 /* Not necessary for correctness, but improves performance. The
1734 * specific value is taken from the proprietary driver.
1735 */
1736 num_patches = MIN2(num_patches, 40);
1737
1738 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1739 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1740 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1741 num_patches = MIN2(num_patches, one_wave);
1742 }
1743
1744 output_patch0_offset = input_patch_size * num_patches;
1745 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1746
1747 lds_size = output_patch0_offset + output_patch_size * num_patches;
1748
1749 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1750 assert(lds_size <= 65536);
1751 lds_size = align(lds_size, 512) / 512;
1752 } else {
1753 assert(lds_size <= 32768);
1754 lds_size = align(lds_size, 256) / 256;
1755 }
1756 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1757
1758 tess->lds_size = lds_size;
1759
1760 tess->tcs_in_layout = (input_patch_size / 4) |
1761 ((input_vertex_size / 4) << 13);
1762 tess->tcs_out_layout = (output_patch_size / 4) |
1763 ((output_vertex_size / 4) << 13);
1764 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1765 ((perpatch_output_offset / 16) << 16);
1766 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1767 (num_tcs_output_cp << 9) | num_patches;
1768
1769 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1770 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1771 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1772 tess->num_patches = num_patches;
1773 tess->num_tcs_input_cp = num_tcs_input_cp;
1774
1775 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1776 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1777
1778 switch (tes->info.tes.primitive_mode) {
1779 case GL_TRIANGLES:
1780 type = V_028B6C_TESS_TRIANGLE;
1781 break;
1782 case GL_QUADS:
1783 type = V_028B6C_TESS_QUAD;
1784 break;
1785 case GL_ISOLINES:
1786 type = V_028B6C_TESS_ISOLINE;
1787 break;
1788 }
1789
1790 switch (tes->info.tes.spacing) {
1791 case TESS_SPACING_EQUAL:
1792 partitioning = V_028B6C_PART_INTEGER;
1793 break;
1794 case TESS_SPACING_FRACTIONAL_ODD:
1795 partitioning = V_028B6C_PART_FRAC_ODD;
1796 break;
1797 case TESS_SPACING_FRACTIONAL_EVEN:
1798 partitioning = V_028B6C_PART_FRAC_EVEN;
1799 break;
1800 default:
1801 break;
1802 }
1803
1804 if (tes->info.tes.point_mode)
1805 topology = V_028B6C_OUTPUT_POINT;
1806 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1807 topology = V_028B6C_OUTPUT_LINE;
1808 else if (tes->info.tes.ccw)
1809 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1810 else
1811 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1812
1813 if (pipeline->device->has_distributed_tess) {
1814 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1815 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1816 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1817 else
1818 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1819 } else
1820 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1821
1822 tess->tf_param = S_028B6C_TYPE(type) |
1823 S_028B6C_PARTITIONING(partitioning) |
1824 S_028B6C_TOPOLOGY(topology) |
1825 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1826 }
1827
1828 static const struct radv_prim_vertex_count prim_size_table[] = {
1829 [V_008958_DI_PT_NONE] = {0, 0},
1830 [V_008958_DI_PT_POINTLIST] = {1, 1},
1831 [V_008958_DI_PT_LINELIST] = {2, 2},
1832 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1833 [V_008958_DI_PT_TRILIST] = {3, 3},
1834 [V_008958_DI_PT_TRIFAN] = {3, 1},
1835 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1836 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1837 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1838 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1839 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1840 [V_008958_DI_PT_RECTLIST] = {3, 3},
1841 [V_008958_DI_PT_LINELOOP] = {2, 1},
1842 [V_008958_DI_PT_POLYGON] = {3, 1},
1843 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1844 };
1845
1846 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1847 {
1848 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1849 unsigned cut_mode;
1850
1851 if (gs_max_vert_out <= 128) {
1852 cut_mode = V_028A40_GS_CUT_128;
1853 } else if (gs_max_vert_out <= 256) {
1854 cut_mode = V_028A40_GS_CUT_256;
1855 } else if (gs_max_vert_out <= 512) {
1856 cut_mode = V_028A40_GS_CUT_512;
1857 } else {
1858 assert(gs_max_vert_out <= 1024);
1859 cut_mode = V_028A40_GS_CUT_1024;
1860 }
1861
1862 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1863 S_028A40_CUT_MODE(cut_mode)|
1864 S_028A40_ES_WRITE_OPTIMIZE(1) |
1865 S_028A40_GS_WRITE_OPTIMIZE(1);
1866 }
1867
1868 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1869 {
1870 struct radv_shader_variant *vs;
1871 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1872
1873 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1874
1875 pipeline->graphics.vgt_primitiveid_en = false;
1876 pipeline->graphics.vgt_gs_mode = 0;
1877
1878 if (radv_pipeline_has_gs(pipeline)) {
1879 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1880 } else if (outinfo->export_prim_id) {
1881 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1882 pipeline->graphics.vgt_primitiveid_en = true;
1883 }
1884 }
1885
1886 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1887 {
1888 struct radv_shader_variant *vs;
1889 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1890
1891 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1892
1893 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1894 clip_dist_mask = outinfo->clip_dist_mask;
1895 cull_dist_mask = outinfo->cull_dist_mask;
1896 total_mask = clip_dist_mask | cull_dist_mask;
1897
1898 bool misc_vec_ena = outinfo->writes_pointsize ||
1899 outinfo->writes_layer ||
1900 outinfo->writes_viewport_index;
1901 pipeline->graphics.pa_cl_vs_out_cntl =
1902 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1903 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1904 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1905 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1906 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1907 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1908 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1909 cull_dist_mask << 8 |
1910 clip_dist_mask;
1911
1912 }
1913
1914 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1915 {
1916 uint32_t ps_input_cntl;
1917 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1918 ps_input_cntl = S_028644_OFFSET(offset);
1919 if (flat_shade)
1920 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1921 } else {
1922 /* The input is a DEFAULT_VAL constant. */
1923 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1924 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1925 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1926 ps_input_cntl = S_028644_OFFSET(0x20) |
1927 S_028644_DEFAULT_VAL(offset);
1928 }
1929 return ps_input_cntl;
1930 }
1931
1932 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1933 {
1934 struct radv_shader_variant *ps, *vs;
1935 struct ac_vs_output_info *outinfo;
1936
1937 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1938 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1939
1940 outinfo = &vs->info.vs.outinfo;
1941
1942 unsigned ps_offset = 0;
1943
1944 if (ps->info.fs.prim_id_input) {
1945 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1946 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1947 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1948 ++ps_offset;
1949 }
1950 }
1951
1952 if (ps->info.fs.layer_input) {
1953 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1954 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1955 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1956 ++ps_offset;
1957 }
1958 }
1959
1960 if (ps->info.fs.has_pcoord) {
1961 unsigned val;
1962 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1963 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1964 ps_offset++;
1965 }
1966
1967 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1968 unsigned vs_offset;
1969 bool flat_shade;
1970 if (!(ps->info.fs.input_mask & (1u << i)))
1971 continue;
1972
1973 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1974 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1975 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1976 ++ps_offset;
1977 continue;
1978 }
1979
1980 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1981
1982 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1983 ++ps_offset;
1984 }
1985
1986 pipeline->graphics.ps_input_cntl_num = ps_offset;
1987 }
1988
1989 VkResult
1990 radv_pipeline_init(struct radv_pipeline *pipeline,
1991 struct radv_device *device,
1992 struct radv_pipeline_cache *cache,
1993 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1994 const struct radv_graphics_pipeline_create_info *extra,
1995 const VkAllocationCallbacks *alloc)
1996 {
1997 struct radv_shader_module fs_m = {0};
1998 VkResult result;
1999
2000 if (alloc == NULL)
2001 alloc = &device->alloc;
2002
2003 pipeline->device = device;
2004 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2005
2006 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2007 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2008 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2009 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2010 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2011 pStages[stage] = &pCreateInfo->pStages[i];
2012 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2013 }
2014
2015 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2016
2017 if (!modules[MESA_SHADER_FRAGMENT]) {
2018 nir_builder fs_b;
2019 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2020 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2021 fs_m.nir = fs_b.shader;
2022 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2023 }
2024
2025 if (modules[MESA_SHADER_FRAGMENT]) {
2026 union ac_shader_variant_key key;
2027 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2028 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2029
2030 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2031
2032 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2033 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2034 stage ? stage->pName : "main",
2035 MESA_SHADER_FRAGMENT,
2036 stage ? stage->pSpecializationInfo : NULL,
2037 pipeline->layout, &key);
2038 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2039 }
2040
2041 if (fs_m.nir)
2042 ralloc_free(fs_m.nir);
2043
2044 if (modules[MESA_SHADER_VERTEX]) {
2045 bool as_es = false;
2046 bool as_ls = false;
2047 bool export_prim_id = false;
2048 if (modules[MESA_SHADER_TESS_CTRL])
2049 as_ls = true;
2050 else if (modules[MESA_SHADER_GEOMETRY])
2051 as_es = true;
2052 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2053 export_prim_id = true;
2054 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2055
2056 pipeline->shaders[MESA_SHADER_VERTEX] =
2057 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2058 pStages[MESA_SHADER_VERTEX]->pName,
2059 MESA_SHADER_VERTEX,
2060 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2061 pipeline->layout, &key);
2062
2063 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2064 }
2065
2066 if (modules[MESA_SHADER_GEOMETRY]) {
2067 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2068
2069 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2070 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2071 pStages[MESA_SHADER_GEOMETRY]->pName,
2072 MESA_SHADER_GEOMETRY,
2073 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2074 pipeline->layout, &key);
2075
2076 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2077 }
2078
2079 if (modules[MESA_SHADER_TESS_EVAL]) {
2080 assert(modules[MESA_SHADER_TESS_CTRL]);
2081
2082 radv_tess_pipeline_compile(pipeline,
2083 cache,
2084 modules[MESA_SHADER_TESS_CTRL],
2085 modules[MESA_SHADER_TESS_EVAL],
2086 pStages[MESA_SHADER_TESS_CTRL]->pName,
2087 pStages[MESA_SHADER_TESS_EVAL]->pName,
2088 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2089 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2090 pipeline->layout,
2091 pCreateInfo->pTessellationState->patchControlPoints);
2092 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2093 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2094 }
2095
2096 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2097 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2098 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2099 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2100 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2101
2102 if (radv_pipeline_has_gs(pipeline)) {
2103 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2104 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2105 } else {
2106 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2107 }
2108 if (extra && extra->use_rectlist) {
2109 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2110 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2111 pipeline->graphics.can_use_guardband = true;
2112 }
2113 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2114 /* prim vertex count will need TESS changes */
2115 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2116
2117 /* Ensure that some export memory is always allocated, for two reasons:
2118 *
2119 * 1) Correctness: The hardware ignores the EXEC mask if no export
2120 * memory is allocated, so KILL and alpha test do not work correctly
2121 * without this.
2122 * 2) Performance: Every shader needs at least a NULL export, even when
2123 * it writes no color/depth output. The NULL export instruction
2124 * stalls without this setting.
2125 *
2126 * Don't add this to CB_SHADER_MASK.
2127 */
2128 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2129 if (!pipeline->graphics.blend.spi_shader_col_format) {
2130 if (!ps->info.fs.writes_z &&
2131 !ps->info.fs.writes_stencil &&
2132 !ps->info.fs.writes_sample_mask)
2133 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2134 }
2135
2136 unsigned z_order;
2137 pipeline->graphics.db_shader_control = 0;
2138 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2139 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2140 else
2141 z_order = V_02880C_LATE_Z;
2142
2143 pipeline->graphics.db_shader_control =
2144 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2145 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2146 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2147 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2148 S_02880C_Z_ORDER(z_order) |
2149 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2150 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2151 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2152
2153 pipeline->graphics.shader_z_format =
2154 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2155 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2156 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2157 V_028710_SPI_SHADER_ZERO;
2158
2159 calculate_vgt_gs_mode(pipeline);
2160 calculate_pa_cl_vs_out_cntl(pipeline);
2161 calculate_ps_inputs(pipeline);
2162
2163 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2164 if (pipeline->shaders[i]) {
2165 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2166 }
2167 }
2168
2169 uint32_t stages = 0;
2170 if (radv_pipeline_has_tess(pipeline)) {
2171 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2172 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2173
2174 if (radv_pipeline_has_gs(pipeline))
2175 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2176 S_028B54_GS_EN(1) |
2177 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2178 else
2179 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2180
2181 } else if (radv_pipeline_has_gs(pipeline))
2182 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2183 S_028B54_GS_EN(1) |
2184 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2185
2186 if (device->physical_device->rad_info.chip_class >= GFX9)
2187 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2188
2189 pipeline->graphics.vgt_shader_stages_en = stages;
2190
2191 if (radv_pipeline_has_gs(pipeline))
2192 calculate_gs_ring_sizes(pipeline);
2193
2194 if (radv_pipeline_has_tess(pipeline)) {
2195 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2196 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2197 pipeline->graphics.prim_vertex_count.incr = 1;
2198 }
2199 calculate_tess_state(pipeline, pCreateInfo);
2200 }
2201
2202 const VkPipelineVertexInputStateCreateInfo *vi_info =
2203 pCreateInfo->pVertexInputState;
2204 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2205 const VkVertexInputAttributeDescription *desc =
2206 &vi_info->pVertexAttributeDescriptions[i];
2207 unsigned loc = desc->location;
2208 const struct vk_format_description *format_desc;
2209 int first_non_void;
2210 uint32_t num_format, data_format;
2211 format_desc = vk_format_description(desc->format);
2212 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2213
2214 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2215 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2216
2217 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2218 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2219 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2220 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2221 S_008F0C_NUM_FORMAT(num_format) |
2222 S_008F0C_DATA_FORMAT(data_format);
2223 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2224 pipeline->va_offset[loc] = desc->offset;
2225 pipeline->va_binding[loc] = desc->binding;
2226 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2227 }
2228
2229 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2230 const VkVertexInputBindingDescription *desc =
2231 &vi_info->pVertexBindingDescriptions[i];
2232
2233 pipeline->binding_stride[desc->binding] = desc->stride;
2234 }
2235
2236 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2237 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2238 if (loc->sgpr_idx != -1) {
2239 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2240 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2241 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2242 pipeline->graphics.vtx_emit_num = 3;
2243 else
2244 pipeline->graphics.vtx_emit_num = 2;
2245 }
2246 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2247 radv_dump_pipeline_stats(device, pipeline);
2248 }
2249
2250 result = radv_pipeline_scratch_init(device, pipeline);
2251 return result;
2252 }
2253
2254 VkResult
2255 radv_graphics_pipeline_create(
2256 VkDevice _device,
2257 VkPipelineCache _cache,
2258 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2259 const struct radv_graphics_pipeline_create_info *extra,
2260 const VkAllocationCallbacks *pAllocator,
2261 VkPipeline *pPipeline)
2262 {
2263 RADV_FROM_HANDLE(radv_device, device, _device);
2264 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2265 struct radv_pipeline *pipeline;
2266 VkResult result;
2267
2268 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2269 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2270 if (pipeline == NULL)
2271 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2272
2273 memset(pipeline, 0, sizeof(*pipeline));
2274 result = radv_pipeline_init(pipeline, device, cache,
2275 pCreateInfo, extra, pAllocator);
2276 if (result != VK_SUCCESS) {
2277 radv_pipeline_destroy(device, pipeline, pAllocator);
2278 return result;
2279 }
2280
2281 *pPipeline = radv_pipeline_to_handle(pipeline);
2282
2283 return VK_SUCCESS;
2284 }
2285
2286 VkResult radv_CreateGraphicsPipelines(
2287 VkDevice _device,
2288 VkPipelineCache pipelineCache,
2289 uint32_t count,
2290 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2291 const VkAllocationCallbacks* pAllocator,
2292 VkPipeline* pPipelines)
2293 {
2294 VkResult result = VK_SUCCESS;
2295 unsigned i = 0;
2296
2297 for (; i < count; i++) {
2298 VkResult r;
2299 r = radv_graphics_pipeline_create(_device,
2300 pipelineCache,
2301 &pCreateInfos[i],
2302 NULL, pAllocator, &pPipelines[i]);
2303 if (r != VK_SUCCESS) {
2304 result = r;
2305 pPipelines[i] = VK_NULL_HANDLE;
2306 }
2307 }
2308
2309 return result;
2310 }
2311
2312 static VkResult radv_compute_pipeline_create(
2313 VkDevice _device,
2314 VkPipelineCache _cache,
2315 const VkComputePipelineCreateInfo* pCreateInfo,
2316 const VkAllocationCallbacks* pAllocator,
2317 VkPipeline* pPipeline)
2318 {
2319 RADV_FROM_HANDLE(radv_device, device, _device);
2320 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2321 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2322 struct radv_pipeline *pipeline;
2323 VkResult result;
2324
2325 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2326 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2327 if (pipeline == NULL)
2328 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2329
2330 memset(pipeline, 0, sizeof(*pipeline));
2331 pipeline->device = device;
2332 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2333
2334 pipeline->shaders[MESA_SHADER_COMPUTE] =
2335 radv_pipeline_compile(pipeline, cache, module,
2336 pCreateInfo->stage.pName,
2337 MESA_SHADER_COMPUTE,
2338 pCreateInfo->stage.pSpecializationInfo,
2339 pipeline->layout, NULL);
2340
2341
2342 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2343 result = radv_pipeline_scratch_init(device, pipeline);
2344 if (result != VK_SUCCESS) {
2345 radv_pipeline_destroy(device, pipeline, pAllocator);
2346 return result;
2347 }
2348
2349 *pPipeline = radv_pipeline_to_handle(pipeline);
2350
2351 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2352 radv_dump_pipeline_stats(device, pipeline);
2353 }
2354 return VK_SUCCESS;
2355 }
2356 VkResult radv_CreateComputePipelines(
2357 VkDevice _device,
2358 VkPipelineCache pipelineCache,
2359 uint32_t count,
2360 const VkComputePipelineCreateInfo* pCreateInfos,
2361 const VkAllocationCallbacks* pAllocator,
2362 VkPipeline* pPipelines)
2363 {
2364 VkResult result = VK_SUCCESS;
2365
2366 unsigned i = 0;
2367 for (; i < count; i++) {
2368 VkResult r;
2369 r = radv_compute_pipeline_create(_device, pipelineCache,
2370 &pCreateInfos[i],
2371 pAllocator, &pPipelines[i]);
2372 if (r != VK_SUCCESS) {
2373 result = r;
2374 pPipelines[i] = VK_NULL_HANDLE;
2375 }
2376 }
2377
2378 return result;
2379 }